)]}' { "log": [ { "commit": "725fb29fd4bcda958b32f4479ad9934117c22019", "tree": "85d8760fca2aaa32e22d40de3930626ce1186d44", "parents": [ "4c011b1fb853776459c7d3d7de7b14fa41f28c46" ], "author": { "name": "Kumar Gala", "email": "galak@kernel.crashing.org", "time": "Fri Nov 09 03:51:14 2007 -0600" }, "committer": { "name": "Kumar Gala", "email": "galak@kernel.crashing.org", "time": "Fri Nov 09 03:51:14 2007 -0600" }, "message": "[POWERPC] Fix oops related to 4xx flush_tlb_page modification\n\nkmap_atomic calls flush_tlb_page with a NULL VMA and thus we end\nup dereferencing a NULL pointer to try and get the context.id.\n\nIf the VMA is null use the global pid value of 0.\n\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n" }, { "commit": "e701d269aa28996f3502780951fe1b12d5d66b49", "tree": "a55db7df5755bf9c69f466432786de7e7e445ba8", "parents": [ "57d75561be5496289601b2c94787ec38c718fcae" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Tue Oct 30 09:46:06 2007 +1100" }, "committer": { "name": "Josh Boyer", "email": "jwboyer@linux.vnet.ibm.com", "time": "Thu Nov 01 07:15:09 2007 -0500" }, "message": "[POWERPC] 4xx: Fix 4xx flush_tlb_page()\n\nOn 4xx CPUs, the current implementation of flush_tlb_page() uses\na low level _tlbie() assembly function that only works for the\ncurrent PID. Thus, invalidations caused by, for example, a COW\nfault triggered by get_user_pages() from a different context will\nnot work properly, causing among other things, gdb breakpoints\nto fail.\n\nThis patch adds a \"pid\" argument to _tlbie() on 4xx processors,\nand uses it to flush entries in the right context. FSL BookE\nalso gets the argument but it seems they don\u0027t need it (their\ntlbivax form ignores the PID when invalidating according to the\ndocument I have).\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\nSigned-off-by: Josh Boyer \u003cjwboyer@linux.vnet.ibm.com\u003e\n" }, { "commit": "1c7037db50ebecf3d5cfbf7082daa5d97d900fef", "tree": "1843c417160b79c3f79a54d546ddcf5ccdb1b44b", "parents": [ "22124c9999f00340b062fff740db30187bf18454" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Thu Oct 18 23:39:14 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Fri Oct 19 11:53:34 2007 -0700" }, "message": "remove unused flush_tlb_pgtables\n\nNobody uses flush_tlb_pgtables anymore, this patch removes all remaining\ntraces of it from all archs.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: \u003clinux-arch@vger.kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "1189be6508d45183013ddb82b18f4934193de274", "tree": "58924481b4de56699e4a884dce8dc601e71cf7d1", "parents": [ "287e5d6fcccfa38b953cebe307e1ddfd32363355" ], "author": { "name": "Paul Mackerras", "email": "paulus@samba.org", "time": "Thu Oct 11 20:37:10 2007 +1000" }, "committer": { "name": "Paul Mackerras", "email": "paulus@samba.org", "time": "Fri Oct 12 14:05:17 2007 +1000" }, "message": "[POWERPC] Use 1TB segments\n\nThis makes the kernel use 1TB segments for all kernel mappings and for\nuser addresses of 1TB and above, on machines which support them\n(currently POWER5+, POWER6 and PA6T).\n\nWe detect that the machine supports 1TB segments by looking at the\nibm,processor-segment-sizes property in the device tree.\n\nWe don\u0027t currently use 1TB segments for user addresses \u003c 1T, since\nthat would effectively prevent 32-bit processes from using huge pages\nunless we also had a way to revert to using 256MB segments. That\nwould be possible but would involve extra complications (such as\nkeeping track of which segment size was used when HPTEs were inserted)\nand is not addressed here.\n\nParts of this patch were originally written by Ben Herrenschmidt.\n\nSigned-off-by: Paul Mackerras \u003cpaulus@samba.org\u003e\n" }, { "commit": "3d5134ee8341bffc4f539049abb9e90d469b448d", "tree": "037958e0daa97b4ef350908a53182167ee2c8a03", "parents": [ "c19c03fc749147f565e807fa65f1729066800571" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Mon Jun 04 15:15:36 2007 +1000" }, "committer": { "name": "Paul Mackerras", "email": "paulus@samba.org", "time": "Thu Jun 14 22:29:56 2007 +1000" }, "message": "[POWERPC] Rewrite IO allocation \u0026 mapping on powerpc64\n\nThis rewrites pretty much from scratch the handling of MMIO and PIO\nspace allocations on powerpc64. The main goals are:\n\n - Get rid of imalloc and use more common code where possible\n - Simplify the current mess so that PIO space is allocated and\n mapped in a single place for PCI bridges\n - Handle allocation constraints of PIO for all bridges including\n hot plugged ones within the 2GB space reserved for IO ports,\n so that devices on hotplugged busses will now work with drivers\n that assume IO ports fit in an int.\n - Cleanup and separate tracking of the ISA space in the reserved\n low 64K of IO space. No ISA -\u003e Nothing mapped there.\n\nI booted a cell blade with IDE on PIO and MMIO and a dual G5 so\nfar, that\u0027s it :-)\n\nWith this patch, all allocations are done using the code in\nmm/vmalloc.c, though we use the low level __get_vm_area with\nexplicit start/stop constraints in order to manage separate\nareas for vmalloc/vmap, ioremap, and PCI IOs.\n\nThis greatly simplifies a lot of things, as you can see in the\ndiffstat of that patch :-)\n\nA new pair of functions pcibios_map/unmap_io_space() now replace\nall of the previous code that used to manipulate PCI IOs space.\nThe allocation is done at mapping time, which is now called from\nscan_phb\u0027s, just before the devices are probed (instead of after,\nwhich is by itself a bug fix). The only other caller is the PCI\nhotplug code for hot adding PCI-PCI bridges (slots).\n\nimalloc is gone, as is the \"sub-allocation\" thing, but I do beleive\nthat hotplug should still work in the sense that the space allocation\nis always done by the PHB, but if you unmap a child bus of this PHB\n(which seems to be possible), then the code should properly tear\ndown all the HPTE mappings for that area of the PHB allocated IO space.\n\nI now always reserve the first 64K of IO space for the bridge with\nthe ISA bus on it. I have moved the code for tracking ISA in a separate\nfile which should also make it smarter if we ever are capable of\nhot unplugging or re-plugging an ISA bridge.\n\nThis should have a side effect on platforms like powermac where VGA IOs\nwill no longer work. This is done on purpose though as they would have\nworked semi-randomly before. The idea at this point is to isolate drivers\nthat might need to access those and fix them by providing a proper\nfunction to obtain an offset to the legacy IOs of a given bus.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Paul Mackerras \u003cpaulus@samba.org\u003e\n" }, { "commit": "621023072524fc0155ed16490255e1ea3aa11585", "tree": "77fec16321fe72ef75532c4f07ffee004b57bbfe", "parents": [ "687304014f7ca8e2fbb3feaefef356b4a0da65ad" ], "author": { "name": "David Gibson", "email": "david@gibson.dropbear.id.au", "time": "Tue Apr 24 13:09:12 2007 +1000" }, "committer": { "name": "Paul Mackerras", "email": "paulus@samba.org", "time": "Tue Apr 24 22:08:56 2007 +1000" }, "message": "[POWERPC] Cleanup and fix breakage in tlbflush.h\n\nBenH\u0027s commit a741e67969577163a4cfc78d7fd2753219087ef1 in powerpc.git,\nalthough (AFAICT) only intended to affect ppc64, also has side-effects\nwhich break 44x. I think 40x, 8xx and Freescale Book E are also\naffected, though I haven\u0027t tested them.\n\nThe problem lies in unconditionally removing flush_tlb_pending() from\nthe versions of flush_tlb_mm(), flush_tlb_range() and\nflush_tlb_kernel_range() used on ppc64 - which are also used the\nembedded platforms mentioned above.\n\nThe patch below cleans up the convoluted #ifdef logic in tlbflush.h,\nin the process restoring the necessary flushes for the software TLB\nplatforms. There are three sets of definitions for the flushing\nhooks: the software TLB versions (revised to avoid using names which\nappear to related to TLB batching), the 32-bit hash based versions\n(external functions) amd the 64-bit hash based versions (which\nimplement batching).\n\nIt also moves the declaration of update_mmu_cache() to always be in\ntlbflush.h (previously it was in tlbflush.h except for PPC64, where it\nwas in pgtable.h).\n\nBooted on Ebony (440GP) and compiled for 64-bit and 32-bit\nmultiplatform.\n\nSigned-off-by: David Gibson \u003cdavid@gibson.dropbear.id.au\u003e\nAcked-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Paul Mackerras \u003cpaulus@samba.org\u003e\n" }, { "commit": "a741e67969577163a4cfc78d7fd2753219087ef1", "tree": "bac4162aaf15367e896429afa60465e201c9204c", "parents": [ "e4ee3891db35aa9a069bb403c2a66a8fbfa274d6" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Tue Apr 10 17:09:37 2007 +1000" }, "committer": { "name": "Paul Mackerras", "email": "paulus@samba.org", "time": "Fri Apr 13 04:09:38 2007 +1000" }, "message": "[POWERPC] Make tlb flush batch use lazy MMU mode\n\nThe current tlb flush code on powerpc 64 bits has a subtle race since we\nlost the page table lock due to the possible faulting in of new PTEs\nafter a previous one has been removed but before the corresponding hash\nentry has been evicted, which can leads to all sort of fatal problems.\n\nThis patch reworks the batch code completely. It doesn\u0027t use the mmu_gather\nstuff anymore. Instead, we use the lazy mmu hooks that were added by the\nparavirt code. They have the nice property that the enter/leave lazy mmu\nmode pair is always fully contained by the PTE lock for a given range\nof PTEs. Thus we can guarantee that all batches are flushed on a given\nCPU before it drops that lock.\n\nWe also generalize batching for any PTE update that require a flush.\n\nBatching is now enabled on a CPU by arch_enter_lazy_mmu_mode() and\ndisabled by arch_leave_lazy_mmu_mode(). The code epects that this is\nalways contained within a PTE lock section so no preemption can happen\nand no PTE insertion in that range from another CPU. When batching\nis enabled on a CPU, every PTE updates that need a hash flush will\nuse the batch for that flush.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Paul Mackerras \u003cpaulus@samba.org\u003e\n" }, { "commit": "62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f", "tree": "e85ca2d0dd43f90dccf758338764c3caa55f333f", "parents": [ "089f26d5e31b7bf42a9a8fefec08b30cd27f4b0e" ], "author": { "name": "David Woodhouse", "email": "dwmw2@infradead.org", "time": "Wed Apr 26 12:56:16 2006 +0100" }, "committer": { "name": "David Woodhouse", "email": "dwmw2@infradead.org", "time": "Wed Apr 26 12:56:16 2006 +0100" }, "message": "Don\u0027t include linux/config.h from anywhere else in include/\n\nSigned-off-by: David Woodhouse \u003cdwmw2@infradead.org\u003e\n" }, { "commit": "3c726f8dee6f55e96475574e9f645327e461884c", "tree": "f67c381e8f57959aa4a94bda4c68e24253cd8171", "parents": [ "f912696ab330bf539231d1f8032320f2a08b850f" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Mon Nov 07 11:06:55 2005 +1100" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sun Nov 06 16:56:47 2005 -0800" }, "message": "[PATCH] ppc64: support 64k pages\n\nAdds a new CONFIG_PPC_64K_PAGES which, when enabled, changes the kernel\nbase page size to 64K. The resulting kernel still boots on any\nhardware. On current machines with 4K pages support only, the kernel\nwill maintain 16 \"subpages\" for each 64K page transparently.\n\nNote that while real 64K capable HW has been tested, the current patch\nwill not enable it yet as such hardware is not released yet, and I\u0027m\nstill verifying with the firmware architects the proper to get the\ninformation from the newer hypervisors.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "1970282f3b453b7aac3b192a44705dcb5277fd82", "tree": "03993bd7b9e69619313da19c137cdde2df9416c5", "parents": [ "9a0f78f63bc05d195aab781486ed57d1418d5f59" ], "author": { "name": "Stephen Rothwell", "email": "sfr@canb.auug.org.au", "time": "Fri Nov 04 16:58:59 2005 +1100" }, "committer": { "name": "Stephen Rothwell", "email": "sfr@canb.auug.org.au", "time": "Fri Nov 04 16:58:59 2005 +1100" }, "message": "powerpc: merge tlbflush.h\n\nSigned-off-by: Stephen Rothwell \u003csfr@canb.auug.org.au\u003e\n" } ] }