)]}' { "log": [ { "commit": "6a03513825db4db57fa93821a0c04dbbb39a68e6", "tree": "cddcf6a74ee0022d62218bf4a6caf6f4fe952b0c", "parents": [ "ab7798ffcf98b11a9525cf65bacdae3fd58d357f" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Mar 25 12:21:38 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Mar 25 22:09:00 2011 +0100" }, "message": "dma: Ipu: Convert interupt code\n\nConvert to the new irq chip functions and cleanup the name space.\n\n[ Guennadi reported: irq_data_get_chip_data is undefined. Yes, I screwed up. \n it needs to be irq_data_get_irq_chip_data ]\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nTested-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Dan Williams \u003cdan.j.williams@intel.com\u003e\nLKML-Reference: \u003calpine.LFD.2.00.1103251220000.31464@localhost6.localdomain6\u003e\n" }, { "commit": "a646bd7f0824d3e0f02ff8d7410704f965de01bc", "tree": "8504b83156a36ce508821a334b67d8a55b7dca89", "parents": [ "8179661694595eb3a4f2ff9bb0b73acbb7d2f4a9" ], "author": { "name": "Anatolij Gustschin", "email": "agust@denx.de", "time": "Mon Jan 31 13:22:29 2011 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Feb 14 02:28:16 2011 -0800" }, "message": "dma: ipu_idmac: do not lose valid received data in the irq handler\n\nCurrently when two or more buffers are queued by the camera driver\nand so the double buffering is enabled in the idmac, we lose one\nframe comming from CSI since the reporting of arrival of the first\nframe is deferred by the DMAIC_7_EOF interrupt handler and reporting\nof the arrival of the last frame is not done at all. So when requesting\nN frames from the image sensor we actually receive N - 1 frames in\nuser space.\n\nThe reason for this behaviour is that the DMAIC_7_EOF interrupt\nhandler misleadingly assumes that the CUR_BUF flag is pointing to the\nbuffer used by the IDMAC. Actually it is not the case since the\nCUR_BUF flag will be flipped by the FSU when the FSU is sending the\n\u003cTASK\u003e_NEW_FRM_RDY signal when new frame data is delivered by the CSI.\nWhen sending this singal, FSU updates the DMA_CUR_BUF and the\nDMA_BUFx_RDY flags: the DMA_CUR_BUF is flipped, the DMA_BUFx_RDY\nis cleared, indicating that the frame data is beeing written by\nthe IDMAC to the pointed buffer. DMA_BUFx_RDY is supposed to be\nset to the ready state again by the MCU, when it has handled the\nreceived data. DMAIC_7_CUR_BUF flag won\u0027t be flipped here by the\nIPU, so waiting for this event in the EOF interrupt handler is wrong.\nActually there is no spurious interrupt as described in the comments,\nthis is the valid DMAIC_7_EOF interrupt indicating reception of the\nframe from CSI.\n\nThe patch removes code that waits for flipping of the DMAIC_7_CUR_BUF\nflag in the DMAIC_7_EOF interrupt handler. As the comment in the\ncurrent code denotes, this waiting doesn\u0027t help anyway. As a result\nof this removal the reporting of the first arrived frame is not\ndeferred to the time of arrival of the next frame and the drivers\nsoftware flag \u0027ichan-\u003eactive_buffer\u0027 is in sync with DMAIC_7_CUR_BUF\nflag, so the reception of all requested frames works.\n\nThis has been verified on the hardware which is triggering the\nimage sensor by the programmable state machine, allowing to\nobtain exact number of frames. On this hardware we do not tolerate\nlosing frames.\n\nThis patch also removes resetting the DMA_BUFx_RDY flags of\nall channels in ipu_disable_channel() since transfers on other\nDMA channels might be triggered by other running tasks and the\nbuffers should always be ready for data sending or reception.\n\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nReviewed-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nTested-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "058276303dbc4ed089c1f7dad0871810b1f5ddf1", "tree": "df26ff701721b2a91d61bd29e48bad7cbcedd746", "parents": [ "4aed79b2818e7330b5d00143e4c20bc6555df91f" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Mon May 17 16:30:42 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon May 17 16:30:42 2010 -0700" }, "message": "DMAENGINE: extend the control command to include an arg\n\nThis adds an argument to the DMAengine control function, so that\nwe can later provide control commands that need some external data\npassed in through an argument akin to the ioctl() operation\nprototype.\n\n[dan.j.williams@intel.com: fix up some missed conversions]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bca3469205402d9fb14060d255d8786ae2256640", "tree": "3b0c7f246fb9a6eafd3a82dd621dd9753589b3f4", "parents": [ "0793448187643b50af89d36b08470baf45a3cab4" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Mar 26 16:52:10 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Mar 26 16:52:10 2010 -0700" }, "message": "dmaengine: provide helper for setting txstate\n\nSimple conditional struct filler to cut out some duplicated code.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0793448187643b50af89d36b08470baf45a3cab4", "tree": "b3313ff58d47e26a8cf707d196177effa1aadfbe", "parents": [ "c3635c78e500a52c9fcd55de381a72928d9e054d" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Fri Mar 26 16:50:49 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Mar 26 16:50:49 2010 -0700" }, "message": "DMAENGINE: generic channel status v2\n\nConvert the device_is_tx_complete() operation on the\nDMA engine to a generic device_tx_status()operation which\ncan return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE,\nDMA_TX_PAUSED.\n\n[dan.j.williams@intel.com: update for timberdale]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nCc: Pavel Machek \u003cpavel@ucw.cz\u003e\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nCc: Magnus Damm \u003cdamm@opensource.se\u003e\nCc: Liam Girdwood \u003clrg@slimlogic.co.uk\u003e\nCc: Joe Perches \u003cjoe@perches.com\u003e\nCc: Roland Dreier \u003crdreier@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "c3635c78e500a52c9fcd55de381a72928d9e054d", "tree": "87403f402227cd8b5572550e70facf81c9eaa0d9", "parents": [ "0f65169b1bf44220308e1ce1f6666ad03ddc27af" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Fri Mar 26 16:44:01 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Mar 26 16:44:01 2010 -0700" }, "message": "DMAENGINE: generic slave control v2\n\nConvert the device_terminate_all() operation on the\nDMA engine to a generic device_control() operation\nwhich can now optionally support also pausing and\nresuming DMA on a certain channel. Implemented for the\nCOH 901 318 DMAC as an example.\n\n[dan.j.williams@intel.com: update for timberdale]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nCc: Pavel Machek \u003cpavel@ucw.cz\u003e\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nCc: Magnus Damm \u003cdamm@opensource.se\u003e\nCc: Liam Girdwood \u003clrg@slimlogic.co.uk\u003e\nCc: Joe Perches \u003cjoe@perches.com\u003e\nCc: Roland Dreier \u003crdreier@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "dd58ffcf5a5352fc10820c8ffbcd5fed416a2c3a", "tree": "f36172b40f9f3fc2c646f70da40e01705399b6b8", "parents": [ "aa4d72ae946a4fa40486b871717778734184fa29", "56a5d3cf21c71963c8fc506e9b9d3f71641d9c71" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:22:21 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:22:21 2010 -0700" }, "message": "Merge branch \u0027coh\u0027 into dmaengine\n" }, { "commit": "8f98781e0f15207b6ab33bee1fae05428be0475b", "tree": "31830720fd57bd11191e85bbdc98eaefe061f127", "parents": [ "b953df7c70740cd7593072ebec77a8f658505630" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed Feb 10 17:32:38 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 10 12:01:06 2010 -0700" }, "message": "async-tx: fix buffer submission error handling in ipu_idma.c\n\nIf submitting new buffer failed, a wrong descriptor gets completed and it\ndoesn\u0027t check, if a callback is at all defined, which can lead to an Oops. Fix\nthese bugs and make ipu_update_channel_buffer() void, because it never fails.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9ad7bd2944bd979ef4877cd439719be44c5f3b47", "tree": "cf70d092016d677b68b4178b7f669939c3820b63", "parents": [ "4b1cf1facca31b7db2a61d8aa2ba40d5a93a0957" ], "author": { "name": "Roel Kluin", "email": "roel.kluin@gmail.com", "time": "Wed Jan 20 01:25:56 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 23:42:25 2010 -0700" }, "message": "dma: cases IPU_PIX_FMT_BGRA32, BGR32 and ABGR32 are the same in ipu_ch_param_set_size()\n\nIn these cases the same statements are executed.\n\nSigned-off-by: Roel Kluin \u003croel.kluin@gmail.com\u003e\nAcked-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ad567ffb32f067b30606071eb568cf637fe42185", "tree": "0913e4e6cc06dd59a5a8a2367d30a2e46fad649f", "parents": [ "4f005dbe5584fe54c9f6d6d4f0acd3fb29be84da" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Tue May 12 09:16:29 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue May 12 14:41:48 2009 -0700" }, "message": "dma: fix ipu_idmac.c to not discard the last queued buffer\n\nThis also fixes the case of a single queued buffer, for example, when taking a\nsingle frame snapshot with the mx3_camera driver.\n\nReported-by: Agustin Ferrin Pozuelo \u003cgatoguan-os@yahoo.com\u003e\nTested-by: Agustin Ferrin Pozuelo \u003cgatoguan-os@yahoo.com\u003e\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ca50a51e890b0a62b44b5642c1ba5049909e5a8b", "tree": "d5804f7a5ab5760e996093690654df3a59e9adf8", "parents": [ "c56c81abe7e684bc6203632d807303eb765690dc" ], "author": { "name": "Ben Nizette", "email": "bn@niasdigital.com", "time": "Thu Apr 16 05:54:12 2009 +1000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue May 05 12:16:56 2009 -0700" }, "message": "ipu_idmac: Use disable_irq_nosync() from within irq handlers.\n\ndisable_irq() should wait for all running handlers to complete\nbefore returning. As such, if it\u0027s used to disable an interrupt\nfrom that interrupt\u0027s handler it will deadlock. This replaces\nthe dangerous instances with the _nosync() variant which doesn\u0027t\nhave this problem.\n\nNote the 2 handlers in question are only used #ifdef DEBUG so\nI imagine these code paths don\u0027t get hit often.\n\nSigned-off-by: Ben Nizette \u003cbn@niasdigital.com\u003e\nAcked-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "133e2a3164771454aa326859c2b293687189b553", "tree": "4e21f63be087738d7ffe7526d41e15140fc63ff0", "parents": [ "20bec8ab1458c24bed0d5492ee15d87807fc415a", "8c6db1bbf80123839ec87bdd6cb364aea384623d" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Apr 03 12:13:45 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Apr 03 12:13:45 2009 -0700" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanup\n dw_dmac: add cyclic API to DW DMA driver\n dmaengine: Add privatecnt to revert DMA_PRIVATE property\n dmatest: add dma interrupts and callbacks\n dmatest: add xor test\n dmaengine: allow dma support for async_tx to be toggled\n async_tx: provide __async_inline for HAS_DMA\u003dn archs\n dmaengine: kill some unused headers\n dmaengine: initialize tx_list in dma_async_tx_descriptor_init\n dma: i.MX31 IPU DMA robustness improvements\n dma: improve section assignment in i.MX31 IPU DMA driver\n dma: ipu_idmac driver cosmetic clean-up\n dmaengine: fail device registration if channel registration fails\n" }, { "commit": "8c6db1bbf80123839ec87bdd6cb364aea384623d", "tree": "848b8d42f093c03a046bd9ae204b360b5174ea28", "parents": [ "d9de451989a88a2003ca06e524aca4665c0c7f06" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Thu Apr 02 11:36:58 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 02 16:59:10 2009 -0700" }, "message": "dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanup\n\nAdd Start-of-Frame and End-of-Frame debugging to ipu_idmac.c, in the\nfuture it might also be needed for the actual video processing in\nmx3-camera, at which point, the ISRs will have to be transferred to\nmx3_camera.c, for which ipu_irq_map() and ipu_irq_unmap() functions will\nhave to be exported.\n\nAlso simplify a couple of pointer-dereferences.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ccccce229c633a92c42cd1a40c0738d7b0d12644", "tree": "a954537ae73f2e03c4431b244796cdc255af7a10", "parents": [ "8d47bae004f062630f69f7f83d098424252e232d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "message": "dmaengine: initialize tx_list in dma_async_tx_descriptor_init\n\nCentralize this common initialization (and one case where ipu_idmac is\nduplicating -\u003echan initialization).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "8d47bae004f062630f69f7f83d098424252e232d", "tree": "68379790587eef10926d029ffce74b763175b10c", "parents": [ "234f2df56f5b05756c444edc9879145deddf69f4" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "message": "dma: i.MX31 IPU DMA robustness improvements\n\nAdd DMA error handling to the ISR, move common code fragments to functions, fix\nscatter-gather element queuing in the ISR, survive channel freeing and\nre-allocation in a quick succession.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "234f2df56f5b05756c444edc9879145deddf69f4", "tree": "6946d1561e3243cbb4046652d1d70b647bb7947d", "parents": [ "0149f7d5dc66dcffbb044ba005a5378a5864d2a3" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "message": "dma: improve section assignment in i.MX31 IPU DMA driver\n\nThe i.MX31 IPU DMA driver is a platform driver, but doesn\u0027t need hotplug, so we\ncan use __init and __exit function attributes.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0149f7d5dc66dcffbb044ba005a5378a5864d2a3", "tree": "9ba399f0c71d62d23563d74308a58cc7eb5baf62", "parents": [ "257b17ca030387cb17314cd1851507bdd1b4ddd5" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Wed Mar 25 09:13:23 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:23 2009 -0700" }, "message": "dma: ipu_idmac driver cosmetic clean-up\n\nRemove superfluous semicolons, update comments.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9eb2eb8c40ffd30da322648c4415bae0288eb167", "tree": "b2402fd33314e4a78d11d8429c86ffe15cac8d4c", "parents": [ "9a51157bab06ab54d6ee442e34fe9574ff14c8c3" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Wed Feb 18 11:55:33 2009 +0100" }, "committer": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Fri Mar 13 10:34:32 2009 +0100" }, "message": "MX31 clkdev support\n\nThis patch adds clkdev support for i.MX31. This is done in a\nsimilar way done previously for i.MX27\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\n" }, { "commit": "c74ef1f867d18171c8617519ee5fe40b02903934", "tree": "35aacfe4325ecf38bea4ec484444fc4b04d66b6d", "parents": [ "a09b09ae51ace43d28cd9bc1c8bb97986f2b55a6" ], "author": { "name": "Luotao Fu", "email": "l.fu@pengutronix.de", "time": "Thu Feb 26 12:29:20 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 04 16:04:41 2009 -0700" }, "message": "ipu_idmac: fix spinlock type\n\nfix a probably accidently dropped reference operator while calling\nspin_unlock_restore to an ipu lock.\n\nSigned-off-by: Luotao Fu \u003cl.fu@pengutronix.de\u003e\nCc: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5296b56d1b2000b60fb966be161c1f8fb629786b", "tree": "18277748caa9ba43610f76a310d34a3b2155e1a5", "parents": [ "ef560682a97491f62ef538931a4861b57d66c52c" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Mon Jan 19 15:36:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 19 15:36:21 2009 -0700" }, "message": "i.MX31: Image Processing Unit DMA and IRQ drivers\n\ni.MX3x SoCs contain an Image Processing Unit, consisting of a Control\nModule (CM), Display Interface (DI), Synchronous Display Controller (SDC),\nAsynchronous Display Controller (ADC), Image Converter (IC), Post-Filter\n(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).\nCM contains, among other blocks, an Interrupt Generator (IG) and a Clock\nand Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are\nsupported over dmaengine and irq-chip APIs respectively.\n\nIDMAC is a specialised DMA controller, its DMA channels cannot be used for\ngeneral-purpose operations, even though it might be possible to configure\na memory-to-memory channel for memcpy operation. This driver will not work\nwith generic dmaengine clients, clients, wishing to use it must use\nrespective wrapper structures, they also must specify which channels they\nrequire, as channels are hard-wired to specific IPU functions.\n\nAcked-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" } ] }