)]}'
{
  "log": [
    {
      "commit": "b0b1d60a64054697ef828e0565f006cc0f823590",
      "tree": "3ca024704b8f7967d460f954db68f0aaadaf7d25",
      "parents": [
        "4cc2f7a84d64d25a16bb9383148c1467284e2356"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Dec 29 01:30:24 2006 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Sat Dec 30 17:05:08 2006 +0000"
      },
      "message": "[ARM] 4077/1: iop13xx: fix __io() macro\n\nSince iop13xx defines the PCI I/O spaces with physical resource addresses\nthe __io macro needs to perform the physical to virtual conversion.  I\nincorrectly assumed that this would be handled by ioremap, but drivers\n(like e1000) directly dereference the address returned from __io.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "6d2e857d02a59332b7cd89aeac8b5962a357ac7a",
      "tree": "09e1a3435dc87326785e5382c550ccbfe1a2a47c",
      "parents": [
        "99e4a6dda9dc4b863773c0a5857b762474b817cf"
      ],
      "author": {
        "name": "Lennert Buytenhek",
        "email": "buytenh@wantstofly.org",
        "time": "Mon Dec 18 01:01:08 2006 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Mon Dec 18 00:14:56 2006 +0000"
      },
      "message": "[ARM] 4055/1: iop13xx: fix phys_io/io_pg_offst for iq81340mc/sc\n\nThe phys_io/io_pg_offst machine record variables were being set\nto bogus values, causing problems when enabling DEBUG_LL.\n\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@wantstofly.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "285f5fa7e9a35e75d9022f9b036ed709721c5cdf",
      "tree": "d977aecd1a350e2c14086005b873141d8d829e12",
      "parents": [
        "4dbda6a50ae34d853353f15d30a166c87143408f"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Dec 07 02:59:39 2006 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Thu Dec 07 17:20:21 2006 +0000"
      },
      "message": "[ARM] 3995/1: iop13xx: add iop13xx support\n\nThe iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a\nSerial Attached SCSI (SAS) controller, multi-ported DDR2 memory\ncontroller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz\nPCI-X interface, a x8 PCI-Express interface, and other peripherals to form\na system-on-a-chip RAID subsystem engine.\n\nThe iop342 processor replaces the SAS controller with a second Xscale core\nfor dual core embedded applications.\n\nThe iop341 processor is the single core version of iop342.\n\nThis patch supports the two Intel customer reference platforms iq81340mc\nfor external storage and iq81340sc for direct attach (HBA) development.\n\nThe developer\u0027s manual is available here:\nftp://download.intel.com/design/iio/docs/31503701.pdf\n\nChangelog:\n* removed virtual addresses from resource definitions\n* cleaned up some unnecessary #include\u0027s\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    }
  ]
}