)]}' { "log": [ { "commit": "ca21a146a45a179a2a7bc86d938a2fbf571a7510", "tree": "cd0e029a9b29a083e8245ae6cf7aa01f6e1fd99f", "parents": [ "b14dab792dee3245b628e046d80a7fad5573fea6" ], "author": { "name": "Rongjun Ying", "email": "Rongjun.Ying@csr.com", "time": "Thu Oct 27 19:22:39 2011 -0700" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Fri Nov 18 12:25:22 2011 +0530" }, "message": "dmaengine: add CSR SiRFprimaII DMAC driver\n\nCc: Jassi Brar \u003cjaswinder.singh@linaro.org\u003e\nCc: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Rongjun Ying \u003crongjun.ying@csr.com\u003e\nSigned-off-by: Barry Song \u003cBaohua.Song@csr.com\u003e\n[fixed direction enums and cyclic api based on changes\n already merged]\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "ca7fe2db892dcf91b2c72ee352eda4ff867903a7", "tree": "3e549eb73405d9168a8c93a0a3670ff5688b549a", "parents": [ "e79e72be298dc4726a641686032b8296c2fb473e" ], "author": { "name": "Tomoya MORINAGA", "email": "tomoya.rohm@gmail.com", "time": "Thu Nov 17 16:14:23 2011 +0900" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Thu Nov 17 14:27:41 2011 +0530" }, "message": "pch_dma: Support new device LAPIS Semiconductor ML7831 IOH\n\nML7831 is companion chip for Intel Atom E6xx series.\n\nSigned-off-by: Tomoya MORINAGA \u003ctomoya.rohm@gmail.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "e79e72be298dc4726a641686032b8296c2fb473e", "tree": "0d12afe85913df834fc57d0ffd87f569774a48f2", "parents": [ "8e2d41f8c85613a3739e8b2600ac2c66c08422f3" ], "author": { "name": "Tomoya MORINAGA", "email": "tomoya.rohm@gmail.com", "time": "Thu Nov 17 16:14:22 2011 +0900" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Thu Nov 17 14:27:41 2011 +0530" }, "message": "pch_dma: Change company name OKI SEMICONDUCTOR to LAPIS Semiconductor\n\nOn October 1 in 2011,\nOKI SEMICONDUCTOR Co., Ltd. changed the company name in to LAPIS Semiconductor\nCo., Ltd.\n\nSigned-off-by: Tomoya MORINAGA \u003ctomoya.rohm@gmail.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "8e2d41f8c85613a3739e8b2600ac2c66c08422f3", "tree": "ea75c81772247d94c8b9fe9d223d4f14e4511f7c", "parents": [ "dbb004294a934d030a9d716692a1dd6f677fc90e" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Wed Aug 24 08:41:09 2011 +0200" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@linux.intel.com", "time": "Thu Nov 17 14:26:16 2011 +0530" }, "message": "dma i.MX: remove individual SOC dependency\n\nThe individual SoC dependency in Kconfig hardly scales anymore.\nInstead of having such a fine grained dependency just depend\non ARCH_MXC and risk that the uninformed user has to look in\nthe help text to figure out which driver is the correct one.\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nCc: Vinod Koul \u003cvinod.koul@intel.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@linux.intel.com\u003e\n" }, { "commit": "1b9bb715e7c4c189c4215a11a09e2ccb16598d86", "tree": "e274c2a58ec31185e0871255a5fd64c177ee4898", "parents": [ "a2f5203fec3c06d68a6bb45ad41f2adebf9ac5e0" ], "author": { "name": "Boojin Kim", "email": "boojin.kim@samsung.com", "time": "Fri Sep 02 09:44:30 2011 +0900" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@intel.com", "time": "Wed Sep 14 11:10:01 2011 +0530" }, "message": "DMA: PL330: Update PL330 DMA API driver\n\nThis patch updates following 3 items.\n1. Removes unneccessary code.\n2. Add AMBA, PL330 configuration\n3. Change the meaning of \u0027peri_id\u0027 variable\n from PL330 event number to specific dma id by user.\n\nSigned-off-by: Boojin Kim \u003cboojin.kim@samsung.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nAcked-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\nCc: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\n" }, { "commit": "760ee1c4aafac8fcaf3be5ff2b19c5485c5886e1", "tree": "fc8408001ecba7a7b575f8fa839fcc6989f852bb", "parents": [ "b6336ca2982ccac98d9d017426c53ff1e13c017f" ], "author": { "name": "Mika Westerberg", "email": "mika.westerberg@iki.fi", "time": "Sun May 29 13:10:02 2011 +0300" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Wed Jun 08 15:10:44 2011 -0600" }, "message": "dmaengine: add ep93xx DMA support\n\nThe ep93xx DMA controller has 10 independent memory to peripheral (M2P)\nchannels, and 2 dedicated memory to memory (M2M) channels. M2M channels can\nalso be used by SPI and IDE to perform DMA transfers to/from their memory\nmapped FIFOs.\n\nThis driver supports both M2P and M2M channels with DMA_SLAVE, DMA_CYCLIC and\nDMA_MEMCPY (M2M only) capabilities.\n\nSigned-off-by: Mika Westerberg \u003cmika.westerberg@iki.fi\u003e\nSigned-off-by: Ryan Mallon \u003crmallon@gmail.com\u003e\nAcked-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nAcked-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "c0dfc04ac96847913a791f5459f4ac83a81a4745", "tree": "321c07adc696aa3bf4853afb988ff1a5b126f754", "parents": [ "194f5f2706c7472f9c6bb2d17fa788993606581f" ], "author": { "name": "Tomoya MORINAGA", "email": "tomoya-linux@dsn.okisemi.com", "time": "Mon May 09 16:09:39 2011 +0900" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@intel.com", "time": "Mon May 09 17:12:23 2011 +0530" }, "message": "pch_dma: Support new device ML7223 IOH\n\nSupport new device OKI SEMICONDUCTOR ML7223 IOH(Input/Output Hub).\nThe ML7223 IOH is for MP(Media Phone) use.\nThe ML7223 is companion chip for Intel Atom E6xx series.\nThe ML7223 is completely compatible for Intel EG20T PCH.\n\nSigned-off-by: Tomoya MORINAGA \u003ctomoya-linux@dsn.okisemi.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\n" }, { "commit": "5b9a4f98b2e29fb92a4a54ef12b2e3940f941ed9", "tree": "6811bbf0924085a9f17029d82e2065e3be5c1520", "parents": [ "a00ae34ac8bc8a5897d9b6b9b685c39b955b14b9" ], "author": { "name": "Uwe Kleine-König", "email": "u.kleine-koenig@pengutronix.de", "time": "Tue Mar 22 10:35:17 2011 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Mar 22 11:11:20 2011 -0700" }, "message": "dma: let IMX_DMA depend on IMX_HAVE_DMA_V1 instead of an explicit list of SoCs\n\nAs a side effect this makes IMX_DMA selectable on i.MX21 again, because\nthe symbol ARCH_MX21 doesn\u0027t exist (MACH_MX21 would have been more correct).\n\nSigned-off-by: Uwe Kleine-König \u003cu.kleine-koenig@pengutronix.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f44ad7e91dd12bed0959b3e715f4f3ab84951a59", "tree": "ad40522874528c87cfc367f882df147afdf71e9d", "parents": [ "a580b8c5429a624d120cd603e1498bf676e2b4da" ], "author": { "name": "Viresh Kumar", "email": "viresh.kumar@st.com", "time": "Thu Mar 03 15:47:14 2011 +0530" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@intel.com", "time": "Mon Mar 07 01:12:27 2011 +0530" }, "message": "dw_dmac: Remove compilation dependency from AVR32 and put on HAVE_CLK\n\nThis driver will now be used in atleast two platforms AVR32 \u0026 ARM. And there is\nno actual hardware dependency of this driver over AVR32 or ARM. So this\ndependency can be removed altogether.\n\nAlso dw_dmac driver uses clk framework and must have compilation dependency on\nHAVE_CLK\n\nSigned-off-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\n" }, { "commit": "a580b8c5429a624d120cd603e1498bf676e2b4da", "tree": "14e4bd82f203bf9f43fa19341d85d993e5a4c569", "parents": [ "26d890f0d09fd58f7194aad651e86283cb9e6574" ], "author": { "name": "Shawn Guo", "email": "shawn.guo@freescale.com", "time": "Sun Feb 27 00:47:42 2011 +0800" }, "committer": { "name": "Vinod Koul", "email": "vinod.koul@intel.com", "time": "Wed Mar 02 07:06:27 2011 +0530" }, "message": "dmaengine: mxs-dma: add dma support for i.MX23/28\n\nThis patch adds dma support for Freescale MXS-based SoC i.MX23/28,\nincluding apbh-dma and apbx-dma.\n\n* apbh-dma and apbx-dma are supported in the driver as two mxs-dma\n instances.\n\n* apbh-dma is different between mx23 and mx28, hardware version\n register is used to differentiate.\n\n* mxs-dma supports pio function besides data transfer. The driver\n uses dma_data_direction DMA_NONE to identify the pio mode, and\n steals sgl and sg_len to get pio words and numbers from clients.\n\n* mxs dmaengine has some very specific features, like sense function\n and the special NAND support (nand_lock, nand_wait4ready). These\n are too specific to implemented in generic dmaengine driver.\n\n* The driver refers to imx-sdma and only a single descriptor is\n statically assigned to each channel.\n\nSigned-off-by: Shawn Guo \u003cshawn.guo@freescale.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\n" }, { "commit": "e1288cd72f54e7fc16ae9ebb4d0647537ef848d4", "tree": "b4fd87b9307d8041fb680cb9b8fbf787ec968df7", "parents": [ "e78bf5e6cbe837daa6ab628a5f679548742994d3", "94ae85220a07d357d4937086c490854f63344de4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jan 17 10:54:41 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jan 17 10:54:41 2011 -0800" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (63 commits)\n ARM: PL08x: cleanup comments\n Update CONFIG_MD_RAID6_PQ to CONFIG_RAID6_PQ in drivers/dma/iop-adma.c\n ARM: PL08x: fix a warning\n Fix dmaengine_submit() return type\n dmaengine: at_hdmac: fix race while monitoring channel status\n dmaengine: at_hdmac: flags located in first descriptor\n dmaengine: at_hdmac: use subsys_initcall instead of module_init\n dmaengine: at_hdmac: no need set ACK in new descriptor\n dmaengine: at_hdmac: trivial add precision to unmapping comment\n dmaengine: at_hdmac: use dma_address to program DMA hardware\n pch_dma: support new device ML7213 IOH\n ARM: PL08x: prevent dma_set_runtime_config() reconfiguring memcpy channels\n ARM: PL08x: allow dma_set_runtime_config() to return errors\n ARM: PL08x: fix locking between prepare function and submit function\n ARM: PL08x: introduce \u0027phychan_hold\u0027 to hold on to physical channels\n ARM: PL08x: put txd\u0027s on the pending list in pl08x_tx_submit()\n ARM: PL08x: rename \u0027desc_list\u0027 as \u0027pend_list\u0027\n ARM: PL08x: implement unmapping of memcpy buffers\n ARM: PL08x: store prep_* flags in async_tx structure\n ARM: PL08x: shrink srcbus/dstbus in txd structure\n ...\n" }, { "commit": "2cdf2455a660ea860272ef3f833f0e5c4cc80205", "tree": "716d5ba5695ea3a13c5bebe1d5afab5d115dee18", "parents": [ "bc0fa81473c077bf4403e3b7b3397326204b65cd" ], "author": { "name": "Tomoya MORINAGA", "email": "tomoya-linux@dsn.okisemi.com", "time": "Wed Jan 05 17:43:52 2011 +0900" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jan 14 16:24:53 2011 -0800" }, "message": "pch_dma: support new device ML7213 IOH\n\nSupport new device OKI SEMICONDUCTOR\u0027s ML7213 IOH(Input/Output Hub) which is for\nIVI(In-Vehicle Infotainment) use.\nThe ML7213 is companion chip for Intel Atom E6xx series.\nThe ML7213 is completely compatible for Intel EG20T PCH.\n\nSigned-off-by: Tomoya MORINAGA \u003ctomoya-linux@dsn.okisemi.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ba2eea251f815b3674cde13ecdba4772332bf56e", "tree": "858c0d3657b5aabed3bcd5f5fbf677dd3f95d9f9", "parents": [ "2862559e8a1e7c47bb3003f0edbc9db9009dc32b" ], "author": { "name": "Ilya Yanok", "email": "yanok@emcraft.com", "time": "Wed Oct 27 01:52:57 2010 +0200" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Wed Dec 29 22:29:02 2010 -0700" }, "message": "powerpc/512x: add MPC8308 dma support\n\nMPC8308 has pretty much the same DMA controller as MPC5121 and\nthis patch adds support for MPC8308 to the mpc512x_dma driver.\n\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nAcked-by: Wolfgang Denk \u003cwd@denx.de\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "d2df40857fd57f02906e6ac1484d10cb7accbc86", "tree": "e38165d29e15ada205297786ca33e088ad92a347", "parents": [ "1e431a9d6478940c0b5fcfa1c17a336fc0683409" ], "author": { "name": "Valdis.Kletnieks@vt.edu", "email": "Valdis.Kletnieks@vt.edu", "time": "Fri Oct 29 17:03:46 2010 -0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Oct 29 14:14:02 2010 -0700" }, "message": "drivers/dma/Kconfig: add part number for Topcliff.\n\nProduct codenames are OK, but once an actual product name is available,\nit should be referenced as well.\n\n http://ark.intel.com/chipset.aspx?familyID\u003d52499\n\nSigned-off-by: Valdis Kletnieks \u003cvaldis.kletnieks@vt.edu\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "5fc6d897fde352bad5db5767e7260741a8cdd9e9", "tree": "cb918dd33b8288aadead08b04b9f308f9d8bcbd1", "parents": [ "400fb7f6a0cfe13025cb0296fdb4737da7025a8a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 16:44:50 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 17:08:32 2010 -0700" }, "message": "async_tx: make async_tx channel switching opt-in\n\nThe majority of drivers in drivers/dma/ will never establish cross\nchannel operation chains and do not need the extra overhead in struct\ndma_async_tx_descriptor. Make channel switching opt-in by default.\n\nCc: Anatolij Gustschin \u003cagust@denx.de\u003e\nCc: Ira Snyder \u003ciws@ovro.caltech.edu\u003e\nCc: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nCc: Saeed Bishara \u003csaeed@marvell.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6391987d6f8ced7d0fafaa1440dcc57bb4b34d8f", "tree": "027a3989fceb18c45cf6d435a87b9879e38b8216", "parents": [ "9646b7985e906e5fcea9375f016b4519c8318c21", "e8689e63d4d2046079f2db9d494ac05c6885ac0c", "0d688662aab9d80078be82aa5aea561346643298", "1f1846c6ceed07c03ef036a27864befe0f773997", "20dd63900d238e17b122fe0c7376ff090867f528" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:19:01 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:19:01 2010 -0700" }, "message": "Merge branches \u0027dma40\u0027, \u0027pl08x\u0027, \u0027fsldma\u0027, \u0027imx\u0027 and \u0027intel-mid\u0027 into dmaengine\n" }, { "commit": "1f1846c6ceed07c03ef036a27864befe0f773997", "tree": "107e5cabb0e33c041283a2cebd46482381878adb", "parents": [ "1ec1e82f2510e2bdcb6268ed74aa79e1a7bc9594" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Wed Oct 06 10:25:55 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:18:03 2010 -0700" }, "message": "dmaengine: Add Freescale i.MX1/21/27 DMA driver\n\nThis driver is currently implemented as a user to the old i.MX\nDMA API. This allows us to convert each user of the old API to\nthe dmaengine API one by one. Once this is done the old DMA\ndriver can be merged into the i.MX dmaengine driver.\n\nV2: remove some debug leftovers and unused variables\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1ec1e82f2510e2bdcb6268ed74aa79e1a7bc9594", "tree": "f274f0b9ff704416492fe420174e65b9b640eff2", "parents": [ "6e3ecaf0ad49de0bed829d409a164e7107c02993" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Thu Sep 30 13:56:34 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 05 15:49:26 2010 -0700" }, "message": "dmaengine: Add Freescale i.MX SDMA support\n\nThis patch adds support for the Freescale i.MX SDMA engine.\n\nThe SDMA engine is a scatter/gather DMA engine which is implemented\nas a seperate coprocessor. SDMA needs its own firmware which is\nrequested using the standard request_firmware mechanism. The firmware\nhas different entry points for each peripheral type, so drivers\nhave to pass the peripheral type to the DMA engine which in turn\npicks the correct firmware entry point from a table contained in\nthe firmware image itself.\nThe original Freescale code also supports support for transfering\ndata to the internal SRAM which needs different entry points to\nthe firmware. Support for this is currently not implemented. Also,\nsupport for the ASRC (asymmetric sample rate converter) is skipped.\n\nI took a very simple approach to implement dmaengine support. Only\na single descriptor is statically assigned to a each channel. This\nmeans that transfers can\u0027t be queued up but only a single transfer\nis in progress. This simplifies implementation a lot and is sufficient\nfor the usual device/memory transfers.\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nReviewed-by: Linus Walleij \u003clinus.ml.walleij@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e8689e63d4d2046079f2db9d494ac05c6885ac0c", "tree": "29196d65697acc7fd49af9e00f2068413e29b771", "parents": [ "b30a3f6257ed2105259b404d419b4964e363928c" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Sep 28 15:57:37 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 29 16:13:51 2010 -0700" }, "message": "dmaengine: driver for the ARM PL080/PL081 PrimeCells v5\n\nThis creates a DMAengine driver for the ARM PL080/PL081 PrimeCells\nbased on the implementation earlier submitted by Peter Pearse.\nThis is working like a charm for memcpy and slave DMA to the PL011\nPrimeCell on the PB11MPCore.\n\nThis DMA controller is used in mostly unmodified form in the ARM\nRealView and Versatile platforms, in the ST-Ericsson Nomadik, and\nin the ST SPEAr platform.\n\nIt has been converted to use the header from the Samsung PL080\nderivate instead of its own defintions. The Samsungs have a custom\ndriver in their mach-* folders though, atleast we can share the\nregister definitions.\n\nCc: Peter Pearse \u003cpeter.pearse@arm.com\u003e\nCc: Ben Dooks \u003cben-linux@fluff.org\u003e\nCc: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nCc: Alessandro Rubini \u003crubini@unipv.it\u003e\nAcked-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\n[GFP_KERNEL to GFP_NOWAIT in pl08x_prep_dma_memcpy]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0b019a41553a919965bb02d07d54e3e6c57a796d", "tree": "6e329b4159b440d2aac5200a5c07103fe261c096", "parents": [ "5f6878b0d22f9b93f9698f88c335007e2a3c3bbc", "054d5c9238f3c577ad51195c3ee7803613f322cc" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Aug 10 23:17:52 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Aug 10 23:17:52 2010 +0100" }, "message": "Merge branches \u0027master\u0027 and \u0027devel\u0027 into for-linus\n\nConflicts:\n\tarch/arm/Kconfig\n\tarch/arm/mm/Kconfig\n" }, { "commit": "0c42bd0e425e9c8ddb7019fc446f7d915e36c5f6", "tree": "8d89f7b5907bed52847451ab37619e9516ed7c3c", "parents": [ "b3c567e474b5ba4447b6e16063a3b0cffc22d205" ], "author": { "name": "Yong Wang", "email": "yong.y.wang@linux.intel.com", "time": "Fri Jul 30 16:23:03 2010 +0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Aug 04 14:12:05 2010 -0700" }, "message": "dmaengine: Driver for Topcliff PCH DMA controller\n\nTopcliff PCH is the platform controller hub that is going to\nbe used in Intel\u0027s upcoming general embedded platforms. This\nadds the driver for Topcliff PCH DMA controller. The DMA\nchannels are strictly for device to host or host to device\ntransfers and cannot be used for generic memcpy.\n\nSigned-off-by: Yong Wang \u003cyong.y.wang@intel.com\u003e\n[kill GFP_ATOMIC, kill __raw_{read|write}l, locking fixlet]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b3c567e474b5ba4447b6e16063a3b0cffc22d205", "tree": "fa5f4f72fcf12dc53a5e58b5359038864595fe3e", "parents": [ "084a2ab9c258fb1efbb009f1bb1c6976da1f73f4" ], "author": { "name": "Vinod Koul", "email": "vinod.koul@intel.com", "time": "Wed Jul 21 13:28:10 2010 +0530" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 27 23:32:57 2010 -0700" }, "message": "intel_mid: Add Mrst \u0026 Mfld DMA Drivers\n\nThis patch add DMA drivers for DMA controllers in Langwell chipset\nof Intel(R) Moorestown platform and DMA controllers in Penwell of\nIntel(R) Medfield platfrom\n\nThis patch adds support for Moorestown DMAC1 and DMAC2 controllers.\nIt also add support for Medfiled GP DMA and DMAC1 controllers.\nThese controllers supports memory to peripheral and peripheral to\nmemory transfers. It support only single block transfers.\n\nThis driver is based on Kernel DMA engine\nAnyone who wishes to use this controller should use DMA engine APIs\n\nThis controller exposes DMA_SLAVE capabilities and notifies the client drivers\nof DMA transaction completion\n\nConfig option required to be enabled CONFIG_INTEL_MID_DMAC\u003dy\n\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d5b732b17ca2fc74f370bdba5aae6c804fac8c35", "tree": "4facc6d96116b032a3c1cb2ced9b2a3008e9216e", "parents": [ "eb6e8605ee5f5b4e116451bf01b3f35eac446dde", "67a3e12b05e055c0415c556a315a3d3eb637e29e" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon May 31 13:14:26 2010 +0900" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon May 31 13:14:26 2010 +0900" }, "message": "Merge branch \u0027master\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6\n" }, { "commit": "b3040e40675ec2c43542331cd30d4ee3dae797e8", "tree": "a327c4a92118dd0e1c61b8455e744910cd121f57", "parents": [ "6f68fbaafbaa033205cd131d3e1f3c4b914e9b78" ], "author": { "name": "Jassi Brar", "email": "jassi.brar@samsung.com", "time": "Sun May 23 20:28:19 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun May 23 20:28:19 2010 -0700" }, "message": "DMA: PL330: Add dma api driver\n\nAdd DMA Engine API driver for the PL330 DMAC.\nThis driver is supposed to be reusable by various\nplatforms that have one or more PL330 DMACs.\nAtm, DMA_SLAVE and DMA_MEMCPY capabilities have been\nimplemented.\n\nSigned-off-by: Jassi Brar \u003cjassi.brar@samsung.com\u003e\nReviewed-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\n[dan.j.williams@intel.com: missing slab.h and -\u003edevice_control() fixups]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1f782fee18b39b9ad438ebbd82c2915a16c879ee", "tree": "f292930065e6c860714c134790ab8882680ac739", "parents": [ "8eda2f21ed9c936a54fd7bc16cbfa5ee656635c2", "f4b87dee923342505e1ddba8d34ce9de33e75050" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon May 24 08:52:55 2010 +0900" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon May 24 08:52:55 2010 +0900" }, "message": "Merge branch \u0027master\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6\n" }, { "commit": "8d318a50b3d72e3daf94131f91e1ab799a8d5ad4", "tree": "ae36452931d2e836f725b3f91eebd7f4d9e27589", "parents": [ "6a3cd3ea48584d14f60dce0b3c4e9e4428beb0fe" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Mar 30 15:33:42 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Apr 14 14:49:20 2010 -0700" }, "message": "DMAENGINE: Support for ST-Ericssons DMA40 block v3\n\nThis is a straightforward driver for the ST-Ericsson DMA40 DMA\ncontroller found in U8500, implemented akin to the existing\nCOH 901 318 driver.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Srinidh Kasagar \u003csrinidhi.kasagar@stericsson.com\u003e\nCc: STEricsson_nomadik_linux@list.st.com\nCc: Alessandro Rubini \u003crubini@unipv.it\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "927a7c9c1793def3a55d60c926d3945528e6bf1b", "tree": "d7ea66aa528c619644522041a553ce64e0e3638e", "parents": [ "b2623a61cfd3c6badb8396dc85ab5a70f4a05f61" ], "author": { "name": "Magnus Damm", "email": "damm@opensource.se", "time": "Fri Mar 19 04:47:19 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Wed Apr 07 16:17:01 2010 +0900" }, "message": "dmaengine: shdma: Enable on SH-Mobile ARM\n\nEnable the shdma dmaengine driver on SH-Mobile ARM.\n\nSigned-off-by: Magnus Damm \u003cdamm@opensource.se\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "de5d4453c5b224eefd02b6a141ed411a76d458af", "tree": "2c208ec52e52363b1f403b82b570b843e98d1384", "parents": [ "84c8447c544bc7579097649273bc3f4e1b5de6af" ], "author": { "name": "Richard Röjfors", "email": "richard.rojfors@pelagicore.com", "time": "Thu Mar 25 19:44:21 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Mar 25 17:18:43 2010 -0700" }, "message": "dma: Add timb-dma\n\nAdds the support for the DMA engine withing the timberdale FPGA.\n\nThe DMA channels are strict device to host, or host to device\nand can not be used for generic memcpy.\n\nSigned-off-by: Richard Röjfors \u003crichard.rojfors@pelagicore.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0fb6f739bb612bc989d295056877374b749e721b", "tree": "a7105b3d73736535b3bdb0f15f8f8c0869b81279", "parents": [ "6c664a8915f5341c2e7f1df0bb4b9b4a88f6ad77" ], "author": { "name": "Piotr Ziecik", "email": "kosmo@semihalf.com", "time": "Fri Feb 05 03:42:52 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Mar 01 22:16:42 2010 -0700" }, "message": "dma: Add MPC512x DMA driver\n\nAdds initial version of MPC512x DMA driver.\nOnly memory to memory transfers are currenly supported.\n\nSigned-off-by: Piotr Ziecik \u003ckosmo@semihalf.com\u003e\nSigned-off-by: Wolfgang Denk \u003cwd@denx.de\u003e\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nCc: John Rigby \u003cjcrigby@gmail.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6c664a8915f5341c2e7f1df0bb4b9b4a88f6ad77", "tree": "031bab9e62b2948ef3fc8a0a3223e8074bc201bb", "parents": [ "f1acb878b6070941e844dfc4ca1b3b9e5a70426c" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Feb 09 22:34:54 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Mar 01 22:13:20 2010 -0700" }, "message": "Debugging options for the DMA engine subsystem\n\nThis adds Kconfig options for DEBUG and VERBOSE_DEBUG to the DMA\nengine subsystem, I got tired of editing the Makefile manually\neach time I want to debug things in here, modelled this on the\ndebug switches for other subsystems and works like a charm when\nworking on our DMA engines.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7949456b1b96924c2d9ae5aea5fa7d4c81c946ed", "tree": "819e64dcd686c8b53c698c164aea96a002e8b5f8", "parents": [ "60d9aa758c00f20ade0cb1951f6a934f628dd2d7", "12458ea06efd7b44281e68fe59c950ec7d59c649" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 16 10:28:56 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 16 10:28:56 2009 -0800" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n ppc440spe-adma: adds updated ppc440spe adma driver\n iop-adma.c: use resource_size()\n dmaengine: clarify the meaning of the DMA_CTRL_ACK flag\n sh: stylistic improvements for the DMA driver\n dmaengine: fix dmatest to verify minimum transfer length and test buffer size\n sh: DMA driver has to specify its alignment requirements\n Add COH 901 318 DMA block driver v5\n" }, { "commit": "12458ea06efd7b44281e68fe59c950ec7d59c649", "tree": "264df3c6fa054b7b866bb2eccca5f83e41044632", "parents": [ "2e032b62c4c8560d6416ad3cc925cfc2a5eafb07" ], "author": { "name": "Anatolij Gustschin", "email": "agust@denx.de", "time": "Fri Dec 11 21:24:44 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Dec 11 21:24:44 2009 -0700" }, "message": "ppc440spe-adma: adds updated ppc440spe adma driver\n\nThis patch adds new version of the PPC440SPe ADMA driver.\n\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e28edb723e64200554194da17617ee6e82de6690", "tree": "6116b7166054a17c9fbd94ade6db070d31c7c786", "parents": [ "2fc42814d8a9dd757abc7f80fbf11e9247e97d40", "01c62c9b32ec122bf5e3edeecec4d826cb8e81e5", "43234b1ef630388c2cffb34eeeaa84dd731602cc", "183bd50f4fe6cd49c1790a90163e3d1ece80f344", "50dcfa0234753c32e1c838cc0e6d7952dda73201", "045868df2c5eee2330c052f8237b428afa9394fd", "6635529987cd01f9af0c3996cf2e7b9e2bbb4aa7", "870725d9fcdecb23eab696d405fa90df46151865" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 05 10:35:18 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 05 10:35:18 2009 +0000" }, "message": "Merge branches \u0027at91\u0027, \u0027ep93xx\u0027, \u0027etm\u0027, \u0027ks8695\u0027, \u0027nuc\u0027, \u0027u300\u0027 and \u0027u8500\u0027 into devel\n" }, { "commit": "61f135b92f4758bc4d4767cd0a5d2da954e27f14", "tree": "388fdc08150e2f8fcb2859f70ca67cdd86616f36", "parents": [ "b419148e567728f6af0c3b01965c1cc141e3e13a" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Thu Nov 19 19:49:17 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:45:19 2009 -0700" }, "message": "Add COH 901 318 DMA block driver v5\n\nThis patch adds support for the ST-Ericsson COH 901 318 DMA block,\nfound in the U300 series platforms. It registers a DMA slave for\ndevice I/O and also a memcpy slave for memcpy.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7b3cc2b1fc2066391e498f3387204908c4eced21", "tree": "8a2bc28955710c580201046d04843773cb7d87a1", "parents": [ "4499a24dec00e037da7d09caccad45e7594a9c19" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "async_tx: build-time toggling of async_{syndrome,xor}_val dma support\n\nioat3.2 does not support asynchronous error notifications which makes\nthe driver experience latencies when non-zero pq validate results are\nexpected. Provide a mechanism for turning off async_xor_val and\nasync_syndrome_val via Kconfig. This approach is generally useful for\nany driver that specifies ASYNC_TX_DISABLE_CHANNEL_SWITCH and would like\nto force the async_tx api to fall back to the synchronous path for\ncertain operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "cd3abf98aeaec9b23a926159856b54a95707ee88", "tree": "c5d73254dce77c63e88ac9010322fbd1da032984", "parents": [ "f51f78c06c7fb442d304b93b68b3a1ebe3785a55" ], "author": { "name": "Yegor Yefremov", "email": "yegorslists@googlemail.com", "time": "Fri Oct 23 11:27:59 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Oct 25 16:00:34 2009 +0000" }, "message": "ARM: 5770/1: Add DMA Engine support to at91sam9g45\n\nAdd at91sam9g45 dependency to drivers/dma/Kconfig\n\nSigned-off-by: Yegor Yefremov \u003cyegorslists@googlemail.com\u003e\nAcked-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9a8de639f35ca3951b910d5e3a2f92f4cf3afc8f", "tree": "58d799166b6facdf25e314885ee7fadd20597482", "parents": [ "d8902adcc1a9fd484c8cb5e575152e32192c1ff8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 15:06:10 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:56:37 2009 -0700" }, "message": "async_tx: remove HIGHMEM64G restriction\n\nThis restriction prevented ASYNC_TX_DMA from being enabled on platform\nconfigurations where DMA address conversion could not be performed in\nplace on the stack. Since commit 04ce9ab3 (\"async_xor: permit callers\nto pass in a \u0027dma/page scribble\u0027 region\") the async_tx api now either\nuses a caller provided \u0027scribble\u0027 buffer, or performs the conversion in\nplace when sizeof(dma_addr_t) \u003c\u003d sizeof(struct page *).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d8902adcc1a9fd484c8cb5e575152e32192c1ff8", "tree": "305109ce60db5ea9710dddce9db8a23f65ff4572", "parents": [ "9134d02bc0af4a8747d448d1f811ec5f8eb96df6" ], "author": { "name": "Nobuhiro Iwamatsu", "email": "iwamatsu.nobuhiro@renesas.com", "time": "Mon Sep 07 03:26:23 2009 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:56:02 2009 -0700" }, "message": "dmaengine: sh: Add Support SuperH DMA Engine driver\n\nThis supported all DMA channels, and it was tested in SH7722,\nSH7780, SH7785 and SH7763.\nThis can not use with SH DMA API.\n\nSigned-off-by: Nobuhiro Iwamatsu \u003ciwamatsu.nobuhiro@renesas.com\u003e\nReviewed-by: Matt Fleming \u003cmatt@console-pimps.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bbb20089a3275a19e475dbc21320c3742e3ca423", "tree": "216fdc1cbef450ca688135c5b8969169482d9a48", "parents": [ "3e48e656903e9fd8bc805c6a2c4264d7808d315b", "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "message": "Merge branch \u0027dmaengine\u0027 into async-tx-next\n\nConflicts:\n\tcrypto/async_tx/async_xor.c\n\tdrivers/dma/ioat/dma_v2.h\n\tdrivers/dma/ioat/pci.c\n\tdrivers/md/raid5.c\n" }, { "commit": "138f4c359d23d2ec38d18bd70dd9613ae515fe93", "tree": "ad7fafba6eac74d9d92ade839a65171466d67a70", "parents": [ "0403e3827788d878163f9ef0541b748b0f88ca5d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "message": "dmaengine, async_tx: add a \"no channel switch\" allocator\n\nChannel switching is problematic for some dmaengine drivers as the\narchitecture precludes separating the -\u003eprep from -\u003esubmit. In these\ncases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify\nthe async_tx allocator to only return channels that support all of the\nrequired asynchronous operations.\n\nFor example MD_RAID456\u003dy selects support for asynchronous xor, xor\nvalidate, pq, pq validate, and memcpy. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dy any channel with all these\ncapabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to\nquickly locate compatible channels with the guarantee that dependency\nchains will remain on one channel. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dn async_tx_find_channel() may select\nchannels that lead to operation chains that need to cross channel\nboundaries using the async_tx channel switch capability.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a348a7e6fdbcd2d5192a09719a479bb238fde727", "tree": "5ff94185f4e5a810777469d7fe7832a8ec2d3430", "parents": [ "808347f6a31792079e345ec865e9cfcb6e8ae6b2", "28d0325ce6e0a52f53d8af687e6427fee59004d3" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 14:32:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 14:32:24 2009 -0700" }, "message": "Merge commit \u0027v2.6.31-rc1\u0027 into dmaengine\n" }, { "commit": "dc78baa2b90b289590911b40b6800f77d0dc935a", "tree": "db54dedb1e13a413190ad637ccaf6f5557dc9c10", "parents": [ "f1aef8b6e6abf32a3a269542f95a19e2cb319f6c" ], "author": { "name": "Nicolas Ferre", "email": "nicolas.ferre@atmel.com", "time": "Fri Jul 03 19:24:33 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 22 22:41:27 2009 -0700" }, "message": "dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller\n\nThis AHB DMA Controller (aka HDMA or DMAC on AT91 systems) is availlable on\nat91sam9rl chip. It will be used on other products in the future.\n\nThis first release covers only the memory-to-memory tranfer type. This is the\nonly tranfer type supported by this chip. On other products, it will be used\nalso for peripheral DMA transfer (slave API support to come).\n\nI used dmatest client without problem in different configurations to test it.\n\nFull documentation for this controller can be found in the SAM9RL datasheet:\nhttp://www.atmel.com/dyn/products/product_card.asp?part_id\u003d4243\n\nSigned-off-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "daf4219dbcbb2efcd638fcd3c29a622e1c18cc38", "tree": "8683d86a8a8de2060c83aed7efe5f66b94027a2b", "parents": [ "43a1a3ed6bf5a1b9ae197b4f5f20033baf19db61" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 01 16:12:53 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 01 16:12:53 2009 -0700" }, "message": "dmaengine: move HIGHMEM64G restriction to ASYNC_TX_DMA\n\nOn HIGHMEM64G systems dma_addr_t is known to be larger than (void *)\nwhich precludes async_xor from performing dma address conversions by\nreusing the input parameter address list. However, other parts of the\ndmaengine infrastructure do not suffer this constraint, so the\nHIGHMEM64G restriction can be down-levelled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "ea76f0b3759283ec3cc06c86e266bf0fa6a981d2", "tree": "36719ab69e7d94cc59c909526022219376807313", "parents": [ "a43da03ca4719276b9601730627d20b2a71fb6ba" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Thu Apr 23 00:40:30 2009 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Jun 17 11:06:25 2009 +0100" }, "message": "DMA: TXx9 Soc DMA Controller driver\n\nThis patch adds support for the integrated DMAC of the TXx9 family.\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "04ce9ab385dc97eb55299d533cd3af79b8fc7529", "tree": "9b8d0b9c1eba820a8a107d05abc2e2f8d4d20a59", "parents": [ "a08abd8ca890a377521d65d493d174bebcaf694b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jun 03 14:22:28 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jun 03 14:22:28 2009 -0700" }, "message": "async_xor: permit callers to pass in a \u0027dma/page scribble\u0027 region\n\nasync_xor() needs space to perform dma and page address conversions. In\nmost cases the code can simply reuse the struct page * array because the\nsize of the native pointer matches the size of a dma/page address. In\norder to support archs where sizeof(dma_addr_t) is larger than\nsizeof(struct page *), or to preserve the input parameters, we utilize a\nmemory region passed in by the caller.\n\nSince the code is now prepared to handle the case where it cannot\nperform address conversions on the stack, we no longer need the\n!HIGHMEM64G dependency in drivers/dma/Kconfig.\n\n[ Impact: don\u0027t clobber input buffers for address conversions ]\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "729b5d1b8ec72c28e99840b3f300ba67726e3ab9", "tree": "8eac6444ea80bf05f461eb77243f56b008ee5083", "parents": [ "06164f3194e01ea4c76941ac60f541d656c8975f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:25 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:25 2009 -0700" }, "message": "dmaengine: allow dma support for async_tx to be toggled\n\nProvide a config option for blocking the allocation of dma channels to\nthe async_tx api.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5296b56d1b2000b60fb966be161c1f8fb629786b", "tree": "18277748caa9ba43610f76a310d34a3b2155e1a5", "parents": [ "ef560682a97491f62ef538931a4861b57d66c52c" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Mon Jan 19 15:36:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 19 15:36:21 2009 -0700" }, "message": "i.MX31: Image Processing Unit DMA and IRQ drivers\n\ni.MX3x SoCs contain an Image Processing Unit, consisting of a Control\nModule (CM), Display Interface (DI), Synchronous Display Controller (SDC),\nAsynchronous Display Controller (ADC), Image Converter (IC), Post-Filter\n(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).\nCM contains, among other blocks, an Interrupt Generator (IG) and a Clock\nand Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are\nsupported over dmaengine and irq-chip APIs respectively.\n\nIDMAC is a specialised DMA controller, its DMA channels cannot be used for\ngeneral-purpose operations, even though it might be possible to configure\na memory-to-memory channel for memcpy operation. This driver will not work\nwith generic dmaengine clients, clients, wishing to use it must use\nrespective wrapper structures, they also must specify which channels they\nrequire, as channels are hard-wired to specific IPU functions.\n\nAcked-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "07f2211e4fbce6990722d78c4f04225da9c0e9cf", "tree": "51934e20a334e93c8c399d2e6375f264551e9bc3", "parents": [ "28405d8d9ce05f5bd869ef8b48da5086f9527d73" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 05 17:14:31 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 05 18:10:19 2009 -0700" }, "message": "dmaengine: remove dependency on async_tx\n\nasync_tx.ko is a consumer of dma channels. A circular dependency arises\nif modules in drivers/dma rely on common code in async_tx.ko. It\nprevents either module from being unloaded.\n\nMove dma_wait_for_async_tx and async_tx_run_dependencies to dmaeninge.o\nwhere they should have been from the beginning.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "77cd62e8082b9743b59ee1946a4c3ee2e3cd2bce", "tree": "8fe08914499988f47f51e74395522e5862b0c31d", "parents": [ "59f647c25a4f27c1e5c84710e0608b36303089f9" ], "author": { "name": "Timur Tabi", "email": "timur@freescale.com", "time": "Fri Sep 26 17:00:11 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Sep 26 17:00:11 2008 -0700" }, "message": "fsldma: allow Freescale Elo DMA driver to be compiled as a module\n\nModify the Freescale Elo / Elo Plus DMA driver so that it can be compiled as\na module.\n\nThe primary change is to stop treating the DMA controller as a bus, and the\nDMA channels as devices on the bus. This is because the Open Firmware (OF)\nkernel code does not allow busses to be removed, so although we can call\nof_platform_bus_probe() to probe the DMA channels, there is no\nof_platform_bus_remove(). Instead, the DMA channels are manually probed,\nsimilar to what fsl_elbc_nand.c does.\n\nCc: Scott Wood \u003cscottwood@freescale.com\u003e\nAcked-by: Li Yang \u003cleoli@freescale.com\u003e\nSigned-off-by: Timur Tabi \u003ctimur@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "3bfb1d20b547a5071d01344581eac5846ea84491", "tree": "3cdbd3b5d59c93f257573cc894db2a000698f02b", "parents": [ "dc0ee6435cb92ccc81b14ff28d163fecc5a7f120" ], "author": { "name": "Haavard Skinnemoen", "email": "haavard.skinnemoen@atmel.com", "time": "Tue Jul 08 11:59:42 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:59:42 2008 -0700" }, "message": "dmaengine: Driver for the Synopsys DesignWare DMA controller\n\nThis adds a driver for the Synopsys DesignWare DMA controller (aka\nDMACA on AVR32 systems.) This DMA controller can be found integrated\non the AT32AP7000 chip and is primarily meant for peripheral DMA\ntransfer, but can also be used for memory-to-memory transfers.\n\nThis patch is based on a driver from David Brownell which was based on\nan older version of the DMA Engine framework. It also implements the\nproposed extensions to the DMA Engine API for slave DMA operations.\n\nThe dmatest client shows no problems, but there may still be room for\nimprovement performance-wise. DMA slave transfer performance is\ndefinitely \"good enough\"; reading 100 MiB from an SD card running at ~20\nMHz yields ~7.2 MiB/s average transfer rate.\n\nFull documentation for this controller can be found in the Synopsys\nDW AHB DMAC Databook:\n\nhttp://www.synopsys.com/designware/docs/iip/DW_ahb_dmac/latest/doc/dw_ahb_dmac_db.pdf\n\nThe controller has lots of implementation options, so it\u0027s usually a\ngood idea to check the data sheet of the chip it\u0027s intergrated on as\nwell. The AT32AP7000 data sheet can be found here:\n\nhttp://www.atmel.com/dyn/products/datasheets.asp?family_id\u003d682\n\n\nChanges since v4:\n * Use client_count instead of dma_chan_is_in_use()\n * Add missing include\n * Unmap buffers unless client told us not to\n\nChanges since v3:\n * Update to latest DMA engine and DMA slave APIs\n * Embed the hw descriptor into the sw descriptor\n * Clean up and update MODULE_DESCRIPTION, copyright date, etc.\n\nChanges since v2:\n * Dequeue all pending transfers in terminate_all()\n * Rename dw_dmac.h -\u003e dw_dmac_regs.h\n * Define and use controller-specific dma_slave data\n * Fix up a few outdated comments\n * Define hardware registers as structs (doesn\u0027t generate better\n code, unfortunately, but it looks nicer.)\n * Get number of channels from platform_data instead of hardcoding it\n based on CONFIG_WHATEVER_CPU.\n * Give slave clients exclusive access to the channel\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e,\nSigned-off-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "4a776f0aa922a552460192c07b56f4fe9cd82632", "tree": "ae6c2fef63e40fcdcac22483f3aa35eab95e64de", "parents": [ "ff7b04796d9866327ea76e1393f1e902ef032f84" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Tue Jul 08 11:58:45 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:58:45 2008 -0700" }, "message": "dmatest: Simple DMA memcpy test client\n\nThis client tests DMA memcpy using various lengths and various offsets\ninto the source and destination buffers. It will initialize both\nbuffers with a repeatable pattern and verify that the DMA engine copies\nthe requested region and nothing more. It will also verify that the\nbytes aren\u0027t swapped around, and that the source buffer isn\u0027t modified.\n\nThe dmatest module can be configured to test a specific device, a\nspecific channel. It can also test multiple channels at the same time,\nand it can start multiple threads competing for the same channel.\n\nChanges since v2:\n * Support testing multiple channels at the same time\n * Support testing with multiple threads competing for the same channel\n * Use counting test patterns in order to catch byte ordering issues\n\nChanges since v1:\n * Remove extra dashes around \"help\"\n * Remove \"default n\" from Kconfig\n * Turn TEST_BUF_SIZE into a module parameter\n * Return DMA_NAK instead of DMA_DUP\n * Print unhandled events\n * Support testing specific channels and devices\n * Move to the end of the Makefile\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ff7b04796d9866327ea76e1393f1e902ef032f84", "tree": "42fd30c8e2051e7c6acc15da363960647030d3d3", "parents": [ "ebabe2762607147d28aa395ea6df2a0ee7f795a1" ], "author": { "name": "Saeed Bishara", "email": "saeed@marvell.com", "time": "Tue Jul 08 11:58:36 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:58:36 2008 -0700" }, "message": "dmaengine: DMA engine driver for Marvell XOR engine\n\nThe XOR engine found in Marvell\u0027s SoCs and system controllers\nprovides XOR and DMA operation, iSCSI CRC32C calculation, memory\ninitialization, and memory ECC error cleanup operation support.\n\nThis driver implements the DMA engine API and supports the following\ncapabilities:\n- memcpy\n- xor\n- memset\n\nThe XOR engine can be used by DMA engine clients implemented in the\nkernel, one of those clients is the RAID module. In that case, I\nobserved 20% improvement in the raid5 write throughput, and 40%\ndecrease in the CPU utilization when doing array construction, those\nresults obtained on an 5182 running at 500Mhz.\n\nWhen enabling the NET DMA client, the performance decreased, so\nmeanwhile it is recommended to keep this client off.\n\nSigned-off-by: Saeed Bishara \u003csaeed@marvell.com\u003e\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9c402f4e196290692d998b188f9094deb1619e57", "tree": "d61209d265890e20d8d2933e88fb58c8075454ac", "parents": [ "1099dc79245719c046e632212ec09d6ec1154ef5" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jun 27 01:21:11 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:58:12 2008 -0700" }, "message": "dmaengine: remove arch dependency from DMADEVICES\n\nThe dependency is redundant since all drivers set their specific arch\ndependencies. The NET_DMA option is modified to be enabled only on platforms\nwhere it is known to have a positive effect. HAS_DMA is added as an explicit\ndependency for the DMADEVICES menu.\n\nAcked-by: Adrian Bunk \u003cbunk@kernel.org\u003e\nAcked-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "411e23dbe9c5867045f34ba83ee84b31b5b9950c", "tree": "bbdf0ce4244c52e1256082711da17c8775a2f48f", "parents": [ "4b119e21d0c66c22e8ca03df05d9de623d0eb50f" ], "author": { "name": "Zhang Wei", "email": "wei.zhang@freescale.com", "time": "Thu Apr 17 20:17:25 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 13:22:15 2008 -0700" }, "message": "fsldma: Remove CONFIG_FSL_DMA_SELFTEST, keep fsl_dma_self_test() running always.\n\nAlways enabling the fsl_dma_self_test() to ensure the DMA controller\nshould works well after the driver probed.\n\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "173acc7ce8538f1f3040791dc622a92aadc12cf4", "tree": "f408e415851cf3343af6077287984169958951ad", "parents": [ "976dde010e513a9c7c3117a32b7b015f84b37430" ], "author": { "name": "Zhang Wei", "email": "wei.zhang@freescale.com", "time": "Sat Mar 01 07:42:48 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Mar 04 10:16:46 2008 -0700" }, "message": "dmaengine: add driver for Freescale MPC85xx DMA controller\n\nThe driver implements DMA engine API for Freescale MPC85xx DMA controller,\nwhich could be used by devices in the silicon. The driver supports the\nBasic mode of Freescale MPC85xx DMA controller. The MPC85xx processors\nsupported include MPC8540/60, MPC8555, MPC8548, MPC8641 and so on.\n\nThe MPC83xx(MPC8349, MPC8360) are also supported.\n\n[kamalesh@linux.vnet.ibm.com: build fix]\n[dan.j.williams@intel.com: merge mm fixes, rebase on async_tx-2.6.25]\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by: Ebony Zhu \u003cebony.zhu@freescale.com\u003e\nAcked-by: Kumar Gala \u003cgalak@gate.crashing.org\u003e\nCc: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Paul Mackerras \u003cpaulus@samba.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0036731c88fdb5bf4f04a796a30b5e445fc57f54", "tree": "66982e4a9fdb92fedadca35c0ccaa0b9a75e9d2e", "parents": [ "d909b347591a23c5a2c324fbccd4c9c966f31c67" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Feb 02 19:49:57 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 06 10:12:17 2008 -0700" }, "message": "async_tx: kill tx_set_src and tx_set_dest methods\n\nThe tx_set_src and tx_set_dest methods were originally implemented to allow\nan array of addresses to be passed down from async_xor to the dmaengine\ndriver while minimizing stack overhead. Removing these methods allows\ndrivers to have all transaction parameters available at \u0027prep\u0027 time, saves\ntwo function pointers in struct dma_async_tx_descriptor, and reduces the\nnumber of indirect branches..\n\nA consequence of moving this data to the \u0027prep\u0027 routine is that\nmulti-source routines like async_xor need temporary storage to convert an\narray of linear addresses into an array of dma addresses. In order to keep\nthe same stack footprint of the previous implementation the input array is\nreused as storage for the dma addresses. This requires that\nsizeof(dma_addr_t) be less than or equal to sizeof(void *). As a\nconsequence CONFIG_DMADEVICES now depends on !CONFIG_HIGHMEM64G. It also\nrequires that drivers be able to make descriptor resources available when\nthe \u0027prep\u0027 routine is polled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\n" }, { "commit": "6d4f5879b6f4da50bde94e1cae73755978ed048f", "tree": "149340866e3a7d65fca49763ce7caa56ada370c4", "parents": [ "e593f070b40887dc0415646a4c0720eb8630c722" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Wed Nov 28 16:21:43 2007 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Thu Nov 29 09:24:53 2007 -0800" }, "message": "dmaengine: correct invalid assumptions in the Kconfig text\n\nThis patch corrects recently changed (and now invalid) Kconfig descriptions\nfor the DMA engine framework:\n\n - Non-Intel(R) hardware also has DMA engines;\n - DMA is used for more than memcpy and RAID offloading.\n\nIn fact, on most platforms memcpy and RAID aren\u0027t factors, and DMA\nexists so that peripherals can transfer data to/from memory while\nthe CPU does other work.\n\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nSigned-off-by: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "4138f08d1c2783a28df2af6ed81aa180462ec374", "tree": "11b9d3b4cbafe4c9d1dd7c9b7ef934dee2bafdb4", "parents": [ "bc2a3f86f46569fb091792867ce67c9ab24dfd0f" ], "author": { "name": "Andi Kleen", "email": "ak@suse.de", "time": "Mon Oct 29 14:37:18 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Tue Oct 30 08:06:55 2007 -0700" }, "message": "Remove bogus default y for DMAR and NET_DMA\n\nNo reason I can think of of making them default y Most people don\u0027t have\nthe hardware and with default y they just pollute lots of configs during\nmake oldconfig.\n\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nAcked-by: Jeff Garzik \u003cjeff@garzik.org\u003e\nAcked-by: \"Nelson, Shannon\" \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "2ed6dc34f9ed39bb8e4c81ea1056f0ba56315841", "tree": "e3f6ca7961f9c4e34453d06e584c0bc98ec630d7", "parents": [ "7589670f37736bcc119ebfbd69aafea6d585d1d4" ], "author": { "name": "Shannon Nelson", "email": "shannon.nelson@intel.com", "time": "Tue Oct 16 01:27:42 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Tue Oct 16 09:43:09 2007 -0700" }, "message": "I/OAT: Add DCA services\n\nAdd code to connect to the DCA driver and provide cpu tags for use by\ndrivers that would like to use Direct Cache Access hints.\n\n [Adrian Bunk] Several Kconfig cleanup items\n [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when\n\t\t\t built for uni-processor\n\nSigned-off-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "1b0fac45878bb88759eec347c273285195649ff7", "tree": "a9871a47ef98c90bac3f65a7f9309e87420c694c", "parents": [ "9e7bf24b1b979db256ddc84d0d4ac6040d706da6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Jul 15 23:40:26 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Jul 16 09:05:45 2007 -0700" }, "message": "dma-mapping: prevent dma dependent code from linking on !HAS_DMA archs\n\nContinuing the work started in 411f0f3edc141a582190d3605cadd1d993abb6df ...\n\nThis enables code with a dma path, that compiles away, to build without\nrequiring additional code factoring. It also prevents code that calls\ndma_alloc_coherent and dma_free_coherent from linking whereas previously\nthe code would hit a BUG() at run time. Finally, it allows archs that set\n!HAS_DMA to delete their asm/dma-mapping.h file.\n\nCc: Cornelia Huck \u003ccornelia.huck@de.ibm.com\u003e\nCc: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\nCc: Heiko Carstens \u003cheiko.carstens@de.ibm.com\u003e\nCc: John W. Linville \u003clinville@tuxdriver.com\u003e\nCc: Kyle McMartin \u003ckyle@parisc-linux.org\u003e\nCc: James Bottomley \u003cJames.Bottomley@SteelEye.com\u003e\nCc: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Jeff Garzik \u003cjeff@garzik.org\u003e\nCc: \u003cgeert@linux-m68k.org\u003e\nCc: \u003czippel@linux-m68k.org\u003e\nCc: \u003cspyro@f2s.com\u003e\nCc: \u003cysato@users.sourceforge.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "c211092313b90f898dec61f35207fc282d1eadc3", "tree": "30df0c81f207d0babb3fe56a17419f37e71e973a", "parents": [ "f6dff381af01006ffae3c23cd2e07e30584de0ec" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 02 13:52:26 2007 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 13 08:06:18 2007 -0700" }, "message": "dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines\n\nThe Intel(R) IOP series of i/o processors integrate an Xscale core with\nraid acceleration engines. The capabilities per platform are:\n\niop219:\n (2) copy engines\niop321:\n (2) copy engines\n (1) xor and block fill engine\niop33x:\n (2) copy and crc32c engines\n (1) xor, xor zero sum, pq, pq zero sum, and block fill engine\niop34x (iop13xx):\n (2) copy, crc32c, xor, xor zero sum, and block fill engines\n (1) copy, crc32c, xor, xor zero sum, pq, pq zero sum, and block fill engine\n\nThe driver supports the features of the async_tx api:\n* asynchronous notification of operation completion\n* implicit (interupt triggered) handling of inter-channel transaction\n dependencies\n\nThe driver adapts to the platform it is running by two methods.\n1/ #include \u003casm/arch/adma.h\u003e which defines the hardware specific\n iop_chan_* and iop_desc_* routines as a series of static inline\n functions\n2/ The private platform data attached to the platform_device defines the\n capabilities of the channels\n\n20070626: Callbacks are run in a tasklet. Given the recent discussion on\nLKML about killing tasklets in favor of workqueues I did a quick conversion\nof the driver. Raid5 resync performance dropped from 50MB/s to 30MB/s, so\nthe tasklet implementation remains until a generic softirq interface is\navailable.\n\nChangelog:\n* fixed a slot allocation bug in do_iop13xx_adma_xor that caused too few\nslots to be requested eventually leading to data corruption\n* enabled the slot allocation routine to attempt to free slots before\nreturning -ENOMEM\n* switched the cleanup routine to solely use the software chain and the\nstatus register to determine if a descriptor is complete. This is\nnecessary to support other IOP engines that do not have status writeback\ncapability\n* make the driver iop generic\n* modified the allocation routines to understand allocating a group of\nslots for a single operation\n* added a null xor initialization operation for the xor only channel on\niop3xx\n* support xor operations on buffers larger than the hardware maximum\n* split the do_* routines into separate prep, src/dest set, submit stages\n* added async_tx support (dependent operations initiation at cleanup time)\n* simplified group handling\n* added interrupt support (callbacks via tasklets)\n* brought the pending depth inline with ioat (i.e. 4 descriptors)\n* drop dma mapping methods, suggested by Chris Leech\n* don\u0027t use inline in C files, Adrian Bunk\n* remove static tasklet declarations\n* make iop_adma_alloc_slots easier to read and remove chances for a\n corrupted descriptor chain\n* fix locking bug in iop_adma_alloc_chan_resources, Benjamin Herrenschmidt\n* convert capabilities over to dma_cap_mask_t\n* fixup sparse warnings\n* add descriptor flush before iop_chan_enable\n* checkpatch.pl fixes\n* gpl v2 only correction\n* move set_src, set_dest, submit to async_tx methods\n* move group_list and phys to async_tx\n\nCc: Russell King \u003crmk@arm.linux.org.uk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9bc89cd82d6f88fb0ca39b30445c329a430fd66b", "tree": "7bd0e856abd359f84edea1bacfd1dd32edd93fbb", "parents": [ "685784aaf3cd0e3ff5e36c7ecf6f441cdbf57f73" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 02 11:10:44 2007 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 13 08:06:14 2007 -0700" }, "message": "async_tx: add the async_tx api\n\nThe async_tx api provides methods for describing a chain of asynchronous\nbulk memory transfers/transforms with support for inter-transactional\ndependencies. It is implemented as a dmaengine client that smooths over\nthe details of different hardware offload engine implementations. Code\nthat is written to the api can optimize for asynchronous operation and the\napi will fit the chain of operations to the available offload resources. \n \n\tI imagine that any piece of ADMA hardware would register with the\n\t\u0027async_*\u0027 subsystem, and a call to async_X would be routed as\n\tappropriate, or be run in-line. - Neil Brown\n\nasync_tx exploits the capabilities of struct dma_async_tx_descriptor to\nprovide an api of the following general format:\n\nstruct dma_async_tx_descriptor *\nasync_\u003coperation\u003e(..., struct dma_async_tx_descriptor *depend_tx,\n\t\t\tdma_async_tx_callback cb_fn, void *cb_param)\n{\n\tstruct dma_chan *chan \u003d async_tx_find_channel(depend_tx, \u003coperation\u003e);\n\tstruct dma_device *device \u003d chan ? chan-\u003edevice : NULL;\n\tint int_en \u003d cb_fn ? 1 : 0;\n\tstruct dma_async_tx_descriptor *tx \u003d device ?\n\t\tdevice-\u003edevice_prep_dma_\u003coperation\u003e(chan, len, int_en) : NULL;\n\n\tif (tx) { /* run \u003coperation\u003e asynchronously */\n\t\t...\n\t\ttx-\u003etx_set_dest(addr, tx, index);\n\t\t...\n\t\ttx-\u003etx_set_src(addr, tx, index);\n\t\t...\n\t\tasync_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);\n\t} else { /* run \u003coperation\u003e synchronously */\n\t\t...\n\t\t\u003coperation\u003e\n\t\t...\n\t\tasync_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);\n\t}\n\n\treturn tx;\n}\n\nasync_tx_find_channel() returns a capable channel from its pool. The\nchannel pool is organized as a per-cpu array of channel pointers. The\nasync_tx_rebalance() routine is tasked with managing these arrays. In the\nuniprocessor case async_tx_rebalance() tries to spread responsibility\nevenly over channels of similar capabilities. For example if there are two\ncopy+xor channels, one will handle copy operations and the other will\nhandle xor. In the SMP case async_tx_rebalance() attempts to spread the\noperations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor\nchannel0 while cpu1 gets copy channel 1 and xor channel 1. When a\ndependency is specified async_tx_find_channel defaults to keeping the\noperation on the same channel. A xor-\u003ecopy-\u003exor chain will stay on one\nchannel if it supports both operation types, otherwise the transaction will\ntransition between a copy and a xor resource.\n\nCurrently the raid5 implementation in the MD raid456 driver has been\nconverted to the async_tx api. A driver for the offload engines on the\nIntel Xscale series of I/O processors, iop-adma, is provided in a later\ncommit. With the iop-adma driver and async_tx, raid456 is able to offload\ncopy, xor, and xor-zero-sum operations to hardware engines.\n \nOn iop342 tiobench showed higher throughput for sequential writes (20 - 30%\nimprovement) and sequential reads to a degraded array (40 - 55%\nimprovement). For the other cases performance was roughly equal, +/- a few\npercentage points. On a x86-smp platform the performance of the async_tx\nimplementation (in synchronous mode) was also +/- a few percentage points\nof the original implementation. According to \u0027top\u0027 on iop342 CPU\nutilization drops from ~50% to ~15% during a \u0027resync\u0027 while the speed\naccording to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.\n \nThe tiobench command line used for testing was: tiobench --size 2048\n--block 4096 --block 131072 --dir /mnt/raid --numruns 5\n* iop342 had 1GB of memory available\n\nDetails:\n* if CONFIG_DMA_ENGINE\u003dn the asynchronous path is compiled away by making\n async_tx_find_channel a static inline routine that always returns NULL\n* when a callback is specified for a given transaction an interrupt will\n fire at operation completion time and the callback will occur in a\n tasklet. if the the channel does not support interrupts then a live\n polling wait will be performed\n* the api is written as a dmaengine client that requests all available\n channels\n* In support of dependencies the api implicitly schedules channel-switch\n interrupts. The interrupt triggers the cleanup tasklet which causes\n pending operations to be scheduled on the next channel\n* Xor engines treat an xor destination address differently than a software\n xor routine. To the software routine the destination address is an implied\n source, whereas engines treat it as a write-only destination. This patch\n modifies the xor_blocks routine to take a an explicit destination address\n to mirror the hardware.\n\nChangelog:\n* fixed a leftover debug print\n* don\u0027t allow callbacks in async_interrupt_cond\n* fixed xor_block changes\n* fixed usage of ASYNC_TX_XOR_DROP_DEST\n* drop dma mapping methods, suggested by Chris Leech\n* printk warning fixups from Andrew Morton\n* don\u0027t use inline in C files, Adrian Bunk\n* select the API when MD is enabled\n* BUG_ON xor source counts \u003c\u003d 1\n* implicitly handle hardware concerns like channel switching and\n interrupts, Neil Brown\n* remove the per operation type list, and distribute operation capabilities\n evenly amongst the available channels\n* simplify async_tx_find_channel to optimize the fast path\n* introduce the channel_table_initialized flag to prevent early calls to\n the api\n* reorganize the code to mimic crypto\n* include mm.h as not all archs include it in dma-mapping.h\n* make the Kconfig options non-user visible, Adrian Bunk\n* move async_tx under crypto since it is meant as \u0027core\u0027 functionality, and\n the two may share algorithms in the future\n* move large inline functions into c files\n* checkpatch.pl fixes\n* gpl v2 only correction\n\nCc: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-By: NeilBrown \u003cneilb@suse.de\u003e\n" }, { "commit": "9556fb73edfc37410cab3b47ae5e94bcecd8edf2", "tree": "dbe5fed3ab9f58f8ab804cb3f243b9259867cf3f", "parents": [ "e25df1205f37c7bff3ab14fdfc8a5249f3c69c82" ], "author": { "name": "Martin Schwidefsky", "email": "schwidefsky@de.ibm.com", "time": "Thu May 10 15:45:58 2007 +0200" }, "committer": { "name": "Martin Schwidefsky", "email": "schwidefsky@de.ibm.com", "time": "Thu May 10 15:46:07 2007 +0200" }, "message": "[S390] Kconfig: unwanted menus for s390.\n\nDisable some more menus in the configuration files that are of no\ninterest to a s390 machine.\n\nSigned-off-by: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\n" }, { "commit": "db21733488f84a596faaad0d05430b3f51804692", "tree": "a2c1f6d39ce27d2e86b395f2bf536c1ab7396411", "parents": [ "57c651f74cd8383df10a648e677902849de1bc0b" ], "author": { "name": "Chris Leech", "email": "christopher.leech@intel.com", "time": "Sat Jun 17 21:24:58 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Jun 17 21:24:58 2006 -0700" }, "message": "[I/OAT]: Setup the networking subsystem as a DMA client\n\nAttempts to allocate per-CPU DMA channels\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "0bbd5f4e97ff9c057b385a1886b4aed1fb0300f1", "tree": "0c3d8528c31e8291fb78c2e7a287910987ed2888", "parents": [ "c13c8260da3155f2cefb63b0d1b7dcdcb405c644" ], "author": { "name": "Chris Leech", "email": "christopher.leech@intel.com", "time": "Tue May 23 17:35:34 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Jun 17 21:18:46 2006 -0700" }, "message": "[I/OAT]: Driver for the Intel(R) I/OAT DMA engine\n\nAdds a new ioatdma driver\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c13c8260da3155f2cefb63b0d1b7dcdcb405c644", "tree": "ecfe02fa44a423a948f5fb5ad76497da2bb7a402", "parents": [ "427abfa28afedffadfca9dd8b067eb6d36bac53f" ], "author": { "name": "Chris Leech", "email": "christopher.leech@intel.com", "time": "Tue May 23 17:18:44 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Jun 17 21:18:43 2006 -0700" }, "message": "[I/OAT]: DMA memcpy subsystem\n\nProvides an API for offloading memory copies to DMA devices\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" } ] }