)]}' { "log": [ { "commit": "86ef5c9a8edd78e6bf92879f32329d89b2d55b5a", "tree": "7bf46885326a6fdbb0c3596855408e9a5634dd3a", "parents": [ "d221938c049f4845da13c8593132595a6b9222a8" ], "author": { "name": "Gautham R Shenoy", "email": "ego@in.ibm.com", "time": "Fri Jan 25 21:08:02 2008 +0100" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Fri Jan 25 21:08:02 2008 +0100" }, "message": "cpu-hotplug: replace lock_cpu_hotplug() with get_online_cpus()\n\nReplace all lock_cpu_hotplug/unlock_cpu_hotplug from the kernel and use\nget_online_cpus and put_online_cpus instead as it highlights the\nrefcount semantics in these operations.\n\nThe new API guarantees protection against the cpu-hotplug operation, but\nit doesn\u0027t guarantee serialized access to any of the local data\nstructures. Hence the changes needs to be reviewed.\n\nIn case of pseries_add_processor/pseries_remove_processor, use\ncpu_maps_update_begin()/cpu_maps_update_done() as we\u0027re modifying the\ncpu_present_map there.\n\nSigned-off-by: Gautham R Shenoy \u003cego@in.ibm.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "af5ca3f4ec5cc4432a42a73b050dd8898ce8fd00", "tree": "3e5a3081b2802547f10da72c0026b4929d0e287b", "parents": [ "528a4bf1d5ffed310d26fc1d82d45c02949f71cf" ], "author": { "name": "Kay Sievers", "email": "kay.sievers@vrfy.org", "time": "Thu Dec 20 02:09:39 2007 +0100" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Thu Jan 24 20:40:40 2008 -0800" }, "message": "Driver core: change sysdev classes to use dynamic kobject names\n\nAll kobjects require a dynamically allocated name now. We no longer\nneed to keep track if the name is statically assigned, we can just\nunconditionally free() all kobject names on cleanup.\n\nSigned-off-by: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "06675e6f4fb00a63575f4b85da305c3ab19e6e5d", "tree": "44de5812ffda9fa328c201efca743c7d14e9bd57", "parents": [ "0487de91427925e7c43debeb948bdf53b10ef32c" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Sat Jan 19 01:15:52 2008 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 22 00:35:23 2008 +0000" }, "message": "tc35815: Use irq number for tc35815-mac platform device id\n\nThe tc35815-mac platform device used a pci bus number and a devfn to\nidentify its target device, but the pci bus number may vary if some\nbus-bridges are found. Use irq number which is be unique for embedded\ncontrollers.\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "0487de91427925e7c43debeb948bdf53b10ef32c", "tree": "e911ecd1291b7ac0c7fe85d1a28102a07e150f21", "parents": [ "c2a04c4f0e1b09b58d7279e2facd306c40583ec1" ], "author": { "name": "Dmitri Vorobiev", "email": "dmitri.vorobiev@gmail.com", "time": "Tue Jan 15 00:27:46 2008 +0300" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 22 00:35:23 2008 +0000" }, "message": "[MIPS] Malta: Fix reading the PCI clock frequency on big-endian\n\nThe JMPRS register on Malta boards keeps a 32-bit CPU-endian\nvalue. The readw() function assumes that the value it reads is a\nlittle-endian 16-bit number. Therefore, using readw() to obtain\nthe value of the JMPRS register is a mistake. This error leads\nto incorrect reading of the PCI clock frequency on big-endian\nduring board start-up.\n\nChange readw() to __raw_readl().\n\nThis was tested by injecting a call to printk() and verifying\nthat the value of the jmpr variable was consistent with current\nsetting of the JP4 \"PCI CLK\" jumper.\n\nSigned-off-by: Dmitri Vorobiev \u003cdmitri.vorobiev@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c60ecec67ab3f6b5791ef49d502b7a61909aa13e", "tree": "e8180ad2ec48a6063277ee51cf10dc8541dcac2f", "parents": [ "c23f72cae9523d29ff94eec8f30ccbdaf234b20e", "2e4f95822cc17cb7095d50babe2d2fc4c043fa25" ], "author": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Jan 14 21:25:39 2008 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Jan 14 21:25:39 2008 -0800" }, "message": "Merge branch \u0027upstream\u0027 of git://ftp.linux-mips.org/pub/scm/upstream-linus\n\n* \u0027upstream\u0027 of git://ftp.linux-mips.org/pub/scm/upstream-linus:\n [MIPS] Cacheops.h: Fix typo.\n [MIPS] Cobalt: Qube1 has no serial port so don\u0027t use it\n [MIPS] Cobalt: Fix ethernet interrupts for RaQ1\n [MIPS] Kconfig fixes for BCM47XX platform\n" }, { "commit": "c43756da94863395d5ee088659676029b3ae7191", "tree": "f5778b886527af2333bfa451d58221a75e9d4de3", "parents": [ "f6c0f32ee8d21e800097fc35ba8ab2b5a3b9bdfa" ], "author": { "name": "Thomas Bogendoerfer", "email": "tsbogend@alpha.franken.de", "time": "Sat Jan 12 00:25:17 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 15 01:04:42 2008 +0000" }, "message": "[MIPS] Cobalt: Qube1 has no serial port so don\u0027t use it\n\nBecause Qube1 doesn\u0027t have a serial chip waiting for transmit fifo empty\ntakes forever, which isn\u0027t a good idea. No prom_putchar/early console\nfor Qube1 fixes this.\n\nSigned-off-by: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nAcked-by: Yoichi Yuasa \u003cyoichi_yuasa@tripeaks.co.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f6c0f32ee8d21e800097fc35ba8ab2b5a3b9bdfa", "tree": "207e4b67003eab4c5e9eb9e8f014601f2049b2eb", "parents": [ "2f02c15a5d963007bd721d76f644c9491f6fec06" ], "author": { "name": "Thomas Bogendoerfer", "email": "tsbogend@alpha.franken.de", "time": "Sat Jan 12 00:25:14 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 15 01:04:42 2008 +0000" }, "message": "[MIPS] Cobalt: Fix ethernet interrupts for RaQ1\n\nRAQ1 uses the same interrupt routing as Qube2.\n\nSigned-off-by: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "2f02c15a5d963007bd721d76f644c9491f6fec06", "tree": "b2703396e25d2e37129cb01a7ad66f138a60559a", "parents": [ "88fb61e4ba263685a0d5b82c7e9cd6f22a9e6a9d" ], "author": { "name": "Aurelien Jarno", "email": "aurelien@aurel32.net", "time": "Tue Dec 11 11:30:34 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 15 01:04:41 2008 +0000" }, "message": "[MIPS] Kconfig fixes for BCM47XX platform\n\nThe patch below fixes two problems for Kconfig on the BCM47xx platform:\n\n- arch/mips/bcm47xx/gpio.c uses ssb_extif_* functions. Selecting\n SSB_DRIVER_EXTIF makes sure those functions are available.\n- arch/mips/pci/pci.c needs, when enabled, platform specific functions,\n which are defined when SSB_PCICORE_HOSTMODE is enabled.\n\nSigned-off-by: Aurelien Jarno \u003caurelien@aurel32.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "e452e94e21e8f4a3c2ff045b301ca21c1f6d03bf", "tree": "5785060011dbe098753f30d303d2fe2ceb298e69", "parents": [ "778bc145feb68f365339d6b5c9e35af2a86fb233" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Tue Jan 08 00:41:13 2008 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Jan 11 17:05:42 2008 +0000" }, "message": "[MIPS] Replace 40c7869b693b18412491fdcff64682215b739f9e kludge\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "778bc145feb68f365339d6b5c9e35af2a86fb233", "tree": "8655809bb2adbde989b0b77ad84853af7497bdaa", "parents": [ "84c21e254205ecac98f75b01589996440c6a6db0" ], "author": { "name": "WANG Cong", "email": "xiyou.wangcong@gmail.com", "time": "Wed Jan 02 14:21:36 2008 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Jan 11 17:05:42 2008 +0000" }, "message": "[MIPS] Lasat: Fix built in separate object directory.\n\nSigned-off-by: WANG Cong \u003cxiyou.wangcong@gmail.com\u003e\n\n[Ralf: The LDSCRIPT script needed fixing, too]\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "84c21e254205ecac98f75b01589996440c6a6db0", "tree": "77d0c87cd919fded83e70caae461afbbae7a6eae", "parents": [ "1b1c5f0d96eb05cf6cd4702dabf4e003eded08c2" ], "author": { "name": "Dmitri Vorobiev", "email": "dmitri.vorobiev@gmail.com", "time": "Tue Jan 08 06:44:00 2008 +0300" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Jan 11 17:05:41 2008 +0000" }, "message": "[MIPS] Malta: Fix software reset on big endian\n\nI noticed that the commit f197465384bf7ef1af184c2ed1a4e268911a91e3\n(MIPS Tech: Get rid of volatile in core code) broke the software\nreset functionality for MIPS Malta boards in big-endian mode.\n\nAccording to the MIPS Malta board user\u0027s manual, writing the magic\n32-bit GORESET value into the SOFTRES register initiates board soft\nreset. My experimentation has shown that the endianness of the GORESET\ninteger should thereby be the same as the endianness, which has been\nset for the CPU itself. The writew() function used to write the magic\nvalue in the code introduced by the commit mentioned above, however,\nswaps bytes for big-endian kernels and transfers 16 bits instead of 32.\n\nThe patch below replaces the writew() function by the __raw_writel()\nroutine, which leaves the byte order intact and transfers the whole\nMIPS machine word. Trivial code cleanup (replacing spaces by a tab\nand cutting oversized lines to make checkpatch.pl happy) is also\nincluded.\n\nThe patch was tested using a Malta evaluation board running in both\nBE and LE modes. For both modes, software reset was fully functional\nafter the change.\n\nP.S. I suspect that the same commit broke the \"standby\" functionality\nfor MIPS Atlas boards. However, I did not touch the Atlas code as I\ndon\u0027t have such board at my disposal and also because the linux-mips.org\nWeb site claims that Atlas support is scheduled for removal.\n\nSigned-off-by: Dmitri Vorobiev \u003cdmitri.vorobiev@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "1b1c5f0d96eb05cf6cd4702dabf4e003eded08c2", "tree": "5be9a68c8ef5b6cad1f4e8bc63f1ff446eef9455", "parents": [ "320167182dc3e351d2608cb7dccde12a47e3f51d" ], "author": { "name": "Vitaly Wool", "email": "vitalywool@gmail.com", "time": "Thu Jan 10 17:10:05 2008 +0300" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Jan 11 17:05:41 2008 +0000" }, "message": "[MIPS] pnx8xxx: move to clocksource\n\nThis patch converts PNX8XXX system timer to clocksource restoring PNX8550\nsupport back to live.\n\nSigned-off-by: Vitaly Wool \u003cvitalywool@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "320167182dc3e351d2608cb7dccde12a47e3f51d", "tree": "6583a349f5e713f0f96a2be14e9a3c544467d0b7", "parents": [ "88fb61e4ba263685a0d5b82c7e9cd6f22a9e6a9d" ], "author": { "name": "Thomas Bogendoerfer", "email": "tsbogend@alpha.franken.de", "time": "Sun Dec 30 12:45:40 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Jan 11 17:05:41 2008 +0000" }, "message": "[MIPS] Wrong CONFIG option prevents setup of DMA zone.\n\nSigned-off-by: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ba820c5c51296343be202c9afb072b7b943099cb", "tree": "5046795c606f66545844e79aa6b435d5e916d3dc", "parents": [ "ce202cbb9e0b623671e8ecb3d53afdd42b8e458f" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Jan 07 15:09:50 2008 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Jan 07 15:32:04 2008 +0000" }, "message": "[MIPS] Fix CONFIG_BOOT_RAW.\n\nThis was broken by 017e3a492683b32d17dcd1b13b279745cc656073 (lmo) /\n396a2ae08e5080b140330645743ab2567f6bc426 (kernel.org).\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ce202cbb9e0b623671e8ecb3d53afdd42b8e458f", "tree": "43791d3e8780fda3c1770f391306795f6b041159", "parents": [ "c990081bf87bf5afcd6d39d8bfce9c6d60b1f2eb" ], "author": { "name": "Thomas Bogendoerfer", "email": "tsbogend@alpha.franken.de", "time": "Fri Jan 04 23:38:31 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Jan 07 15:32:03 2008 +0000" }, "message": "[MIPS] Assume R4000/R4400 newer than 3.0 don\u0027t have the mfc0 count bug\n\nThis seems as reasonable assumption and gets some SNI machines to work\nwhich currently must rely on the cp0 counter as clocksource.\n\nSigned-off-by: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c990081bf87bf5afcd6d39d8bfce9c6d60b1f2eb", "tree": "f1d87ded4fc653bcf0a35c24ea53b4fd18d4cbd4", "parents": [ "9cfacb790f581000a7ec8455785d131aca923ded" ], "author": { "name": "Thomas Bogendoerfer", "email": "tsbogend@alpha.franken.de", "time": "Sat Jan 05 12:13:11 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Jan 07 15:32:03 2008 +0000" }, "message": "[MIPS] Fix IP32 breakage\n\n- suppress master aborts during config read\n- set io_map_base\n- only fixup end of iomem resource to avoid failing request_resource\n in serial driver\n- killed useless setting of crime_int bit, which caused wrong interrupts\n- use physcial address for serial port platform device and let 8250\n driver do the ioremap\n\nSigned-off-by: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "9cfacb790f581000a7ec8455785d131aca923ded", "tree": "d157df01abc4671933787e3d5a14374699665b74", "parents": [ "c4eee283e004751143fb81dbf4f8cfe7b8dcc970" ], "author": { "name": "Sergei Shtylyov", "email": "sshtylyov@ru.mvista.com", "time": "Tue Dec 25 21:00:45 2007 +0300" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Jan 07 15:32:03 2008 +0000" }, "message": "[MIPS] Alchemy: Fix use of __init code bug exposed by modpost warning\n\nWARNING: vmlinux.o(.text+0x1ca608): Section mismatch: reference to\n.init.text: add_wired_entry (between \u0027config_access\u0027 and \u0027config_read\u0027)\n\nby refactoring the code calling add_wired_entry() from config_access() to\na separate function which is called from aau1x_pci_setup(). While at it:\n\n- make some unnecassarily global variables \u0027static\u0027;\n\n- fix the letter case, whitespace, etc. in the comments...\n\nSigned-off-by: Sergei Shtylyov \u003csshtylyov@ru.mvista.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c4eee283e004751143fb81dbf4f8cfe7b8dcc970", "tree": "7441008d2d368800a5f89fc7f63307e6bec2c6b2", "parents": [ "3ce54450461bad18bbe1f9f5aa3ecd2f8e8d1235" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Mon Nov 12 01:05:16 2007 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Jan 07 15:32:03 2008 +0000" }, "message": "[MIPS] Move inclusing of kernel/time/Kconfig menu to appropriate place\n\nCONFIG_NO_HZ, CONFIG_HIGH_RES_TIMERS should be selected in \"Kernel\ntype\" menu, not in \"CPU selection\" menu.\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "bbaf238b5f910f8f3dda4b96cf844f50b2dcc6fa", "tree": "5fe8f78dcc4ac82f468e4976f28e798b9052f6e1", "parents": [ "4037500ebcfd172a15aed40caa847c52e9906712" ], "author": { "name": "Chris Dearman", "email": "chris@mips.com", "time": "Thu Dec 13 22:42:19 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Dec 14 17:34:30 2007 +0000" }, "message": "[MIPS] Ensure that ST0_FR is never set on a 32 bit kernel\n\nSigned-off-by: Chris Dearman \u003cchris@mips.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "4037500ebcfd172a15aed40caa847c52e9906712", "tree": "6957163263ef1e1161d92a8973c69b60031f8011", "parents": [ "d20e47e153dcfddca5a066ff0f8da2d1104d08ea" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Dec 14 00:05:34 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Dec 14 17:34:30 2007 +0000" }, "message": "[MIPS] time: Delete weak definition of plat_time_init() due to gcc bug.\n\nFrank Rowand \u003cfrank.rowand@am.sony.com\u003e reports:\n\n\u003e In linux-2.6.24-rc4 the Toshiba RBTX4927 hangs on boot.\n\u003e\n\u003e The cause is that plat_time_init() from arch/mips/tx4927/common/\n\u003e tx4927_setup.c does not override the __weak plat_time_init() from\n\u003e arch/mips/kernel/time.c. This is due to a compiler bug in gcc 4.1.1. The\n\u003e bug is reported to not exist in earlier versions of gcc, and to be fixed in\n\u003e 4.1.2. The problem is that the __weak plat_time_init() is empty and thus\n\u003e gets optimized out of existence (thus the linker is never given the option\n\u003e to replace the __weak function).\n\n[ He meant the call to plat_time_init() from time_init() gets optimized away ]\n\n\u003e For more info on the gcc bug see\n\u003e\n\u003e http://gcc.gnu.org/bugzilla/show_bug.cgi?id\u003d27781\n\u003e\n\u003e The attached patch is one workaround. Another possible workaround\n\n[ His patch adds -fno-unit-at-a-time for time.c ]\n\n\u003e would be to change the __weak plat_time_init() to be a non-empty\n\u003e function.\n\nThe __weak definition of plat_time_init was only ever meant to be a\nmigration helper to keep platforms that don\u0027t have a plat_time_init\ncompiling. A few greps says that all platforms now supply their own\nplat_time_init() so the weak definition is no longer needed. So I\ninstead delete it.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d20e47e153dcfddca5a066ff0f8da2d1104d08ea", "tree": "f587d4b9b7c67ca5ced4e9eb1ebdcfafcd259a55", "parents": [ "40c7869b693b18412491fdcff64682215b739f9e" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Dec 11 19:49:24 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Dec 14 17:34:29 2007 +0000" }, "message": "[MIPS] PCI: Make pcibios_fixup_device_resources ignore legacy resources.\n\nThere might be other reasons why a resource might be marked as fixed\nsuch as a PCI UART holding the system console but until we use\nIORESOURCE_PCI_FIXED that way also this will work.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "40c7869b693b18412491fdcff64682215b739f9e", "tree": "a873e35640b25d3eab0b27ebc9a631f8d46970dc", "parents": [ "b87bb40b62310328e908d580e013e0575b05886c" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Dec 11 19:38:12 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Dec 14 17:34:29 2007 +0000" }, "message": "[MIPS] Atlas, Malta: Don\u0027t free firmware memory on free_initmem.\n\nA proper fix for this needs to turn a few MIPS-generic bits which I\ndon\u0027t want at this stage.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "b87bb40b62310328e908d580e013e0575b05886c", "tree": "aa095d0a19180ff62a8cfa879e20c8cf5fe6f937", "parents": [ "dd99d9661c72fe251b842705f2e7cfaa4918a13c" ], "author": { "name": "Sergei Shtylyov", "email": "sshtylyov@ru.mvista.com", "time": "Mon Dec 10 20:36:50 2007 +0300" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Dec 14 17:34:29 2007 +0000" }, "message": "[MIPS] Alchemy: fix off by two error in __fixup_bigphys_addr()\n\nthe PCI specific code in this function doesn\u0027t check for the address range\nbeing under the upper bound of the PCI memory window correctly -- fix this,\nsomewhat beautifying the code around the check, while at it...\n\nSigned-off-by: Sergei Shtylyov \u003csshtylyov@ru.mvista.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "dd99d9661c72fe251b842705f2e7cfaa4918a13c", "tree": "b3d3a402005a083c9273cc10ecc9fc87da719e58", "parents": [ "18ca38d26f65c849af109eb911295c7dde71ce3b" ], "author": { "name": "Sergei Shtylyov", "email": "sshtylyov@ru.mvista.com", "time": "Mon Dec 10 20:28:51 2007 +0300" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Dec 14 17:34:29 2007 +0000" }, "message": "[MIPS] Alchemy: fix PCI resource conflict\n\n... by getting the PCI resources back into the 32-bit range -- there\u0027s no\nneed therefore for CONFIG_RESOURCES_64BIT either. This makes Alchemy PCI\nwork again while currently the kernel skips the bus scan.\n\nSigned-off-by: Sergei Shtylyov \u003csshtylyov@ru.mvista.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "18ca38d26f65c849af109eb911295c7dde71ce3b", "tree": "7d743a2827c8facd4b69e55f4add2443fc0534a5", "parents": [ "da8cadb31b82c9d41fc593c8deab6aa20b162d6b" ], "author": { "name": "Yoichi Yuasa", "email": "yoichi_yuasa@tripeaks.co.jp", "time": "Sun Dec 09 21:22:04 2007 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Dec 14 17:34:29 2007 +0000" }, "message": "[MIPS] time: Set up Cobalt\u0027s mips_hpt_frequency\n\nSigned-off-by: Yoichi Yuasa \u003cyoichi_yuasa@tripeaks.co.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ba0f00b9fcb02b10cc9929fec660f86d1af6a41a", "tree": "c1924fdf5cedb3d8c8d1cbe911290d2c1279d801", "parents": [ "5ef1b9a0f6cbb1269fc8b8d7704d146f22bf7aa6" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 16 14:54:46 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Dec 09 04:51:10 2007 +0000" }, "message": "[MIPS] Malta: Enable tickless and highres timers.\n\nMost Malta use an FPGA CPU card which rarely is good for more than 40MHz.\nSo the performance penalta of the regular timer interrupt, especially\nfor the VSMP kernel model is significant, even at a mere 100Hz.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "5ef1b9a0f6cbb1269fc8b8d7704d146f22bf7aa6", "tree": "134ed87dc69815f2f72d2a3b03b7b60f15218a6c", "parents": [ "8f7e7d67cbcbcfd2c72d496f01f5e4c78853ef7d" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 16 23:15:51 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Dec 09 04:51:10 2007 +0000" }, "message": "[MIPS] Bigsur: Enable tickless and and highres timers.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "8f7e7d67cbcbcfd2c72d496f01f5e4c78853ef7d", "tree": "bebad4ebbb4ce264e9dd11f0e643e15491bc315a", "parents": [ "0f5e49a2e2de69ee05ad8783274b0672247fd18f" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Fri Nov 23 00:44:06 2007 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Dec 09 04:51:10 2007 +0000" }, "message": "qemu: do not enable IP7 blindly\n\nIP7 will be enabled automatically in mips_clockevent_init(), if available.\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "6d2d419ffd83502d105014288e6af171a0a89544", "tree": "f7bc3aef5a2cbf2079784e2da3e7bb5fbaf097e2", "parents": [ "94545baded0bfbabdc30a3a4cb48b3db479dd6ef" ], "author": { "name": "Chris Dearman", "email": "chris@mips.com", "time": "Thu Dec 06 15:35:54 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Dec 09 04:51:09 2007 +0000" }, "message": "[MIPS] Don\u0027t byteswap writes to display when running bigendian\n\nSigned-off-by: Chris Dearman \u003cchris@mips.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ceaeee6ad6c2a24bf37d9f426414cf3007432352", "tree": "fa330133773d10a9d7f329e3db2cc371999c6d86", "parents": [ "3743d33edf4e49376384822c57c4ee5cdf2d32f8", "5e2862eb5a263a0339a85545d96fb20995d67b1f" ], "author": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Thu Dec 06 09:43:26 2007 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Thu Dec 06 09:43:26 2007 -0800" }, "message": "Merge branch \u0027upstream\u0027 of git://ftp.linux-mips.org/pub/scm/upstream-linus\n\n* \u0027upstream\u0027 of git://ftp.linux-mips.org/pub/scm/upstream-linus:\n [MIPS] Oprofile: Fix computation of number of counters.\n [MIPS] Alchemy: fix IRQ bases\n [MIPS] Alchemy: replace ffs() with __ffs()\n [MIPS] BCM1480: Fix interrupt routing, take 2.\n" }, { "commit": "00a5825332769706eb2e276c101dd20269a53992", "tree": "7ae71fbd4e111dc80e493d25fc12b855f7028e85", "parents": [ "7e1fb765c613298d861f80fa18af26df87a4ec19" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 06 16:53:19 2007 +0000" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Thu Dec 06 09:37:03 2007 -0800" }, "message": "Fix oprofile configuration breakage\n\nThe cleanup 09cadedbdc01f1a4bea1f427d4fb4642eaa19da9 broke the oprofile\nconfiguration for MIPS by allowing oprofile support to be built for\nkernel models where oprofile doesn\u0027t have a chance in hell to work.\n\nJust a dependecy list on a number of architectures is - surprise - broken\nand should as per past discussions probably in most considered to be\nbroken in most cases. So I introduce a dependency for the oprofile\nconfiguration on ARCH_SUPPORTS_OPROFILE.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "5e2862eb5a263a0339a85545d96fb20995d67b1f", "tree": "a455b6c67268f31662d61276602509b3221cba1f", "parents": [ "0e8120e0946152720af3d73691550bba108a3826" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 06 09:12:28 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 06 17:15:58 2007 +0000" }, "message": "[MIPS] Oprofile: Fix computation of number of counters.\n\nVSMP kernels will split the available performance counters between the two\nprocessors / cores. But don\u0027t do this when we\u0027re not on a VSMP system ...\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "0e8120e0946152720af3d73691550bba108a3826", "tree": "4802cffba4b829c77b30630fea822988e153bd7c", "parents": [ "4b36673284f86c649b9d9ec5818b1912fde556b3" ], "author": { "name": "Sergei Shtylyov", "email": "sshtylyov@ru.mvista.com", "time": "Wed Dec 05 19:08:26 2007 +0300" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 06 17:15:58 2007 +0000" }, "message": "[MIPS] Alchemy: fix IRQ bases\n\nDo what the commits commits f3e8d1da389fe2e514e31f6e93c690c8e1243849 and\n9d360ab4a7568a8d177280f651a8a772ae52b9b9 failed to achieve -- actually\nconvert the Alchemy code to irq_cpu.\n\nSigned-off-by: Sergei Shtylyov \u003csshtylyov@ru.mvista.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "4b36673284f86c649b9d9ec5818b1912fde556b3", "tree": "b8f4a90a85babb175b74091efae5c33beef94b75", "parents": [ "f435a91e66e7776f0c73fca5af3cb87c61130ed6" ], "author": { "name": "Sergei Shtylyov", "email": "sshtylyov@ru.mvista.com", "time": "Wed Dec 05 19:08:24 2007 +0300" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 06 17:15:58 2007 +0000" }, "message": "[MIPS] Alchemy: replace ffs() with __ffs()\n\nFix havoc wrought by commit 56f621c7f6f735311eed3f36858b402013023c18 --\nau_ffs() and ffs() are equivalent, that patch should have just replaced one\nwith another. Now replace ffs() with __ffs() which returns an unbiased bit\nnumber.\n\nSigned-off-by: Sergei Shtylyov \u003csshtylyov@ru.mvista.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f435a91e66e7776f0c73fca5af3cb87c61130ed6", "tree": "439a0e66278ce743d750300d816b561e69bccbe8", "parents": [ "7e1fb765c613298d861f80fa18af26df87a4ec19" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 06 17:15:57 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 06 17:15:57 2007 +0000" }, "message": "[MIPS] BCM1480: Fix interrupt routing, take 2.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a6733f2e146a5f4884bc23023bf56f3a2698b547", "tree": "78e6687f31a1ee2d61f879d8aa335361e3f8b66c", "parents": [ "1a2edea9aff48c31302e07100ddbaba358596cd7" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Dec 02 12:09:11 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Dec 03 19:40:26 2007 +0000" }, "message": "[MIPS] BCM1480: Fix interrupt routing.\n\nThe old code did did only work as long as CFE and the kernel were using\nthe same interrupt numbering ...\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "e6a1bb725eab1348d4a985b7faeff8186210d7b4", "tree": "89ab8c1f804a3658938250fe58ba40b2fb318da0", "parents": [ "54fd6441e04696c046d93e4407a9e1ee9b874e51" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Nov 28 15:07:42 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Dec 01 00:39:37 2007 +0000" }, "message": "[MIPS] Fix build.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "68576cf122bc5195c758ed295e78b5858472378a", "tree": "5b6b7cb9608bf757bf3368c808f14bf206eddbe8", "parents": [ "6d4f5879b6f4da50bde94e1cae73755978ed048f" ], "author": { "name": "Thomas Bogendoerfer", "email": "tsbogend@alpha.franken.de", "time": "Wed Nov 28 16:21:44 2007 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Thu Nov 29 09:24:53 2007 -0800" }, "message": "IP22ZILOG: fix lockup and sysrq\n\n - fix lockup when switching from early console to real console\n - make sysrq reliable\n - fix panic, if sysrq is issued before console is opened\n\nSigned-off-by: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nAcked-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Alan Cox \u003calan@lxorguk.ukuu.org.uk\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "b1e3afa001db8845eb60981f6ab925503ed94e53", "tree": "bdfb7ba962a7d41fa805ce23d298f32d93e284bc", "parents": [ "8142294dda12d5fd7615eed7986ad0d276793c03" ], "author": { "name": "Joe Perches", "email": "joe@perches.com", "time": "Mon Nov 19 17:47:54 2007 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 26 17:26:15 2007 +0000" }, "message": "[MIPS] vpe: Add missing \"space\"\n\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "8142294dda12d5fd7615eed7986ad0d276793c03", "tree": "67576cec1c971db1e29fe5f6ae13a8acb5028d4d", "parents": [ "5b3af8f19fd3c61369da73476737fea058f1fccd" ], "author": { "name": "Richard Knutsson", "email": "ricknu-0@student.ltu.se", "time": "Sat Nov 24 22:22:19 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 26 17:26:15 2007 +0000" }, "message": "[MIPS] Compliment va_start() with va_end().\n\nSigned-off-by: Richard Knutsson \u003cricknu-0@student.ltu.se\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "5b3af8f19fd3c61369da73476737fea058f1fccd", "tree": "e8be7656668f2c0ac45a7975da6b9e13bfa94286", "parents": [ "68de4803726224a7cfe09c8052f0ce5e532c6847" ], "author": { "name": "Thomas Bogendoerfer", "email": "tsbogend@alpha.franken.de", "time": "Fri Nov 23 20:40:15 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 26 17:26:14 2007 +0000" }, "message": "[MIPS] IP22: Fix broken eeprom access by using __raw_readl/__raw_writel\n\nSigned-off-by: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "68de4803726224a7cfe09c8052f0ce5e532c6847", "tree": "2f6a9595768f75d417c30d1966012845d477f1ad", "parents": [ "cce335ae47e231398269fb05fa48e0e9cbf289e0" ], "author": { "name": "Thomas Bogendoerfer", "email": "tsbogend@alpha.franken.de", "time": "Fri Nov 23 20:34:16 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 26 17:26:14 2007 +0000" }, "message": "[MIPS] IP22: Fix broken EISA interrupt setup by switching to generic i8259\n\nSigned-off-by: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "cce335ae47e231398269fb05fa48e0e9cbf289e0", "tree": "a01ea9ad318d459393a905df5c53b68b754300da", "parents": [ "940f6b48a130e0a33cb8bd397dd0e277166470ad" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Nov 03 02:05:43 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 26 17:26:14 2007 +0000" }, "message": "[MIPS] 64-bit Sibyte kernels need DMA32.\n\nSibyte SOCs only have 32-bit PCI. Due to the sparse use of the address\nspace only the first 1GB of memory is mapped at physical addresses\nbelow 1GB. If a system has more than 1GB of memory 32-bit DMA will\nnot be able to reach all of it.\n\nFor now this patch is good enough to keep Sibyte users happy but it seems\neventually something like swiotlb will be needed for Sibyte.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "940f6b48a130e0a33cb8bd397dd0e277166470ad", "tree": "03bd36fcb9b5c8d77f5de2930ff32d770f5cdf4e", "parents": [ "5aa85c9fc49a6ce44dc10a42e2011bbde9dc445a" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Nov 24 22:33:28 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 26 17:26:14 2007 +0000" }, "message": "[MIPS] Only build r4k clocksource for systems that work ok with it.\n\nIn particular as-is it\u0027s not suited for multicore and mutiprocessors\nsystems where there is on guarantee that the counter are synchronized\nor running from the same clock at all. This broke Sibyte and probably\nothers since the \"[MIPS] Handle R4000/R4400 mfc0 from count register.\"\ncommit.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "5aa85c9fc49a6ce44dc10a42e2011bbde9dc445a", "tree": "14b8d1a014349568be39753f879c152e1e3f2b41", "parents": [ "0f67e90e1caea4a0a14d2c60102547bce29f7f08" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Nov 21 16:39:44 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 26 17:26:14 2007 +0000" }, "message": "[MIPS] Handle R4000/R4400 mfc0 from count register.\n\nThe R4000 and R4400 have an errata where if the cp0 count register is read\nin the exact moment when it matches the compare register no interrupt will\nbe generated.\n\nThis bug may be triggered if the cp0 count register is being used as\nclocksource and the compare interrupt as clockevent. So a simple\nworkaround is to avoid using the compare for both facilities on the\naffected CPUs.\n\nThis is different from the workaround suggested in the old errata documents;\nat some opportunity probably the official version should be implemented\nand tested. Another thing to find out is which processor versions\nexactly are affected. I only have errata documents upto R4400 V3.0\navailable so for the moment the code treats all R4000 and R4400 as broken.\n\nThis is potencially a problem for some machines that have no other decent\nclocksource available; this workaround will cause them to fall back to\nanother clocksource, worst case the \"jiffies\" source.\n" }, { "commit": "98ce472181e760a552314850c238b14bbf3f04ec", "tree": "e2868580151a44e5853f1383b728984a6984ccf0", "parents": [ "526a6770692477ff258621b1b8838cce9304f8e4" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Oct 30 15:43:44 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 26 17:26:13 2007 +0000" }, "message": "[MIPS] IP32: More interrupt renumbering fixes.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "526a6770692477ff258621b1b8838cce9304f8e4", "tree": "176274d8ad98bdd82f09a3bad78507211eb9f138", "parents": [ "aea6863944efdf42b7de96e71545e0ce4c317a1f" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Oct 30 15:39:18 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 26 17:26:13 2007 +0000" }, "message": "[MIPS] time: MIPSsim\u0027s plat_time_init doesn\u0027t need to be irq safe.\n\nIt\u0027s running early during the bootup process so interrupts are still off.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "aea6863944efdf42b7de96e71545e0ce4c317a1f", "tree": "d6e8fe8aad1c66d100f3898a239fd6f409dffe44", "parents": [ "cfb6f26035b17d5d280ce4a6ceb041438643ba63" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Oct 30 02:21:08 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 26 17:26:13 2007 +0000" }, "message": "[MIPS] time: Fix negated condition in cevt-r4k driver.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "72e510654c814e2c5c9227e95ae02ea77e015ce4", "tree": "4fb4e13a9c8ffa1a10516ed9e56d8692a5eedb66", "parents": [ "30e748a507919a41f9eb4d10b4954f453325a37d" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 22:20:33 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:52 2007 +0000" }, "message": "[MIPS] N32 needs to use the compat version of sys_nfsservctl.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "30e748a507919a41f9eb4d10b4954f453325a37d", "tree": "a499fb079d632e401d8313caa229e899f6a251b3", "parents": [ "f99f2cc9363a08cdbd6cfbe3f29234e3235d05e8" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 19:37:15 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:52 2007 +0000" }, "message": "[MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts.\n\nThis matters to any sort of device that is wired to one of the CPU\ninterrupt pins on an SMP system. Typically the scenario is most easily\ntriggered with the count/compare timer interrupt where the same interrupt\nnumber and thus irq_desc is used on each processor.\n\n CPU A\t\t\tCPU B\n\n do_IRQ()\n generic_handle_irq()\n handle_level_irq()\n spin_lock(desc_lock)\n set IRQ_INPROGRESS\n spin_unlock(desc_lock)\n\t\t\t\tdo_IRQ()\n\t\t\t\tgeneric_handle_irq()\n\t\t\t\thandle_level_irq()\n\t\t\t\tspin_lock(desc_lock)\n\t\t\t\tIRQ_INPROGRESS set \u003d\u003e bail out\n spin_lock(desc_lock)\n clear IRQ_INPROGRESS\n spin_unlock(desc_lock)\n\nIn case of the cp0 compare interrupt this means the interrupt will be\nacked and not handled or re-armed on CPU b, so there won\u0027t be any timer\ninterrupt until the count register wraps around.\n\nWith kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just\nworking right on VSMP because the count registers are synchronized on\nbootup so it takes something that disables interrupts for a long time on\none processor to trigger this one.\n\nFor scenarios where an interrupt is multicasted or broadcasted over several\nCPUs the existing code was safe and the fix will break it. There is no\nway to know in the interrupt controller code because it is abstracted from\nthe platform code. I think we do not have such a setup currently, so this\nshould be ok.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f99f2cc9363a08cdbd6cfbe3f29234e3235d05e8", "tree": "8985a00d59f39aaebccf9e7ba69814faa8b0a87a", "parents": [ "eae5fdc3e5032304a7d53bd06784b7ee71abccaf" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Nov 13 00:35:13 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:51 2007 +0000" }, "message": "[MIPS] Sibyte: Fix name of clocksource.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "eae5fdc3e5032304a7d53bd06784b7ee71abccaf", "tree": "1ec4eaa3ecd0e5a3cf421e18860a49a8c05b6f4c", "parents": [ "3247989ee864db2cc5dccb14460573fee82b6832" ], "author": { "name": "Maciej W. Rozycki", "email": "macro@linux-mips.org", "time": "Mon Nov 12 17:32:48 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:51 2007 +0000" }, "message": "[MIPS] SNI: s/achknowledge/acknowledge/\n\nSigned-off-by: Maciej W. Rozycki \u003cmacro@linux-mips.org\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "3247989ee864db2cc5dccb14460573fee82b6832", "tree": "2c35f1965acef9e99da6fdd56a5a4692f15ba38f", "parents": [ "7c3a622d9c8e88117a8d647756827852dd8c8432" ], "author": { "name": "Maciej W. Rozycki", "email": "macro@linux-mips.org", "time": "Mon Nov 12 17:30:52 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:51 2007 +0000" }, "message": "[MIPS] Makefile: Fix canonical system names\n\nThe GNU `config.guess\u0027 uses \"linux-gnu\" as the canonical system name.\nFix the list of compiler prefixes checked to spell it correctly.\n\nSigned-off-by: Maciej W. Rozycki \u003cmacro@linux-mips.org\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "7c3a622d9c8e88117a8d647756827852dd8c8432", "tree": "e30d2274855e61cab96cc4abebcab7e69263c641", "parents": [ "8dfa741f146b39eb59ef2094e03f47079ca99eb0" ], "author": { "name": "Nigel Stephens", "email": "nigel@mips.com", "time": "Thu Nov 08 13:25:51 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:50 2007 +0000" }, "message": "[MIPS] vpe: handle halting TCs in an errata safe way.\n\nAdds a JR.HB after halting a TC, to ensure that the TC has really halted.\nonly modifies the TCSTATUS register when the TC is safely halted.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "8dfa741f146b39eb59ef2094e03f47079ca99eb0", "tree": "823c790dff8619a3671c1a8a19671e020b9b4e2d", "parents": [ "622477533d3dc24845c847f386533f3c0e6a1be6" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Nov 11 17:33:55 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:50 2007 +0000" }, "message": "[MIPS] Sibyte: Stop timers before programming next even.\n\nWe have no guarantee by the generic time code that the timer is stopped\nwhen the -\u003enext_event method is called. Modifying the Timer Initial Count\nregister while the timer is enabled has UNPREDICTABLE effect according to\nthe BCM1250/BCM1125/BCM1125H User Manual. So stop the timer before\nreprogramming.\n\nThis is a paranoia fix; no ill effects have been observed previously.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "622477533d3dc24845c847f386533f3c0e6a1be6", "tree": "24503bc9ebe8496566991c5a7a689b4115065e7b", "parents": [ "89becf5c0d9019f4f9300840f08a98ee33d57d37" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Nov 11 17:24:46 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:50 2007 +0000" }, "message": "[MIPS] Sibyte: Increase minimum oneshot timer interval to two ticks.\n\nFor the old minimum of a single tick a value of zero would be programmed\ninto the init value register which in the BCM1250/BCM1125/BCM1125H User\nManual in the Timer Special Cases section is documented to have\nUNPREDICTABLE effect.\n\nObservable sympthoms of this bug were hangs of several seconds on the\nconsole during bootup and later if both dyntick and highres timer options\nwere activated.\n\nIn theory contiguous mode of the timers is also affected but in an act of\nhopeless lack of realism I\u0027ll assume nobody will ever configure a KERNEL\nfor HZ \u003e 500kHz but if so I leave that to evolution to sort out.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "89becf5c0d9019f4f9300840f08a98ee33d57d37", "tree": "8b6a9295e957de54fdad6866c1437f3d48b12be0", "parents": [ "fcee3faf8339bb65660c9a22123f71aa0cc30514" ], "author": { "name": "Yoichi Yuasa", "email": "yoichi_yuasa@tripeaks.co.jp", "time": "Fri Nov 09 18:42:35 2007 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:50 2007 +0000" }, "message": "[MIPS] Lasat: Fix overlap of interrupt number ranges.\n\nThe range of MIPS_CPU IRQ and the range of LASAT IRQ overlap.\n\nSigned-off-by: Yoichi Yuasa \u003cyoichi_yuasa@tripeaks.co.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "fcee3faf8339bb65660c9a22123f71aa0cc30514", "tree": "cd0f28ed904d6b52f613e6ef117838e8820215dc", "parents": [ "f6771dbb27c704ce837ba3bb1dcaa53f48f76ea8" ], "author": { "name": "Thomas Bogendoerfer", "email": "tsbogend@alpha.franken.de", "time": "Thu Nov 08 22:09:11 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:50 2007 +0000" }, "message": "[MIPS] SNI PCIT CPLUS: workaround for b0rked irq wiring of onboard PCI bus 1\n\nSigned-off-by: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f6771dbb27c704ce837ba3bb1dcaa53f48f76ea8", "tree": "efec5eacc34a9e412a193a79d575cbf3b90acf23", "parents": [ "efb9ca08b5a2374b29938cdcab417ce4feb14b54" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 08 18:02:29 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:49 2007 +0000" }, "message": "[MIPS] Fix shadow register support.\n\nShadow register support would not possibly have worked on multicore\nsystems. The support code for it was also depending not on MIPS R2 but\nVSMP or SMTC kernels even though it makes perfect sense with UP kernels.\n\nSR sets are a scarce resource and the expected usage pattern is that\nusers actually hardcode the register set numbers in their code. So fix\nthe allocator by ditching it. Move the remaining CPU probe bits into\nthe generic CPU probe.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c6563e85f73e5806d58d8b0230edecbc65537200", "tree": "a5bd2a7ebcd0c3dcd561f1e38517c3149ae4fa44", "parents": [ "33b75e5c51e119c903681f592b4ec6c772def0e0" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Wed Nov 07 01:08:48 2007 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:49 2007 +0000" }, "message": "[MIPS] Fix typo in R3000 TRACE_IRQFLAGS code\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "33b75e5c51e119c903681f592b4ec6c772def0e0", "tree": "6a52a667fe9ba5c43e3c5f082354f3233c42f609", "parents": [ "bb856c5b494049584eca61c6069eb8e1b0f9ce35" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Nov 06 00:43:51 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:49 2007 +0000" }, "message": "[MIPS] Sibyte: Replace use of removed IO_SPACE_BASE with IOADDR.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "bb856c5b494049584eca61c6069eb8e1b0f9ce35", "tree": "eea7971b6423dba1c429da4ad3c2508f9344095f", "parents": [ "a8401fa57f1600ca0ad74b958c2c9eb494f40dc8" ], "author": { "name": "Roel Kluin", "email": "12o3l@tiscali.nl", "time": "Sun Nov 04 13:00:06 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:49 2007 +0000" }, "message": "[MIPS] iounmap if in vr41xx_pciu_init() pci clock is over 33MHz\n\niounmap if pci clock is over 33MHz. Cosmetic because the iomap() in this\ncase is just a bit of address magic.\n\nSigned-off-by: Roel Kluin \u003c12o3l@tiscali.nl\u003e\nAcked-by: Yoichi Yuasa \u003cyoichi_yuasa@tripeaks.co.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a8401fa57f1600ca0ad74b958c2c9eb494f40dc8", "tree": "5ac72807d2335a9a345ada669232b4e654862960", "parents": [ "07a80e49240ff57bccc3c65944d35947c3d33697" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 05 00:29:45 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:49 2007 +0000" }, "message": "[MIPS] BCM1480: Remove duplicate acknowledge of timer interrupt.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "07a80e49240ff57bccc3c65944d35947c3d33697", "tree": "9a90258c6f5f060ac3fd5f6f827907f421e4637b", "parents": [ "a57c228935fd55c4a1cf7c0b7823537c81914000" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 05 00:18:05 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:48 2007 +0000" }, "message": "[MIPS] Sibyte: pin timer interrupt to their cores.\n\nOr strange things will happen.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a57c228935fd55c4a1cf7c0b7823537c81914000", "tree": "36a2aa23cf2f6aec80cb0c46469f8e9cdcddcabe", "parents": [ "a8049c53cdad347b5b1234969dba65a179fdf8f1" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Nov 04 04:49:44 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:48 2007 +0000" }, "message": "[MIPS] Qemu: Add early printk, your friend in a cold night.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a8049c53cdad347b5b1234969dba65a179fdf8f1", "tree": "01386830e7ce44c66318a1b479daffa65d63182b", "parents": [ "a754f70886ebcc7fda3d18a828e0e54e3ffc86d9" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Nov 04 04:42:03 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:48 2007 +0000" }, "message": "[MIPS] Convert reference to mem_map to pfn_to_page().\n\nThis was crashing the combination of highmem and sparsemem.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a754f70886ebcc7fda3d18a828e0e54e3ffc86d9", "tree": "c070ecad253f24e32cb8036e6f720e0dbdcf23b6", "parents": [ "99fee6d7e5748d96884667a4628118f7fc130ea0" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Nov 03 01:01:37 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 15 23:21:48 2007 +0000" }, "message": "[MIPS] Sibyte: resurrect old cache hack.\n\nThe recent switch of the Sibyte SOCs from the processor specific cache\nmanagment code in c-sb1.c to c-r4k.c lost this old hack\n\n [MIPS] Hack for SB1 cache issues\n\n Removing flush_icache_page a while ago broke SB1 which was using an empty\n flush_data_cache_page function. This glues things well enough so a more\n efficient but also more intrusive solution can be found later.\n\n Signed-Off-By: Thiemo Seufer \u003cths@networkno.de\u003e\n Signed-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\nin the hope it was no longer needed. As it turns it still is so resurrect\nit until there is a better solution.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c0f2a9d75aed1a4be40c3975b94fd39066bd11bb", "tree": "9d73066a4d79d07dd8da0d3eece2924b7308292b", "parents": [ "5c6ff79d0908df0d281c05b5b693eaba55b06e0f" ], "author": { "name": "Roel Kluin", "email": "12o3l@tiscali.nl", "time": "Wed Nov 14 17:00:06 2007 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Wed Nov 14 18:45:42 2007 -0800" }, "message": "mips: undo locking on error path returns\n\n[akpm@linux-foundation.org: coding-style cleanups]\nSigned-off-by: Roel Kluin \u003c12o3l@tiscali.nl\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "74521c28e550c4ec265cda14114bd9b908e9de34", "tree": "6e9ab675eb69329db5188783a11a76a826055531", "parents": [ "a89b7717a8c9be41a4856134b60a4d7a66df13f6" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 17:26:06 2007 +0000" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Fri Nov 02 19:39:18 2007 -0700" }, "message": "Use i8253.c lock for PC speaker on MIPS, too.\n\nThe Jazz machines have to use the PIT timer for dyntick and highresolution\nkernels. This may break because currently just like i386 used to do MIPS\nuses two separate spinlocks in the actual PIT code and the PC speaker\ncode. So switch to do it the same that x86 currently does PIT locking.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "3be51f70e1f5e11a723d28b3dde26bc3aacdbc71", "tree": "29feea1c950109cba0ec3e68619acb18e64daf77", "parents": [ "651194f82066ba3688630b5a0d79d13d26a7ccbb" ], "author": { "name": "Thomas Bogendoerfer", "email": "tsbogend@alpha.franken.de", "time": "Fri Nov 02 11:17:13 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:49 2007 +0000" }, "message": "[MIPS] Jazz: disable PIT; cleanup R4030 clockevent\n\nFix ISA irq acknowledge.\nMake r4030 clockevent code look like other mips clockevent code.\n\nSigned-off-by: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "651194f82066ba3688630b5a0d79d13d26a7ccbb", "tree": "40f6b2d402203946be2d3fca88077b764dae62b6", "parents": [ "9603a23d3b28bc1d52492a927d8256f8c46e8f41" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 21:55:39 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:49 2007 +0000" }, "message": "[MIPS] Bigsur supports highmem.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "9603a23d3b28bc1d52492a927d8256f8c46e8f41", "tree": "fe994eee076b755aec549e4aafd8ce0dc9196db5", "parents": [ "e7c9d6b927191602cf79ea0183727c7112e79673" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 16:50:06 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:49 2007 +0000" }, "message": "[MIPS] mtx-1: Enable -Werror.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "e7c9d6b927191602cf79ea0183727c7112e79673", "tree": "3888daeb49cc4b1383637ade84957b7e24900ebc", "parents": [ "ae11e3214b0ecfcb2dd2536aab68e8d3834d5c5b" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 16:49:12 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:49 2007 +0000" }, "message": "[MIPS] mtx-1: Remove unused mtx1_sys_btn.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ae11e3214b0ecfcb2dd2536aab68e8d3834d5c5b", "tree": "db1fd98b3cb7d5c0c377334bdd5477edf0e5b878", "parents": [ "72fc19ff51cc32fe85ddb085cb0622b7b97b2158" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 16:46:14 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:48 2007 +0000" }, "message": "[MIPS] Pb1200: Enable -Werror.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c9294022af5022584756d67164e68dba0be9302b", "tree": "859de6852ed4bf9254a2da8e335c6547c145a377", "parents": [ "f6a8cc31aa23318c6c95aabad7f49874fb79e527" ], "author": { "name": "Thomas Bogendoerfer", "email": "tsbogend@alpha.franken.de", "time": "Thu Nov 01 11:36:42 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:48 2007 +0000" }, "message": "[MIPS] SNI: register a02r clockevent; don\u0027t use PIT timer\n\nRegister A20R clockevent.\nRemove PIT timer setup because it doesn\u0027t work\n\nSigned-off-by: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "dd3db6eb0e47b4480eeea30394d19bd826e64964", "tree": "b568e78a08bfc57d2727d6f887235b8abef02f5d", "parents": [ "9aa4cc11b22ec447b42c5df03fdab5eb748971e2" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 14:38:20 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:48 2007 +0000" }, "message": "[MIPS] i8253: Cleanup.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "db0c19e1a6abd9a9bdbf3ffbabc1e8e4995cb462", "tree": "296239b964b471e03deb836e51dbd72ea53115ad", "parents": [ "f5cd9f14e2660e610d8bb99ce723ef098b65ae9c" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 12:59:18 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:48 2007 +0000" }, "message": "[MIPS] Pb1200: Fix warning.\n\narch/mips/au1000/pb1200/irqmap.c:101: warning: ignoring return value of \u0027request_irq\u0027, declared with attribute warn_unused_result\n\nAnd while at it a few coding style cleanups.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f5cd9f14e2660e610d8bb99ce723ef098b65ae9c", "tree": "0e2a4dda36b6d058c8dedfcba0cab96698a93e54", "parents": [ "c8925297e875168a7c08965b4f80b418524fb8ce" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 12:22:53 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:47 2007 +0000" }, "message": "[MIPS] Pb1200: Fix warning.\n\narch/mips/au1000/pb1200/board_setup.c:71: warning: unused variable \u0027pin_func\u0027\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c8925297e875168a7c08965b4f80b418524fb8ce", "tree": "3694fb96964d728781203c3069053ec2b880d517", "parents": [ "07f6169cffdca076ef9a67bd69dd1085dc668618" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 12:20:51 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:47 2007 +0000" }, "message": "[MIPS] IP27: Fix build error.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "07f6169cffdca076ef9a67bd69dd1085dc668618", "tree": "e6cdd0aa35af0bd9f4ff24d1942d375e4caf6f42", "parents": [ "217dd11e9d0442767fa13c9c188be0b92dc93d7e" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 12:16:20 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:47 2007 +0000" }, "message": "[MIPS] Excite: Fix build error.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "217dd11e9d0442767fa13c9c188be0b92dc93d7e", "tree": "9557e15fbad397fcc5a707e85cf1a68132ee6c31", "parents": [ "f3f9ad0edcc1b7bf154bb34fe3b3f71e5379c9f0" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 01:57:55 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:47 2007 +0000" }, "message": "[MIPS] Sibyte: Split and move clock code.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f3f9ad0edcc1b7bf154bb34fe3b3f71e5379c9f0", "tree": "d553ebebfad8bf083342e6af704ae62ae252d0f2", "parents": [ "faf2782bf3903391936aba0b575fd39b1da10d00" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 00:24:50 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:47 2007 +0000" }, "message": "[MIPS] Sibyte: Fixes for oneshot timer mode.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "faf2782bf3903391936aba0b575fd39b1da10d00", "tree": "de4d64d1fd6b26c53791ad18e37b9efc11ba9a3b", "parents": [ "211a29a87cbde00d8c34fb6d92fc91a87c2c9b47" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Nov 01 00:10:07 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:47 2007 +0000" }, "message": "[MIPS] Sibyte: Remove blank line.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "211a29a87cbde00d8c34fb6d92fc91a87c2c9b47", "tree": "23c2670f9109cf6baf1cb092b094c6edebf6a9ab", "parents": [ "d9eec1a5d6ae54b0f7562ffe07008a33ac39e8fe" ], "author": { "name": "Thiemo Seufer", "email": "ths@networkno.de", "time": "Wed Oct 31 16:26:56 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:47 2007 +0000" }, "message": "[MIPS] Swarm: Fix build failure\n\nSigned-off-by: Thiemo Seufer \u003cths@networkno.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d9eec1a5d6ae54b0f7562ffe07008a33ac39e8fe", "tree": "2da898720a0240a778df00a0488db3f9593da190", "parents": [ "1d0a909cfc41f17175023b939b28322e427746b4" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Wed Oct 31 01:21:03 2007 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:46 2007 +0000" }, "message": "[MIPS] time: Code cleanups\n\n* Do not include unnecessary headers.\n* Do not mention time.README.\n* Do not mention mips_timer_ack.\n* Make clocksource_mips static. It is now dedicated to c0_timer.\n* Initialize clocksource_mips.read statically.\n* Remove null_hpt_read.\n* Remove an argument of plat_timer_setup. It is just a placeholder.\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "1d0a909cfc41f17175023b939b28322e427746b4", "tree": "c6451b458ad8658e03500532435c9d794a1ba063", "parents": [ "81b635ef368d994a86f20c0ea5a82f45045da1e9" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Oct 30 14:24:51 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:46 2007 +0000" }, "message": "[MIPS] time: Remove now unused local_timer_interrupt.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "81b635ef368d994a86f20c0ea5a82f45045da1e9", "tree": "15108ff3d707082be9442ef82b323476f45e1833", "parents": [ "46abf4b39a555294ec0df138923daed1ccb9adb5" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Oct 31 13:10:00 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:46 2007 +0000" }, "message": "[MIPS] IP32: Fix address of 2nd serial interface.\n\nFound by Giuseppe Sacco \u003cgiuseppe@eppesuigoccas.homedns.org\u003e.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "46abf4b39a555294ec0df138923daed1ccb9adb5", "tree": "211315bce777186654b098eb11ee6e76f765d4c2", "parents": [ "d1598b6adb0e7d9615f751f3bced128bcceb7378" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Oct 31 12:42:56 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:46 2007 +0000" }, "message": "[MIPS] SB1250: Use the right irqaction for the timer interrupt.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d1598b6adb0e7d9615f751f3bced128bcceb7378", "tree": "0006dbc03b05ae3e42e658ab5e2d8120967f96f4", "parents": [ "2e5dcd2b4ce97ebc43703f2645bf2fe978da1627" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Oct 31 12:36:42 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:46 2007 +0000" }, "message": "[MIPS] SB1250: Remove stray assignment of cpumask.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "2e5dcd2b4ce97ebc43703f2645bf2fe978da1627", "tree": "188c4aafc087e9632bb335b9d6af61149255555d", "parents": [ "9e32a510afa62c0d548d78572031e6112d21e0ea" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Oct 31 12:34:42 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:46 2007 +0000" }, "message": "[MIPS] Sibyte: Fix names of the clockevent devices.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "9e32a510afa62c0d548d78572031e6112d21e0ea", "tree": "02df5485ffc1b995011d0b694b75b2a45a6dc3d9", "parents": [ "54866f032307063776b4eff7eadb131d47f9f9b4" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Oct 31 00:08:06 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Nov 02 16:13:46 2007 +0000" }, "message": "[MIPS] Sibyte: Build fixes / dead code removal.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "1a3b7920fe55247d39c3e1ac1e9b8aca607d0188", "tree": "37e5d585cbdf5324c160bf456be417ed6a9ba491", "parents": [ "a76ab5c10d99bdf458067cb495e72c0ee5f09909" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 29 19:35:37 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 29 19:35:37 2007 +0000" }, "message": "[MIPS] tb0219: Update copyright message.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a76ab5c10d99bdf458067cb495e72c0ee5f09909", "tree": "6623ea1ee8c9a273afe1a05069f54b6ca745b91b", "parents": [ "a370605594bc9f375d2912096f01643c46b4b709" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 08 16:38:37 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 29 19:35:37 2007 +0000" }, "message": "[MIPS] MT: Fix bug in multithreaded kernels.\n\nWhen GDB writes a breakpoint into address area of inferior process the\nkernel needs to invalidate the modified memory in the inferior which\nis done by calling flush_cache_page which in turns calls\nr4k_flush_cache_page and local_r4k_flush_cache_page for VSMP or SMTC\nkernel via r4k_on_each_cpu().\n\nAs the VSMP and SMTC SMP kernels for 34K are running on a single shared\ncaches it is possible to get away without interprocessor function calls.\nThis optimization is implemented in r4k_on_each_cpu, so\nlocal_r4k_flush_cache_page is only ever called on the local CPU.\n\nThis is where the following code in local_r4k_flush_cache_page() strikes:\n\n /*\n * If ownes no valid ASID yet, cannot possibly have gotten\n * this page into the cache.\n */\n if (cpu_context(smp_processor_id(), mm) \u003d\u003d 0)\n return;\n\nOn VSMP and SMTC had a function of cpu_context() for each CPU(TC).\n\nSo in case another CPU than the CPU executing local_r4k_cache_flush_page\nhas not accessed the mm but one of the other CPUs has there may be data\nto be flushed in the cache yet local_r4k_cache_flush_page will falsely\nreturn leaving the I-cache inconsistent for the breakpoint.\n\nWhile the issue was discovered with GDB it also exists in\nlocal_r4k_flush_cache_range() and local_r4k_flush_cache().\n\nFixed by introducing a new function has_valid_asid which on MT kernels\nreturns true if a mm is active on any processor in the system.\n\nThis is relativly expensive since for memory acccesses in that loop\ncache misses have to be assumed but it seems the most viable solution\nfor 2.6.23 and older -stable kernels.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a370605594bc9f375d2912096f01643c46b4b709", "tree": "fec6407440a4968692c5b8d685fc2c4f27add773", "parents": [ "1553f6a2ca53b0d723f21d915fdd3d2cf7c8f852" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 29 19:35:37 2007 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 29 19:35:37 2007 +0000" }, "message": "[MIPS] Alchemy: Remove CONFIG_TS_AU1X00_ADS7846 from defconfigs.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "1553f6a2ca53b0d723f21d915fdd3d2cf7c8f852", "tree": "24ff29e3460c3ec133f9cdac154cb30e1e04d570", "parents": [ "d9ba26a93a691df24fa520dc47ee9f6f05014bf1" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Oct 09 15:15:21 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 29 19:35:37 2007 +0000" }, "message": "Author: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\n[MIPS] MSP71xx: Fix bitrot.\n \nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d9ba26a93a691df24fa520dc47ee9f6f05014bf1", "tree": "ea9ff61d256d2b25419d452e9f006fdf8d857061", "parents": [ "16be243589934f5e76f7fc2c3eb65c9909d56f93" ], "author": { "name": "Maciej W. Rozycki", "email": "macro@linux-mips.org", "time": "Fri Oct 12 16:46:56 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 29 19:35:37 2007 +0000" }, "message": "[MIPS] sb1250: Enable GenBus IDE in defconfig.\n\nEnable the onboard GenBus IDE interface in the default configuration.\n\nSigned-off-by: Maciej W. Rozycki \u003cmacro@linux-mips.org\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "16be243589934f5e76f7fc2c3eb65c9909d56f93", "tree": "f9a39fe5946f90469bc474dc6cecdd2481ed12ae", "parents": [ "21b2aecaae3a46a13dbe775639e7d060bec033bd" ], "author": { "name": "Franck Bui-Huu", "email": "fbuihuu@gmail.com", "time": "Thu Oct 18 23:12:32 2007 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 29 19:35:37 2007 +0000" }, "message": "[MIPS] vmlinux.ld.S: correctly indent .data section\n\nSigned-off-by: Franck Bui-Huu \u003cfbuihuu@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "21b2aecaae3a46a13dbe775639e7d060bec033bd", "tree": "d0a1bed8b37ec3cf79ff08a47ebb1a820158ef90", "parents": [ "62b14c24b10033591bbab16dea165d696a616f37" ], "author": { "name": "Maciej W. Rozycki", "email": "macro@linux-mips.org", "time": "Wed Oct 17 11:51:39 2007 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 29 19:35:36 2007 +0000" }, "message": "[MIPS] c-r3k: Implement flush_cache_range()\n\nContrary to the belief of some, the R3000 and related processors did have\ncaches, both a data and an instruction cache. Here is an implementation\nof r3k_flush_cache_page(), which is the processor-specific back-end for\nflush_cache_range(), done according to the spec in\nDocumentation/cachetlb.txt.\n\nWhile at it, remove an unused local function: get_phys_page(), do some\ntrivial formatting fixes and modernise debugging facilities.\n\nSigned-off-by: Maciej W. Rozycki \u003cmacro@linux-mips.org\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "62b14c24b10033591bbab16dea165d696a616f37", "tree": "838b49148ee2a558d71d8ab7dc92b2e6b230d53b", "parents": [ "26c288f82c74dba08da6321c626c101a7aa8575b" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Fri Oct 26 00:53:02 2007 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 29 19:35:36 2007 +0000" }, "message": "[MIPS] Store sign-extend register values for PTRACE_GETREGS\n\nA comment on ptrace_getregs() states \"Registers are sign extended to\nfill the available space.\" but it is not true. Fix code to match the\ncomment. Also fix casts on each caller to get rid of some warnings.\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "26c288f82c74dba08da6321c626c101a7aa8575b", "tree": "c92dda5bd85d3f6d21c80f6d1816b8575bc860b8", "parents": [ "098362e72002d01fdd18afee2e635ffdcdc89e2c" ], "author": { "name": "Florian Fainelli", "email": "florian.fainelli@telecomint.eu", "time": "Tue Oct 23 18:55:55 2007 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 29 19:35:36 2007 +0000" }, "message": "[MIPS] Alchemy: Register platform devices\n\nThis patch separates the platform devices registration for the MTX-1\nspecific devices: GPIO leds and watchdog.\n\n[Minor fixup and formatting change -- Ralf]\n\nSigned-off-by: Florian Fainelli \u003cflorian.fainelli@telecomint.eu\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" } ], "next": "098362e72002d01fdd18afee2e635ffdcdc89e2c" }