)]}'
{
  "log": [
    {
      "commit": "10cd706d180b62a61aace5b440247c8785026ac1",
      "tree": "4bc544761719fd10ecfa977e6f4bfd8f1249d8b9",
      "parents": [
        "c7e872e7da5514d014707a407ea562d197cc0136"
      ],
      "author": {
        "name": "Peter Zijlstra",
        "email": "a.p.zijlstra@chello.nl",
        "time": "Thu Oct 11 22:11:12 2007 +0200"
      },
      "committer": {
        "name": "Peter Zijlstra",
        "email": "a.p.zijlstra@chello.nl",
        "time": "Thu Oct 11 22:11:12 2007 +0200"
      },
      "message": "lockdep: x86_64: connect the sysexit hook\n\nRun the lockdep_sys_exit hook after all other C code on the syscall\nreturn path.\n\nSigned-off-by: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n"
    },
    {
      "commit": "c7e872e7da5514d014707a407ea562d197cc0136",
      "tree": "eab8cc63a0ef14afbaa9b61153f30f7ed1a94e6f",
      "parents": [
        "b351d164e860d1ffffdc501c32f55dd1446c385b"
      ],
      "author": {
        "name": "Peter Zijlstra",
        "email": "a.p.zijlstra@chello.nl",
        "time": "Thu Oct 11 22:11:12 2007 +0200"
      },
      "committer": {
        "name": "Peter Zijlstra",
        "email": "a.p.zijlstra@chello.nl",
        "time": "Thu Oct 11 22:11:12 2007 +0200"
      },
      "message": "lockdep: i386: connect the sysexit hook\n\nRun the lockdep_sys_exit hook after all other C code on the syscall\nreturn path.\n\nSigned-off-by: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n"
    },
    {
      "commit": "3749c66c67fb5c257771815c186bc32290cacf44",
      "tree": "de6634f722a9b79c60fabbd605660e46741f7160",
      "parents": [
        "835c34a1687f524c37d4fb8bad18d642c74bed8d",
        "8a45450d0a559912873428077908f9bc1411042c"
      ],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Sat Oct 13 10:02:11 2007 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Sat Oct 13 10:02:11 2007 -0700"
      },
      "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm: (106 commits)\n  KVM: Replace enum by #define\n  KVM: Skip pio instruction when it is emulated, not executed\n  KVM: x86 emulator: popf\n  KVM: x86 emulator: fix src, dst value initialization\n  KVM: x86 emulator: jmp abs\n  KVM: x86 emulator: lea\n  KVM: X86 emulator: jump conditional short\n  KVM: x86 emulator: imlpement jump conditional relative\n  KVM: x86 emulator: sort opcodes into ascending order\n  KVM: Improve emulation failure reporting\n  KVM: x86 emulator: pushf\n  KVM: x86 emulator: call near\n  KVM: x86 emulator: push imm8\n  KVM: VMX: Fix exit qualification width on i386\n  KVM: Move main vcpu loop into subarch independent code\n  KVM: VMX: Move vm entry failure handling to the exit handler\n  KVM: MMU: Don\u0027t do GFP_NOWAIT allocations\n  KVM: Rename kvm_arch_ops to kvm_x86_ops\n  KVM: Simplify memory allocation\n  KVM: Hoist SVM\u0027s get_cs_db_l_bits into core code.\n  ...\n"
    },
    {
      "commit": "2b8232ce512105e28453f301d1510de8363bccd1",
      "tree": "13e15a4f629c72b8737e20221998cb1e55e98d58",
      "parents": [
        "c4ea43c552ecc9ccc564e11e70d397dbdf09484b"
      ],
      "author": {
        "name": "Al Viro",
        "email": "viro@ftp.linux.org.uk",
        "time": "Sat Oct 13 08:16:04 2007 +0100"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Sat Oct 13 09:57:15 2007 -0700"
      },
      "message": "minimal build fixes for uml (fallout from x86 merge)\n\n a) include/asm-um/arch can\u0027t just point to include/asm-$(SUBARCH) now\n b) arch/{i386,x86_64}/crypto are merged now\n c) subarch-obj needed changes\n d) cpufeature_64.h should pull \"cpufeature_32.h\", not \u003casm/cpufeature_32.h\u003e\n    since it can be included from asm-um/cpufeature.h\n e) in case of uml-i386 we need CONFIG_X86_32 for make and gcc, but not\n    for Kconfig\n f) sysctl.c shouldn\u0027t do vdso_enabled for uml-i386 (actually, that one\n    should be registered from corresponding arch/*/kernel/*, with ifdef\n    going away; that\u0027s a separate patch, though).\n\nWith that and with Stephen\u0027s patch (\"[PATCH net-2.6] uml: hard_header fix\")\nwe have uml allmodconfig building both on i386 and amd64.\n\nSigned-off-by: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "7075bc816cfad142da92207ed5a6f3da55b143ef",
      "tree": "d7b7581a9968d89fac5587d2378390b5939d28ec",
      "parents": [
        "8fc0d085f521a2a76418f8f569cf1cd27f0e43d4"
      ],
      "author": {
        "name": "Rusty Russell",
        "email": "rusty@rustcorp.com.au",
        "time": "Tue Jul 17 23:37:17 2007 +1000"
      },
      "committer": {
        "name": "Avi Kivity",
        "email": "avi@qumranet.com",
        "time": "Sat Oct 13 10:18:19 2007 +0200"
      },
      "message": "KVM: Use standard CR8 flags, and fix TPR definition\n\nIntel manual (and KVM definition) say the TPR is 4 bits wide.  Also fix\nCR8_RESEVED_BITS typo.\n\nSigned-off-by: Rusty Russell \u003crusty@rustcorp.com.au\u003e\nAcked-by: H. Peter Anvin \u003chpa@zytor.com\u003e\nSigned-off-by: Avi Kivity \u003cavi@qumranet.com\u003e\n"
    },
    {
      "commit": "81fe96bde7db24c02adf245604f073ea9e8d941a",
      "tree": "355cb6fe27a1b37715049cf7b0f924bb48f289c3",
      "parents": [
        "752097cec53eea111d087c545179b421e2bde98a"
      ],
      "author": {
        "name": "Avi Kivity",
        "email": "avi@qumranet.com",
        "time": "Thu Sep 27 10:07:04 2007 +0200"
      },
      "committer": {
        "name": "Avi Kivity",
        "email": "avi@qumranet.com",
        "time": "Sat Oct 13 10:18:17 2007 +0200"
      },
      "message": "i386: Expose IOAPIC register definitions even if CONFIG_X86_IO_APIC is not set\n\nKVM reuses the IOAPIC register definitions, and needs them even if the\nhost is not compiled with IOAPIC support.  Move the #ifdef below so that only\nthe IOAPIC variables and functions are protected, and the register definitions\nare available to all.\n\nSigned-off-by: Avi Kivity \u003cavi@qumranet.com\u003e\n"
    },
    {
      "commit": "b6c7347fffa655a3000d9d41640d222c19fc3065",
      "tree": "ef1789ab0656997f0491e051b92cf833948f2307",
      "parents": [
        "4071c718555d955a35e9651f77086096ad87d498"
      ],
      "author": {
        "name": "Nick Piggin",
        "email": "npiggin@suse.de",
        "time": "Sat Oct 13 03:07:38 2007 +0200"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Fri Oct 12 18:41:21 2007 -0700"
      },
      "message": "x86: optimise barriers\n\nAccording to latest memory ordering specification documents from Intel\nand AMD, both manufacturers are committed to in-order loads from\ncacheable memory for the x86 architecture.  Hence, smp_rmb() may be a\nsimple barrier.\n\nAlso according to those documents, and according to existing practice in\nLinux (eg.  spin_unlock doesn\u0027t enforce ordering), stores to cacheable\nmemory are visible in program order too.  Special string stores are safe\n-- their constituent stores may be out of order, but they must complete\nin order WRT surrounding stores.  Nontemporal stores to WB memory can go\nout of order, and so they should be fenced explicitly to make them\nappear in-order WRT other stores.  Hence, smp_wmb() may be a simple\nbarrier.\n\n    http://developer.intel.com/products/processor/manuals/318147.pdf\n    http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf\n\nIn userspace microbenchmarks on a core2 system, fence instructions range\nanywhere from around 15 cycles to 50, which may not be totally\ninsignificant in performance critical paths (code size will go down\ntoo).\n\nHowever the primary motivation for this is to have the canonical barrier\nimplementation for x86 architecture.\n\nsmp_rmb on buggy pentium pros remains a locked op, which is apparently\nrequired.\n\nSigned-off-by: Nick Piggin \u003cnpiggin@suse.de\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "4071c718555d955a35e9651f77086096ad87d498",
      "tree": "5189a9995143892a8ef7ecfc04c11c1d546bc21b",
      "parents": [
        "df1bdc0667eb3132fe60b3562347ca9133694ee0"
      ],
      "author": {
        "name": "Nick Piggin",
        "email": "npiggin@suse.de",
        "time": "Sat Oct 13 03:06:55 2007 +0200"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Fri Oct 12 18:41:21 2007 -0700"
      },
      "message": "x86: fix IO write barrier\n\nwmb() on x86 must always include a barrier, because stores can go out of\norder in many cases when dealing with devices (eg. WC memory).\n\nSigned-off-by: Nick Piggin \u003cnpiggin@suse.de\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "6a84258e5f5bb8b9bd72e06a5837fa6fdacaf5c5",
      "tree": "3c4911a489c85e908b0ef3ed83d78264788f858c",
      "parents": [
        "efefc6eb38d43b8e5daef482f575d767b002004e",
        "f3e6f164c2389853432454c89b316a8ab7485e2f"
      ],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Fri Oct 12 15:50:23 2007 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Fri Oct 12 15:50:23 2007 -0700"
      },
      "message": "Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6\n\n* master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6: (37 commits)\n  PCI: merge almost all of pci_32.h and pci_64.h together\n  PCI: X86: Introduce and enable PCI domain support\n  PCI: Add \u0027nodomains\u0027 boot option, and pci_domains_supported global\n  PCI: modify PCI bridge control ISA flag for clarity\n  PCI: use _CRS for PCI resource allocation\n  PCI: avoid P2P prefetch window for expansion ROMs\n  PCI: skip ISA ioresource alignment on some systems\n  PCI: remove transparent bridge sizing\n  pci: write file size to inode on proc bus file write\n  pci: use size stored in proc_dir_entry for proc bus files\n  pci: implement \"pci\u003dnoaer\"\n  PCI: fix IDE legacy mode resources\n  MSI: Use correct data offset for 32-bit MSI in read_msi_msg()\n  PCI: Fix incorrect argument order to list_add_tail() in PCI dynamic ID code\n  PCI: i386: Compaq EVO N800c needs PCI bus renumbering\n  PCI: Remove no longer correct documentation regarding MSI vector assignment\n  PCI: re-enable onboard sound on \"MSI K8T Neo2-FIR\"\n  PCI: quirk_vt82c586_acpi: Omit reading PCI revision ID\n  PCI: quirk amd_8131_mmrbc: Omit reading pci revision ID\n  cpqphp: Use PCI_CLASS_REVISION instead of PCI_REVISION_ID for read\n  ...\n"
    },
    {
      "commit": "f3e6f164c2389853432454c89b316a8ab7485e2f",
      "tree": "0e3074fae2e0563def88f9b50e3441f864517b1d",
      "parents": [
        "a79e4198d1effbba040e9bf407a95fc9b3418789"
      ],
      "author": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Fri Oct 12 14:07:23 2007 -0700"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Fri Oct 12 15:03:20 2007 -0700"
      },
      "message": "PCI: merge almost all of pci_32.h and pci_64.h together\n\nIt was just duplicated code...\n\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n"
    },
    {
      "commit": "a79e4198d1effbba040e9bf407a95fc9b3418789",
      "tree": "bbfeed15db3a03c3e7f50ae36f18c017fb940b9e",
      "parents": [
        "32a2eea795643929a43cbbba00d8c4a176b309bf"
      ],
      "author": {
        "name": "Jeff Garzik",
        "email": "jeff@garzik.org",
        "time": "Thu Oct 11 16:58:30 2007 -0400"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Fri Oct 12 15:03:19 2007 -0700"
      },
      "message": "PCI: X86: Introduce and enable PCI domain support\n\n* fix bug in pci_read() and pci_write() which prevented PCI domain\n  support from working (hardcoded domain 0).\n\n* unconditionally enable CONFIG_PCI_DOMAINS\n\n* implement pci_domain_nr() and pci_proc_domain(), as required of\n  all arches when CONFIG_PCI_DOMAINS is enabled.\n\n* store domain in struct pci_sysdata, as assigned by ACPI\n\n* support \"pci\u003dnodomains\"\n\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n"
    },
    {
      "commit": "bfe0c1cc6456bba1f4e3cc1fe29c0ea578ac763a",
      "tree": "7bf60e24749a33fdac079a9c9829da24cf468e00",
      "parents": [
        "59c69f2a51b41e9886b85f61c04e8d0d2a35f37b"
      ],
      "author": {
        "name": "Venki Pallipadi",
        "email": "venkatesh.pallipadi@intel.com",
        "time": "Fri Oct 12 23:04:24 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:24 2007 +0200"
      },
      "message": "x86: HPET force enable for ICH5\n\nforce_enable hpet for ICH5.\n\n[ Build fixes from Andrew Morton ]\n\nSigned-off-by: Venkatesh Pallipadi \u003cvenkatesh.pallipadi@intel.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: john stultz \u003cjohnstul@us.ibm.com\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "59c69f2a51b41e9886b85f61c04e8d0d2a35f37b",
      "tree": "3512523870b3a34a976777c2cb332bd29d7aab59",
      "parents": [
        "d54bd57d6580250e6551261f3b15c45a9d90c77b"
      ],
      "author": {
        "name": "Venki Pallipadi",
        "email": "venkatesh.pallipadi@intel.com",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "message": "x86: HPET try to activate force detected hpet\n\nEnable HPET later during boot, after the force detect in PCI quirks.  Also add\na call to repeat the force enabling at resume time.\n\nSigned-off-by: Venkatesh Pallipadi \u003cvenkatesh.pallipadi@intel.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: john stultz \u003cjohnstul@us.ibm.com\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "d54bd57d6580250e6551261f3b15c45a9d90c77b",
      "tree": "12cb06b4adb9494e67cefdc691643e333fef3b91",
      "parents": [
        "610bf2f143b9c5cda768a2d428d66d3a16769930"
      ],
      "author": {
        "name": "Venki Pallipadi",
        "email": "venkatesh.pallipadi@intel.com",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "message": "x86: HPET force enable o ICH7 and later\n\nForce detect and/or enable HPET on ICH chipsets.  This patch just handles the\ndetection part and following patches use this information.  Adds a function to\nrepeat the force enabling during resume time.\n\nUsing HPET this way, instead of PIT increases the time CPUs can reside in\nC-state when system is totally idle.  On my test system with Core 2 Duo,\naverage C-state residency goes up from ~20mS to ~80mS.\n\n[ Build fixed from Andrew Morton ]\n\nSigned-off-by: Venkatesh Pallipadi \u003cvenkatesh.pallipadi@intel.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: john stultz \u003cjohnstul@us.ibm.com\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "31c435d75e7d15a5f965c5eb0e33fe0e236f49a4",
      "tree": "800c8fe9722e34bfbf3ba52c2393b22264ba4bed",
      "parents": [
        "39d0b7ba7b9c0a2c594073400cde1d0beffa0bea"
      ],
      "author": {
        "name": "Chris Wright",
        "email": "chrisw@sous-sol.org",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "message": "i386/x8664: cleanup the shared hpet code\n\nRemove hpet_readl/writel from vsyscall.h, where it does not belong\nanyway. Use the hpet code itself.\n\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "39d0b7ba7b9c0a2c594073400cde1d0beffa0bea",
      "tree": "5809ffeaf92a22e9eec7a8a019df3c836d00378a",
      "parents": [
        "43ca7ec96f01bd921e772112729005d4474fdbf4"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "message": "i386: Remove the useless #ifdef in i8253.h\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "9f75e9b74a45d7d3c343c8979f49d5e6b92bbce3",
      "tree": "ca7115bd03031db131dda5912e2d9cd302046608",
      "parents": [
        "2f0798a3b1c2155b8f30858e853557aef9da2e4e"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "message": "x86_64: remove now unused code\n\nRemove the unused code after the switch to clock events.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "2f0798a3b1c2155b8f30858e853557aef9da2e4e",
      "tree": "a7a8c08d84dea9bef33e02eeccd499a6e8f6fc75",
      "parents": [
        "5d5a2989b72847e1f5763420ea31383ca63ebf53"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "message": "x86: unify timex.h variants\n\nCombine the timex.h variants and move the TSC related code into tsc.h.\nMove the set_cyc2ns_scale() call into the tsc calibraction code, where\nit belongs.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "5d5a2989b72847e1f5763420ea31383ca63ebf53",
      "tree": "8eacc41a879de2a1d72699e1a15f2e0d2f612650",
      "parents": [
        "fb79d22e1d4b06385796cc0db0084a2e07beccee"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:23 2007 +0200"
      },
      "message": "x86: kill 8253pit.h\n\nUseless header file with 32 bit and 64 bit variants. Move the\nsingle useful line to the place where it is used.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "fb79d22e1d4b06385796cc0db0084a2e07beccee",
      "tree": "f62b850b9b8ee1b7a4264b29e30fd7c360e23c94",
      "parents": [
        "4e77ae3e105d28aa9410585715d83818f0abe871"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Oct 12 23:04:07 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:07 2007 +0200"
      },
      "message": "x86: disable apic timer for AMD C1E enabled CPUs\n\nAMDs C1E enabled CPUs stop the local apic timer, when both cores are\nidle. This is a hardware feature which breaks highres/dynticks.\nAdd the same quirk as we have for 32 bit already.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "4e77ae3e105d28aa9410585715d83818f0abe871",
      "tree": "4ba47b6741a1d941908b4d73394ffbbd4a37ac73",
      "parents": [
        "b8ce33590687888ebb900d09557b8807c4539022"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Oct 12 23:04:07 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:07 2007 +0200"
      },
      "message": "x86: Fix irq0 / local apic timer accounting\n\nThe clock events merge introduced a change to the nmi watchdog code to\nhandle the not longer increasing local apic timer count in the\nbroadcast mode. This is fine for UP, but on SMP it pampers over a\nstuck CPU which is not handling the broadcast interrupt due to the\nunconditional sum up of local apic timer count and irq0 count.\n\nTo cover all cases we need to keep track on which CPU irq0 is\nhandled. In theory this is CPU#0 due to the explicit disabling of irq\nbalancing for irq0, but there are systems which ignore this on the\nhardware level. The per cpu irq0 accounting allows us to remove the\nirq0 to CPU0 binding as well.\n\nAdd a per cpu counter for irq0 and evaluate this instead of the global\nirq0 count in the nmi watchdog code.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "b8ce33590687888ebb900d09557b8807c4539022",
      "tree": "0e51543c7d4febff8ff6ad7660268bea2035f9ce",
      "parents": [
        "ba7eda4c60e1d070b2f6586d42719ec1d5302d3b"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Oct 12 23:04:07 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:07 2007 +0200"
      },
      "message": "x86_64: convert to clock events\n\nFinally switch to the clockevents code. Share code with i386 for\nhpet and PIT.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "7ffeeb1e03c4fc1c7e8434c5496018dd035f8924",
      "tree": "85be569203f1dffc9a4a96811a36e6e161e88c40",
      "parents": [
        "0190dae54de62fbb9ced75d134015266987eb6b8"
      ],
      "author": {
        "name": "Yinghai Lu",
        "email": "yhlu.kernel@gmail.com",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "message": "x86: remove never used apic_mapped\n\n[ tglx: arch/x86 adaptation ]\n\nSigned-off-by: Yinghai Lu \u003cyhlu.kernel@gmail.com\u003e\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nCc: Christoph Lameter \u003cclameter@sgi.com\u003e\nCc: Len Brown \u003clenb@kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n\n"
    },
    {
      "commit": "0190dae54de62fbb9ced75d134015266987eb6b8",
      "tree": "5ae8ac1d0da98e39535c8bffd904a9e2c0311e40",
      "parents": [
        "f5e0e93faf8421083853b2d7a217267f49e27cc3"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "message": "i386: prepare sharing the PIT code\n\nPIT clock events work already and the PIT handling is the same for\ni386 and x86_64. x86_64 does not support PIT as a clock source, so\ndisable the PIT clocksource for x86_64.\n\nUse the i386 i8253.h include file for x86_64 as well to share the\nexports and the PIT constants.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "f5e0e93faf8421083853b2d7a217267f49e27cc3",
      "tree": "07feecfe09654c49a9f21ed93616793003a9f49c",
      "parents": [
        "28769149c285e0a392d2e601ae0cc71ffc345f7d"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "message": "i386: prepare sharing the PIT code\n\nPIT clock events work already and the PIT handling is the same for\ni386 and x86_64. x86_64 does not support PIT as a clock source, so\ndisable the PIT clocksource for x86_64.\n\nPrepare i8253.h to be shared with x8664\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "d371698efd45c3664fd1726780c360f02e1f9580",
      "tree": "f6c45126c49f35a62520b89d1bc74fca1a6f9ff9",
      "parents": [
        "89b2bbd69b89b4c5efdc112a88d72419bdeb8dfc"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "message": "x86_64: Consolidate tsc calibration\n\nMove the TSC calibration code to tsc.c. Reimplement it so the\npm timer can be used as a reference as well.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "83d7384f8d4aa216b49cf9cb286ea743054b119f",
      "tree": "9f56bf83bbbb0dc7056c3dd5e11b1d0ab0d4cefb",
      "parents": [
        "5fa3a246ea2e1be2ffaa01343bc183c8c0bfa472"
      ],
      "author": {
        "name": "Andres Salomon",
        "email": "dilinger@queued.net",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "message": "x86: Geode Multi-Function General Purpose Timers support\n\nThis adds support for Multi-Function General Purpose Timers.  It detects the\navailable timers during southbridge init, and provides an API for allocating\nand setting the timers.  They\u0027re higher resolution than the standard PIT, so\nthe MFGPTs come in handy for quite a few things.\n\nNote that we never clobber the timers that the BIOS might have opted to use;\nwe just check for unused timers.\n\nSigned-off-by: Jordan Crouse \u003cjordan.crouse@amd.com\u003e\nSigned-off-by: Andres Salomon \u003cdilinger@debian.org\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: Alan Cox \u003calan@lxorguk.ukuu.org.uk\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "3c9aea47425885ec8b1f7b0df88c2ebc6f747c9d",
      "tree": "17fefa5b3d6cef5f92ac07551ae27c3228c970ff",
      "parents": [
        "c8a1d398de70a7774359b4720c392891cdd485f9"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@inhelltoy.tec.linutronix.de",
        "time": "Fri Oct 12 23:04:06 2007 +0200"
      },
      "message": "x86: Fix irq0 / local apic timer accounting\n\nThe clock events merge introduced a change to the nmi watchdog code to\nhandle the not longer increasing local apic timer count in the\nbroadcast mode. This is fine for UP, but on SMP it pampers over a\nstuck CPU which is not handling the broadcast interrupt due to the\nunconditional sum up of local apic timer count and irq0 count.\n\nTo cover all cases we need to keep track on which CPU irq0 is\nhandled. In theory this is CPU#0 due to the explicit disabling of irq\nbalancing for irq0, but there are systems which ignore this on the\nhardware level. The per cpu irq0 accounting allows us to remove the\nirq0 to CPU0 binding as well.\n\nAdd a per cpu counter for irq0 and evaluate this instead of the global\nirq0 count in the nmi watchdog code.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\n\n"
    },
    {
      "commit": "96a388de5dc53a8b234b3fd41f3ae2cedc9ffd42",
      "tree": "d947a467aa2da3140279617bc4b9b101640d7bf4",
      "parents": [
        "27bd0c955648646abf2a353a8371d28c37bcd982"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Thu Oct 11 11:20:03 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Thu Oct 11 11:20:03 2007 +0200"
      },
      "message": "i386/x86_64: move headers to include/asm-x86\n\nMove the headers to include/asm-x86 and fixup the\nheader install make rules\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n"
    }
  ]
}