)]}' { "log": [ { "commit": "6020dff09252e3670a89edb36baaa4afb9b10d15", "tree": "e242232e97e71045f51bda9e0a5bb2e8f8df1c29", "parents": [ "a6f36be32622730710b2fadacb6e2649defa4371" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Dec 30 23:17:40 2006 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 08 19:49:58 2007 +0000" }, "message": "[ARM] Resolve fuse and direct-IO failures due to missing cache flushes\n\nfuse does not work on ARM due to cache incoherency issues - fuse wants\nto use get_user_pages() to copy data from the current process into\nkernel space. However, since this accesses userspace via the kernel\nmapping, the kernel mapping can be out of date wrt data written to\nuserspace.\n\nThis can lead to unpredictable behaviour (in the case of fuse) or data\ncorruption for direct-IO.\n\nThis resolves debian bug #402876\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "1c9d3df5e88ad7db23f5b22f4341c39722a904a4", "tree": "dbabefd52a5f8a5f35216bda33f29e4b9b398569", "parents": [ "b0b1d60a64054697ef828e0565f006cc0f823590" ], "author": { "name": "Richard Purdie", "email": "rpurdie@rpsys.net", "time": "Sat Dec 30 16:08:50 2006 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 30 17:05:08 2006 +0000" }, "message": "[ARM] 4078/1: Fix ARM copypage cache coherency problems\n\nIf PG_dcache_dirty is set for a page, we need to flush the source page\nbefore performing any copypage operation using a different virtual address.\n\nThis fixes the copypage implementations for XScale, StrongARM and ARMv6.\n\nThis patch fixes segmentation faults seen in the dynamic linker under\nthe usage patterns in glibc 2.4/2.5.\n\nSigned-off-by: Richard Purdie \u003crpurdie@rpsys.net\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ec8c0446b6e2b67b5c8813eb517f4bf00efa99a9", "tree": "e7c12d7c486c958a5e38888b41cfcd6a558f1aff", "parents": [ "bcd022801ee514e28c32837f0b3ce18c775f1a7b" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Dec 12 17:14:57 2006 +0000" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.osdl.org", "time": "Wed Dec 13 09:27:08 2006 -0800" }, "message": "[PATCH] Optimize D-cache alias handling on fork\n\nVirtually index, physically tagged cache architectures can get away\nwithout cache flushing when forking. This patch adds a new cache\nflushing function flush_cache_dup_mm(struct mm_struct *) which for the\nmoment I\u0027ve implemented to do the same thing on all architectures\nexcept on MIPS where it\u0027s a no-op.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "6cc7cbef948ea2660cc40d7aab090a479f7db6a2", "tree": "7f755b98add50c5bca9b6c4410baa4d7bd555b79", "parents": [ "6b237a355afd342509f1471e0c338637bcd958bc" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Wed Sep 27 18:00:35 2006 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Sep 27 18:00:35 2006 +0100" }, "message": "[ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h\n\nThree of the generic cache method options were using explicit CPU\ntypes, whereas they could use the CPU_CACHE_* definitions instead.\nSwitch them over to use the CPU_CACHE_* definitions.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f37f46eb1c0bd0b11c34ef06c7365658be989d80", "tree": "1790995456cafc852899927140e5dd7523463fdb", "parents": [ "d60674eb5d961b2421db16cc373dc163f38cc105" ], "author": { "name": "Hyok S. Choi", "email": "hyok.choi@samsung.com", "time": "Tue Sep 26 17:38:32 2006 +0900" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Sep 27 17:39:19 2006 +0100" }, "message": "[ARM] nommu: add ARM946E-S core support\n\nThis patch adds ARM946E-S core support which has typically 8KB I\u0026D cache.\nIt has a MPU and supports ARMv5TE instruction set.\n\nBecause the ARM946E-S core can be synthesizable with various cache size,\nCONFIG_CPU_DCACHE_SIZE is defined for vendor specific configurations.\n\nSigned-off-by: Hyok S. Choi \u003chyok.choi@samsung.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d60674eb5d961b2421db16cc373dc163f38cc105", "tree": "f2d6e9fad27cd132e5a45f88350f80cae7444e5c", "parents": [ "43f5f0146ef5c3a3421ea53a0708fd37edcb8905" ], "author": { "name": "Hyok S. Choi", "email": "hyok.choi@samsung.com", "time": "Tue Sep 26 17:38:18 2006 +0900" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Sep 27 17:39:18 2006 +0100" }, "message": "[ARM] nommu: add ARM940T core support\n\nThis patch adds ARM940T core support which has 4KB D-cache, 4KB I-cache\nand a MPU.\n\nSigned-off-by: Hyok S. Choi \u003chyok.choi@samsung.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "43f5f0146ef5c3a3421ea53a0708fd37edcb8905", "tree": "9bc8d546aa0d801f28ef882937af929b0f4f22d3", "parents": [ "b731c3118d87f26c8bf3f358ffbbc24450af50a6" ], "author": { "name": "Hyok S. Choi", "email": "hyok.choi@samsung.com", "time": "Tue Sep 26 17:38:05 2006 +0900" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Sep 27 17:39:17 2006 +0100" }, "message": "[ARM] nommu: add ARM9TDMI core support\n\nThis patch adds ARM9TDMI core support which has no cache and no CP15\nregister(no memory control unit).\n\nSigned-off-by: Hyok S. Choi \u003chyok.choi@samsung.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b731c3118d87f26c8bf3f358ffbbc24450af50a6", "tree": "63e280a475d81eb39c16a7fbd4cd12568b4e1f1e", "parents": [ "07e0da78abdc679714a12e7a60137d950c346681" ], "author": { "name": "Hyok S. Choi", "email": "hyok.choi@samsung.com", "time": "Tue Sep 26 17:37:50 2006 +0900" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Sep 27 17:39:17 2006 +0100" }, "message": "[ARM] nommu: add ARM740T core support\n\nThis patch adds ARM740T core support which has a MPU and 4KB or 8KB cache.\n\nSigned-off-by: Hyok S. Choi \u003chyok.choi@samsung.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "07e0da78abdc679714a12e7a60137d950c346681", "tree": "5a6e759c1063d8ec5113c37f72a906c7db711307", "parents": [ "f12d0d7c7786af39435ef6ae9defe47fb58f6091" ], "author": { "name": "Hyok S. Choi", "email": "hyok.choi@samsung.com", "time": "Tue Sep 26 17:37:36 2006 +0900" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Sep 27 17:39:17 2006 +0100" }, "message": "[ARM] nommu: add ARM7TDMI core support\n\nThis patch adds ARM7TDMI core support which has no cache and no CP15\nregister(no memory control unit).\n\nSigned-off-by: Hyok S. Choi \u003chyok.choi@samsung.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a188ad2bc7dbfa16ccdcaa8d43ade185b969baff", "tree": "7938fff8dded204e92bd7c3149875abb8d7060aa", "parents": [ "57bcdafcb1e0782e7ae13471d9223c69e3a6cba2" ], "author": { "name": "George G. Davis", "email": "davis_g@mvista.com", "time": "Sat Sep 02 18:43:20 2006 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Sep 02 18:43:20 2006 +0100" }, "message": "[ARM] 3762/1: Fix ptrace cache coherency bug for ARM1136 VIPT nonaliasing Harvard caches\n\nPatch from George G. Davis\n\nResolve ARM1136 VIPT non-aliasing cache coherency issues observed when\nusing ptrace to set breakpoints and cleanup copy_{to,from}_user_page()\nwhile we\u0027re here as requested by Russell King because \"it\u0027s also far\ntoo heavy on non-v6 CPUs\".\n\nNOTES:\n\n1. Only access_process_vm() calls copy_{to,from}_user_page().\n2. access_process_vm() calls get_user_pages() to pin down the \"page\".\n3. get_user_pages() calls flush_dcache_page(page) which ensures cache\n coherency between kernel and userspace mappings of \"page\". However\n flush_dcache_page(page) may not invalidate I-Cache over this range\n for all cases, specifically, I-Cache is not invalidated for the VIPT\n non-aliasing case. So memory is consistent between kernel and user\n space mappings of \"page\" but I-Cache may still be hot over this\n range. IOW, we don\u0027t have to worry about flush_cache_page() before\n memcpy().\n4. Now, for the copy_to_user_page() case, after memcpy(), we must flush\n the caches so memory is consistent with kernel cache entries and\n invalidate the I-Cache if this mm region is executable. We don\u0027t\n need to do anything after memcpy() for the copy_from_user_page()\n case since kernel cache entries will be invalidated via the same\n process above if we access \"page\" again. The flush_ptrace_access()\n function (borrowed from SPARC64 implementation) is added to handle\n cache flushing after memcpy() for the copy_to_user_page() case.\n\nSigned-off-by: George G. Davis \u003cgdavis@mvista.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f", "tree": "e85ca2d0dd43f90dccf758338764c3caa55f333f", "parents": [ "089f26d5e31b7bf42a9a8fefec08b30cd27f4b0e" ], "author": { "name": "David Woodhouse", "email": "dwmw2@infradead.org", "time": "Wed Apr 26 12:56:16 2006 +0100" }, "committer": { "name": "David Woodhouse", "email": "dwmw2@infradead.org", "time": "Wed Apr 26 12:56:16 2006 +0100" }, "message": "Don\u0027t include linux/config.h from anywhere else in include/\n\nSigned-off-by: David Woodhouse \u003cdwmw2@infradead.org\u003e\n" }, { "commit": "23bdf86aa06ebe71bcbf6b7d25de9958c6ab33fa", "tree": "56636558e8cdeee0739e7d8c82d66ffe625340b3", "parents": [ "de4533a04eb4f66dbef71f59a9c118256b886823" ], "author": { "name": "Lennert Buytenhek", "email": "buytenh@wantstofly.org", "time": "Tue Mar 28 21:00:40 2006 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Mar 28 21:00:40 2006 +0100" }, "message": "[ARM] 3377/2: add support for intel xsc3 core\n\nPatch from Lennert Buytenhek\n\nThis patch adds support for the new XScale v3 core. This is an\nARMv5 ISA core with the following additions:\n\n- L2 cache\n- I/O coherency support (on select chipsets)\n- Low-Locality Reference cache attributes (replaces mini-cache)\n- Supersections (v6 compatible)\n- 36-bit addressing (v6 compatible)\n- Single instruction cache line clean/invalidate\n- LRU cache replacement (vs round-robin)\n\nI attempted to merge the XSC3 support into proc-xscale.S, but XSC3\ncores have separate errata and have to handle things like L2, so it\nis simpler to keep it separate.\n\nL2 cache support is currently a build option because the L2 enable\nbit must be set before we enable the MMU and there is no easy way to\ncapture command line parameters at this point.\n\nThere are still optimizations that can be done such as using LLR for\ncopypage (in theory using the exisiting mini-cache code) but those\ncan be addressed down the road.\n\nSigned-off-by: Deepak Saxena \u003cdsaxena@plexity.net\u003e\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@wantstofly.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "78ff18a412da24a4b79c6a97000ef5e467e813da", "tree": "901d67dc2c709b71fba37b37b901ea167cef21a2", "parents": [ "9d4f13e531b4722fe40cc8e28c02a495bdd49267" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Tue Jan 03 17:39:34 2006 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jan 03 17:39:34 2006 +0000" }, "message": "[ARM] Cleanup ARM includes\n\narch/arm/kernel/entry-armv.S has contained a comment suggesting\nthat asm/hardware.h and asm/arch/irqs.h should be moved into the\nasm/arch/entry-macro.S include. So move the includes to these\ntwo files as required.\n\nAdd missing includes (asm/hardware.h, asm/io.h) to asm/arch/system.h\nincludes which use those facilities, and remove asm/io.h from\nkernel/process.c.\n\nRemove other unnecessary includes from arch/arm/kernel, arch/arm/mm\nand arch/arm/mach-footbridge.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d7b6b3589471c3856f1e6dc9c77abc4af962ffdb", "tree": "82751eba321a062ce91af7f0f0bff8c4c5531a1c", "parents": [ "b38d950d3aedf90c8b15b3c7c799b5eb53c47c45" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Sep 08 15:32:23 2005 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Sep 08 15:32:23 2005 +0100" }, "message": "[ARM] Fix ARMv6 VIPT cache \u003e\u003d 32K\n\nThis adds the necessary changes to ensure that we flush the\ncaches correctly with aliasing VIPT caches.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b8a9b66fbee09d0cc71c272b5c1d1f3320afbbf0", "tree": "25be8fc2ef91f6dcbb7f7dd2b9e3db2a95963477", "parents": [ "8830f04a092b47f3d246271b24685cd9eab82027" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Jun 20 11:31:09 2005 +0100" }, "committer": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Jun 20 11:31:09 2005 +0100" }, "message": "[PATCH] ARM: Add common CACHE_COLOUR macro\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2", "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d", "parents": [], "author": { "name": "Linus Torvalds", "email": "torvalds@ppc970.osdl.org", "time": "Sat Apr 16 15:20:36 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@ppc970.osdl.org", "time": "Sat Apr 16 15:20:36 2005 -0700" }, "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n" } ] }