)]}' { "log": [ { "commit": "1946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7", "tree": "d6cb6a56623d39021e30bb6d1892bfda7edb123a", "parents": [ "eb5f4ca9536ba297c98721ecbbdf41ec5b987bd5" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Jun 01 12:50:33 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jun 02 22:36:20 2009 +0100" }, "message": "[ARM] ARMv7 errata: only apply fixes when running on applicable CPU\n\nCurrently, whenever an erratum workaround is enabled, it will be\napplied whether or not the erratum is relevent for the CPU. This\npatch changes this - we check the variant and revision fields in the\nmain ID register to determine which errata to apply.\n\nWe also avoid re-applying erratum 460075 if it has already been applied.\nApplying this fix in non-secure mode results in the kernel failing to\nboot (or even do anything.)\n\nThis fixes booting on some ARMv7 based platforms which otherwise\nsilently fail.\n\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "2142babac999a5ba169348892a8e3ac222bec7a4", "tree": "eb862396a9864b34e2335b7cc0c6114c56f9ec1a", "parents": [ "bb402c4fb5bba4edf5b8c72b3db8760e60df4876", "0516e4643cd22fc9f535aef02ad1de66c382c93b" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat May 02 16:40:20 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat May 02 16:40:20 2009 -0700" }, "message": "Merge master.kernel.org:/home/rmk/linux-2.6-arm\n\n* master.kernel.org:/home/rmk/linux-2.6-arm: (45 commits)\n [ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data\n [ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created\n [ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch\n [ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail\n davinci: DM644x: NAND: update partitioning\n davinci: update DM644x support in preparation for more SoCs\n davinci: DM644x: rename board file\n davinci: update pin-multiplexing support\n davinci: serial: generalize for more SoCs\n davinci: DM355 IRQ Definitions\n davinci: DM646x: add interrupt number and priorities\n davinci: PSC: Clear bits in MDCTL reg before setting new bits\n davinci: gpio bugfixes\n davinci: add EDMA driver\n davinci: timers: use clk_get_rate()\n [ARM] pxa/littleton: add missing da9034 touchscreen support\n [ARM] pxa/zylonite: configure GPIO18/19 correctly, used by 2 GPIO expanders\n [ARM] pxa/zylonite: fix the issue of unused SDATA_IN_1 pin get AC97 not working\n [ARM] pxa: make ads7846 on corgi and spitz to sync on HSYNC\n [ARM] pxa: remove unused CPU_FREQ_PXA Kconfig symbol\n ...\n" }, { "commit": "0516e4643cd22fc9f535aef02ad1de66c382c93b", "tree": "8b82945aa5f1ef825656aed2580cacafcd829ac3", "parents": [ "855c551f5b8cc3815d58e1056c1f1e7c461e2d24" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Apr 30 17:06:20 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Apr 30 20:13:00 2009 +0100" }, "message": "[ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data\n\nThis patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It\nconfigures the L2 cache auxiliary control register so that the Write\nAllocate mode for the L2 cache is disabled.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "855c551f5b8cc3815d58e1056c1f1e7c461e2d24", "tree": "c2a84666b3a86c3e5cb5272ed42b802f9411ec33", "parents": [ "7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Apr 30 17:06:15 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Apr 30 20:12:59 2009 +0100" }, "message": "[ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created\n\nThis patch adds a workaround for the 458693 Cortex-A8 (r2p0)\nerratum. It sets the corresponding bits in the auxiliary control\nregister so that the PLD instruction becomes a NOP.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47", "tree": "1f092413fbe0c91350e7861638dec7bb475c8435", "parents": [ "9cba3ccc8fe77b67aff2db8f5827d7cb752ce11f" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Apr 30 17:06:09 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Apr 30 20:12:50 2009 +0100" }, "message": "[ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch\n\nThis patch adds the workaround for the 430973 Cortex-A8 (r1p0..r1p2)\nerratum. The BTAC/BTB is now flushed at every context switch.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9cba3ccc8fe77b67aff2db8f5827d7cb752ce11f", "tree": "cb73cbaa3c197180b7f9d829561121197a8c69db", "parents": [ "10993374f84cc1c4100aea9eca7fa154518ffc5e" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Apr 30 17:06:03 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Apr 30 20:12:47 2009 +0100" }, "message": "[ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail\n\nThis patch implements the recommended workaround for erratum 411920\n(ARM1136, ARM1156, ARM1176).\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "991da17ec0b9f396154c8120ffd10e5d7d7aa361", "tree": "e53b6ce7d3482afb516e806bfc69966a6af0b7c0", "parents": [ "df1f6d200c1e20788184251c49f349b38d90889c" ], "author": { "name": "Tim Abbott", "email": "tabbott@MIT.EDU", "time": "Mon Apr 27 14:02:22 2009 -0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Apr 27 19:51:58 2009 -0700" }, "message": "arm: Use __INIT macro instead of .text.init.\n\narm is placing some code in the .text.init section, but it does not\nreference that section in its linker scripts.\n\nThis change moves this code from the .text.init section to the\n.init.text section, which is presumably where it belongs.\n\nSigned-off-by: Tim Abbott \u003ctabbott@mit.edu\u003e\nAcked-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nAcked-by: Sam Ravnborg \u003csam@ravnborg.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "81854f82c5c1a203b2f5c94f6aa2ed8b8e19f025", "tree": "2eac472ee815f31cfeca6ab396c6cd6347dc2871", "parents": [ "8c8aa5fa3060abc17e8a07d15f575485f6a0c0b8" ], "author": { "name": "Marek Vasut", "email": "marek.vasut@gmail.com", "time": "Sat Mar 28 12:37:42 2009 +0100" }, "committer": { "name": "Eric Miao", "email": "eric.miao@marvell.com", "time": "Sat Apr 04 10:26:34 2009 +0800" }, "message": "[ARM] pxa: Add support for suspend on PalmTX, T5 and LD\n\nSigned-off-by: Marek Vasut \u003cmarek.vasut@gmail.com\u003e\nSigned-off-by: Eric Miao \u003ceric.miao@marvell.com\u003e\n" }, { "commit": "fe68e68f6a379d317a87ae24de050a65b11ea1fb", "tree": "7e6099b993d9385eae4e7a892271c3fd38a7c207", "parents": [ "01a24d2b9309676ec2e7069cd19f5b1c4a1505e0" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Wed Apr 01 13:53:48 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Apr 01 22:15:57 2009 +0100" }, "message": "[ARM] 5439/1: Do not clear bit 10 of DFSR during abort handling on ARMv6\n\nBecause of an ARM1136 erratum (326103), the current v6_early_abort\nfunction needs to set the correct FSR[11] value which determines whether\nthe data abort was caused by a read or write. For legacy reasons (bit 10\nnot handled by software), bit 10 was also cleared masking out imprecise\naborts on ARMv6 CPUs. This patch removes the clearing of bit 10 of FSR.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f000328ac10f23f4841b83ddc60eceb3ba0ac176", "tree": "bcd9597eb25e0285f3d9a61c6203e8ec92d8cdfb", "parents": [ "d75de08727018659cd7e060cf0018eaf53e49aaf" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Fri Mar 27 14:22:26 2009 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sat Mar 28 22:39:30 2009 -0400" }, "message": "[ARM] Kirkwood: small L2 code cleanup\n\nStrictly speaking, a MCR instruction does not produce any output.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "d75de08727018659cd7e060cf0018eaf53e49aaf", "tree": "355e43af6605aeff23102af26615c9a679306407", "parents": [ "c31f403de62415c738ddc9e673cf8e722c82f861" ], "author": { "name": "Maxime Bizon", "email": "mbizon@freebox.fr", "time": "Fri Mar 27 18:42:19 2009 +0100" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sat Mar 28 22:39:30 2009 -0400" }, "message": "[ARM] Kirkwood: invalidate L2 cache before enabling it\n\nI get random oopses on my Kirkwood board at startup when L2 cache is\nenabled. FYI I\u0027m using Marvell uboot version 3.4.16\n\nEach boot produces the same oops, but anything that changes the kernel\nsize (even only changing initramfs) makes the oops different.\n\nI noticed that nothing invalidates the L2 cache before enabling it,\ndoing so fixes my problem.\n\nSigned-off-by: Maxime Bizon \u003cmbizon@freebox.fr\u003e\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "9759d22c8348343b0da4e25d6150c41712686c14", "tree": "338b185f11d705258888a8f2318a3a3b7ea0968d", "parents": [ "ed40d0c472b136682b2fcba05f89762859c7374f", "f0bba9f934517533acbda7329be93f55d5a01c03" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Mar 28 20:30:18 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Mar 28 20:30:18 2009 +0000" }, "message": "Merge branch \u0027master\u0027 into devel\n\nConflicts:\n\tarch/arm/include/asm/elf.h\n\tarch/arm/kernel/module.c\n" }, { "commit": "f0bba9f934517533acbda7329be93f55d5a01c03", "tree": "8b70d9651e235d44a175154146cf50597665549d", "parents": [ "803c78e4da28d7d7cb0642caf643b9289ae7838a" ], "author": { "name": "Mikael Pettersson", "email": "mikpe@it.uu.se", "time": "Sat Mar 28 19:18:05 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Mar 28 20:21:20 2009 +0000" }, "message": "[ARM] 5435/1: fix compile warning in sanity_check_meminfo()\n\nCompiling recent 2.6.29-rc kernels for ARM gives me the following warning:\n\narch/arm/mm/mmu.c: In function \u0027sanity_check_meminfo\u0027:\narch/arm/mm/mmu.c:697: warning: comparison between pointer and integer\n\nThis is because commit 3fd9825c42c784a59b3b90bdf073f49d4bb42a8d\n\"[ARM] 5402/1: fix a case of wrap-around in sanity_check_meminfo()\"\nin 2.6.29-rc5-git4 added a comparison of a pointer with PAGE_OFFSET,\nwhich is an integer.\n\nFixed by casting PAGE_OFFSET to void *.\n\nSigned-off-by: Mikael Pettersson \u003cmikpe@it.uu.se\u003e\nAcked-by: Nicolas Pitre \u003cnico@cam.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "542f869f1826f092606efd0c4c771f070d1314f5", "tree": "9c9d265ab0c87ea7862ccb70933f33d3d7011334", "parents": [ "e8b374bb6c888a70530d800c9e2fcd153e2c325d", "839e642f3dda44a35c6a91780bff41d84c288022" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Mar 26 23:10:11 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 26 23:10:11 2009 +0000" }, "message": "Merge branch \u0027for-rmk\u0027 of git://gitorious.org/linux-gemini/mainline into devel\n\nConflicts:\n\tarch/arm/mm/Kconfig\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "28853ac8fe5221de74a14f1182d7b2b383dfd85c", "tree": "dcfd9b20028e5a3a9504e26d2c9060f4746fc83a", "parents": [ "bba7d0b9ba0f04d25145de8170a17a3a07bbfdde" ], "author": { "name": "Paulius Zaleckas", "email": "paulius.zaleckas@teltonika.lt", "time": "Wed Mar 25 13:10:01 2009 +0200" }, "committer": { "name": "Paulius Zaleckas", "email": "paulius.zaleckas@teltonika.lt", "time": "Wed Mar 25 13:10:01 2009 +0200" }, "message": "ARM: Add support for FA526 v2\n\nAdds support for Faraday FA526 core. This core is used at least by:\nCortina Systems Gemini and Centroid family\nCavium Networks ECONA family\nGrain Media GM8120\nPixelplus ImageARM\nProlific PL-1029\nFaraday IP evaluation boards\n\nv2:\n- move TLB_BTB to separate patch\n- update copyrights\n\nSigned-off-by: Paulius Zaleckas \u003cpaulius.zaleckas@teltonika.lt\u003e\n" }, { "commit": "fbf2b1f9cfdb4e4b5d042839142ed19ff5d46679", "tree": "3a17c02aa0cf9bdbed9aa479739974aa2416ecac", "parents": [ "9a38e989b8ce04923f919fc2a8a24eb07fb484e2", "053a96ca11a9785a7e63fc89eed4514a6446ec58" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Tue Mar 24 22:47:45 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Mar 24 22:47:45 2009 +0000" }, "message": "Merge branch \u0027highmem\u0027 into devel\n" }, { "commit": "9a38e989b8ce04923f919fc2a8a24eb07fb484e2", "tree": "6b99638dc32b99420ada46ca8d1373ad7aa5a208", "parents": [ "7d83f8fca517b123cf0136503a9e50974f65ec49", "5fa82eb8ff06cd3ac4d64c6875922ae1dfa003c5" ], "author": { "name": "root", "email": "root@dyn-67.arm.linux.org.uk", "time": "Tue Mar 24 22:04:25 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Mar 24 22:04:25 2009 +0000" }, "message": "Merge branch \u0027devel\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel\n" }, { "commit": "49cbe78637eb0503f45fc9b556ec08918a616534", "tree": "96de29959c5ef512d8f1e0bea7eae2245b7cc3f9", "parents": [ "f8dec04d33b94a4cfa9358fd9666c01480bb164d" ], "author": { "name": "Eric Miao", "email": "eric.miao@marvell.com", "time": "Tue Jan 20 14:15:18 2009 +0800" }, "committer": { "name": "Eric Miao", "email": "eric.miao@marvell.com", "time": "Mon Mar 23 10:11:34 2009 +0800" }, "message": "[ARM] pxa: add base support for Marvell\u0027s PXA168 processor line\n\n\"\"\"The Marvell® PXA168 processor is the first in a family of application\nprocessors targeted at mass market opportunities in computing and consumer\ndevices. It balances high computing and multimedia performance with low\npower consumption to support extended battery life, and includes a wealth\nof integrated peripherals to reduce overall BOM cost .... \"\"\"\n\nSee http://www.marvell.com/featured/pxa168.jsp for more information.\n\n 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core,\n there are many enhancements like instructions for flushing the\n whole D-cache, and so on\n\n 2. Clock reuses Russell\u0027s common clkdev, and added the basic support\n for UART1/2.\n\n 3. Devices are a bit different from the \u0027mach-pxa\u0027 way, the platform\n devices are now dynamically allocated only when necessary (i.e.\n when pxa_register_device() is called). Description for each device\n are stored in an array of \u0027struct pxa_device_desc\u0027. Now that:\n\n a. this array of device description is marked with __initdata and\n can be freed up system is fully up\n\n b. which means board code has to add all needed devices early in\n his initializing function\n\n c. platform specific data can now be marked as __initdata since\n they are allocated and copied by platform_device_add_data()\n\n 4. only the basic UART1/2/3 are added, more devices will come later.\n\nSigned-off-by: Jason Chagas \u003cchagas@marvell.com\u003e\nSigned-off-by: Eric Miao \u003ceric.miao@marvell.com\u003e\n" }, { "commit": "7d83f8fca517b123cf0136503a9e50974f65ec49", "tree": "92ed1faaf112e98e29a00efc99e1a4e6c79e6a8e", "parents": [ "be093beb608edf821b45fe00a8a080fb5c6ed4af", "569106c70e49ad67c69fa7d43a2a5218e63a4619" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Mar 19 23:10:40 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 19 23:10:40 2009 +0000" }, "message": "Merge branch \u0027master\u0027 of git://git.marvell.com/orion into devel\n\nConflicts:\n\n\tarch/arm/mach-mx1/devices.c\n" }, { "commit": "3f973e22160257c5bda85815be5b1540d391a671", "tree": "c453cc200f3cd71bd28195e9959034aa673a7693", "parents": [ "3902a15e784e9b1efa8e6ad246489c609e0ef880" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Tue Nov 04 00:48:42 2008 -0500" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:22 2009 -0400" }, "message": "[ARM] ignore high memory with VIPT aliasing caches\n\nVIPT aliasing caches have issues of their own which are not yet handled.\nUsage of discard_old_kernel_data() in copypage-v6.c is not highmem ready,\nkmap/fixmap stuff doesn\u0027t take account of cache colouring, etc.\nIf/when those issues are handled then this could be reverted.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "3902a15e784e9b1efa8e6ad246489c609e0ef880", "tree": "8b674544cc2b3381fa9481d2e1e60eb99ef62a71", "parents": [ "1bb772679ffb0ba1ff1d40d8c6b855ab029f177d" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Thu Sep 18 22:55:47 2008 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:21 2009 -0400" }, "message": "[ARM] xsc3: add highmem support to L2 cache handling code\n\nOn xsc3, L2 cache ops are possible only on virtual addresses. The code\nis rearranged so to have a linear progression requiring the least amount\nof pte setups in the highmem case. To protect the virtual mapping so\ncreated, interrupts must be disabled currently up to a page worth of\naddress range.\n\nThe interrupt disabling is done in a way to minimize the overhead within\nthe inner loop. The alternative would consist in separate code for\nthe highmem and non highmem compilation which is less preferable.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "1bb772679ffb0ba1ff1d40d8c6b855ab029f177d", "tree": "c76eb84a6f8df764f0c8e13d84964968c3ab10b7", "parents": [ "58edb515724f9e63e569536d01ac8d8f8ddb367a" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Fri Sep 12 16:11:51 2008 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:21 2009 -0400" }, "message": "[ARM] Feroceon: add highmem support to L2 cache handling code\n\nThe choice is between looping over the physical range and performing\nsingle cache line operations, or to map highmem pages somewhere, as\ncache range ops are possible only on virtual addresses.\n\nBecause L2 range ops are much faster, we go with the later by factoring\nthe physical-to-virtual address conversion and use a fixmap entry for it\nin the HIGHMEM case.\n\nPossible future optimizations to avoid the pte setup cost:\n\n - do the pte setup for highmem pages only\n\n - determine a threshold for doing a line-by-line processing on physical\n addresses when the range is small\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "43377453af83b8ff8c1c731da1508bd6b84ebfea", "tree": "42a55f4d1856ced05d9e21f8619005e8b76694c3", "parents": [ "3297e760776af18a26bf30046cbaaae2e730c5c2" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Thu Mar 12 22:52:09 2009 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:21 2009 -0400" }, "message": "[ARM] introduce dma_cache_maint_page()\n\nThis is a helper to be used by the DMA mapping API to handle cache\nmaintenance for memory identified by a page structure instead of a\nvirtual address. Those pages may or may not be highmem pages, and\nwhen they\u0027re highmem pages, they may or may not be virtually mapped.\nWhen they\u0027re not mapped then there is no L1 cache to worry about. But\neven in that case the L2 cache must be processed since unmapped highmem\npages can still be L2 cached.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "3835f6cb645bdb9a58aa6e062fe1d5777f1a9748", "tree": "de3429794bb06cab351a7909da7c8c33bfa38567", "parents": [ "d73cd42893f4cdc06e6829fea2347bb92cb789d1" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Wed Sep 17 15:21:55 2008 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:21 2009 -0400" }, "message": "[ARM] mem_init(): make highmem pages available for use\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "d73cd42893f4cdc06e6829fea2347bb92cb789d1", "tree": "fddff067f2b09aa13741bc9d05956429616e986a", "parents": [ "5f0fbf9ecaf354fa4bbf266fffdea2ea3d14a0ed" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Mon Sep 15 16:44:55 2008 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:20 2009 -0400" }, "message": "[ARM] kmap support\n\nThe kmap virtual area borrows a 2MB range at the top of the 16MB area\nbelow PAGE_OFFSET currently reserved for kernel modules and/or the\nXIP kernel. This 2MB corresponds to the range covered by 2 consecutive\nsecond-level page tables, or a single pmd entry as seen by the Linux\npage table abstraction. Because XIP kernels are unlikely to be seen\non systems needing highmem support, there shouldn\u0027t be any shortage of\nVM space for modules (14 MB for modules is still way more than twice the\ntypical usage).\n\nBecause the virtual mapping of highmem pages can go away at any moment\nafter kunmap() is called on them, we need to bypass the delayed cache\nflushing provided by flush_dcache_page() in that case.\n\nThe atomic kmap versions are based on fixmaps, and\n__cpuc_flush_dcache_page() is used directly in that case.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "5f0fbf9ecaf354fa4bbf266fffdea2ea3d14a0ed", "tree": "9f0c59760b2bec510519118ddb17d4b15db473f5", "parents": [ "1522ac3ec95ff0230e7aa516f86b674fdf72866c" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Tue Sep 16 13:05:53 2008 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:20 2009 -0400" }, "message": "[ARM] fixmap support\n\nThis is the minimum fixmap interface expected to be implemented by\narchitectures supporting highmem.\n\nWe have a second level page table already allocated and covering\n0xfff00000-0xffffffff because the exception vector page is located\nat 0xffff0000, and various cache tricks already use some entries above\n0xffff0000. Therefore the PTEs covering 0xfff00000-0xfffeffff are free\nto be used.\n\nHowever the XScale cache flushing code already uses virtual addresses\nbetween 0xfffe0000 and 0xfffeffff.\n\nSo this reserves the 0xfff00000-0xfffdffff range for fixmap stuff.\n\nThe Documentation/arm/memory.txt information is updated accordingly,\nincluding the information about the actual top of DMA memory mapping\nregion which didn\u0027t match the code.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "97fb44eb6bc01f4ffed4300e475aa15e44877375", "tree": "481ed6efd0babe7185cae04f2fd295426b36411d", "parents": [ "e4707dd3e9d0cb57597b6568a5e51fea5d6fca41", "148854c65ea8046b045672fd49f4333aefaa3ab5" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Fri Mar 13 21:44:51 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Mar 13 21:44:51 2009 +0000" }, "message": "Merge branch \u0027for-rmk\u0027 of git://git.pengutronix.de/git/imx/linux-2.6 into devel\n\nConflicts:\n\n\tarch/arm/mach-at91/gpio.c\n" }, { "commit": "cb88214d726b337d49c1f65cbc5e5ac85837b11b", "tree": "286cb0b63eeb16c4c3f3f728813cabc2298dc730", "parents": [ "9536ff33619e13fcc4bd16354faea97dba244f73" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Sun Feb 08 02:00:50 2009 +0100" }, "committer": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Fri Mar 13 10:34:29 2009 +0100" }, "message": "[ARM] MX31/MX35: Add l2x0 cache support\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\n" }, { "commit": "1522ac3ec95ff0230e7aa516f86b674fdf72866c", "tree": "77444039536e70b3e9fbb38f686104cb5054aba3", "parents": [ "305b07680f6c6a7e59f996c5bd85f009caff5bb1" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Mar 12 17:03:48 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 12 23:09:09 2009 +0000" }, "message": "[ARM] Fix virtual to physical translation macro corner cases\n\nThe current use of these macros works well when the conversion is\nentirely linear. In this case, we can be assured that the following\nholds true:\n\n\t__va(p + s) - s \u003d __va(p)\n\nHowever, this is not always the case, especially when there is a\nnon-linear conversion (eg, when there is a 3.5GB hole in memory.)\nIn this case, if \u0027s\u0027 is the size of the region (eg, PAGE_SIZE) and\n\u0027p\u0027 is the final page, the above is most definitely not true.\n\nSo, we must ensure that __va() and __pa() are only used with valid\nkernel direct mapped RAM addresses. This patch tweaks the code\nto achieve this.\n\nTested-by: Charles Moschel \u003cfred99@carolina.rr.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "446c92b2901bedb3725d29b4e73def8aba623ffc", "tree": "5669761e042f8321214ca5a975fec536fa5f0efd", "parents": [ "9311c593f24f28de2a339da602644f0f7ae0fc60" ], "author": { "name": "Uwe Kleine-König", "email": "u.kleine-koenig@pengutronix.de", "time": "Thu Mar 12 18:03:16 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 12 21:33:03 2009 +0000" }, "message": "[ARM] 5421/1: ftrace: fix crash due to tracing of __naked functions\n\nThis is a fix for the following crash observed in 2.6.29-rc3:\nhttp://lkml.org/lkml/2009/1/29/150\n\nOn ARM it doesn\u0027t make sense to trace a naked function because then\nmcount is called without stack and frame pointer being set up and there\nis no chance to restore the lr register to the value before mcount was\ncalled.\n\nReported-by: Matthias Kaehlcke \u003cmatthias@kaehlcke.net\u003e\nTested-by: Matthias Kaehlcke \u003cmatthias@kaehlcke.net\u003e\n\nCc: Abhishek Sagar \u003csagar.abhishek@gmail.com\u003e\nCc: Steven Rostedt \u003crostedt@home.goodmis.org\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Uwe Kleine-König \u003cu.kleine-koenig@pengutronix.de\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "e4707dd3e9d0cb57597b6568a5e51fea5d6fca41", "tree": "c76a6cb54e4f90a8deebf380bf8fe8a5f6eb2750", "parents": [ "6dc4a47a0cf423879b505af0e29997fca4088630" ], "author": { "name": "Paul Walmsley", "email": "paul@pwsan.com", "time": "Thu Mar 12 20:11:43 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 12 19:25:02 2009 +0000" }, "message": "[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type\n\nThis patch adds a Non-cacheable Normal ARM executable memory type,\nMT_MEMORY_NONCACHED.\n\nOn OMAP3, this is used for rapid dynamic voltage/frequency scaling in\nthe VDD2 voltage domain. OMAP3\u0027s SDRAM controller (SDRC) is in the\nVDD2 voltage domain, and its clock frequency must change along with\nvoltage. The SDRC clock change code cannot run from SDRAM itself,\nsince SDRAM accesses are paused during the clock change. So the\ncurrent implementation of the DVFS code executes from OMAP on-chip\nSRAM, aka \"OCM RAM.\"\n\nIf the OCM RAM pages are marked as Cacheable, the ARM cache controller\nwill attempt to flush dirty cache lines to the SDRC, so it can fill\nthose lines with OCM RAM instruction code. The problem is that the\nSDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU\nsubsystem to hang.\n\nTI\u0027s original solution to this problem was to mark the OCM RAM\nsections as Strongly Ordered memory, thus preventing caching. This is\noverkill: since the memory is marked as non-bufferable, OCM RAM writes\nbecome needlessly slow. The idea of \"Strongly Ordered SRAM\" is also\nconceptually disturbing. Previous LAKML list discussion is here:\n\nhttp://www.spinics.net/lists/arm-kernel/msg54312.html\n\nThis memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future\npatch.\n\nCc: Richard Woodruff \u003cr-woodruff2@ti.com\u003e\nSigned-off-by: Paul Walmsley \u003cpaul@pwsan.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "25ef4a67e78e1322d55f0a38783537ed89addc02", "tree": "030221d967bba0ab8d5274159063f839e6f503cc", "parents": [ "c8532db7f2661b63f658b9a08cf4053a3e6abb78" ], "author": { "name": "Seth Forshee", "email": "seth.forshee@gmail.com", "time": "Mon Mar 02 22:39:36 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Mar 03 12:11:25 2009 +0000" }, "message": "[ARM] 5416/1: Use unused address in v6_early_abort\n\nThe target of the strex instruction to clear the exlusive monitor\nis currently the top of the stack. If the store succeeeds this\ncorrupts r0 in pt_regs. Use the next stack location instead of\nthe current one to prevent any chance of corrupting an in-use\naddress.\n\nSigned-off-by: Seth Forshee \u003cseth.forshee@gmail.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "3fd9825c42c784a59b3b90bdf073f49d4bb42a8d", "tree": "ae0910729307786e5393b66373239c4dee48303f", "parents": [ "fd4b9b3650076ffadbdd6e360eb198f5d61747c0" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Wed Feb 18 22:29:22 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 19 09:49:45 2009 +0000" }, "message": "[ARM] 5402/1: fix a case of wrap-around in sanity_check_meminfo()\n\nIn the non highmem case, if two memory banks of 1GB each are provided,\nthe second bank would evade suppression since its virtual base would\nbe 0. Fix this by disallowing any memory bank which virtual base\naddress is found to be lower than PAGE_OFFSET.\n\nReported-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "08e445bd6a98fa09befe0cf6d67705324f913fc6", "tree": "34308727da79a6a36fc52ebe5b5d960b2bafaf6d", "parents": [ "ecbab71c521819716e204659dfe72fc39d00630a" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Fri Jan 16 23:02:54 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jan 28 16:55:00 2009 +0000" }, "message": "[ARM] 5366/1: fix shared memory coherency with VIVT L1 + L2 caches\n\nWhen there are multiple L1-aliasing userland mappings of the same physical\npage, we currently remap each of them uncached, to prevent VIVT cache\naliasing issues. (E.g. writes to one of the mappings not being immediately\nvisible via another mapping.) However, when we do this remapping, there\ncould still be stale data in the L2 cache, and an uncached mapping might\nbypass L2 and go straight to RAM. This would cause reads from such\nmappings to see old data (until the dirty L2 line is eventually evicted.)\n\nThis issue is solved by forcing a L2 cache flush whenever the shared page\nis made L1 uncacheable.\n\nIdeally, we would make L1 uncacheable and L2 cacheable as L2 is PIPT. But\nFeroceon does not support that combination, and the TEX\u003d5 C\u003d0 B\u003d0 encoding\nfor XSc3 doesn\u0027t appear to work in practice.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "24f11ec001920f1cfaeeed8e8b55725d900bbb56", "tree": "bb7a1007374c9ce9f60962c22f8bccb31bd6cb44", "parents": [ "fb22d72782b023cda5e9876d3381f30932a64f91" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Jan 25 17:36:34 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Jan 25 17:36:34 2009 +0000" }, "message": "[ARM] fix section-based ioremap\n\nTomi Valkeinen reports:\n Running with latest linux-omap kernel on OMAP3 SDP board, I have\n problem with iounmap(). It looks like iounmap() does not properly\n free large areas. Below is a test which fails for me in 6-7 loops.\n\n\tfor (i \u003d 0; i \u003c 200; ++i) {\n\t\tvaddr \u003d ioremap(paddr, size);\n\t\tif (!vaddr) {\n\t\t\tprintk(\"couldn\u0027t ioremap\\n\");\n\t\t\tbreak;\n\t\t}\n\t\tiounmap(vaddr);\n\t}\n\nThe changes to vmalloc.c weren\u0027t reflected in the ARM ioremap\nimplementation. Turns out the fix is rather simple.\n\nTested-by: Tomi Valkeinen \u003ctomi.valkeinen@nokia.com\u003e\nTested-by: Matt Gerassimoff \u003cmgeras@gmail.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7dd8c4f3526b16edb1a3f4edb4665a8fa6e632d8", "tree": "12b54dbe73f40a701d52dd7f97ad2a11e86f032e", "parents": [ "953a7e8476bbd7367cebdb868c326ba42968bc13" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Jan 18 16:24:19 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Jan 24 11:41:17 2009 +0000" }, "message": "[ARM] fix StrongARM-11x0 page copy implementation\n\nWhich had the \u0027from\u0027 and \u0027to\u0027 pages reversed.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "98007c230eb1e85ff5d49b4a697835680483dafd", "tree": "a5074e8b1330de2f8ff8b4a6a3ce3a31a5f0f702", "parents": [ "d672d2fc13242f9284345cb7e4c5a32cd5edefa3" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Fri Jan 09 15:28:55 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 12 13:51:03 2009 +0000" }, "message": "[ARM] 5364/1: allow flush_ioremap_region() to be used from modules\n\nWithout this, the pxa2xx-flash driver cannot be used as a module.\n\nReported-by: Chris Lawrence \u003cchrisdl@netspace.net.au\u003e\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9c93af1ede9418bb3f1b9dd442faf91ba796a0ff", "tree": "a5185e6af336e3c00343e7791517b70f00d0c2df", "parents": [ "0e8f989a253b1bf85ea1c8d7987d67c054f4af91" ], "author": { "name": "David Howells", "email": "dhowells@redhat.com", "time": "Thu Jan 08 12:04:47 2009 +0000" }, "committer": { "name": "David Howells", "email": "dhowells@redhat.com", "time": "Thu Jan 08 12:04:47 2009 +0000" }, "message": "NOMMU: Rename ARM\u0027s struct vm_region\n\nRename ARM\u0027s struct vm_region so that I can introduce my own global version\nfor NOMMU. It\u0027s feasible that the ARM version may wish to use my global one\ninstead.\n\nThe NOMMU vm_region struct defines areas of the physical memory map that are\nunder mmap. This may include chunks of RAM or regions of memory mapped\ndevices, such as flash. It is also used to retain copies of file content so\nthat shareable private memory mappings of files can be made. As such, it may\nbe compatible with what is described in the banner comment for ARM\u0027s vm_region\nstruct.\n\nSigned-off-by: David Howells \u003cdhowells@redhat.com\u003e\n" }, { "commit": "c613bbba6f39c8804f1f26e96fb68a117cc9e282", "tree": "85fbc24f26b61ce4e7a908d18952e3abc1f5cd10", "parents": [ "cd4348339c21f4a15c01f3f120e92b3224a0a7da", "80eee6bca4069c48247005aa07cb5e8e86042aa3" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Wed Dec 17 20:04:45 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 17 20:04:45 2008 +0000" }, "message": "Merge branch \u0027mxc-pu-imxfb\u0027 of git://pasiphae.extern.pengutronix.de/git/imx/linux-2.6 into devel\n" }, { "commit": "7e1548a597ef7e26d5d62f8be3be6da9e101b26c", "tree": "fe6cbf4d9a3c1afdba04fb276fef0f932403727c", "parents": [ "1f7f569c0ae6e619504095eabf796edd712d943d", "2619bc327417f549f1c89d5ef9b4a4aa768f41a2" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Dec 15 22:13:26 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 15 22:13:26 2008 +0000" }, "message": "Merge branch \u0027omap3-upstream\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into devel\n" }, { "commit": "67306da610a3e4824192e92888634d3d8700bfc1", "tree": "cd60e44ac249e4a4c3f131d4d179c39d40793ac5", "parents": [ "3909845e26439148a484d1ac30bb65e5e0ff63ec" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Dec 14 18:01:44 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 15 10:34:48 2008 +0000" }, "message": "[ARM] Ensure linux/hardirqs.h is included where required\n\n... for the removal of it from asm-generic/local.h\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "6ce1b871db6a3ca69ed1e35956d89d3cacd7ba08", "tree": "fa3a1d73cc601de707ec21dad485319d42f7bfb5", "parents": [ "d517cab1c7fc92178e11c7ded2548b06b273d293" ], "author": { "name": "Julia Lawall", "email": "julia@diku.dk", "time": "Mon Dec 01 14:15:41 2008 -0800" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Dec 14 12:05:03 2008 +0000" }, "message": "[ARM] eliminate NULL test and memset after alloc_bootmem\n\nAs noted by Akinobu Mita in patch b1fceac2b9e04d278316b2faddf276015fc06e3b,\nalloc_bootmem and related functions never return NULL and always return a\nzeroed region of memory. Thus a NULL test or memset after calls to these\nfunctions is unnecessary.\n\nThis was fixed using the following semantic patch.\n(http://www.emn.fr/x-info/coccinelle/)\n\n// \u003csmpl\u003e\n@@\nexpression E;\nstatement S;\n@@\n\nE \u003d \\(alloc_bootmem\\|alloc_bootmem_low\\|alloc_bootmem_pages\\|alloc_bootmem_low_pages\\|alloc_bootmem_node\\|alloc_bootmem_low_pages_node\\|alloc_bootmem_pages_node\\)(...)\n... when !\u003d E\n(\n- BUG_ON (E \u003d\u003d NULL);\n|\n- if (E \u003d\u003d NULL) S\n)\n\n@@\nexpression E,E1;\n@@\n\nE \u003d \\(alloc_bootmem\\|alloc_bootmem_low\\|alloc_bootmem_pages\\|alloc_bootmem_low_pages\\|alloc_bootmem_node\\|alloc_bootmem_low_pages_node\\|alloc_bootmem_pages_node\\)(...)\n... when !\u003d E\n- memset(E,0,E1);\n// \u003c/smpl\u003e\n\nSigned-off-by: Julia Lawall \u003cjulia@diku.dk\u003e\nCc: Russell King \u003crmk@arm.linux.org.uk\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "baa745a3378046ca1c5477495df6ccbec7690428", "tree": "bc3a1339a45d70b6810f2ca88a7f46e89b33b2d2", "parents": [ "794baba637999b81aa40e60fae1fa91978e08808" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Dec 07 09:44:55 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Dec 07 09:44:55 2008 +0000" }, "message": "[ARM] Fix alignment fault handling for ARMv6 and later CPUs\n\nOn ARMv6 and later CPUs, it is possible for userspace processes to\nget stuck on a misaligned load or store due to the \"ignore fault\"\nsetting; unlike previous CPUs, retrying the instruction without\nthe \u0027A\u0027 bit set does not always cause the load to succeed.\n\nWe have no real option but to default to fixing up alignment faults\non these CPUs, and having the CPU fix up those misaligned accesses\nwhich it can.\n\nReported-by: Wolfgang Grandegger \u003cwg@grandegger.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "c5b84b3bb0c055d70dc9f1b5e900378bc9d059ea", "tree": "bd5b0b4efb552bacd812f9e6e08a29bae70c0da1", "parents": [ "d281bc9d8a22419abc254f86a7fc268bb99914e1", "bc2fd1c09c226ea47ab8301cde6dbcf9e5c78b73" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Tue Dec 02 22:07:40 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Dec 02 22:07:40 2008 +0000" }, "message": "Merge branch \u0027for-rmk\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel\n\nConflicts:\n\n\tarch/arm/mach-pxa/pxa25x.c\n" }, { "commit": "59c7bcd4d60812ca10ec691376f43d6a5fbfb4f8", "tree": "74ebe42f17a16018dbbafb0ae7e7ad18f185e4fe", "parents": [ "f1c6cd62cc4f7e55a803c4b9b92a67488d765a8f" ], "author": { "name": "Eric Miao", "email": "eric.miao@marvell.com", "time": "Sat Nov 29 21:42:39 2008 +0800" }, "committer": { "name": "Eric Miao", "email": "eric.miao@marvell.com", "time": "Tue Dec 02 14:42:40 2008 +0800" }, "message": "[ARM] pxa: add base PXA935 support due to CPUID change\n\nPXA935 has changed its implementor ID from Intel to Marvell, this\npatch modifies arch/arm/boot/compressed/head.S and proc-xsc3.S to\nsupport a smooth bootup.\n\nSigned-off-by: Eric Miao \u003ceric.miao@marvell.com\u003e\n" }, { "commit": "657e1de8e742cf81153d2d15545948bd58294200", "tree": "0fa3df23305e3763027f819cde6016dde8b24223", "parents": [ "93982535a201399c0023c1166a7f16a335134d5a", "6f13d278836d7251168631faeb0cbf5e4cdd98e5" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Dec 01 17:53:45 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 01 17:53:45 2008 +0000" }, "message": "Merge branch \u0027for-rmk-realview\u0027 of git://linux-arm.org/linux-2.6 into devel\n" }, { "commit": "4c3ea3717103ffcccfaebedb98c2dadfb54e0482", "tree": "aeef9b14e999051c9b1e3cb01c0dae48428f16d8", "parents": [ "8aa2da872a492a2196397603ed756a4c48677122" ], "author": { "name": "Jon Callan", "email": "Jon.Callan@arm.com", "time": "Mon Dec 01 14:54:56 2008 +0000" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Mon Dec 01 14:54:56 2008 +0000" }, "message": "RealView: Add Cortex-A9 support to the EB board\n\nThis patch adds the necessary definitions and Kconfig entries to enable\nCortex-A9 (ARMv7 SMP) tiles on the RealView/EB board.\n\nSigned-off-by: Jon Callan \u003cJon.Callan@arm.com\u003e\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n\n\n\n" }, { "commit": "37efe6427dd50e889473fb3c7fcec02dbbd098eb", "tree": "d5a6b3e6fbd5d60a1a145f5801002e96bcb9af9e", "parents": [ "112243034cec7c3ef0499fdebf39218714da453d" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Dec 01 11:53:07 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 01 11:53:07 2008 +0000" }, "message": "[ARM] use asm/sections.h\n\nUpdate to use the asm/sections.h header rather than declaring these\nsymbols ourselves. Change __data_start to _data to conform with the\nnaming found within asm/sections.h.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "87c52578bd050ba395b0cae7079b1128abd2422d", "tree": "e3b5ddbcafc52eb50e60516b0bcf7f20a51a270d", "parents": [ "f40b121d983dfc53bde882aadec7f2f0bbcbd1c2" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Nov 29 17:35:51 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Nov 29 18:49:55 2008 +0000" }, "message": "[ARM] Remove linux/sched.h from asm/cacheflush.h and asm/uaccess.h\n\n... and fix those drivers that were incorrectly relying upon\nthat include.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "5bed1fb3287dfb1f6cf717ec200b23d3e537c9ae", "tree": "59b6a3c32e8d02fb9022b598b5cf8fc306faf833", "parents": [ "0b3ce7fc3b9949a9867b810372226f5bc21dde1a" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Fri Nov 28 22:48:33 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Nov 28 23:20:39 2008 +0000" }, "message": "[ARM] Remove unnecessary mach/hardware.h includes in arch/arm/mm\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7ef4de17cc55a3c3b8d093743b1e3b845d8eba47", "tree": "adf87c996affbb6c42850d55cb34c0e5a2f6d340", "parents": [ "f412b09f4ed7c57f5b8935ed7d6fc786f402a629", "b5ee9002583fc14e6d45a04c18f208987a8fbced" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Fri Nov 28 15:39:02 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Nov 28 15:39:02 2008 +0000" }, "message": "Merge branch \u0027highmem\u0027 into devel\n\nConflicts:\n\n\tarch/arm/mach-clps7500/include/mach/memory.h\n" }, { "commit": "252d4c276dc0895834af48743579cf19d1fa150b", "tree": "ff0005eeff89ad8bcc5ebd197055ce01cadc96df", "parents": [ "9210807cb5a3f19a0e954dd401e3a2c3626d1b48" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Thu Sep 11 11:52:02 2008 -0400" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Nov 28 15:36:47 2008 +0000" }, "message": "[ARM] remove bogus #ifdef CONFIG_HIGHMEM in show_pte()\n\nThe restriction on !CONFIG_HIGHMEM is unneeded since page tables are\ncurrently never allocated with highmem pages, and actually disable PTE\ndump whenever highmem is configured. Let\u0027s have a dynamic test to better\ndescribe the current limitation instead.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9210807cb5a3f19a0e954dd401e3a2c3626d1b48", "tree": "d73afb5a664ba8fcbbd0b5e5d48ac5533f7d4da0", "parents": [ "6db015e49c03d42247d2a985475b833635406a4f" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Fri Sep 19 10:43:06 2008 -0400" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Nov 28 15:36:47 2008 +0000" }, "message": "[ARM] prevent the vmalloc cmdline argument from eating all memory\n\nCommit 8d5796d2ec6b5a4e7a52861144e63af438d6f8f7 allows for the vmalloc\narea to be resized from the kernel cmdline. Make sure it cannot overlap\nwith RAM entirely.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "6db015e49c03d42247d2a985475b833635406a4f", "tree": "933168a174d2294fa5e89a4eb60be77e01194bcd", "parents": [ "a1bbaec0cd2a59d4bb09b72e4541a8a12e480d5d" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Wed Sep 17 14:50:42 2008 -0400" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Nov 28 15:36:46 2008 +0000" }, "message": "[ARM] mem_init() cleanups\n\nMake free_area() arguments pfn based, and return number of freed pages.\nThis will simplify highmem initialization later.\n\nAlso, codepages, datapages and initpages are actually codesize, datasize\nand initsize.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a1bbaec0cd2a59d4bb09b72e4541a8a12e480d5d", "tree": "c574a8fb0078ea5931264bbac8ee6dfc5e3bc6e5", "parents": [ "4b5f32cee0cce7b9783ced5cbeabd17aa53c51fb" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Tue Sep 02 11:44:21 2008 -0400" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Nov 28 15:36:45 2008 +0000" }, "message": "[ARM] split highmem into its own memory bank\n\nDoing so will greatly simplify the bootmem initialization code as each\nbank is therefore entirely lowmem or highmem with no crossing between\nthose zones.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "4b5f32cee0cce7b9783ced5cbeabd17aa53c51fb", "tree": "95d3f2af07733cf70419ea5c3ae1100be2533197", "parents": [ "43ae286b7d4d8c4983bc263ef2e3cccc10dedb2b" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Mon Oct 06 13:24:40 2008 -0400" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Nov 28 15:36:44 2008 +0000" }, "message": "[ARM] rationalize memory configuration code some more\n\nCurrently there are two instances of struct meminfo: one in\nkernel/setup.c marked __initdata, and another in mm/init.c with\npermanent storage. Let\u0027s keep only the later to directly populate\nthe permanent version from arm_add_memory().\n\nAlso move common validation tests between the MMU and non-MMU cases\ninto arm_add_memory() to remove some duplication. Protection against\noverflowing the membank array is also moved in there in order to cover\nthe kernel cmdline parsing path as well.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "43ae286b7d4d8c4983bc263ef2e3cccc10dedb2b", "tree": "be10faffb48904e5bb962fbd45f7cb2ff395caea", "parents": [ "303c6443659bc1dc911356f5de149f48ff1d97b8" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Tue Nov 04 02:42:27 2008 -0500" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Nov 28 15:36:43 2008 +0000" }, "message": "[ARM] fix a couple clear_user_highpage assembly constraints\n\nIn all cases the kaddr is assigned an input register even though it is\nmodified in the assembly code. Let\u0027s assign a new variable to the\nmodified value and mark those inline asm with volatile otherwise they\nget optimized away because the output variable is otherwise not used.\n\nAlso fix a few conversion errors in copypage-feroceon.c and\ncopypage-v4mc.c.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "303c6443659bc1dc911356f5de149f48ff1d97b8", "tree": "75da0aef28ec8e843cdeb24c96349bdf812e2740", "parents": [ "063b0a4207e43acbeff3d4b09f43e750e0212b48" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Fri Oct 31 16:32:19 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Nov 27 23:53:48 2008 +0000" }, "message": "[ARM] clearpage: provide our own clear_user_highpage()\n\nFor similar reasons as copy_user_page(), we want to avoid the\nadditional kmap_atomic if it\u0027s unnecessary.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "063b0a4207e43acbeff3d4b09f43e750e0212b48", "tree": "eb2a2c1faa732c763102040478830111fc13f2a5", "parents": [ "d73e60b7144a86baf0fdfcc9537a70bb4f72e11c" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Fri Oct 31 15:08:35 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Nov 27 23:53:47 2008 +0000" }, "message": "[ARM] copypage: provide our own copy_user_highpage()\n\nWe used to override the copy_user_page() function. However, this\nis not only inefficient, it also causes additional complexity for\nhighmem support, since we convert from a struct page to a kernel\ndirect mapped address and back to a struct page again.\n\nMoreover, with highmem support, we end up pointlessly setting up\nkmap entries for pages which we\u0027re going to remap. So, push the\nkmapping down into the copypage implementation files where it\u0027s\nrequired.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d73e60b7144a86baf0fdfcc9537a70bb4f72e11c", "tree": "02155154caf6f1a5d6ce38f2a89ed67f875c7791", "parents": [ "487ff32082a9bd7489d8185cf7d7a2fdf18a22fa" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Fri Oct 31 13:08:02 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Nov 27 23:53:46 2008 +0000" }, "message": "[ARM] copypage: convert assembly files to C\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f412b09f4ed7c57f5b8935ed7d6fc786f402a629", "tree": "34fe1b4b64db4993e9fb21a70812fafed0437870", "parents": [ "31bccbf39208133415000520c79ebe7b291786df", "7f1fd31db158c95418d9cc5690ab60ecc6fb632d" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Nov 27 12:42:48 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Nov 27 12:42:48 2008 +0000" }, "message": "Merge branch \u0027for-rmk\u0027 of git://linux-arm.org/linux-2.6 into devel\n" }, { "commit": "c750815e2d436f4379c7af8a8770ef2ae71c5607", "tree": "a63ddc8af77e0cd86aa837bc77f98a1c18fbc685", "parents": [ "59f0cb0fddc14ffc6676ae62e911f8115ebc8ccf" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Oct 26 10:55:14 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Nov 27 12:38:00 2008 +0000" }, "message": "[ARM] Arrange for platforms to select appropriate CPU support\n\nRather than:\n\n\tconfig CPU_BLAH\n\t\tbool\n\t\tdepends on ARCH_FOO || MACH_BAR\n\t\tdefault y if ARCH_FOO || MACH_BAR\n\narrange for ARCH_FOO and MACH_BAR to select CPU_BLAH directly.\n\nAcked-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nAcked-by: Andrew Victor \u003clinux@maxim.org.za\u003e\nAcked-by: Brian Swetland \u003cswetland@google.com\u003e\nAcked-by: Eric Miao \u003ceric.miao@marvell.com\u003e\nAcked-by: Nicolas Bellido \u003cml@acolin.be\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "59f0cb0fddc14ffc6676ae62e911f8115ebc8ccf", "tree": "1e5fc347287c02e83dce967180c96906f6ed7455", "parents": [ "ed313489badef16d700f5a3be50e8fd8f8294bc8" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Oct 27 11:24:09 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Nov 27 12:37:59 2008 +0000" }, "message": "[ARM] remove memzero()\n\nAs suggested by Andrew Morton, remove memzero() - it\u0027s not supported\non other architectures so use of it is a potential build breaking bug.\nSince the compiler optimizes memset(x,0,n) to __memzero() perfectly\nwell, we don\u0027t miss out on the underlying benefits of memzero().\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "8553cb67d2318db327071018fc81084cbabccc46", "tree": "f2db64a188cbf2cce745720bf3d279daa2768609", "parents": [ "73b63efaac7352c9e2bf1570fac98fd44a99f8f9" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Mon Nov 10 14:14:11 2008 +0000" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Mon Nov 10 14:14:11 2008 +0000" }, "message": "Modern processors may need to drain the WB before WFI\n\nSince WFI may cause the processor to enter a low-power mode, data may\nstill be in the write buffer. This patch adds a DSB (or DWB) to the\ncpu_(v6|v7)_do_idle functions before the WFI.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n\n\n\n\n\n" }, { "commit": "ebb4c65869db7213280ad9c510637683939b5ff8", "tree": "e9aa372c806fad73a04ba2f9d16d1f17491a11cf", "parents": [ "7bfc0b2e266dd4cd3d3f27a3ad31bf79974190b1" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Nov 09 11:18:36 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Nov 09 11:18:36 2008 +0000" }, "message": "[ARM] iop: iop3xx needs registers mapped uncached+unbuffered\n\nMikael Pettersson reported:\n\n The 2.6.28-rc kernels fail to detect PCI device 0000:00:01.0\n (the first ethernet port) on my Thecus n2100 XScale box.\n\n There is however still a strange \"ghost\" device that gets partially\n detected in 2.6.28-rc2 vanilla.\n\nThe IOP321 manual says:\n\n The user designates the memory region containing the OCCDR as\n non-cacheable and non-bufferable from the IntelR XScaleTM core.\n This guarantees that all load/stores to the OCCDR are only of\n DWORD quantities.\n\nEnsure that the OCCDR is so mapped.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "72bc2b1ad62f4d2f0a51b35829093d41f55accce", "tree": "56a6c8db69e4835259ba135c721a28b3a91ba4ed", "parents": [ "4bab0ea1d42dd1927af9df6fbf0003fc00617c50" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sat Nov 08 21:15:53 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Nov 08 23:08:54 2008 +0000" }, "message": "[ARM] 5329/1: Feroceon: fix feroceon_l2_inv_range\n\nSame fix as commit c7cf72dcadb: when \u0027start\u0027 and \u0027end\u0027 are less than a\ncacheline apart and \u0027start\u0027 is unaligned we are done after cleaning and\ninvalidating the first cacheline.\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "878708f290f6ed8b108d73fd6ab624cda6266a1e", "tree": "249f991f231ef8532c7f44b592bbfe78194f7e2e", "parents": [ "b1cce6b1b2785fd61454b47ceacb461815407662", "c7cf72dcadbe39c2077b32460f86c9f8167be3be" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Nov 06 18:04:23 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Nov 06 18:04:23 2008 +0000" }, "message": "Merge branch \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/xscaleiop\n" }, { "commit": "c7cf72dcadbe39c2077b32460f86c9f8167be3be", "tree": "66984afe9b390596d1ae97e35aaeb4e6f52c412d", "parents": [ "45beca08dd8b6d6a65c5ffd730af2eac7a2c7a03" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 06 17:43:55 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 06 10:48:29 2008 -0700" }, "message": "[ARM] xsc3: fix xsc3_l2_inv_range\n\nWhen \u0027start\u0027 and \u0027end\u0027 are less than a cacheline apart and \u0027start\u0027 is\nunaligned we are done after cleaning and invalidating the first\ncacheline. So check for (start \u003c end) which will not walk off into\ninvalid address ranges when (start \u003e end).\n\nThis issue was caught by drivers/dma/dmatest.\n\n2.6.27 is susceptible.\n\nCc: \u003cstable@kernel.org\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nCc: Lothar WaÃ\u003c9f\u003emann \u003cLW@KARO-electronics.de\u003e\nCc: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\nCc: Eric Miao \u003ceric.miao@marvell.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b1cce6b1b2785fd61454b47ceacb461815407662", "tree": "90a877fcab8defd4a6770aaab4dcb3de6e69ba04", "parents": [ "ab4f2ee130d5ffcf35616e1f5c6ab75af5b463b6" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Tue Nov 04 10:52:28 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Nov 06 17:45:32 2008 +0000" }, "message": "[ARM] mm: fix page table initialization\n\nAs a result of the ptebits changes, we ended up marking device mappings\nas normal memory on ARMv7 CPUs, resulting in undesirable behaviour with\nserial ports and the like. While reviewing the section mapping table\nentries, other errors in the memory type settings for devices were\ndetected and confirmed to prevent Xscale3 platforms booting.\n\nTested on:\n\tOMAP34xx (ARMv7),\n\tOMAP24xx (ARMv6),\n\tOMAP16xx (ARM926T, ARMv5),\n\tPXA311 (Xscale3),\n\tPXA272 (Xscale),\n\tPXA255 (Xscale),\n\tIXP42x (Xscale),\n\tS3C2410 (ARM920T, ARMv4T),\n\tARM720T (ARMv4T)\n\tStrongARM-110 (ARMv4)\n\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nTested-by: Robert Jarzmik \u003crobert.jarzmik@free.fr\u003e\nTested-by: Mike Rapoport \u003cmike@compulab.co.il\u003e\nTested-by: Ben Dooks \u003cben-linux@fluff.org\u003e\nTested-by: Anders Grafström \u003cgrfstrm@users.sourceforge.net\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ab4f2ee130d5ffcf35616e1f5c6ab75af5b463b6", "tree": "7532eb50e674402f8f658094acb71b8dfb1117bf", "parents": [ "d2ed5cb80a241518dd71f467c884bfabbe15f68c" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Nov 06 17:11:07 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Nov 06 17:13:47 2008 +0000" }, "message": "[ARM] fix naming of MODULE_START / MODULE_END\n\nAs of 73bdf0a60e607f4b8ecc5aec597105976565a84f, the kernel needs\nto know where modules are located in the virtual address space.\nOn ARM, we located this region between MODULE_START and MODULE_END.\nUnfortunately, everyone else calls it MODULES_VADDR and MODULES_END.\nUpdate ARM to use the same naming, so is_vmalloc_or_module_addr()\ncan work properly. Also update the comment on mm/vmalloc.c to\nreflect that ARM also places modules in a separate region from the\nvmalloc space.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "73b63efaac7352c9e2bf1570fac98fd44a99f8f9", "tree": "9bdb18703567d643f57bc7e068f1f47df487fd88", "parents": [ "6b07d7fea0496374ff7754dc3d1dca03b2911828" ], "author": { "name": "Jon Callan", "email": "Jon.Callan@arm.com", "time": "Thu Nov 06 13:23:09 2008 +0000" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Nov 06 13:23:09 2008 +0000" }, "message": "ARMv7: Add SMP initialisation to proc-v7.S\n\nThis patch adds the SMP/nAMP mode setting to __v7_setup and also sets\nTTBR to shared page table walks if SMP is enabled. The PTWs are also\nmarked inner cacheable for both SMP and UP modes (setting this is fine\neven if the CPU doesn\u0027t support the feature).\n\nSigned-off-by: Jon Callan \u003cJon.Callan@arm.com\u003e\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n\n\n\n\n" }, { "commit": "6b07d7fea0496374ff7754dc3d1dca03b2911828", "tree": "9a457c335982777e172fffad192c43b65d810b1e", "parents": [ "376e14218d3d791127e9b9bfbe2f99c44c2a19c2" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Nov 06 13:23:08 2008 +0000" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Nov 06 13:23:08 2008 +0000" }, "message": "ARMv7: Do not set TTBR0 in __v7_setup\n\nThis register is set in __enable_mmu in the head.S file.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n\n\n\n\n" }, { "commit": "c30c2f99e10b6a810dae9a25b35c6d48796d8ffb", "tree": "ba62c6796e789fc5dfcb16ec8cddb2f1c89203b8", "parents": [ "2bedbdf4148ebbe48c7a89449ab52e475a788f42" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Nov 06 13:23:07 2008 +0000" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Nov 06 13:23:07 2008 +0000" }, "message": "ARMv7: Add extra barriers for flush_cache_all compressed/head.S\n\nThe flush_cache_all function on ARMv7 is implemented as a series of\ncache operations by set/way. These are not guaranteed to be ordered with\nprevious memory accesses, requiring a DMB. This patch also adds barriers\nfor the TLB operations in compressed/head.S\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n\n\n\n\n" }, { "commit": "6bee00dbbcb1e9feb0510e9a7104b4af00adc574", "tree": "dd0b20bbbe353ece29a78a75b155e6d8bbd2c86e", "parents": [ "e013e13bf605b9e6b702adffbe2853cfc60e7806" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Oct 24 10:21:45 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Oct 24 10:21:45 2008 -0700" }, "message": "[ARM] xsc3: revert writethrough memory-type encoding change\n\nCommit 40df2d1d \"[ARM] Update Xscale and Xscale3 PTE mappings\" was\nfingered by git-bisect for a boot failure on iop13xx. The change made\nL_PTE_MT_WRITETHROUGH mappings L2-uncacheable. Russell points out that\nthis mapping is used for the vector page. Given the regression, and the\nfact this page is used often, restore the old behaviour.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f80a3bb252cbb0959259328b9ab02b019123ed05", "tree": "bfc9cf861aa4ff025dbdf524c1b70700354ff7c1", "parents": [ "085eefb5948bb43020792f31406da2ee2ef4e924" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Wed Oct 22 13:04:30 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 22 19:40:21 2008 +0100" }, "message": "[ARM] 5318/1: Swap the PRRR and NMRR values in proc-v7.S\n\nA typo caused these values to be swapped leading to incorrect memory\ntype attributes.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f20e3b5fe7ead0615309433260b9784d8da0bbbd", "tree": "eabb2e47a0355ac4e8024b7087b4e7cb9f324358", "parents": [ "bcbfe664e7af019e698cef2feb85ac2b4f1ac11d", "f030d7b65e4e6399f23de2a41a58d1b607b6bd89" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Wed Oct 22 19:34:09 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 22 19:34:09 2008 +0100" }, "message": "Merge branch \u0027for-rmk\u0027 of git://git.android.com/kernel into devel\n" }, { "commit": "1637de0c9b4dbac0f185e94b2b8cd2c2db78700d", "tree": "4b7f9662891e90036a5e03b3241641c5b27c2af5", "parents": [ "2515ddc6db8eb49a79f0fe5e67ff09ac7c81eab4" ], "author": { "name": "Brian Swetland", "email": "swetland@google.com", "time": "Tue Sep 09 07:13:33 2008 -0700" }, "committer": { "name": "Brian Swetland", "email": "swetland@google.com", "time": "Wed Oct 22 02:39:32 2008 -0700" }, "message": "[ARM] msm: rename ARCH_MSM7X00A to ARCH_MSM\n\nThe MSM architecture covers a wider family of chips than just the MSM7X00A.\nMove to a more generic name, in perparation for supporting the specific\nSoC variants as sub-architectures (ARCH_MSM7X01A, ARCH_MSM722X, etc). This\ngives us ARCH_MSM for the (many) common peripherals.\n\nThis also removes the unused/obsolete config item MSM7X00A_IDLE.\n\nSigned-off-by: Brian Swetland \u003cswetland@google.com\u003e\n" }, { "commit": "e4d2a5985af957d2c0da61fb978d0c414b92a562", "tree": "0f8adefd6c9d91e1da76c3e833d29e36a3a72623", "parents": [ "957cf333b5284943c4866e1d0339a105d2762c9c" ], "author": { "name": "Anders Grafström", "email": "grfstrm@users.sourceforge.net", "time": "Thu Oct 16 17:37:24 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Oct 17 13:44:27 2008 +0100" }, "message": "[ARM] 5310/1: Fix cache flush functions for ARMv4\n\nARMv4 (ARM720T) cache flush functions are broken in 2.6.19+ kernels.\nThe issue was introduced by commit f12d0d7c7786af39435ef6ae9defe47fb58f6091\nThis patch corrects the CPU_CP15 ifdef statements so that they actually\ndo something.\n\nSigned-off-by: Anders Grafström \u003cgrfstrm@users.sourceforge.net\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b6825d2df55aa7d7341c715b577b73a6a03dc944", "tree": "ae4f0f52f4c2ad4e501dd323318486ccdd7fcd93", "parents": [ "6defd90433729c2d795865165cb34d938d8ff07c", "aa59e19d05114f9fb7718d6bc8398255476fb4f5" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Tue Oct 14 22:24:42 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Oct 14 22:24:42 2008 +0100" }, "message": "Merge branch \u0027omap-all\u0027 into devel\n\nConflicts:\n\n\tarch/arm/mach-omap2/gpmc.c\n\tarch/arm/mach-omap2/irq.c\n" }, { "commit": "6defd90433729c2d795865165cb34d938d8ff07c", "tree": "ebb963c6db463296b8f926d79d7ddc8c1251ca24", "parents": [ "c97f68145e8067b3ac4b126a6faebf90f9ffc302", "99c6bb390cf599b9e0aa6e69beacc4e5d875bf77" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Oct 09 21:33:07 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Oct 09 21:33:07 2008 +0100" }, "message": "Merge branch \u0027for-rmk\u0027 of git://git.marvell.com/orion\n\nMerge branch \u0027orion-devel\u0027 into devel\n" }, { "commit": "6a4690c22f5da1eb1c898b61b6a80da52fbd976f", "tree": "a03891a32abe0da191fb765fe669a597e07423c6", "parents": [ "90bb28b0644f7324f8bd1feb27b35146e6785ba2", "8ec53663d2698076468b3e1edc4e1b418bd54de3" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Oct 09 21:31:56 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Oct 09 21:31:56 2008 +0100" }, "message": "Merge branch \u0027ptebits\u0027 into devel\n\nConflicts:\n\n\tarch/arm/Kconfig\n" }, { "commit": "2885f00049f80287b14192145699774fa55c14f7", "tree": "be5eb9664479e80828c1b4b8fc40e382ea668ef4", "parents": [ "cc26b3b01bc96a8b8c36671b0dc4898b2a152ea8" ], "author": { "name": "Syed Mohammed, Khasim", "email": "khasim@ti.com", "time": "Thu Oct 09 17:51:42 2008 +0300" }, "committer": { "name": "Tony Lindgren", "email": "tony@atomide.com", "time": "Thu Oct 09 17:51:42 2008 +0300" }, "message": "ARM: OMAP3: Add minimal Beagle board support\n\nAdd minimal Beagle board support. Based on earlier patches\nby Syed Mohammed Khasim with some fixes from linux-omap tree.\n\nSigned-off-by: Syed Mohammed Khasim \u003ckhasim@ti.com\u003e\nSigned-off-by: Tony Lindgren \u003ctony@atomide.com\u003e\n\n\n" }, { "commit": "000b50259271c9c14f6e175795f5164e1d51d35b", "tree": "d6c5cde5c74cb84e8ad4d3dc5beefdd131c0c010", "parents": [ "3319f5e51a20f3e3c59ed7dac9fc2d5c89aa2d9f" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Oct 03 11:09:10 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Oct 03 11:32:09 2008 +0100" }, "message": "[ARM] 5229/3: Replace some ARMv7 opcodes with the instruction name\n\nThese instructions were placed in the code directly as opcodes because\nearly compilers didn\u0027t support them. Toolchains supporting ARMv7\nunderstand these instructions and the patch puts the mnemonics back.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b7a69ac303cbfc8d6fa8e91d10e8049244ba6847", "tree": "158deb4f96730bb7850ef50dc81dc1df7683439f", "parents": [ "d2a38ef9c1585b47462c7be5501228ac57fbd3b1" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Wed Oct 01 16:58:32 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 01 17:24:04 2008 +0100" }, "message": "[ARM] mm: finish ARM sparsemem support\n\n... including some comments about the ordering required to bring\nsparsemem up. You have to repeatedly guess, test, reguess, try\nagain and again to work out what the right ordering is. Many\nhours later...\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d2a38ef9c1585b47462c7be5501228ac57fbd3b1", "tree": "81ae36059881fbee802ec45081a74a866d92819e", "parents": [ "6c5da7aced798c7781f054a76c769b85f0173561" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Wed Oct 01 16:56:15 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 01 17:22:02 2008 +0100" }, "message": "[ARM] mm: provide helpers for accessing membanks\n\nProvide helpers for getting physical addresses or pfns from the\nmeminfo array, and use them. Move for_each_nodebank() to\nasm/setup.h alongside the meminfo structure definition.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "5ec9407dd1196daaf12b427b351e2cd62d2a16a7", "tree": "023332e9fd67d7ce0897071058db87e679bce58b", "parents": [ "9b727abdff93b0039fba94e96216fc280af4cf01" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Sep 07 19:15:31 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 01 16:41:10 2008 +0100" }, "message": "[ARM] Don\u0027t include asm/elf.h in asm code\n\nasm code really wants asm/hwcap.h, so include that instead.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "db5b7169474882fabbd811a4cf5c1bae3157e677", "tree": "b4218f6251b6719638f716fcc5aac62375903fe4", "parents": [ "40df2d1d8538865341a4cb9d4b7a375296517ad2" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Sep 07 12:42:51 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 01 16:41:06 2008 +0100" }, "message": "[ARM] Remove MT_DEVICE_IXP2000 and associated definitions\n\nAs of the previous commit, MT_DEVICE_IXP2000 encodes to the same\nPTE bit encoding as MT_DEVICE, so it\u0027s now redundant. Convert\nMT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "40df2d1d8538865341a4cb9d4b7a375296517ad2", "tree": "2b97595b5d31917432af57e4d9a70f8a459d8f65", "parents": [ "40d192b63d079db1f76cec9ae8ccbf461fda23e4" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Sep 07 12:36:46 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 01 16:41:04 2008 +0100" }, "message": "[ARM] Update Xscale and Xscale3 PTE mappings\n\nUse \u0027shared device\u0027 mappings for devices, and use the standard\nbit combinations for Xscale3.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "40d192b63d079db1f76cec9ae8ccbf461fda23e4", "tree": "60ea8ec4390964e6f8d09b017f5c871c7ea85df0", "parents": [ "3f69c0c1af288d6b124d0a928a33b51061ebf850" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Sep 06 21:15:56 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 01 16:41:02 2008 +0100" }, "message": "[ARM] remove \u0027prot_pte_ext\u0027 from memory type table\n\nThis member is now redundant; the memory type is encoded in the Linux\nPTE bits.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "3f69c0c1af288d6b124d0a928a33b51061ebf850", "tree": "fb6b4b13c2423e98089489056d5a35cd7b0a0400", "parents": [ "639b0ae7f5bcd645862a9c3ea2d4321475c71d7a" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Sep 15 17:23:10 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 01 16:41:01 2008 +0100" }, "message": "[ARM] Convert ARMv7 to use TEX remapping\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "639b0ae7f5bcd645862a9c3ea2d4321475c71d7a", "tree": "34e26970f8c907c9027037fc9ae5a9ab7cd2d1a2", "parents": [ "9e8b5199a753a2583a8ef8360e6428304a242283" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Sep 06 21:07:45 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 01 16:41:00 2008 +0100" }, "message": "[ARM] Convert ARMv6 and ARMv7 to use new memory types\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9e8b5199a753a2583a8ef8360e6428304a242283", "tree": "cfd065b410dd5fe5c14843b71368e0916a496739", "parents": [ "bb30f36f9b71c31dc8fe3483bba4c9884fc86080" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Sep 06 20:47:54 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 01 16:40:58 2008 +0100" }, "message": "[ARM] Convert Xscale and Xscale3 to use new memory types\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "bb30f36f9b71c31dc8fe3483bba4c9884fc86080", "tree": "c99b583586ebec2a29be2b0173d1eb9ad07a68f9", "parents": [ "9cff96e5bfc8e366166bfb07610604c7604ac48c" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Sep 06 20:04:59 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 01 16:40:56 2008 +0100" }, "message": "[ARM] Introduce new PTE memory type bits\n\nProvide L_PTE_MT_xxx definitions to describe the memory types that we\nuse in Linux/ARM. These definitions are carefully picked such that:\n\n1. their LSBs match what is required for pre-ARMv6 CPUs.\n2. they all have a unique encoding, including after modification\n by build_mem_type_table() (the result being that some have more\n than one combination.)\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "da0916539d20f257dfa46784357300e49d6bfd00", "tree": "e581749819a4a7e5aea471c242a51773a360bd1d", "parents": [ "1ad77a876da48331451698cc4172c90ab9b6372f" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Sep 06 17:19:08 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 01 16:40:52 2008 +0100" }, "message": "[ARM] Convert set_pte_ext implementions to macros\n\nThere are actually only four separate implementations of set_pte_ext.\nUse assembler macros to insert code for these into the proc-*.S files.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "6c5da7aced798c7781f054a76c769b85f0173561", "tree": "a4713f081e16183b6ed00368658ee77bcca83cf6", "parents": [ "eca73214c9c50e290b8dc823b41730b01788872d" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Tue Sep 30 19:31:44 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 30 21:34:16 2008 +0100" }, "message": "[ARM] mm: move vmalloc\u003d parsing to arch/arm/mm/mmu.c\n\nThere\u0027s no point scattering this around the tree, the parsing\nof the parameter might as well live beside the code which uses\nit. That also means we can make vmalloc_reserve a static\nvariable.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "eca73214c9c50e290b8dc823b41730b01788872d", "tree": "22df16b626afa6fb9755ce289c6efa254f1ae3d4", "parents": [ "da46c79a5418dd6ba006665c1535af0713bb77b9" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Tue Sep 30 19:29:25 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 30 21:34:15 2008 +0100" }, "message": "[ARM] mm: move validation of membanks to one place\n\nThe newly introduced sanity_check_meminfo() function should be\nused to collect all validation of the meminfo array, which we\nhave in bootmem_init(). Move it there.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "99c6bb390cf599b9e0aa6e69beacc4e5d875bf77", "tree": "d30e32867cd161001e5ae6fecc51a52f469bbaff", "parents": [ "92a5de80e5c53c56d098ea3cb6266138efd892f6" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Thu Sep 11 15:14:59 2008 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Tue Sep 30 13:41:54 2008 -0400" }, "message": "[ARM] Feroceon: small cleanups to L2 cache code\n\n- Make sure that coprocessor instructions for range ops are contiguous\n and not reordered.\n\n- s/invalidate_and_disable_dcache/flush_and_disable_dcache/\n\n- Don\u0027t re-enable I/D caches if they were not enabled initially.\n\n- Change some masks to shifts for better generated code.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nAcked-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\n" }, { "commit": "da46c79a5418dd6ba006665c1535af0713bb77b9", "tree": "cd7c3530be58cb7dc9fbd1ddd891bddedefcba21", "parents": [ "dfcc64497cbbf942cdd5af4b7eb17542b62aa759" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Tue Sep 30 16:10:11 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 30 16:41:04 2008 +0100" }, "message": "[ARM] 5272/1: remove conditional compilation in show_pte()\n\nThe PTRS_PER_PMD !\u003d 1 condition can be evaluated with C code and\noptimized at compile time.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "309dbbabee7b19e003e1ba4b98f43d28f390a84e", "tree": "ba748b84c0573f5eb151a581e333b95010576521", "parents": [ "0e18b5d7c6339311f1e32e7b186ae3556c5b6d33" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Sep 29 19:50:59 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 30 11:01:36 2008 +0100" }, "message": "[ARM] dma: don\u0027t touch cache on dma_*_for_cpu()\n\nAs per the dma_unmap_* calls, we don\u0027t touch the cache when a DMA\nbuffer transitions from device to CPU ownership. Presently, no\nproblems have been identified with speculative cache prefetching\nwhich in itself is a new feature in later architectures. We may\nhave to revisit the DMA API later for these architectures anyway.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "2638b4dbe768aba023a06acd8e7eba708bb76ee6", "tree": "41e464b337ec85444d8c551947de13bb8731af70", "parents": [ "01135d92c1a540cd3370f7cf3d1c762320b85034" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Sep 25 21:38:41 2008 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Sep 29 10:40:16 2008 +0100" }, "message": "[ARM] dma: Reduce to one dma_sync_sg_* implementation\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" } ], "next": "01135d92c1a540cd3370f7cf3d1c762320b85034" }