)]}' { "log": [ { "commit": "73d2eaac8a3f1ec1d6d0a80ea7302a439ca9b933", "tree": "1656adeecc51ba47cc4c081d0d7c56d7ec75ced2", "parents": [ "2938429501b73f6aeb312236eac7ed0416a07cd5" ], "author": { "name": "Andres Salomon", "email": "dilinger@collabora.co.uk", "time": "Fri Feb 05 01:42:43 2010 -0500" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Feb 05 07:36:50 2010 -0800" }, "message": "CS5536: apply pci quirk for BIOS SMBUS bug\n\nThe new cs5535-* drivers use PCI header config info rather than MSRs to\ndetermine the memory region to use for things like GPIOs and MFGPTs. As\nanticipated, we\u0027ve run into a buggy BIOS:\n\n[ 0.081818] pci 0000:00:14.0: reg 10: [io 0x6000-0x7fff]\n[ 0.081906] pci 0000:00:14.0: reg 14: [io 0x6100-0x61ff]\n[ 0.082015] pci 0000:00:14.0: reg 18: [io 0x6200-0x63ff]\n[ 0.082917] pci 0000:00:14.2: reg 20: [io 0xe000-0xe00f]\n[ 0.083551] pci 0000:00:15.0: reg 10: [mem 0xa0010000-0xa0010fff]\n[ 0.084436] pci 0000:00:15.1: reg 10: [mem 0xa0011000-0xa0011fff]\n[ 0.088816] PCI: pci_cache_line_size set to 32 bytes\n[ 0.088938] pci 0000:00:14.0: address space collision: [io 0x6100-0x61ff] already in use\n[ 0.089052] pci 0000:00:14.0: can\u0027t reserve [io 0x6100-0x61ff]\n\nThis is a Soekris board, and its BIOS sets the size of the PCI ISA bridge\ndevice\u0027s BAR0 to 8k. In reality, it should be 8 bytes (BAR0 is used for\nSMBus stuff). This quirk checks for an incorrect size, and resets it\naccordingly.\n\nSigned-off-by: Andres Salomon \u003cdilinger@collabora.co.uk\u003e\nTested-by: Leigh Porter \u003cleigh@leighporter.org\u003e\nTested-by: Jens Rottmann \u003cJRottmann@LiPPERTEmbedded.de\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "32337f8a7020676b5fd6387def9ccb9060440c5c", "tree": "7688f053cc9a3be1e99a492c33b85473cd57c859", "parents": [ "abe94c756c08d50566c09a65b9c7fe72f83071c5", "94f28da8409c6059135e89ac64a0839993124155" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Feb 01 10:37:58 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Feb 01 10:37:58 2010 -0800" }, "message": "Merge branch \u0027merge\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc\n\n* \u0027merge\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:\n powerpc: TIF_ABI_PENDING bit removal\n powerpc/pseries: Fix xics build without CONFIG_SMP\n powerpc/4xx: Add pcix type 1 transactions\n powerpc/pci: Add missing call to header fixup\n powerpc/pci: Add missing hookup to pci_slot\n powerpc/pci: Add calls to set_pcie_port_type() and set_pcie_hotplug_bridge()\n powerpc/40x: Update the PowerPC 40x board defconfigs\n powerpc/44x: Update PowerPC 44x board defconfigs\n" }, { "commit": "bb209c8287d2d55ec4a67e3933346e0a3ee0da76", "tree": "2e444f273e631fa4dded4ee13ac779565e5efb43", "parents": [ "b04da8bfdfbbd79544cab2fadfdc12e87eb01600" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Tue Jan 26 17:10:03 2010 +0000" }, "committer": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Fri Jan 29 16:51:10 2010 +1100" }, "message": "powerpc/pci: Add calls to set_pcie_port_type() and set_pcie_hotplug_bridge()\n\nWe are missing these when building the pci_dev from scratch off\nthe Open Firmware device-tree\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bd1f46deba615971a58193afd0202878cadf19a7", "tree": "1a197e82ad0f6314f0ff0507c04030aaad933c7c", "parents": [ "61c39bb354a1f791ba6f562b766a72e508a036ee" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Fri Jan 22 14:06:53 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 25 10:42:52 2010 -0800" }, "message": "PCI: fix nested spinlock hang in aer_inject\n\nThe aer_inject module hangs in aer_inject() when checking the device\u0027s\nerror masks. The hang is due to a recursive use of the aer_inject lock.\nThe aer_inject() routine grabs the lock while processing the error and then\ncalls pci_read_config_dword to read the masks. The pci_read_config_dword\nroutine is earlier overridden by pci_read_aer, which among other things,\ngrabs the aer_inject lock.\n\nFixed by moving the pci_read_config_dword calls to read the masks to before\nthe lock is taken.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b49bfd32901625e4adcfee011d2b32a43b4db67d", "tree": "2a83d0d739df23b96b094de83880defc05ea0a6a", "parents": [ "1ae861e652b5457e7fa98ccbc55abea1e207916e" ], "author": { "name": "Youquan,Song", "email": "youquan.song@linux.intel.com", "time": "Thu Dec 17 08:22:48 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 15:52:49 2010 -0800" }, "message": "PCIe AER: prevent AER injection if hardware masks error reporting\n\nThe Correcteable/Uncorrectable Error Mask Registers are used by PCIe AER\ndriver which will controls the reporting of individual errors to PCIe RC\nvia PCIe error messages.\n\nIf hardware masks special error reporting to RC, the aer_inject driver\nshould not inject aer error.\n\nAcked-by: Andi Kleen \u003cak@linux.intel.com\u003e\nSigned-off-by: Youquan, Song \u003cyouquan.song@intel.com\u003e\nAcked-by: Ying, Huang \u003cying.huang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1ae861e652b5457e7fa98ccbc55abea1e207916e", "tree": "d0326aab2746a779f3ab140ec9fdea2508f2e99b", "parents": [ "6be954d1f91b81ca85c74792b13654069278c577" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Thu Dec 31 12:15:54 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 15:41:47 2010 -0800" }, "message": "PCI/PM: Use per-device D3 delays\n\nIt turns out that some PCI devices require extra delays when changing\npower state from D3 to D0 (and the other way around). Although this\nis against the PCI specification, we can handle it quite easily by\nallowing drivers to define arbitrary D3 delays for devices known to\nrequire extra time for switching power states.\n\nIntroduce additional field d3_delay in struct pci_dev and use it to\nstore the value of the device\u0027s D0-\u003eD3 delay, in miliseconds. Make\nthe PCI PM core code use the per-device d3_delay unless\npci_pm_d3_delay is greater (in which case the latter is used).\n[This also allows the driver to specify d3_delay shorter than the\n 10 ms required by the PCI standard if the device is known to be able\n to handle that.]\n\nMake the sky2 driver set d3_delay to 150 for devices handled by it.\n\nFixes http://bugzilla.kernel.org/show_bug.cgi?id\u003d14730 which is a\nlisted regression from 2.6.30.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6be954d1f91b81ca85c74792b13654069278c577", "tree": "c1e769d05028d8b8dc2058b10e7d0be01a9b2be5", "parents": [ "46256f83d0d066f99ffde547f27473dfd2a78009" ], "author": { "name": "David John", "email": "davidjon@xenontk.org", "time": "Mon Jan 04 20:28:57 2010 +0530" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 15:10:56 2010 -0800" }, "message": "PCI: Check the node argument passed to cpumask_of_node\n\nCommit e0cd516 \"PCI: derive nearby CPUs from device\u0027s instead of bus\u0027\nNUMA information\" causes an null pointer dereference when reading from\nthe sysfs attributes local_cpu* on Intel machines with no ACPI NUMA\nproximity info, since dev-\u003enuma_node gets set to -1 for all PCI devices,\nwhich then gets passed to cpumask_of_node.\n\nAdd a check to prevent this.\n\nSigned-off-by: David John \u003cdavidjon@xenontk.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "46256f83d0d066f99ffde547f27473dfd2a78009", "tree": "b70c070f59d510d3d0e974009199a1c175d753d3", "parents": [ "40da4186a53e59d801130156ecb89fc5830ff227" ], "author": { "name": "Youquan,Song", "email": "youquan.song@linux.intel.com", "time": "Fri Dec 11 18:42:35 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 08:31:46 2010 -0800" }, "message": "PCI: AER: fix aer inject result in kernel oops\n\nIf the BIOS does not export _OSC to allow OS take over the PCIe AER, the\npcie aer driver will not initialize the aer service. However, the\naer_inject driver does not check this scenario, which results in a kernel\noops when injecting an aer error into OS. For example:\n\nBUG: unable to handle kernel NULL pointer dereference at 0000000000000350\nIP: [\u003cffffffff812e08f7\u003e] _spin_lock_irqsave+0xc/0x23\nPGD 155c41067 PUD 157fe0067 PMD 0\nOops: 0002 [#1] SMP\nPid: 5119, comm: aer-inject Not tainted 2.6.32-rc8-mce #2\nRIP: 0010:[\u003cffffffff812e08f7\u003e] [\u003cffffffff812e08f7\u003e] _spin_lock_irqsave+0xc/0x23\nRSP: 0018:ffff880157f81e28 EFLAGS: 00010096\nRAX: 0000000000000296 RBX: 0000000000000000 RCX: 0000000000000100\nRDX: 0000000000010000 RSI: 0000000000000246 RDI: 0000000000000350\nRBP: ffff880157f81e28 R08: 0000000000000004 R09: ffff880157f81dac\nR10: ffff88015a666f60 R11: ffff88015a666f40 R12: ffff88015758cc00\nR13: 0000000000000350 R14: 0000000000000000 R15: 0000000000000100\nFS: 00007f4d4a66e6f0(0000) GS:ffff8800282e0000(0000) knlGS:0000000000000000\nCS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b\nCR2: 0000000000000350 CR3: 000000015661a000 CR4: 00000000000006e0\nDR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000\nDR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400\nProcess aer-inject (pid: 5119, threadinfo ffff880157f80000, task ffff8801585f4340)\nStack:\n ffff880157f81e78 ffffffff811b1615 ffff880157f81e78 ffffffff81222823\nCall Trace:\n [\u003cffffffff811b1615\u003e] aer_irq+0x38/0x117\n [\u003cffffffff81222823\u003e] ? device_for_each_child+0x5f/0x6f\n [\u003cffffffffa00967bf\u003e] aer_inject_write+0x409/0x45e [aer_inject]\n [\u003cffffffff810eb80e\u003e] vfs_write+0xae/0x16a\n [\u003cffffffff810eb98e\u003e] sys_write+0x47/0x6e\n [\u003cffffffff8100ba2b\u003e] system_call_fastpath+0x16/0x1b\nRIP [\u003cffffffff812e08f7\u003e] _spin_lock_irqsave+0xc/0x23\n RSP \u003cffff880157f81e28\u003e\nCR2: 0000000000000350\n\nSo check the _OSC before assuming that AER is available to the OS.\n\nSigned-off-by: Youquan, Song \u003cyouquan.song@intel.com\u003e\nAcked-by: Ying, Huang \u003cying.huang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "40da4186a53e59d801130156ecb89fc5830ff227", "tree": "8eab64b223ca9657a65fb0650f10dce68ff6420f", "parents": [ "45d28b097280a78893ce25a5d0db41e6a2717853" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Tue Dec 15 11:38:04 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 08:29:37 2010 -0800" }, "message": "PCI: pcie portdrv: style cleanup\n\nNo change in logic.\n\nBefore:\n drivers/pci/pcie/portdrv_core.c:\n total: 7 errors, 2 warnings, 508 lines checked\n drivers/pci/pcie/portdrv_pci.c:\n total: 4 errors, 2 warnings, 300 lines checked\n\nAfter:\n drivers/pci/pcie/portdrv_core.c:\n total: 0 errors, 0 warnings, 506 lines checked\n drivers/pci/pcie/portdrv_pci.c:\n total: 0 errors, 0 warnings, 299 lines checked\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "df9d1e8a4379119cbc47c474f168b5103e404e17", "tree": "4cb583dd397985c80ebb0e67f9ac566330477929", "parents": [ "c03f6bfc9f4fbeee14abef81ece67e39150a1ab1" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 31 16:44:43 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 31 16:44:43 2009 -0800" }, "message": "pci: avoid compiler warning in quirks.c\n\nIntroduced by commit 5b889bf23 (\"PCI: Fix build if quirks are not\nenabled\"), which made the pci_dev_reset_methods[] array static and\n\u0027const\u0027, but didn\u0027t then change the code to match, and use a const\npointer when moving it to quirks.c.\n\nTrivially fixed by just adding the required \u0027const\u0027 to the iterator\nvariable.\n\nReported-by: Stephen Rothwell \u003csfr@canb.auug.org.au\u003e\nCc: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "5b889bf237fca383b5807ad69fde3ad1e2287e42", "tree": "91c1df6fe04a187d31b62d96b1aa70abf3e04710", "parents": [ "9de54606d3d55095e4426a81a79a41d8e5e5b6be" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Thu Dec 31 19:06:35 2009 +0100" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 31 12:00:45 2009 -0800" }, "message": "PCI: Fix build if quirks are not enabled\n\nAfter commit b9c3b266411d27f1a6466c19d146d08db576bfea (\"PCI: support\ndevice-specific reset methods\") the kernel build is broken if\nCONFIG_PCI_QUIRKS is unset.\n\nFix this by moving pci_dev_specific_reset() to drivers/pci/quirks.c and\nproviding an empty replacement for !CONFIG_PCI_QUIRKS builds.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nReported-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "d661d76b0262f3ed649a1dea24c0119757592b09", "tree": "ff56854943219c16f51e18c5360b9626c3a20474", "parents": [ "b07d41b77e58baa2df2326cec68dde03cb2348c5", "2d1c861871d767153538a77c498752b36d4bb4b8" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 30 13:13:24 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 30 13:13:24 2009 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n PCI/cardbus: Add a fixup hook and fix powerpc\n PCI: change PCI nomenclature in drivers/pci/ (non-comment changes)\n PCI: change PCI nomenclature in drivers/pci/ (comment changes)\n PCI: fix section mismatch on update_res()\n PCI: add Intel 82599 Virtual Function specific reset method\n PCI: add Intel USB specific reset method\n PCI: support device-specific reset methods\n PCI: Handle case when no pci device can provide cache line size hint\n PCI/PM: Propagate wake-up enable for PCIe devices too\n vgaarbiter: fix a typo in the vgaarbiter Documentation\n" }, { "commit": "2d1c861871d767153538a77c498752b36d4bb4b8", "tree": "2ed80140487cd68e539c55876ba361199a4b92c1", "parents": [ "7e8af37a9a71b479f58d2fd5f0ddaa6780c51f11" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Wed Dec 09 17:52:13 2009 +1100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 18:55:51 2009 -0800" }, "message": "PCI/cardbus: Add a fixup hook and fix powerpc\n\nThe cardbus code creates PCI devices without ever going through the\nnecessary fixup bits and pieces that normal PCI devices go through.\n\nThere\u0027s in fact a commented out call to pcibios_fixup_bus() in there,\nit\u0027s commented because ... it doesn\u0027t work.\n\nI could make pcibios_fixup_bus() do the right thing on powerpc easily\nbut I felt it cleaner instead to provide a specific hook pci_fixup_cardbus\nfor which a weak empty implementation is provided by the PCI core.\n\nThis fixes cardbus on powerbooks and probably all other PowerPC\nplatforms which was broken completely for ever on some platforms and\nsince 2.6.31 on others such as PowerBooks when we made the DMA ops\nmandatory (since those are setup by the fixups).\n\nAcked-by: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7e8af37a9a71b479f58d2fd5f0ddaa6780c51f11", "tree": "c83fc67ebf0df900bf7ac3c30cd282f28a13b8a6", "parents": [ "45e829ea412760d2404d7dfc42528df46aedbf62" ], "author": { "name": "Stefan Assmann", "email": "sassmann@redhat.com", "time": "Thu Dec 03 18:00:10 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:54 2009 -0800" }, "message": "PCI: change PCI nomenclature in drivers/pci/ (non-comment changes)\n\nChanging occurrences of variants of PCI-X and PCIe to the PCI-SIG\nterms listed in the \"Trademark and Logo Usage Guidelines\".\nhttp://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf\n\nPatch is limited to drivers/pci/ and changes concern non-comment parts or\nanything that might be visible to the user.\n\nSigned-off-by: Stefan Assmann \u003csassmann@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "45e829ea412760d2404d7dfc42528df46aedbf62", "tree": "869581b5828f9eb16a5ce38231b58a80a30be67c", "parents": [ "5714868812b563ba8816c1d974f4f07c76941c30" ], "author": { "name": "Stefan Assmann", "email": "sassmann@redhat.com", "time": "Thu Dec 03 06:49:24 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:53 2009 -0800" }, "message": "PCI: change PCI nomenclature in drivers/pci/ (comment changes)\n\nChanging occurrences of variants of PCI-X and PCIe to the PCI-SIG\nterms listed in the \"Trademark and Logo Usage Guidelines\".\nhttp://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf\n\nPatch is limited to drivers/pci/ and changes concern comments only.\n\nSigned-off-by: Stefan Assmann \u003csassmann@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c763e7b58f71833e6cb7b05493eb1adda4811b08", "tree": "0fb92e114a0762da1d3f910506bf9c6e2bf6328b", "parents": [ "aeb30016fec3378c543cae33654c2144277fe674" ], "author": { "name": "Dexuan Cui", "email": "dexuan.cui@intel.com", "time": "Mon Dec 07 13:03:23 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:52 2009 -0800" }, "message": "PCI: add Intel 82599 Virtual Function specific reset method\n\nHandle device specific timeout and use FLR.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Dexuan Cui \u003cdexuan.cui@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "aeb30016fec3378c543cae33654c2144277fe674", "tree": "f45c459334b963634d0c54aab4d3c0ff46e686b1", "parents": [ "b9c3b266411d27f1a6466c19d146d08db576bfea" ], "author": { "name": "Dexuan Cui", "email": "dexuan.cui@intel.com", "time": "Mon Dec 07 13:03:22 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:51 2009 -0800" }, "message": "PCI: add Intel USB specific reset method\n\nHandle device specific reset requirements (i.e. vendor reg for reset\nalong with appropriate timeout).\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Dexuan Cui \u003cdexuan.cui@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b9c3b266411d27f1a6466c19d146d08db576bfea", "tree": "c310b37e7dff6607e22eca0b690c2a3f290c85a9", "parents": [ "2820f333e3b4ad96590093efbed7b3400bcf492b" ], "author": { "name": "Dexuan Cui", "email": "dexuan.cui@intel.com", "time": "Mon Dec 07 13:03:21 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:50 2009 -0800" }, "message": "PCI: support device-specific reset methods\n\nAdd a new type of quirk for resetting devices at pci_dev_reset time.\nThis is necessary to handle device with nonstandard reset procedures,\nespecially useful for guest drivers.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Dexuan Cui \u003cdexuan.cui@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2820f333e3b4ad96590093efbed7b3400bcf492b", "tree": "47a9e4ebacfc0df5c070a1f70cc68a9f9af4e164", "parents": [ "dc1a94ae1749d14c55f8b54e9d92bd89df82d51a" ], "author": { "name": "Csaba Henk", "email": "csaba@gluster.com", "time": "Tue Dec 15 17:55:25 2009 +0530" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:50 2009 -0800" }, "message": "PCI: Handle case when no pci device can provide cache line size hint\n\nPrior to this patch, if pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, ...)\nreturns 0 for all dev, pci_cache_line_size ends up set to zero\n(instead of pci_dfl_cache_line_size).\n\nThis patch ensures the pci_cache_line_size \u003d pci_dfl_cache_line_size\nsetting in the above scenario.\n\nThis happens in case of a kvm-88 guest (where, consequently, the rtl8139\nNIC failed to initialize).\n\nAcked-by: Tejun Heo \u003ctj@kernel.org\u003e\nSigned-off-by: Csaba Henk \u003ccsaba@gluster.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dc1a94ae1749d14c55f8b54e9d92bd89df82d51a", "tree": "6a5df75770f1ddf65d70a694fb83d00b8ec986c2", "parents": [ "15293df82bd1c15196e7cb336130c243e9a41806" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sun Nov 29 16:35:54 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:49 2009 -0800" }, "message": "PCI/PM: Propagate wake-up enable for PCIe devices too\n\nHaving read the PM part of the PCIe 2.0 specification more carefully\nI think that it was a mistake to restrict the wake-up enable\npropagation to non-PCIe devices, because if we do not request\ncontrol of the root ports\u0027 PME registers via OSC, PCIe PME is\nsupposed to be handled by the platform, just like the non-PCIe PME.\nEven if we do that, the wake-up propagation is done to allow the\ndevices to wake up the system from sleep states which involves the\nplatform anyway, so it won\u0027t hurt.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a79960e576ebca9dbf24489b562689f2be7e9ff0", "tree": "b0748839230c2bba1d49ccdd732608d7d1f334cb", "parents": [ "661e338f728d101b4839b6b157d44cfcb80e3c5e", "cd7bcf32d42b15891620b3f1387a00178b54291a" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 16 10:11:38 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 16 10:11:38 2009 -0800" }, "message": "Merge git://git.infradead.org/iommu-2.6\n\n* git://git.infradead.org/iommu-2.6:\n implement early_io{re,un}map for ia64\n Revert \"Intel IOMMU: Avoid memory allocation failures in dma map api calls\"\n intel-iommu: ignore page table validation in pass through mode\n intel-iommu: Fix oops with intel_iommu\u003digfx_off\n intel-iommu: Check for an RMRR which ends before it starts.\n intel-iommu: Apply BIOS sanity checks for interrupt remapping too.\n intel-iommu: Detect DMAR in hyperspace at probe time.\n dmar: Fix build failure without NUMA, warn on bogus RHSA tables and don\u0027t abort\n iommu: Allocate dma-remapping structures using numa locality info\n intr_remap: Allocate intr-remapping table using numa locality info\n dmar: Allocate queued invalidation structure using numa locality info\n dmar: support for parsing Remapping Hardware Static Affinity structure\n" }, { "commit": "471452104b8520337ae2fb48c4e61cd4896e025d", "tree": "8594ae4a8362014e3cccf72a4e8834cdbb610bdd", "parents": [ "0ead0f84e81a41c3e98aeceab04af8ab1bb08d1f" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Mon Dec 14 18:00:08 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Dec 15 08:53:25 2009 -0800" }, "message": "const: constify remaining dev_pm_ops\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "11bd04f6f35621193311c32e0721142b073a7794", "tree": "00979740582bb26e8d3756bf3526c85f19f66a46", "parents": [ "4e2ccdb0409146f8cf64a11b6ef82a9c928ced2a", "9e0b5b2c447ad0caa075a5cfef86def62e1782ff" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Dec 11 12:18:16 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Dec 11 12:18:16 2009 -0800" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (109 commits)\n PCI: fix coding style issue in pci_save_state()\n PCI: add pci_request_acs\n PCI: fix BUG_ON triggered by logical PCIe root port removal\n PCI: remove ifdefed pci_cleanup_aer_correct_error_status\n PCI: unconditionally clear AER uncorr status register during cleanup\n x86/PCI: claim SR-IOV BARs in pcibios_allocate_resource\n PCI: portdrv: remove redundant definitions\n PCI: portdrv: remove unnecessary struct pcie_port_data\n PCI: portdrv: minor cleanup for pcie_port_device_register\n PCI: portdrv: add missing irq cleanup\n PCI: portdrv: enable device before irq initialization\n PCI: portdrv: cleanup service irqs initialization\n PCI: portdrv: check capabilities first\n PCI: portdrv: move PME capability check\n PCI: portdrv: remove redundant pcie type calculation\n PCI: portdrv: cleanup pcie_device registration\n PCI: portdrv: remove redundant pcie_port_device_probe\n PCI: Always set prefetchable base/limit upper32 registers\n PCI: read-modify-write the pcie device control register when initiating pcie flr\n PCI: show dma_mask bits in /sys\n ...\n\nFixed up conflicts in:\n\tarch/x86/kernel/amd_iommu_init.c\n\tdrivers/pci/dmar.c\n\tdrivers/pci/hotplug/acpiphp_glue.c\n" }, { "commit": "3067e02f8f3ae2f3f02ba76400d03b8bcb4942b0", "tree": "761e19d279b27a03714a6673811e76e0b1cf2081", "parents": [ "f71eaf68406cfee91b6a96bcdf7ce33dc78829c5", "b00eb796f1b67c46036b5490e83b31741f1eebaf" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 09 19:57:06 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 09 19:57:06 2009 -0800" }, "message": "Merge branch \u0027acpica\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6\n\n* \u0027acpica\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6:\n ACPICA: Update version to 20091112.\n ACPICA: Add additional module-level code support\n ACPICA: Deploy new create integer interface where appropriate\n ACPICA: New internal utility function to create Integer objects\n ACPICA: Add repair for predefined methods that must return sorted lists\n ACPICA: Fix possible fault if return Package objects contain NULL elements\n ACPICA: Add post-order callback to acpi_walk_namespace\n ACPICA: Change package length error message to an info message\n ACPICA: Reduce severity of predefined repair messages, Warning to Info\n ACPICA: Update version to 20091013\n ACPICA: Fix possible memory leak for Scope ASL operator\n ACPICA: Remove possibility of executing _REG methods twice\n ACPICA: Add repair for bad _MAT buffers\n ACPICA: Add repair for bad _BIF/_BIX packages\n" }, { "commit": "849e8dea099aafa56db9e74b580b0d858b956533", "tree": "f97331389507608561e96e96a04546b84a8860fc", "parents": [ "e069efb6bbf8f739a2e084183709b5eb76abf90d", "18ed61da985c57eea3fe8038b13fa2837c9b3c3f" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Dec 08 19:26:55 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Dec 08 19:26:55 2009 -0800" }, "message": "Merge branch \u0027timers-for-linus-hpet\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027timers-for-linus-hpet\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n x86: hpet: Make WARN_ON understandable\n x86: arch specific support for remapping HPET MSIs\n intr-remap: generic support for remapping HPET MSIs\n x86, hpet: Simplify the HPET code\n x86, hpet: Disable per-cpu hpet timer if ARAT is supported\n" }, { "commit": "354bb65e6e0df0aaae0e5b1ea33948d8e0b61418", "tree": "afcb7dca4c8362442ec50ce799290ae1211bde19", "parents": [ "1672af1164d3d50ba8908014fd34cc0b58afdc1e" ], "author": { "name": "KOSAKI Motohiro", "email": "kosaki.motohiro@jp.fujitsu.com", "time": "Tue Nov 17 16:21:09 2009 +0900" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Dec 08 10:12:04 2009 +0000" }, "message": "Revert \"Intel IOMMU: Avoid memory allocation failures in dma map api calls\"\n\ncommit eb3fa7cb51 said Intel IOMMU\n\n Intel IOMMU driver needs memory during DMA map calls to setup its\n internal page tables and for other data structures. As we all know\n that these DMA map calls are mostly called in the interrupt context\n or with the spinlock held by the upper level drivers(network/storage\n drivers), so in order to avoid any memory allocation failure due to\n low memory issues, this patch makes memory allocation by temporarily\n setting PF_MEMALLOC flags for the current task before making memory\n allocation calls.\n\n We evaluated mempools as a backup when kmem_cache_alloc() fails\n and found that mempools are really not useful here because\n 1) We don\u0027t know for sure how much to reserve in advance\n 2) And mempools are not useful for GFP_ATOMIC case (as we call\n memory alloc functions with GFP_ATOMIC)\n\n (akpm: point 2 is wrong...)\n\nThe above description doesn\u0027t justify to waste system emergency memory\nat all. Non MM subsystem must not use PF_MEMALLOC. Memory reclaim need\nfew memory, anyone must not prevent it. Otherwise the system cause\nmysterious hang-up and/or OOM Killer invokation.\n\nPlus, akpm already pointed out what we should do.\n\nThen, this patch revert it.\n\nCc: Keshavamurthy Anil S \u003canil.s.keshavamurthy@intel.com\u003e\nSigned-off-by: KOSAKI Motohiro \u003ckosaki.motohiro@jp.fujitsu.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "1672af1164d3d50ba8908014fd34cc0b58afdc1e", "tree": "b485a7cfb4b305906bb19c145cd3e4ff9e1fe349", "parents": [ "44cd613c0e4cd93079ea2a93aa06649d8ca0830a" ], "author": { "name": "Chris Wright", "email": "chrisw@sous-sol.org", "time": "Wed Dec 02 12:06:34 2009 -0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Dec 08 10:03:25 2009 +0000" }, "message": "intel-iommu: ignore page table validation in pass through mode\n\nWe are seeing a bug when booting w/ iommu\u003dpt with current upstream\n(bisect blames 19943b0e30b05d42e494ae6fef78156ebc8c637e \"intel-iommu:\nUnify hardware and software passthrough support).\n\nThe issue is specific to this loop during identity map initialization\nof each device:\n\ndomain_context_mapping_one(si_domain, ..., CONTEXT_TT_PASS_THROUGH)\n...\n\t\t/* Skip top levels of page tables for\n\t\t* iommu which has less agaw than default.\n\t\t*/\n\t\tfor (agaw \u003d domain-\u003eagaw; agaw !\u003d iommu-\u003eagaw; agaw--) {\n\t\t\tpgd \u003d phys_to_virt(dma_pte_addr(pgd));\n\t\t\tif (!dma_pte_present(pgd)) { \u003c------ failing here\n\t\t\t\tspin_unlock_irqrestore(\u0026iommu-\u003elock, flags);\n\t\t\treturn -ENOMEM;\n\t\t}\n\nThis box has 2 iommu\u0027s in it. The catchall iommu has MGAW \u003d\u003d 48, and\nSAGAW \u003d\u003d 4. The other iommu has MGAW \u003d\u003d 39, SAGAW \u003d\u003d 2.\n\nThe device that\u0027s failing the above pgd test is the only device connected\nto the non-catchall iommu, which has a smaller address width than the\ndomain default. This test is not necessary since the context is in PT\nmode and the ASR is ignored.\n\nThanks to Don Dutile for discovering and debugging this one.\n\nCc: stable@kernel.org\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "44cd613c0e4cd93079ea2a93aa06649d8ca0830a", "tree": "63eb3d5b97569d4db7fa3eb47201d77eaaccaf46", "parents": [ "5595b528b49a702c0428c0762bab60999648254c" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Dec 02 10:18:30 2009 +0000" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Dec 08 10:03:06 2009 +0000" }, "message": "intel-iommu: Fix oops with intel_iommu\u003digfx_off\n\nThe hotplug notifier will call find_domain() to see if the device in\nquestion has been assigned an IOMMU domain. However, this should never\nbe called for devices with a \"dummy\" domain, such as graphics devices\nwhen intel_iommu\u003digfx_off is set and the corresponding IOMMU isn\u0027t even\ninitialised. If you do that, it\u0027ll oops as it dereferences the (-1)\npointer.\n\nThe notifier function should check iommu_no_mapping() for the\ndevice before doing anything else.\n\nCc: stable@kernel.org\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "5595b528b49a702c0428c0762bab60999648254c", "tree": "aa6c04a00e90eb7ac91e24aa295fc2022de4161d", "parents": [ "6ecbf01c7ce4c0f4c3bdfa0e64ac6258328fda6c" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Dec 02 09:21:55 2009 +0000" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Dec 08 10:02:52 2009 +0000" }, "message": "intel-iommu: Check for an RMRR which ends before it starts.\n\nSome HP BIOSes report an RMRR region (a region which needs a 1:1 mapping\nin the IOMMU for a given device) which has an end address lower than its\nstart address. Detect that and warn, rather than triggering the\nBUG() in dma_pte_clear_range().\n\nCc: stable@kernel.org\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "6ecbf01c7ce4c0f4c3bdfa0e64ac6258328fda6c", "tree": "91b5c5cdf8aa7a3f4dea1c8ae46a98765fdd9a6f", "parents": [ "2c99220810c1c79322034628b993573b088ff2da" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Dec 02 09:20:27 2009 +0000" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Dec 08 10:02:39 2009 +0000" }, "message": "intel-iommu: Apply BIOS sanity checks for interrupt remapping too.\n\nThe BIOS errors where an IOMMU is reported either at zero or a bogus\naddress are causing problems even when the IOMMU is disabled -- because\ninterrupt remapping uses the same hardware. Ensure that the checks get\napplied for the interrupt remapping initialisation too.\n\nCc: stable@kernel.org\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "2c99220810c1c79322034628b993573b088ff2da", "tree": "0b5e69d0ad7a6da667b752ffd727781c875cccff", "parents": [ "ec208491936d6adb8a70c3dd4a517cdfe54e823d" ], "author": { "name": "Chris Wright", "email": "chrisw@sous-sol.org", "time": "Wed Dec 02 09:17:13 2009 +0000" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Dec 08 10:02:15 2009 +0000" }, "message": "intel-iommu: Detect DMAR in hyperspace at probe time.\n\nMany BIOSes will lie to us about the existence of an IOMMU, and claim\nthat there is one at an address which actually returns all 0xFF.\n\nWe need to detect this early, so that we know we don\u0027t have a viable\nIOMMU and can set up swiotlb before it\u0027s too late.\n\nCc: stable@kernel.org\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "ec208491936d6adb8a70c3dd4a517cdfe54e823d", "tree": "c7291450e8e559c5fbf3360df30999432204af3c", "parents": [ "aa697079ee66315c4b9747a5eb3e48487fb1b8be", "7b626acb8f983eb83b396ab96cc24b18d635d487" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Dec 08 09:58:33 2009 +0000" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Dec 08 09:59:24 2009 +0000" }, "message": "Merge branch \u0027master\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6\n\nMerge the BIOS workarounds from 2.6.32, and the swiotlb fallback on failure.\n" }, { "commit": "7b626acb8f983eb83b396ab96cc24b18d635d487", "tree": "8c3320191311e6186d3aa722f1acd12acd47ece8", "parents": [ "1ebb275afcf5a47092e995541d6c604eef96062a", "4528752f49c1f4025473d12bc5fa9181085c3f22" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Dec 05 09:49:07 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Dec 05 09:49:07 2009 -0800" }, "message": "Merge branch \u0027core-iommu-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027core-iommu-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (63 commits)\n x86, Calgary IOMMU quirk: Find nearest matching Calgary while walking up the PCI tree\n x86/amd-iommu: Remove amd_iommu_pd_table\n x86/amd-iommu: Move reset_iommu_command_buffer out of locked code\n x86/amd-iommu: Cleanup DTE flushing code\n x86/amd-iommu: Introduce iommu_flush_device() function\n x86/amd-iommu: Cleanup attach/detach_device code\n x86/amd-iommu: Keep devices per domain in a list\n x86/amd-iommu: Add device bind reference counting\n x86/amd-iommu: Use dev-\u003earch-\u003eiommu to store iommu related information\n x86/amd-iommu: Remove support for domain sharing\n x86/amd-iommu: Rearrange dma_ops related functions\n x86/amd-iommu: Move some pte allocation functions in the right section\n x86/amd-iommu: Remove iommu parameter from dma_ops_domain_alloc\n x86/amd-iommu: Use get_device_id and check_device where appropriate\n x86/amd-iommu: Move find_protection_domain to helper functions\n x86/amd-iommu: Simplify get_device_resources()\n x86/amd-iommu: Let domain_for_device handle aliases\n x86/amd-iommu: Remove iommu specific handling from dma_ops path\n x86/amd-iommu: Remove iommu parameter from __(un)map_single\n x86/amd-iommu: Make alloc_new_range aware of multiple IOMMUs\n ...\n" }, { "commit": "9e0b5b2c447ad0caa075a5cfef86def62e1782ff", "tree": "ef8f5d5646ea7d1cd6cba366c5588b9c93ac61ff", "parents": [ "5d990b627537e59a3a2f039ff588a4750e9c1a6a" ], "author": { "name": "Kleber Sacilotto de Souza", "email": "klebers@linux.vnet.ibm.com", "time": "Wed Nov 25 00:55:51 2009 -0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:21:02 2009 -0800" }, "message": "PCI: fix coding style issue in pci_save_state()\n\nRemove a stray space in pci_save_state().\n\nSigned-off-by: Kleber Sacilotto de Souza \u003cklebers@linux.vnet.ibm.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5d990b627537e59a3a2f039ff588a4750e9c1a6a", "tree": "8c0e723c3f9146da52b30c087a80fc417df2b41b", "parents": [ "b26a34aa4792b3db2500b8a98cb7702765c1a92e" ], "author": { "name": "Chris Wright", "email": "chrisw@sous-sol.org", "time": "Fri Dec 04 12:15:21 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:19:24 2009 -0800" }, "message": "PCI: add pci_request_acs\n\nCommit ae21ee65e8bc228416bbcc8a1da01c56a847a60c \"PCI: acs p2p upsteram\nforwarding enabling\" doesn\u0027t actually enable ACS.\n\nAdd a function to pci core to allow an IOMMU to request that ACS\nbe enabled. The existing mechanism of using iommu_found() in the pci\ncore to know when ACS should be enabled doesn\u0027t actually work due to\ninitialization order; iommu has only been detected not initialized.\n\nHave Intel and AMD IOMMUs request ACS, and Xen does as well during early\ninit of dom0.\n\nCc: Allen Kay \u003callen.m.kay@intel.com\u003e\nCc: David Woodhouse \u003cdwmw2@infradead.org\u003e\nCc: Jeremy Fitzhardinge \u003cjeremy@goop.org\u003e\nCc: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b26a34aa4792b3db2500b8a98cb7702765c1a92e", "tree": "2a34bad3bce325dabc1a3aafbe225c62cee3dd77", "parents": [ "638bba08282fb50ba4ebde073ad70551b929e0f2" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Fri Nov 06 11:25:13 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:09:59 2009 -0800" }, "message": "PCI: fix BUG_ON triggered by logical PCIe root port removal\n\nThis problem happened when removing PCIe root port using PCI logical\nhotplug operation.\n\nThe immediate cause of this problem is that the pointer to invalid\ndata structure is passed to pcie_update_aspm_capable() by\npcie_aspm_exit_link_state(). When pcie_aspm_exit_link_state() received\na pointer to root port link, it unconfigures the root port link and\nfrees its data structure at first. At this point, there are not links\nto configure under the root port and the data structure for root port\nlink is already freed. So pcie_aspm_exit_link_state() must not call\npcie_update_aspm_capable() and pcie_config_aspm_path().\n\nThis patch fixes the problem by changing pcie_aspm_exit_link_state()\nnot to call pcie_update_aspm_capable() and pcie_config_aspm_path() if\nthe specified link is root port link.\n\n------------[ cut here ]------------\nkernel BUG at drivers/pci/pcie/aspm.c:606!\ninvalid opcode: 0000 [#1] SMP DEBUG_PAGEALLOC\nlast sysfs file: /sys/devices/pci0000:40/0000:40:13.0/remove\nCPU 1\nModules linked in: shpchp\nPid: 9345, comm: sysfsd Not tainted 2.6.32-rc5 #98 ProLiant DL785 G6\nRIP: 0010:[\u003cffffffff811df69b\u003e] [\u003cffffffff811df69b\u003e] pcie_update_aspm_capable+0x15/0xbe\nRSP: 0018:ffff88082a2f5ca0 EFLAGS: 00010202\nRAX: 0000000000000e77 RBX: ffff88182cc3e000 RCX: ffff88082a33d006\nRDX: 0000000000000001 RSI: ffffffff811dff4a RDI: ffff88182cc3e000\nRBP: ffff88082a2f5cc0 R08: ffff88182cc3e000 R09: 0000000000000000\nR10: ffff88182fc00180 R11: ffff88182fc00198 R12: ffff88182cc3e000\nR13: 0000000000000000 R14: ffff88182cc3e000 R15: ffff88082a2f5e20\nFS: 00007f259a64b6f0(0000) GS:ffff880864600000(0000) knlGS:0000000000000000\nCS: 0010 DS: 0018 ES: 0018 CR0: 000000008005003b\nCR2: 00007feb53f73da0 CR3: 000000102cc94000 CR4: 00000000000006e0\nDR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000\nDR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400\nProcess sysfsd (pid: 9345, threadinfo ffff88082a2f4000, task ffff88082a33cf00)\nStack:\n ffff88182cc3e000 ffff88182cc3e000 0000000000000000 ffff88082a33cf00\n\u003c0\u003e ffff88082a2f5cf0 ffffffff811dff52 ffff88082a2f5cf0 ffff88082c525168\n\u003c0\u003e ffff88402c9fd2f8 ffff88402c9fd2f8 ffff88082a2f5d20 ffffffff811d7db2\nCall Trace:\n [\u003cffffffff811dff52\u003e] pcie_aspm_exit_link_state+0xf5/0x11e\n [\u003cffffffff811d7db2\u003e] pci_stop_bus_device+0x76/0x7e\n [\u003cffffffff811d7d67\u003e] pci_stop_bus_device+0x2b/0x7e\n [\u003cffffffff811d7e4f\u003e] pci_remove_bus_device+0x15/0xb9\n [\u003cffffffff811dcb8c\u003e] remove_callback+0x29/0x3a\n [\u003cffffffff81135aeb\u003e] sysfs_schedule_callback_work+0x15/0x6d\n [\u003cffffffff81072790\u003e] worker_thread+0x19d/0x298\n [\u003cffffffff8107273b\u003e] ? worker_thread+0x148/0x298\n [\u003cffffffff81135ad6\u003e] ? sysfs_schedule_callback_work+0x0/0x6d\n [\u003cffffffff810765c0\u003e] ? autoremove_wake_function+0x0/0x38\n [\u003cffffffff810725f3\u003e] ? worker_thread+0x0/0x298\n [\u003cffffffff8107629e\u003e] kthread+0x7d/0x85\n [\u003cffffffff8102eafa\u003e] child_rip+0xa/0x20\n [\u003cffffffff8102e4bc\u003e] ? restore_args+0x0/0x30\n [\u003cffffffff81076221\u003e] ? kthread+0x0/0x85\n [\u003cffffffff8102eaf0\u003e] ? child_rip+0x0/0x20\nCode: 89 e5 8a 50 48 31 c0 c0 ea 03 83 e2 07 e8 b2 de fe ff c9 48 98 c3 55 48 89 e5 41 56 49 89 fe 41 55 41 54 53 48 83 7f 10 00 74 04 \u003c0f\u003e 0b eb fe 48 8b 05 da 7d 63 00 4c 8d 60 e8 4c 89 e1 eb 24 4c\nRIP [\u003cffffffff811df69b\u003e] pcie_update_aspm_capable+0x15/0xbe\n RSP \u003cffff88082a2f5ca0\u003e\n---[ end trace 6ae0f65bdeab8555 ]---\n\nReported-by: Alex Chiang \u003cachiang@hp.com\u003e\nTested-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "638bba08282fb50ba4ebde073ad70551b929e0f2", "tree": "ba517f15b67b9f5329d6167df27d6198d1a798b0", "parents": [ "6cdfd995a65a52e05b99e3a72a9b979abe73b312" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Thu Dec 03 10:28:25 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:03:19 2009 -0800" }, "message": "PCI: remove ifdefed pci_cleanup_aer_correct_error_status\n\nThe pci_cleanup_aer_correct_error_status() function has been\n#if 0\u0027d out since 2.6.25. Time to remove the dead code.\n\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6cdfd995a65a52e05b99e3a72a9b979abe73b312", "tree": "37b4f67ea9c156710976ad47ec79431c1320551b", "parents": [ "575939cf548951dde8df0786899ea5a91bb669b2" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Thu Dec 03 10:28:20 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:03:11 2009 -0800" }, "message": "PCI: unconditionally clear AER uncorr status register during cleanup\n\nThe current implementation of pci_cleanup_aer_uncorrect_error_status\nonly clears either fatal or non-fatal error status bits depending\non the state of the I/O channel. This implementation will then often\nleave some bits set after PCI error recovery completes. The uncleared bit\nsettings will then be falsely reported the next time an AER interrupt is\ngenerated for that hierarchy. An easy way to illustrate this issue is to\nuse the aer-inject module to simultaneously inject both an uncorrectable\nnon-fatal and uncorrectable fatal error. One of the errors will not be\ncleared.\n\nThis patch resolves this issue by unconditionally clearing all bits in\nthe AER uncorrectable status register. All settings and corrective action\nstrategies are saved and determined before\npci_cleanup_aer_uncorrect_error_status is called, so this change should not\naffect errory handling functionality.\n\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f9f45604edcf87ac86a9d68ca54106c5fb743719", "tree": "1983255e2df44203e0ae7ce8d3aa2c1c9c67b548", "parents": [ "694f88ef7ada0d99e304f687ba92e268a594358b" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:06:51 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:24 2009 -0800" }, "message": "PCI: portdrv: remove redundant definitions\n\nRemove unnecessary definitions from portdrv.h and use generic\ndefinitions instead.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "694f88ef7ada0d99e304f687ba92e268a594358b", "tree": "f7095c20f3a6111947a0edaa99dfddd366dbf4b2", "parents": [ "40717c39b1e6c064f48a263a27e58642221e8661" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:06:15 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:19 2009 -0800" }, "message": "PCI: portdrv: remove unnecessary struct pcie_port_data\n\nRemove \u0027port_type\u0027 field in struct pcie_port_data(), because we can\nget port type information from struct pci_dev. With this change, this\npatch also does followings:\n\n - Remove struct pcie_port_data because it no longer has any field.\n - Remove portdrv private definitions about port type (PCIE_RC_PORT,\n PCIE_SW_UPSTREAM_PORT and PCIE_SW_DOWNSTREAM_PORT), and use generic\n definitions instead.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "40717c39b1e6c064f48a263a27e58642221e8661", "tree": "62c92897f5370900b5cfd6769bfa193ae1a61320", "parents": [ "fbb5de70bbe13ecbebb04226dd6d52b1258dc247" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:05:35 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:10 2009 -0800" }, "message": "PCI: portdrv: minor cleanup for pcie_port_device_register\n\nMinor cleanups for pcie_port_device_register().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fbb5de70bbe13ecbebb04226dd6d52b1258dc247", "tree": "0298455195db5d154718fad4cc411125080a9e3a", "parents": [ "1ce5e83063bf388a2c9fa1e3d4d3122146ad305d" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:05:01 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:06 2009 -0800" }, "message": "PCI: portdrv: add missing irq cleanup\n\nAdd missing service irqs cleanup in the error code path of\npcie_port_device_register().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1ce5e83063bf388a2c9fa1e3d4d3122146ad305d", "tree": "10528a2c8dd991a7c6ad6e55058469d96aa335d5", "parents": [ "dc5351784eb36f1fec4efa88e01581be72c0b711" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:04:30 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:59 2009 -0800" }, "message": "PCI: portdrv: enable device before irq initialization\n\nCall pci_enable_device() before initializing service irqs, because\nlegacy interrupt is initialized in pci_enable_device() on some\narchitectures.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dc5351784eb36f1fec4efa88e01581be72c0b711", "tree": "b91a30f23149bbf7d243c63f68af43bc0e46dc6f", "parents": [ "d013598d9a46befebdfd37195829ce411e4878ea" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:04:00 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:51 2009 -0800" }, "message": "PCI: portdrv: cleanup service irqs initialization\n\nThis patch cleans up the service irqs initialization as follows:\n\n - Remove \u0027irq_mode\u0027 field in pcie_port_data and related definitions,\n which is not needed because we can get the same information from\n \u0027is_msix\u0027, \u0027is_msi\u0027 and \u0027pin\u0027 fields in struct pci_dev.\n\n - Change the name of \u0027vectors\u0027 argument of assign_interrupt_mode() to\n \u0027irqs\u0027 because it holds irq numbers actually. People might confuse\n it with CPU vector or MSI/MSI-X vector.\n\n - Change function name assign_interrupt_mode() to init_service_irqs()\n becasuse we no longer have \u0027irq_mode\u0027 data structure, and new name\n is more straightforward (IMO).\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d013598d9a46befebdfd37195829ce411e4878ea", "tree": "92d461ff66a29cbf9b23af2570de4a99ad9a16c6", "parents": [ "9e5d0b16dada536dfe2f1e893b6ad0225ff8a2c9" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:03:27 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:44 2009 -0800" }, "message": "PCI: portdrv: check capabilities first\n\nMove capability check capability to the beginning of\npcie_port_device_register() prevents redundant execution path.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9e5d0b16dada536dfe2f1e893b6ad0225ff8a2c9", "tree": "1861e7d3d52a5aeb91284ca6b1e310811adb2eb3", "parents": [ "2dd60e96b4d52bccd2dd585e776a3449d7b34b8f" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:02:51 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:37 2009 -0800" }, "message": "PCI: portdrv: move PME capability check\n\nNo reason to check PME capability outside get_port_device_capability().\nDo it in get_port_device_capability().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2dd60e96b4d52bccd2dd585e776a3449d7b34b8f", "tree": "917f339b7542be53ec3b64c12a221d5e6700eec1", "parents": [ "52a0f24beabe9e89223e367c65a0156dff17265c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:02:13 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:26 2009 -0800" }, "message": "PCI: portdrv: remove redundant pcie type calculation\n\nPCIe port type is already stored in \u0027pcie_type\u0027 field of struct\npci_dev. So we don\u0027t need to get it from pci configuration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "52a0f24beabe9e89223e367c65a0156dff17265c", "tree": "d6249304150228dcb15052781cb9f26afae05be4", "parents": [ "898294c97500b1cdff6edce52fd34e024eb070ec" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:01:28 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:18 2009 -0800" }, "message": "PCI: portdrv: cleanup pcie_device registration\n\nIn the current port bus driver implementation, pcie_device allocation,\ninitialization and registration are done in separated functions. Doing\nthose in one function make the code simple and easier to read.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "898294c97500b1cdff6edce52fd34e024eb070ec", "tree": "0f5faec54c06f3775c164b48a1c48659c6ceeb4c", "parents": [ "59353ea30e65ab3ae181d6175e3212e1361c3787" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:00:53 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:12 2009 -0800" }, "message": "PCI: portdrv: remove redundant pcie_port_device_probe\n\nWe don\u0027t need pcie_port_device_probe() because we can get pci\ndevice/port type using pci_is_pcie() and \u0027pcie_type\u0027 fields in struct\npci_dev. Remove pcie_port_device_probe().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "59353ea30e65ab3ae181d6175e3212e1361c3787", "tree": "4fc54f9c8e3b4dd5af6d7f125739ccac9f9d6410", "parents": [ "04b55c4732780381410e52db0e9bfb7661f2b4b3" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@hp.com", "time": "Mon Nov 30 14:51:44 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:52:43 2009 -0800" }, "message": "PCI: Always set prefetchable base/limit upper32 registers\n\nPrior to 1f82de10 we always initialized the upper 32bits of the\nprefetchable memory window, regardless of the address range used.\nNow we only touch it for a \u003e32bit address, which means the upper32\nregisters remain whatever the BIOS initialized them too.\n\nIt\u0027s valid for the BIOS to set the upper32 base/limit to\n0xffffffff/0x00000000, which makes us program prefetchable ranges\nlike 0xffffffffabc00000 - 0x00000000abc00000\n\nRevert the chunk of 1f82de10 that made this conditional so we always\nwrite the upper32 registers and remove now unused pref_mem64 variable.\n\nSigned-off-by: Alex Williamson \u003calex.williamson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "04b55c4732780381410e52db0e9bfb7661f2b4b3", "tree": "6c8a96438f40aa60038a9bd422c38833bdc7aa7a", "parents": [ "bb965401fd2afa26629b244e7bb2e48a117dc238" ], "author": { "name": "Shmulik Ravid", "email": "shmulikr@broadcom.com", "time": "Thu Dec 03 22:27:51 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:49:44 2009 -0800" }, "message": "PCI: read-modify-write the pcie device control register when initiating pcie flr\n\nThe pcie_flr routine writes the device control register with the FLR bit\nset clearing all other fields for the FLR duration. Among other fields,\nthe Max_Payload_Size is also cleared which can cause errors if there are\ntransactions lurking in the HW pipeline. The patch replaces the blank\nwrite with read-modify-write of the control register keeping the other\nfields intact.\n\nSigned-off-by: Shmulik Ravid \u003cshmulikr@broadcom.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bb965401fd2afa26629b244e7bb2e48a117dc238", "tree": "72627abb2f9f65ced77c6c10709e42948fed0592", "parents": [ "c6a415761c59adabb53699c84e5cb42868d97c67" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Tue Nov 24 18:21:21 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:47:50 2009 -0800" }, "message": "PCI: show dma_mask bits in /sys\n\nSo we can catch if the driver sets an incorrect dma_mask.\n\nReviewed-by: Grant Grundler \u003cgrundler@google.com\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c6a415761c59adabb53699c84e5cb42868d97c67", "tree": "0f5f8e1478c46d24748d804de90e4e3268f96c6b", "parents": [ "5c788a695ab5740413d9f9c0035d0d7aeef1c708" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Wed Nov 25 16:28:50 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:46:20 2009 -0800" }, "message": "PCI: add debug output for DMA mask info\n\nThis allows us to find out what DMA mask is used for each PCI device at boot\ntime; useful for debugging.\n\nAfter the patch:\nehci_hcd 0000:00:02.1: using 31bit consistent DMA mask\ne1000 0000:0b:01.0: using 64bit DMA mask\ne1000 0000:0b:01.0: using 64bit consistent DMA mask\ne1000e 0000:04:00.0: using 64bit DMA mask\ne1000e 0000:04:00.0: using 64bit consistent DMA mask\nixgb 0000:0c:01.0: using 64bit DMA mask\nixgb 0000:0c:01.0: using 64bit consistent DMA mask\naacraid 0000:86:00.0: using 32bit DMA mask\naacraid 0000:86:00.0: using 32bit consistent DMA mask\naacraid 0000:86:00.0: using 64bit DMA mask\naacraid 0000:86:00.0: using 64bit consistent DMA mask\nqla2xxx 0000:0c:02.0: using 64bit consistent DMA mask\nqla2xxx 0000:0c:02.1: using 64bit consistent DMA mask\nlpfc 0000:06:00.0: using 64bit DMA mask\nlpfc 0000:06:00.1: using 64bit DMA mask\npata_amd 0000:00:06.0: using 32bit DMA mask\npata_amd 0000:00:06.0: using 32bit consistent DMA mask\nmptsas 0000:0c:04.0: using 64bit DMA mask\nmptsas 0000:0c:04.0: using 64bit consistent DMA mask\n\nforcedeth 0000:00:08.0: using 39bit DMA mask\nforcedeth 0000:00:08.0: using 39bit consistent DMA mask\nniu 0000:02:00.0: using 44bit DMA mask\nniu 0000:02:00.0: using 44bit consistent DMA mask\nsata_nv 0000:00:05.0: using 32bit DMA mask\nsata_nv 0000:00:05.0: using 32bit consistent DMA mask\nib_mthca 0000:03:00.0: using 64bit DMA mask\nib_mthca 0000:03:00.0: using 64bit consistent DMA mask\n\nReviewed-by: Grant Grundler \u003cgrundler@google.com\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5c788a695ab5740413d9f9c0035d0d7aeef1c708", "tree": "8cfa260d86f7c122a501e20723394eeef1b8e3f5", "parents": [ "f6e1d8cc38b3776038fb15d3acc82ed8bb552f82" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:18:01 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:18:01 2009 -0800" }, "message": "PCI: ibmphp_hpc: don\u0027t release hw sem twice if kthread stops\n\nIf we stop the kthread, we may end up up\u0027ing the sem twice, which seems\nunintended.\n\nReported-by: Dan Carpenter \u003cerror27@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2263576cfc6e8f6ab038126c3254404b9fcb1c33", "tree": "1c1bd06cc5d89978a23a19d549764d3dc8c7c6c4", "parents": [ "7d5d05d0704127c9acd24090c14731c111bd0af1" ], "author": { "name": "Lin Ming", "email": "ming.m.lin@intel.com", "time": "Fri Nov 13 10:06:08 2009 +0800" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Tue Nov 24 21:31:10 2009 -0500" }, "message": "ACPICA: Add post-order callback to acpi_walk_namespace\n\nThe existing interface only has a pre-order callback. This change\nadds an additional parameter for a post-order callback which will\nbe more useful for bus scans. ACPICA BZ 779.\n\nAlso update the external calls to acpi_walk_namespace.\n\nhttp://www.acpica.org/bugzilla/show_bug.cgi?id\u003d779\n\nSigned-off-by: Lin Ming \u003cming.m.lin@intel.com\u003e\nSigned-off-by: Bob Moore \u003crobert.moore@intel.com\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "5651c48cfafef1b9a7ebdc00ebeb32f2af887a89", "tree": "98fa6b66b5a88d1a53d041fd0473d9711b8dd88a", "parents": [ "13598378f29c125d78047b23330eb2294b03d414" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Fri Nov 13 15:14:10 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:19 2009 -0800" }, "message": "PCI pciehp: fix power fault interrupt storm problem\n\nEnabling power fault detected event notification in current pciehp\nmight cause power fault interrupt storm on some machines. On those\nmachines. On those machines, power fault detected bit in the slot\nstatus register was set again immediately when it is cleared in the\ninterrupt service routine, and next power fault detected interrupt was\nnotified again. Therefore, disable power fault detected event\nnotification for now.\n\nThis patch also removes unnecessary handling for power fault cleared\nevent because this event is not supported by PCIe spec.\n\nTested-by: Jens Axboe \u003cjens.axboe@oracle.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "13598378f29c125d78047b23330eb2294b03d414", "tree": "9ebf02e2a0ff9745c350d51c0a54d87a2806465a", "parents": [ "b44d7db36480a3b27e78141fc9d6597aa577744b" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:38:16 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:18 2009 -0800" }, "message": "PCI hotplug: use pci_is_pcie()\n\nChange for PCI hotplug to use pci_is_pcie() instead of checking\npci_dev-\u003eis_pcie.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b44d7db36480a3b27e78141fc9d6597aa577744b", "tree": "76780c8f3ed3644fafa3e8c38b8d5608bed83be3", "parents": [ "8b06477dc4fcdfc21442ad334d3f3e335225ea0c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:37:24 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:17 2009 -0800" }, "message": "PCIe AER: use pci_is_pcie()\n\nChanges for PCIe AER driver to use pci_is_pcie() instead of checking\npci_dev-\u003eis_pcie.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8b06477dc4fcdfc21442ad334d3f3e335225ea0c", "tree": "77a614b6b702e884944f2bf7e2b44bef922e4633", "parents": [ "5f4d91a1228ac85c75b099efd36fff1a3407335c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:36:52 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:17 2009 -0800" }, "message": "PCIe ASPM: use pci_is_pcie()\n\nChange for PCIe ASPM driver to use pci_is_pcie() instead of checking\npci_dev-\u003eis_pcie.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5f4d91a1228ac85c75b099efd36fff1a3407335c", "tree": "ed0d13811c60bf3357ef70ea2931e29a358ed023", "parents": [ "7eb776c42e75d17bd8107a1359068d8c742639d1" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:36:17 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:16 2009 -0800" }, "message": "PCI: use pci_is_pcie() in pci core\n\nChange for PCI core to use pci_is_pcie() instead of checking\npci_dev-\u003eis_pcie.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1518c17ab736303098843bd306a0fc4f8f5faa42", "tree": "b2b3a4fdb08aece393eb852aa8d1225d07bf0382", "parents": [ "d3ccc4091f0d63a3e0976c739c27037a5666060d" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:34:52 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:15 2009 -0800" }, "message": "pciehp: use pci_pcie_cap()\n\nUse pci_pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in pciehp driver. This avoids unnecessary search in PCI\nconfiguration space. This patch also removes \u0027cap_base\u0027 field in\nstruct controller, that was used to hold PCIe capability offset by\npciehp itself.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d3ccc4091f0d63a3e0976c739c27037a5666060d", "tree": "047170187ca169a0090728ce92c5c62abbb66b3a", "parents": [ "db9538a7495e33f3571c0e791c7678bc0c6ef50f" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:34:15 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:14 2009 -0800" }, "message": "PCI hotplug: use pci_pcie_cap()\n\nUse pci_pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCI hotplug core. This avoids unnecessary search in PCI\nconfiguration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "db9538a7495e33f3571c0e791c7678bc0c6ef50f", "tree": "690c5977a83e5c7f0423870dd208784afcd4b159", "parents": [ "dba90dfe48e2e00e79a15c95940730b6926ee176" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:33:30 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:14 2009 -0800" }, "message": "PCIe ASPM: use pci_pcie_cap()\n\nUse pci_pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCIe ASPM driver. This avoids unnecessary search in PCI\nconfiguration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dba90dfe48e2e00e79a15c95940730b6926ee176", "tree": "af32687abec213653a6432842a8962adcf3a9e8c", "parents": [ "39a53062cb5b2ceca6035f3ed67317672f0bcf3b" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:32:42 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:13 2009 -0800" }, "message": "PCIe port bus: use pci_pcie_cap()\n\nUse pci_pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCI Express Port Bus driver. This avoids unnecessary serarch\nin PCI configuration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "39a53062cb5b2ceca6035f3ed67317672f0bcf3b", "tree": "cafbfa800f85c28abad3504787555009ebd97dd0", "parents": [ "06a1cbafb253c4c60d6a54a994887f5fbceabcc0" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:31:38 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:13 2009 -0800" }, "message": "PCIe AER: use pci_pcie_cap()\n\nUse pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCIe AER driver. This avoids unnecessary search in PCI\nconfiguration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "06a1cbafb253c4c60d6a54a994887f5fbceabcc0", "tree": "e534c369ab1878a5d86996c29d629d1f5d8f9f75", "parents": [ "d7b7e60526d54da4c94afe5f137714cee7d05c41" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:30:56 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:12 2009 -0800" }, "message": "PCI: use pci_pcie_cap() in pci core\n\nUse pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCI core code. This avoids unnecessary search in PCI\nconfiguration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5854d9c8d18359b1fc2f23c0ef2d51dd53281bd6", "tree": "09a4ca21c3f6358db12f60a599f47150e60f4aea", "parents": [ "66b00a7c93ec782d118d2c03bd599cfd041e80a1" ], "author": { "name": "David Woodhouse", "email": "dwmw2@infradead.org", "time": "Thu Nov 19 02:18:44 2009 +0000" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Nov 19 13:42:02 2009 -0800" }, "message": "Fix handling of the HP/Acer \u0027DMAR at zero\u0027 BIOS error for machines with \u003c4GiB RAM.\n\nCommit 86cf898e1d0fca245173980e3897580db38569a8 (\"intel-iommu: Check for\n\u0027DMAR at zero\u0027 BIOS error earlier.\") was supposed to work by pretending\nnot to detect an IOMMU if it was actually being reported by the BIOS at\nphysical address zero.\n\nHowever, the intel_iommu_init() function is called unconditionally, as\nare the corresponding functions for other IOMMU hardware.\n\nSo the patch only worked if you have RAM above the 4GiB boundary. It\ncaused swiotlb to be initialised when no IOMMU was detected during early\nboot, and thus the later IOMMU init would refuse to run.\n\nBut if you have less RAM than that, swiotlb wouldn\u0027t get set up and the\nIOMMU _would_ still end up being initialised, even though we never\nclaimed to detect it.\n\nThis patch also sets the dmar_disabled flag when the error is detected\nduring the initial detection phase -- so that the later call to\nintel_iommu_init() will return without doing anything, regardless of\nwhether swiotlb is used or not.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "99f4c9de2b707795acb215e2e94df7ea266042b5", "tree": "6123682a8e0d880feebb690a55b3fb442ef3dee8", "parents": [ "62ad33f67003b9a7b6013f0511579b9805e11626", "156171c71a0dc4bce12b4408bb1591f8fe32dc1a" ], "author": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Nov 17 07:51:02 2009 +0100" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Nov 17 07:51:07 2009 +0100" }, "message": "Merge commit \u0027v2.6.32-rc7\u0027 into core/iommu\n\nMerge reason: Add fixes we\u0027ll depend on.\n\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "a9366e61b03f55a6e009e687ad10e706714c9907", "tree": "b68f510ae8924db3385eae783a1294d0af03ae37", "parents": [ "24dfb2b5867df24ba03b6c4418312e23b1300aa8", "99dcadede42f8898d4c963ef69192ef4b9b76ba8" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Nov 14 13:05:27 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Nov 14 13:05:27 2009 -0800" }, "message": "Merge git://git.infradead.org/users/dwmw2/iommu-2.6.32\n\n* git://git.infradead.org/users/dwmw2/iommu-2.6.32:\n intel-iommu: Support PCIe hot-plug\n intel-iommu: Obey coherent_dma_mask for alloc_coherent on passthrough\n intel-iommu: Check for \u0027DMAR at zero\u0027 BIOS error earlier.\n" }, { "commit": "99dcadede42f8898d4c963ef69192ef4b9b76ba8", "tree": "36db26e700bfa17f56a30ef05b4092372149e147", "parents": [ "e8bb910d1bbc65e7081e73aab4b3a3dd8630332c" ], "author": { "name": "Fenghua Yu", "email": "fenghua.yu@intel.com", "time": "Wed Nov 11 07:23:06 2009 -0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Nov 12 02:28:45 2009 +0000" }, "message": "intel-iommu: Support PCIe hot-plug\n\nTo support PCIe hot plug in IOMMU, we register a notifier to respond to device\nchange action.\n\nWhen the notifier gets BUS_NOTIFY_UNBOUND_DRIVER, it removes the device\nfrom its DMAR domain.\n\nA hot added device will be added into an IOMMU domain when it first does IOMMU\nop. So there is no need to add more code for hot add.\n\nWithout the patch, after a hot-remove, a hot-added device on the same\nslot will not work.\n\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nTested-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "e8bb910d1bbc65e7081e73aab4b3a3dd8630332c", "tree": "cb0d40916915916c5fd92da4ff5c8a092a870816", "parents": [ "86cf898e1d0fca245173980e3897580db38569a8" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@hp.com", "time": "Wed Nov 04 15:59:34 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Nov 12 02:10:34 2009 +0000" }, "message": "intel-iommu: Obey coherent_dma_mask for alloc_coherent on passthrough\n\nThe model for IOMMU passthrough is that decent devices that can cope\nwith DMA to all of memory get passthrough; crappy devices with a limited\ndma_mask don\u0027t -- they get to use the IOMMU anyway.\n\nThis is done on the basis that IOMMU passthrough is usually wanted for\nperformance reasons, and it\u0027s only the decent PCI devices that you\nreally care about performance for, while the crappy 32-bit ones like\nyour USB controller can just use the IOMMU and you won\u0027t really care.\n\nUnfortunately, the check for this was only looking at dev-\u003edma_mask, not\nat dev-\u003ecoherent_dma_mask. And some devices have a 32-bit\ncoherent_dma_mask even though they have a full 64-bit dma_mask.\n\nEven more unfortunately, fixing that simple oversight would upset\ncertain broken HP devices. Not only do they have a 32-bit\ncoherent_dma_mask, but they also have a tendency to do stray DMA to\nunmapped addresses. And then they die when they take the DMA fault they\nso richly deserve.\n\nSo if we do the \u0027correct\u0027 fix, it\u0027ll mean that affected users have to\ndisable IOMMU support completely on \"a large percentage of servers from\na major vendor.\"\n\nPersonally, I have little sympathy -- given that this is the _same_\n\u0027major vendor\u0027 who is shipping machines which claim to have IOMMU\nsupport but have obviously never _once_ booted a VT-d capable OS to do\nany form of QA. But strictly speaking, it _would_ be a regression even\nthough it only ever worked by fluke.\n\nFor 2.6.33, we\u0027ll come up with a quirk which gives swiotlb support\nfor this particular device, and other devices with an inadequate\ncoherent_dma_mask will just get normal IOMMU mapping.\n\nThe simplest fix for 2.6.32, though, is just to jump through some hoops\nto try to allocate coherent DMA memory for such devices in a place that\nthey can reach. We\u0027d use dma_generic_alloc_coherent() for this if it\nexisted on IA64.\n\nSigned-off-by: Alex Williamson \u003calex.williamson@hp.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "8c8def26bfaa704db67d515da3eb92cf26067548", "tree": "72e5ffc30964e2838ea3ea985c5bd451c31f5478", "parents": [ "e9d1e4921d5b62a80ed02851639249e2548d24f1" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Nov 09 12:04:32 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 11 08:19:52 2009 +0000" }, "message": "PCI: allow matching of prefetchable resources to non-prefetchable windows\n\nI\u0027m not entirely sure it needs to go into 32, but it\u0027s probably the right\nthing to do. Another way of explaining the patch is:\n\n - we currently pick the _first_ exactly matching bus resource entry, but\n the _last_ inexactly matching one. Normally first/last shouldn\u0027t\n matter, but bus resource entries aren\u0027t actually all created equal: in\n a transparent bus, the last resources will be the parent resources,\n which we should generally try to avoid unless we have no choice. So\n \"first matching\" is the thing we should always aim for.\n\n - the patch is a bit bigger than it needs to be, because I simplified the\n logic at the same time. It used to be a fairly incomprehensible\n\n\tif ((res-\u003eflags \u0026 IORESOURCE_PREFETCH) \u0026\u0026 !(r-\u003eflags \u0026 IORESOURCE_PREFETCH))\n\t\tbest \u003d r; /* Approximating prefetchable by non-prefetchable */\n\n and technically, all the patch did was to make that complex choice be\n even more complex (it basically added a \"\u0026\u0026 !best\" to say that if we\n already gound a non-prefetchable window for the prefetchable resource,\n then we won\u0027t override an earlier one with that later one: remember\n \"first matching\").\n\n - So instead of that complex one with three separate conditionals in one,\n I split it up a bit, and am taking advantage of the fact that we\n already handled the exact case, so if \u0027res-\u003eflags\u0027 has the PREFETCH\n bit, then we already know that \u0027r-\u003eflags\u0027 will _not_ have it. So the\n simplified code drops the redundant test, and does the new \u0027!best\u0027 test\n separately. It also uses \u0027continue\u0027 as a way to ignore the bus\n resource we know doesn\u0027t work (ie a prefetchable bus resource is _not_\n acceptable for anything but an exact match), so it turns into:\n\n\t/* We can\u0027t insert a non-prefetch resource inside a prefetchable parent .. */\n\tif (r-\u003eflags \u0026 IORESOURCE_PREFETCH)\n\t\tcontinue;\n\t/* .. but we can put a prefetchable resource inside a non-prefetchable one */\n\tif (!best)\n\t\tbest \u003d r;\n\n instead. With the comments, it\u0027s now six lines instead of two, but it\u0027s\n conceptually simpler, and I _could_ have written it as two lines:\n\n\tif ((res-\u003eflags \u0026 IORESOURCE_PREFETCH) \u0026\u0026 !best)\n\t\tbest \u003d r;\t/* Approximating prefetchable by non-prefetchable */\n\n but I thought that was too damn subtle.\n\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "75f1cdf1dda92cae037ec848ae63690d91913eac", "tree": "9c12705002ebfa2d75333c20a19d0ac15f1db1d9", "parents": [ "ad32e8cb86e7894aac51c8963eaa9f36bb8a4e14" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Tue Nov 10 19:46:20 2009 +0900" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Nov 10 12:32:07 2009 +0100" }, "message": "x86: Handle HW IOMMU initialization failure gracefully\n\nIf HW IOMMU initialization fails (Intel VT-d often does this,\ntypically due to BIOS bugs), we fall back to nommu. It doesn\u0027t\nwork for the majority since nowadays we have more than 4GB\nmemory so we must use swiotlb instead of nommu.\n\nThe problem is that it\u0027s too late to initialize swiotlb when HW\nIOMMU initialization fails. We need to allocate swiotlb memory\nearlier from bootmem allocator. Chris explained the issue in\ndetail:\n\n http://marc.info/?l\u003dlinux-kernel\u0026m\u003d125657444317079\u0026w\u003d2\n\nThe current x86 IOMMU initialization sequence is too complicated\nand handling the above issue makes it more hacky.\n\nThis patch changes x86 IOMMU initialization sequence to handle\nthe above issue cleanly.\n\nThe new x86 IOMMU initialization sequence are:\n\n1. we initialize the swiotlb (and setting swiotlb to 1) in the case\n of (max_pfn \u003e MAX_DMA32_PFN \u0026\u0026 !no_iommu). dma_ops is set to\n swiotlb_dma_ops or nommu_dma_ops. if swiotlb usage is forced by\n the boot option, we finish here.\n\n2. we call the detection functions of all the IOMMUs\n\n3. the detection function sets x86_init.iommu.iommu_init to the\n IOMMU initialization function (so we can avoid calling the\n initialization functions of all the IOMMUs needlessly).\n\n4. if the IOMMU initialization function doesn\u0027t need to swiotlb\n then sets swiotlb to zero (e.g. the initialization is\n sucessful).\n\n5. if we find that swiotlb is set to zero, we free swiotlb\n resource.\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nCc: chrisw@sous-sol.org\nCc: dwmw2@infradead.org\nCc: joerg.roedel@amd.com\nCc: muli@il.ibm.com\nLKML-Reference: \u003c1257849980-22640-10-git-send-email-fujita.tomonori@lab.ntt.co.jp\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "9d5ce73a64be2be8112147a3e0b551ad9cd1247b", "tree": "8593dc2ca29e95b1a25e6f677459f3fe5c68dee9", "parents": [ "ea1b0d3945c7374849235b6ecaea1191ee1d9d50" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Tue Nov 10 19:46:16 2009 +0900" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Nov 10 12:31:36 2009 +0100" }, "message": "x86: intel-iommu: Convert detect_intel_iommu to use iommu_init hook\n\nThis changes detect_intel_iommu() to set intel_iommu_init() to\niommu_init hook if detect_intel_iommu() finds the IOMMU.\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nCc: chrisw@sous-sol.org\nCc: dwmw2@infradead.org\nCc: joerg.roedel@amd.com\nCc: muli@il.ibm.com\nLKML-Reference: \u003c1257849980-22640-6-git-send-email-fujita.tomonori@lab.ntt.co.jp\u003e\n[ -v2: build fix for the !CONFIG_DMAR case ]\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "86cf898e1d0fca245173980e3897580db38569a8", "tree": "fe9ba4ed67ef8e5ae430f0d7d69fba68f70869d7", "parents": [ "799dd75b1a8380a967c929a4551895788c374b31" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Nov 09 22:15:15 2009 +0000" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Nov 09 22:15:15 2009 +0000" }, "message": "intel-iommu: Check for \u0027DMAR at zero\u0027 BIOS error earlier.\n\nChris Wright has some patches which let us fall back to swiotlb nicely\nif IOMMU initialisation fails. But those are a bit much for 2.6.32.\n\nInstead, let\u0027s shift the check for the biggest problem, the HP and Acer\nBIOS bug which reports a DMAR at physical address zero. That one can\nactually be checked much earlier -- before we even admit to having\ndetected an IOMMU in the first place. So the swiotlb init goes ahead as\nwe want.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "e9d1e4921d5b62a80ed02851639249e2548d24f1", "tree": "5fff809404f6de05ad610cffcb5b912c7dc049f3", "parents": [ "5b5d94487d934be6b0aa966c9acbdf15b07ef627" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Nov 06 22:41:23 2009 +0000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 06 15:06:27 2009 -0800" }, "message": "PCI: Replace old style lock initializer\n\nSPIN_LOCK_UNLOCKED is deprecated. Use DEFINE_SPINLOCK instead.\n\nMake the lock static while at it.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9b536e0b6164d8875b4a5bb66cc102dcf0badeba", "tree": "508affb3c4e5e1193cdcf4c954f0e1219ea8175d", "parents": [ "e0cd5160346f5b88fe536f529066f102518f8acd" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 04 05:59:55 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 06 14:13:32 2009 -0800" }, "message": "PCI hotplug: fix oshp evaluation\n\nIf firmware doesn\u0027t grant over native hotplug control through ACPI\n_OSC method, we must not evaluate OSHP.\n\nAcked-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e0cd5160346f5b88fe536f529066f102518f8acd", "tree": "d6c2ffc944c9ee0d4215287d3b416f2e9712dc10", "parents": [ "ea7f1b6ee9dc96c5827b06ba21d7769d553efb7d" ], "author": { "name": "Andreas Herrmann", "email": "andreas.herrmann3@amd.com", "time": "Fri Apr 17 12:01:55 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 06 14:09:15 2009 -0800" }, "message": "PCI: derive nearby CPUs from device\u0027s instead of bus\u0027 NUMA information\n\nIn case of AMD CPU northbridge functions this NUMA information might\ndiffer. Here is an example from a 4-socket system.\n\nCurrently Linux shows\n\n root@hagen:/sys/devices/pci0000:00/0000:00:1a.4# cat numa_node\n 0\n root@hagen:/sys/devices/pci0000:00/0000:00:1a.4# cat local_cpu*\n 0-3\n 00000000,0000000f\n\nwhich is not correct for northbridge functions as the local CPUs\nare those of the same socket.\n\nWith this patch and a quirk for AMD CPU NB functions Linux can\ndo better and correctly show\n\n root@hagen:/sys/devices/pci0000:00/0000:00:1a.4# cat numa_node\n 2\n root@hagen:/sys/devices/pci0000:00/0000:00:1a.4# cat local_cpu*\n 8-11\n 00000000,00000f00\n\nSigned-off-by: Andreas Herrmann \u003candreas.herrmann3@amd.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "761434a318a64bf521f8abcc920e1d9837640fa2", "tree": "7590c47fbcadbbfea1a6f7ecdda0441dced26791", "parents": [ "91d3f9bacdb4950d2f79fe2ba296aa249f60d06c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Fri Nov 06 16:22:44 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 06 14:01:23 2009 -0800" }, "message": "PCI ASPM: fix oops on root port removal\n\nFix the following BUG_ON() problem reported by Alex Chiang.\n\nThis problem happened when removing PCIe root port using PCI logical\nhotplug operation.\n\nThe immediate cause of this problem is that the pointer to invalid\ndata structure is passed to pcie_update_aspm_capable() by\npcie_aspm_exit_link_state(). When pcie_aspm_exit_link_state() received\na pointer to root port link, it unconfigures the root port link and\nfrees its data structure at first. At this point, there are not links\nto configure under the root port and the data structure for root port\nlink is already freed. So pcie_aspm_exit_link_state() must not call\npcie_update_aspm_capable() and pcie_config_aspm_path().\n\nThis patch fixes the problem by changing pcie_aspm_exit_link_state()\nnot to call pcie_update_aspm_capable() and pcie_config_aspm_path() if\nthe specified link is root port link.\n\n------------[ cut here ]------------\nkernel BUG at drivers/pci/pcie/aspm.c:606!\ninvalid opcode: 0000 [#1] SMP DEBUG_PAGEALLOC\nlast sysfs file: /sys/devices/pci0000:40/0000:40:13.0/remove\nCPU 1\nModules linked in: shpchp\nPid: 9345, comm: sysfsd Not tainted 2.6.32-rc5 #98 ProLiant DL785 G6\nRIP: 0010:[\u003cffffffff811df69b\u003e] [\u003cffffffff811df69b\u003e] pcie_update_aspm_capable+0x15/0xbe\nRSP: 0018:ffff88082a2f5ca0 EFLAGS: 00010202\nRAX: 0000000000000e77 RBX: ffff88182cc3e000 RCX: ffff88082a33d006\nRDX: 0000000000000001 RSI: ffffffff811dff4a RDI: ffff88182cc3e000\nRBP: ffff88082a2f5cc0 R08: ffff88182cc3e000 R09: 0000000000000000\nR10: ffff88182fc00180 R11: ffff88182fc00198 R12: ffff88182cc3e000\nR13: 0000000000000000 R14: ffff88182cc3e000 R15: ffff88082a2f5e20\nFS: 00007f259a64b6f0(0000) GS:ffff880864600000(0000) knlGS:0000000000000000\nCS: 0010 DS: 0018 ES: 0018 CR0: 000000008005003b\nCR2: 00007feb53f73da0 CR3: 000000102cc94000 CR4: 00000000000006e0\nDR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000\nDR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400\nProcess sysfsd (pid: 9345, threadinfo ffff88082a2f4000, task ffff88082a33cf00)\nStack:\n ffff88182cc3e000 ffff88182cc3e000 0000000000000000 ffff88082a33cf00\n\u003c0\u003e ffff88082a2f5cf0 ffffffff811dff52 ffff88082a2f5cf0 ffff88082c525168\n\u003c0\u003e ffff88402c9fd2f8 ffff88402c9fd2f8 ffff88082a2f5d20 ffffffff811d7db2\nCall Trace:\n [\u003cffffffff811dff52\u003e] pcie_aspm_exit_link_state+0xf5/0x11e\n [\u003cffffffff811d7db2\u003e] pci_stop_bus_device+0x76/0x7e\n [\u003cffffffff811d7d67\u003e] pci_stop_bus_device+0x2b/0x7e\n [\u003cffffffff811d7e4f\u003e] pci_remove_bus_device+0x15/0xb9\n [\u003cffffffff811dcb8c\u003e] remove_callback+0x29/0x3a\n [\u003cffffffff81135aeb\u003e] sysfs_schedule_callback_work+0x15/0x6d\n [\u003cffffffff81072790\u003e] worker_thread+0x19d/0x298\n [\u003cffffffff8107273b\u003e] ? worker_thread+0x148/0x298\n [\u003cffffffff81135ad6\u003e] ? sysfs_schedule_callback_work+0x0/0x6d\n [\u003cffffffff810765c0\u003e] ? autoremove_wake_function+0x0/0x38\n [\u003cffffffff810725f3\u003e] ? worker_thread+0x0/0x298\n [\u003cffffffff8107629e\u003e] kthread+0x7d/0x85\n [\u003cffffffff8102eafa\u003e] child_rip+0xa/0x20\n [\u003cffffffff8102e4bc\u003e] ? restore_args+0x0/0x30\n [\u003cffffffff81076221\u003e] ? kthread+0x0/0x85\n [\u003cffffffff8102eaf0\u003e] ? child_rip+0x0/0x20\nCode: 89 e5 8a 50 48 31 c0 c0 ea 03 83 e2 07 e8 b2 de fe ff c9 48 98 c3 55 48 89 e5 41 56 49 89 fe 41 55 41 54 53 48 83 7f 10 00 74 04 \u003c0f\u003e 0b eb fe 48 8b 05 da 7d 63 00 4c 8d 60 e8 4c 89 e1 eb 24 4c\nRIP [\u003cffffffff811df69b\u003e] pcie_update_aspm_capable+0x15/0xbe\n RSP \u003cffff88082a2f5ca0\u003e\n---[ end trace 6ae0f65bdeab8555 ]---\n\nReported-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nTested-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0efea0006335a2425b1a12a2ad35efad626fe353", "tree": "d139b06a32665ec1227c06f1c0a14b21e3c0d654", "parents": [ "1e5ad9679016275d422e36b12a98b0927d76f556" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Thu Nov 05 12:05:11 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 06 13:59:02 2009 -0800" }, "message": "PCI: cache PCIe capability offset\n\nThere are a lot of codes that searches PCI express capability offset\nin the PCI configuration space using pci_find_capability(). Caching it\nin the struct pci_dev will reduce unncecessary search. This patch adds\nan additional \u0027pcie_cap\u0027 fields into struct pci_dev, which is\ninitialized at pci device scan time (in set_pcie_port_type()).\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "865df576e8fc70daf297b53e61a4fbefc719d065", "tree": "59abb13e1dd402bf8cb4496ab94bbceb2ac2ee2b", "parents": [ "0207c356ef0e2bae6ce4603080d42c130d7debc6" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Wed Nov 04 10:32:57 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:44 2009 -0800" }, "message": "PCI: improve discovery/configuration messages\n\nThis makes PCI resource management messages more consistent and adds a few\nnew messages to aid debugging.\n\nWhenever we assign resources to a device, update a BAR, or change a\nbridge aperture, it\u0027s worth noting it.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0207c356ef0e2bae6ce4603080d42c130d7debc6", "tree": "504e801b50b3a0a3782f1749e72468c84e788cf7", "parents": [ "2a6bed8301f8b019717504575a3f9c6cce1fe271" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Wed Nov 04 10:32:52 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:44 2009 -0800" }, "message": "PCI: replace pr_debug with dev_dbg\n\nSince we have a struct device, we might as well use dev_printk. Note that\nboth pr_debug() and dev_dbg() are completely compiled out unless DEBUG or\nDYNAMIC_DEBUG is defined.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "10c3d71d42f341775d96187eedd3e50eb34939d0", "tree": "1b0f751cd43ce628625b3b6abf05507bf3b12c37", "parents": [ "8d6cfdcdb50e94c92b3621422d909fa7cc41f866" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Wed Nov 04 10:32:42 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:42 2009 -0800" }, "message": "PCI: make PME# messages KERN_DEBUG\n\nMessages about PME# being supported and enabled/disabled are probably\nuseful for debug, but maybe don\u0027t need to be on the console.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8d6cfdcdb50e94c92b3621422d909fa7cc41f866", "tree": "31bd8f15f78b6b607df7515f6f8f99d9e0c245bb", "parents": [ "c7dabef8a2c59e6a3de9d66fc35fb6a43ef7172d" ], "author": { "name": "Thadeu Lima de Souza Cascardo", "email": "cascardo@holoscopio.com", "time": "Fri Oct 30 17:46:48 2009 -0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:42 2009 -0800" }, "message": "PCI: remove pci_find_slot from PCI_LEGACY config description\n\nCommit 3b073eda has removed pci_find_slot, so there\u0027s no point in\nmentioning it in the config description as one of the deprecated APIs\nthere are enabled by PCI_LEGACY and still used by some drivers.\n\nSigned-off-by: Thadeu Lima de Souza Cascardo \u003ccascardo@holoscopio.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c7dabef8a2c59e6a3de9d66fc35fb6a43ef7172d", "tree": "0f8b0021e693a0e380ef9026083b59d0909dffc6", "parents": [ "4fd8bdc567e70c02fab7eeaaa7d2a64232add789" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Oct 27 13:26:47 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:41 2009 -0800" }, "message": "vsprintf: use %pR, %pr instead of %pRt, %pRf\n\nJesse accidentally applied v1 [1] of the patchset instead of v2 [2]. This\nis the diff between v1 and v2.\n\nThe changes in this patch are:\n - tidied vsprintf stack buffer to shrink and compute size more\n accurately\n - use %pR for decoding and %pr for \"raw\" (with type and flags) instead\n of adding %pRt and %pRf\n\n[1] http://lkml.org/lkml/2009/10/6/491\n[2] http://lkml.org/lkml/2009/10/13/441\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4fd8bdc567e70c02fab7eeaaa7d2a64232add789", "tree": "4fdea5db907b13830c1adb543f423a392c91082d", "parents": [ "58c08628c4fe664bfd5f8b7e773b4b157bb9686f" ], "author": { "name": "Stefan Assmann", "email": "sassmann@redhat.com", "time": "Tue Oct 27 08:57:42 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:40 2009 -0800" }, "message": "PCI: avoid boot interrupt quirk for AMD 813x B1 devices\n\nAMD 813x rev. B1 (like rev. B2) devices generate no interrupts if\nquirk_disable_amd_813x_boot_interrupt is executed, add an exception.\nhttp://bugzilla.kernel.org/show_bug.cgi?id\u003d14159\n\nPatch also adds missing cases for DECLARE_PCI_FIXUP_RESUME and\nDECLARE_PCI_FIXUP_FINAL calls to quirk_disable_amd_813x_boot_interrupt.\n\nSigned-off-by: Stefan Assmann \u003csassmann@redhat.com\u003e\nTested-by: Gabriele Giorgetti \u003cg.giorgetti@teamsystem.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "58c08628c4fe664bfd5f8b7e773b4b157bb9686f", "tree": "a0eb74068dd019238af73e0569e9351d473a48eb", "parents": [ "204d49a5613a06eb2fa5c3b842a29b1336cc7995" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Mon Oct 26 21:25:27 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:40 2009 -0800" }, "message": "PCI Hotplug: acpiphp: clean up list traversals\n\nUsing list_for_each_entry instead of list_for_each allows us to\nenhance readability and minorly reduce some stack usage.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "204d49a5613a06eb2fa5c3b842a29b1336cc7995", "tree": "942a75a2a900858c7bd34af0669256e09faae577", "parents": [ "476f644edf7c22b47e6a118e4a1e138112a5ef14" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Oct 26 11:20:47 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:39 2009 -0800" }, "message": "PCI hotplug: move IOAPIC support from acpiphp to ioapic driver\n\nThis patch moves PCI I/O APIC support from acpiphp to a separate driver.\n\nLike pciehp and shpchp, acpiphp handles PCI hotplug, i.e., addition and\nremoval of PCI adapters. But in addition, acpiphp handles some ACPI\nhotplug, such as the addition of new host bridges, and the I/O APIC\nsupport was tangled up with that.\n\nI don\u0027t think the I/O APIC support needs to be in acpiphp; PCI I/O APICs\nusually appear as a function on a PCI host bridge, and we\u0027ll enumerate the\nAPIC before any of the devices behind the bridge that use it.\n\nAs far as I know, nobody actually uses I/O APIC hotplug. It depends on\nacpi_register_ioapic(), which is only implemented for ia64, and I don\u0027t\nthink any vendors have supported I/O chassis hotplug yet.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nCC: Satoru Takeuchi \u003ctakeuchi_satoru@jp.fujitsu.com\u003e\nCC: MUNEDA Takahiro \u003cmuneda.takahiro@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "476f644edf7c22b47e6a118e4a1e138112a5ef14", "tree": "bafecfc91290c5d3eb70d3bf7c7561b61bc97c66", "parents": [ "1d0243559497b9cab00099c49a5ba3222cd6576f" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Oct 12 13:14:15 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:38 2009 -0800" }, "message": "PCI: fix memory leak in aer_inject\n\nFixed probable typo in aer_inject cleanup code resulting in a memory\nleak.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1d0243559497b9cab00099c49a5ba3222cd6576f", "tree": "36a0e7707770e5f97df28aa8ec0a92b7307d16aa", "parents": [ "cc5d153a0ca794e3781ef34c76f32ad3e991b13d" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Oct 12 13:14:10 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:38 2009 -0800" }, "message": "PCI: use better error return values in aer_inject\n\nReplaced some error return values in aer_inject. Use -ENODEV when we\ncan\u0027t find a device and -ENOTTY when the device does not support PCIe AER.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "cc5d153a0ca794e3781ef34c76f32ad3e991b13d", "tree": "61feef82ec34c5f6489abe6db95fae8d03a43d0b", "parents": [ "3c299dc22635e500214707aa28be119ff2b3901c" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Oct 12 13:14:05 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:37 2009 -0800" }, "message": "PCI: add support for PCI domains to aer_inject\n\nAdd support for PCI domains (segments) to aer_inject.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3c299dc22635e500214707aa28be119ff2b3901c", "tree": "6d9cb3710c674639041ead3247e179fa82dcaf35", "parents": [ "bc577d2bb98cc44371287fce3e892d26ad4050a8" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Oct 12 13:14:00 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:36 2009 -0800" }, "message": "PCI: add pci_get_domain_bus_and_slot function\n\nAdded the pci_get_domain_and_slot_function which is analogous to\npci_get_bus_and_slot. It returns a pci_dev given a domain (segment) number,\nbus number, and devnr. Like pci_get_bus_and_slot,\npci_get_domain_bus_and_slot holds a reference to the returned pci_dev.\n\nConverted pci_get_bus_and_slot to a wrapper that calls\npci_get_domain_bus_and_slot with the domain hard-coded to 0.\n\nThis routine was patterned off code suggested by Bjorn Helgaas.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bc577d2bb98cc44371287fce3e892d26ad4050a8", "tree": "801ff1dbf10301bda75879141482eb226192e280", "parents": [ "0584396157ad2d008e2cc76b4ed6254151183a25" ], "author": { "name": "Gabe Black", "email": "gabe.black@ni.com", "time": "Tue Oct 06 10:45:19 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:36 2009 -0800" }, "message": "PCI: populate subsystem vendor and device IDs for PCI bridges\n\nChange to populate the subsystem vendor and subsytem device IDs for\nPCI-PCI bridges that implement the PCI Subsystem Vendor ID capability.\nPreviously bridges left subsystem vendor IDs unpopulated.\n\nSigned-off-by: Gabe Black \u003cgabe.black@ni.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0584396157ad2d008e2cc76b4ed6254151183a25", "tree": "8860a033938b1a01cccf9a203208f741758724ac", "parents": [ "8792e11f1c54bcba34412f03959e70ee217f2231" ], "author": { "name": "Matt Domsch", "email": "Matt_Domsch@dell.com", "time": "Mon Nov 02 11:51:24 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:25 2009 -0800" }, "message": "PCI: PCIe AER: honor ACPI HEST FIRMWARE FIRST mode\n\nFeedback from Hidetoshi Seto and Kenji Kaneshige incorporated. This\ncorrectly handles PCI-X bridges, PCIe root ports and endpoints, and\nprints debug messages when invalid/reserved types are found in the\nHEST. PCI devices not in domain/segment 0 are not represented in\nHEST, thus will be ignored.\n\nToday, the PCIe Advanced Error Reporting (AER) driver attaches itself\nto every PCIe root port for which BIOS reports it should, via ACPI\n_OSC.\n\nHowever, _OSC alone is insufficient for newer BIOSes. Part of ACPI\n4.0 is the new APEI (ACPI Platform Error Interfaces) which is a way\nfor OS and BIOS to handshake over which errors for which components\neach will handle. One table in ACPI 4.0 is the Hardware Error Source\nTable (HEST), where BIOS can define that errors for certain PCIe\ndevices (or all devices), should be handled by BIOS (\"Firmware First\nmode\"), rather than be handled by the OS.\n\nDell PowerEdge 11G server BIOS defines Firmware First mode in HEST, so\nthat it may manage such errors, log them to the System Event Log, and\npossibly take other actions. The aer driver should honor this, and\nnot attach itself to devices noted as such.\n\nFurthermore, Kenji Kaneshige reminded us to disallow changing the AER\nregisters when respecting Firmware First mode. Platform firmware is\nexpected to manage these, and if changes to them are allowed, it could\nbreak that firmware\u0027s behavior.\n\nThe HEST parsing code may be replaced in the future by a more\nfeature-rich implementation. This patch provides the minimum needed\nto prevent breakage until that implementation is available.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Matt Domsch \u003cMatt_Domsch@dell.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8792e11f1c54bcba34412f03959e70ee217f2231", "tree": "aa81ae55e49567231b7899b40beb72a64e470e00", "parents": [ "65b947bc5f32d8d4fe1f925a6146a4088d5466f3" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Oct 05 17:46:43 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 09:02:35 2009 -0800" }, "message": "PCI: pciehp: prevent unnecessary power off\n\nPrevent unnecessary power off at initialization time. If slot power\nis already off, we don\u0027t need to power off the slot.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "65b947bc5f32d8d4fe1f925a6146a4088d5466f3", "tree": "38ab3417540aeb18eea8df4c89f7fdc6aeda4c6e", "parents": [ "445f798555e218a5601222ca5849e8553ddd866a" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Oct 05 17:43:29 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 09:02:13 2009 -0800" }, "message": "PCI: pciehp: fix typo in pciehp_probe\n\nFix typo that might cause memory leak in pciehp_probe().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "445f798555e218a5601222ca5849e8553ddd866a", "tree": "54437d660ae3a98b5480050e48f6ecf4051cb660", "parents": [ "586f1d6688c68a6c7fa4e6a00fa3968b16daef75" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Oct 05 17:42:59 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 09:01:59 2009 -0800" }, "message": "PCI: pciehp: return error on read/write failure\n\nCurrent pciehp returns successfully on read/write failure with dummy\nstate values. It should return error instead.\n\nWith this patch, pciehp no longer uses hotplug_slot_info data\nstructure. So this also removes hotplug_slot_info related code. But\nnote that it still allocates hotplug_slot_info because it is required\nby pci hotplug core.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "586f1d6688c68a6c7fa4e6a00fa3968b16daef75", "tree": "08777d2d739a940dac83df927389323f56569ee2", "parents": [ "3c3a1b1759616e6603027108f8abcbec54271e62" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Oct 05 17:41:37 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 09:01:44 2009 -0800" }, "message": "PCI: pciehp: create files only for existing capabilities\n\nCurrent pciehp driver creates \u0027attention\u0027 and \u0027latch\u0027 files even if\nthe controller doesn\u0027t support them. In this case, the contents of\nthose files are meaningless and unpredictable. Those files should be\ncreated only if the controller has the corresponding capabilities.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3c3a1b1759616e6603027108f8abcbec54271e62", "tree": "a6976122e885e46633ebfaceae413e4efb39c00b", "parents": [ "f22daf1fb9970f1565f224a0951ba58b5d044605" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Oct 05 17:40:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 09:01:28 2009 -0800" }, "message": "PCI: pciehp: remove wrong workaround for bad DLLP\n\nRemove wrong workaround for BAD DLLP error, which confused surprise\ndown error with DLL errors.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f22daf1fb9970f1565f224a0951ba58b5d044605", "tree": "44fd8ce2271d05826823085a58db1e882343bbb4", "parents": [ "1ed6743918abbec69c0f0b725fa56e3c3248bbab" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Oct 05 17:40:02 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 09:01:12 2009 -0800" }, "message": "PCI: pciehp: disable DLL state changed event notification\n\nCurrent pciehp doesn\u0027t handle Data Link Layer State Changed Event\nnotification. So it needs to be disabled at initialization time,\notherwise other event notifications are not generated.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" } ], "next": "1ed6743918abbec69c0f0b725fa56e3c3248bbab" }