)]}'
{
  "log": [
    {
      "commit": "54fd6441e04696c046d93e4407a9e1ee9b874e51",
      "tree": "b75c48d3779cb136d09ec7610dc275532b9bfa43",
      "parents": [
        "e1cca7e8d484390169777b423a7fe46c7021fec1"
      ],
      "author": {
        "name": "Pavel Kiryukhin",
        "email": "vksavl@gmail.com",
        "time": "Tue Nov 27 19:20:47 2007 +0300"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Sat Dec 01 00:39:37 2007 +0000"
      },
      "message": "[MIPS] Fix use of smp_processor_id() in preemptible code.\n\nFreeing prom memory: 956kb freed\nFreeing firmware memory: 978944k freed\nFreeing unused kernel memory: 180k freed\nBUG: using smp_processor_id() in preemptible [00000000] code: swapper/1\ncaller is r4k_dma_cache_wback_inv+0x144/0x2a0\nCall Trace:\n [\u003c80117af8\u003e] r4k_dma_cache_wback_inv+0x144/0x2a0\n [\u003c802e4b84\u003e] debug_smp_processor_id+0xd4/0xf0\n [\u003c802e4b7c\u003e] debug_smp_processor_id+0xcc/0xf0\n...\nCONFIG_DEBUG_PREEMPT is enabled.\n--\nBug cause is blast_dcache_range() in preemptible code [in\nr4k_dma_cache_wback_inv()].\nblast_dcache_range() is constructed via __BUILD_BLAST_CACHE_RANGE that\nuses cpu_dcache_line_size(). It uses current_cpu_data that use\nsmp_processor_id() in turn. In case of CONFIG_DEBUG_PREEMPT\nsmp_processor_id emits BUG if we are executing with preemption\nenabled.\n\nCpu options of cpu0 are assumed to be the superset of all processors.\n\nCan I make the same assumptions for cache line size  and fix this\nissue the following way:\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "10cc3529072d5415fb040018a8a99aa7a60190b6",
      "tree": "fe07fb5112c9c34c2aecfac982155307bc168f07",
      "parents": [
        "aeffdbbaff133b0c3989e20af5baa091d3d0b409"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Thu Oct 11 23:46:15 2007 +0100"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Thu Oct 11 23:46:15 2007 +0100"
      },
      "message": "[MIPS] Allow hardwiring of the CPU type to a single type for optimization.\n\nThis saves a few k on systems which only ever ship with a single CPU type.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "641e97f318870921d048154af6807e46e43c307a",
      "tree": "6e0984a1bc8932db848be3fdb104a92c97fe341a",
      "parents": [
        "424b28ba4d25fc41abdb7e6fa90e132f0d9558fb"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Thu Oct 11 23:46:05 2007 +0100"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Thu Oct 11 23:46:05 2007 +0100"
      },
      "message": "[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.\n\nIt may not be perfect yet but the SB1 code is badly borken and has\nhorrible performance issues.\n\nDownside: This seriously breaks support for pass 1 parts of the BCM1250\nwhere indexed cacheops don\u0027t work quite reliable but I seem to be the\nlast one on the planet with a pass 1 part anyway.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "a36920200c5b89d56120a5e839fe4a603d51b16c",
      "tree": "aefb1fc4b0792ef788024fa596954a5689f15d0a",
      "parents": [
        "d223a86154f8c66f5a380b17e1c8091d56f47cf8"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Tue Jul 10 17:33:02 2007 +0100"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Tue Jul 10 17:33:02 2007 +0100"
      },
      "message": "[MIPS] Enable support for the userlocal hardware register\n\nWhich will cut down the cost of RDHWR $29 which is used to obtain the\nTLS pointer and so far being emulated in software down to a single cycle\noperation.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "53dc80287da43b75df2fe2658651d3c5160dad8e",
      "tree": "3c4c97534c379709cd2a1dae5b90df626349f21d",
      "parents": [
        "c6a2f4679331206ef5d353fc9a6cda2fa4aef8c6"
      ],
      "author": {
        "name": "Atsushi Nemoto",
        "email": "anemo@mba.ocn.ne.jp",
        "time": "Sat Mar 10 01:07:45 2007 +0900"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Sat Mar 17 01:03:26 2007 +0000"
      },
      "message": "[MIPS] FPU ownership management \u0026 preemption fixes\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "fc5d2d279ff820172a698706d33e733d4578bd6c",
      "tree": "1b376605e1870af29a49272d85cb589d319e058b",
      "parents": [
        "879ba8c88a32f2bd3d3369837afdc148bd66bb04"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Thu Jul 06 13:04:01 2006 +0100"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Thu Jul 13 21:26:04 2006 +0100"
      },
      "message": "[MIPS] Use the proper technical term for naming some of the cache  macros.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "2e128dedcd66d2f17f42a45dacc223fa2dcd8acd",
      "tree": "392f1f7b9c8673e6310498064e29198667a41425",
      "parents": [
        "70ae6126090686b2e957f0abd2a3c882e94c7071"
      ],
      "author": {
        "name": "Chris Dearman",
        "email": "chris@mips.com",
        "time": "Fri Jun 30 12:32:37 2006 +0100"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Thu Jul 13 21:25:58 2006 +0100"
      },
      "message": "[MIPS] Default cpu_has_mipsmt to a runtime check\n\nSigned-off-by: Chris Dearman \u003cchris@mips.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "f41ae0b2b9e5b4455cfc68dcc885f4fa2a973384",
      "tree": "1d571a10b4265233b511ce2f45d4ca03b9fbb13a",
      "parents": [
        "e73ea273ef87a04ff59fc368fa33333dca275dde"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Mon Jun 05 17:24:46 2006 +0100"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Thu Jun 29 21:10:51 2006 +0100"
      },
      "message": "[MIPS] Fix configuration of R2 CPU features and multithreading.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f",
      "tree": "e85ca2d0dd43f90dccf758338764c3caa55f333f",
      "parents": [
        "089f26d5e31b7bf42a9a8fefec08b30cd27f4b0e"
      ],
      "author": {
        "name": "David Woodhouse",
        "email": "dwmw2@infradead.org",
        "time": "Wed Apr 26 12:56:16 2006 +0100"
      },
      "committer": {
        "name": "David Woodhouse",
        "email": "dwmw2@infradead.org",
        "time": "Wed Apr 26 12:56:16 2006 +0100"
      },
      "message": "Don\u0027t include linux/config.h from anywhere else in include/\n\nSigned-off-by: David Woodhouse \u003cdwmw2@infradead.org\u003e\n"
    },
    {
      "commit": "f088fc84f94c1a36943e28ad704a9a740a35f877",
      "tree": "309add2d3fe666920a681985c36d55f731df9922",
      "parents": [
        "41c594ab65fc89573af296d192aa5235d09717ab"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Wed Apr 05 09:45:47 2006 +0100"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Wed Apr 19 04:14:28 2006 +0200"
      },
      "message": "[MIPS] FPU affinity for MT ASE.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "de62893bc0725f8b5f0445250577cd7a10b2d8f8",
      "tree": "3a5d77b8e8aa66113431ebe287c552749c2e8fee",
      "parents": [
        "a3c4946db4fe64cb21b66a09e89890678aac6d65"
      ],
      "author": {
        "name": "Atsushi Nemoto",
        "email": "anemo@mba.ocn.ne.jp",
        "time": "Mon Mar 13 18:23:03 2006 +0900"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Sat Mar 18 16:59:27 2006 +0000"
      },
      "message": "[MIPS] local_r4k_flush_cache_page fix\n    \nIf dcache_size !\u003d icache_size or dcache_size !\u003d scache_size, or\nset-associative cache, icache/scache does not flushed properly.  Make\nblast_?cache_page_indexed() masks its index value correctly.  Also,\nuse physical address for physically indexed pcache/scache.\n    \nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "0401572a9b9b2f368176b6e53f53004fd048a566",
      "tree": "ac150d269955aeba9eff5bdaa2835626510c9180",
      "parents": [
        "11e6df65dc2bae8e7ad17ff81611ddc850b279cd"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@ongar.mips.com",
        "time": "Fri Dec 09 12:20:49 2005 +0000"
      },
      "committer": {
        "name": "",
        "email": "ralf@denk.linux-mips.net",
        "time": "Tue Jan 10 13:39:07 2006 +0000"
      },
      "message": "MIPS: Reorganize ISA constants strictly as bitmasks.\n    \nSigned-off-by: Ralf Baechle \u003cralf@ongar.mips.com\u003e\n"
    },
    {
      "commit": "b4672d37293cb045ec4d57e8b76a62810c96da71",
      "tree": "21ba827850d7bc7c36d7009575b979d12b35227c",
      "parents": [
        "e7958bb90d57f0da073cbd031a1808de51d1de15"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Thu Dec 08 14:04:24 2005 +0000"
      },
      "committer": {
        "name": "",
        "email": "ralf@denk.linux-mips.net",
        "time": "Tue Jan 10 13:39:06 2006 +0000"
      },
      "message": "MIPS: Introduce machinery for testing for MIPSxxR1/2.\n    \nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "02cf2119684e52e97a8a90bd7630386e0f1a250a",
      "tree": "fbe051feacc403d7703bf27043ac048b5d2f2369",
      "parents": [
        "942d042d17c77febab9af6815b2e77f665d0f9c1"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Sat Oct 01 13:06:32 2005 +0100"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Sat Oct 29 19:32:32 2005 +0100"
      },
      "message": "Cleanup the mess in cpu_cache_init.\n    \nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "8f40611d2b184ca5d525075d273854929cf8d1d0",
      "tree": "962ef8dfa515cee330f506dc4ceac83670d0f84e",
      "parents": [
        "699dbc90e8c7baecae197fb331773f505a46a1eb"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Thu Jul 14 07:34:18 2005 +0000"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Sat Oct 29 19:31:51 2005 +0100"
      },
      "message": "Detect the MIPS R2 vectored interrupt, external interrupt controller\noptions and the precense of the MT ASE.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "02416dcf5a94af34bcd28b4baf25bbbf399d8136",
      "tree": "1906c4266d4e28ef0b13d0579a145603dcbcff1b",
      "parents": [
        "aac8aa7717a23a9bf8740dbfb59755b1d62f04bf"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Wed Jun 15 13:00:12 2005 +0000"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Sat Oct 29 19:31:23 2005 +0100"
      },
      "message": "Redo RM9000 workaround which along with other DSP ASE changes was\ncausing some headache for debuggers knowing about signal frames.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "e50c0a8fa60da9ac0e0a70caa8a3a803815c1f2f",
      "tree": "1928e8b0a4b7fb615e5a9f65dc934ba2e74cb9cd",
      "parents": [
        "10f650db1bcc193ea07d4f8c2f07315da38ea0c4"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Tue May 31 11:49:19 2005 +0000"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Sat Oct 29 19:31:17 2005 +0100"
      },
      "message": "Support the MIPS32 / MIPS64 DSP ASE.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "4194318c3941fa9cfaa63dfdab9054fcae5e08d3",
      "tree": "2b44341a9cb911e34efbb33a35142fd2dcd536ff",
      "parents": [
        "cd21dfcfbb5c43de54f6be795dde07397da2bc2f"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Thu May 05 16:45:59 2005 +0000"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Sat Oct 29 19:31:12 2005 +0100"
      },
      "message": "Cleanup decoding of MIPSxx config registers.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "875d43e72b5bf22161a81de7554f88eccf8a51ae",
      "tree": "a676fe7298b478b7ee9fe7be9cb07c9a0b928370",
      "parents": [
        "63fb6fd1c86181d9dd9ba0e6e6082799e149b56b"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Sat Sep 03 15:56:16 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@evo.osdl.org",
        "time": "Mon Sep 05 00:06:06 2005 -0700"
      },
      "message": "[PATCH] mips: clean up 32/64-bit configuration\n\nStart cleaning 32-bit vs. 64-bit configuration.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2",
      "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d",
      "parents": [],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n"
    }
  ]
}