)]}'
{
  "log": [
    {
      "commit": "5fde244d39b88625ac578d83e6625138714de031",
      "tree": "e50762b22a94f7f7990c9dbab699a857da0982eb",
      "parents": [
        "ce6fce4295ba727b36fdc73040e444bd1aae64cd"
      ],
      "author": {
        "name": "Shaohua Li",
        "email": "shaohua.li@intel.com",
        "time": "Wed Jul 23 10:32:24 2008 +0800"
      },
      "committer": {
        "name": "Jesse Barnes",
        "email": "jbarnes@virtuousgeek.org",
        "time": "Mon Jul 28 14:56:09 2008 -0700"
      },
      "message": "PCI: disable ASPM per ACPI FADT setting\n\nThe ACPI FADT table includes an ASPM control bit. If the bit is set, do\nnot enable ASPM since it may indicate that the platform doesn\u0027t actually\nsupport the feature.\n\nTested-by: Jack Howarth \u003chowarth@bromo.msbb.uc.edu\u003e\nSigned-off-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n"
    },
    {
      "commit": "7d715a6c1ae5785d00fb9a876b5abdfc43abc44b",
      "tree": "58ec6d1969739a590e0c6c976bfebf04c8e9f31e",
      "parents": [
        "657472e9ccd9fccb82b775eb691c4b25b27451da"
      ],
      "author": {
        "name": "Shaohua Li",
        "email": "shaohua.li@intel.com",
        "time": "Mon Feb 25 09:46:41 2008 +0800"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Sun Apr 20 21:47:03 2008 -0700"
      },
      "message": "PCI: add PCI Express ASPM support\n\nPCI Express ASPM defines a protocol for PCI Express components in the D0\nstate to reduce Link power by placing their Links into a low power state\nand instructing the other end of the Link to do likewise. This\ncapability allows hardware-autonomous, dynamic Link power reduction\nbeyond what is achievable by software-only controlled power management.\nHowever, The device should be configured by software appropriately.\nEnabling ASPM will save power, but will introduce device latency.\n\nThis patch adds ASPM support in Linux. It introduces a global policy for\nASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control\nit. The interface can be used as a boot option too. Currently we have\nbelow setting:\n        -default, BIOS default setting\n        -powersave, highest power saving mode, enable all available ASPM\nstate and clock power management\n        -performance, highest performance, disable ASPM and clock power\nmanagement\nBy default, the \u0027default\u0027 policy is used currently.\n\nIn my test, power difference between powersave mode and performance mode\nis about 1.3w in a system with 3 PCIE links.\n\nNote: some devices might not work well with aspm, either because chipset\nissue or device issue. The patch provide API (pci_disable_link_state),\ndriver can disable ASPM for specific device.\n\nSigned-off-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n"
    }
  ]
}