)]}' { "log": [ { "commit": "411f5c7a502769ccc0377c5ba36cb0b283847ba8", "tree": "2c3a29671e3f923de48c55f94194849264a7bf53", "parents": [ "6d7ed21d17e640b120b902a314143e5ef4917a70", "9ced9f03d12d7539e86b0bff5bc750153c976c34" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Mar 17 19:08:06 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Mar 17 19:08:06 2011 -0700" }, "message": "Merge branch \u0027devel-stable\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027devel-stable\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm: (289 commits)\n davinci: DM644x EVM: register MUSB device earlier\n davinci: add spi devices on tnetv107x evm\n davinci: add ssp config for tnetv107x evm board\n davinci: add tnetv107x ssp platform device\n spi: add ti-ssp spi master driver\n mfd: add driver for sequencer serial port\n ARM: EXYNOS4: Implement Clock gating for System MMU\n ARM: EXYNOS4: Enhancement of System MMU driver\n ARM: EXYNOS4: Add support for gpio interrupts\n ARM: S5P: Add function to register gpio interrupt bank data\n ARM: S5P: Cleanup S5P gpio interrupt code\n ARM: EXYNOS4: Add missing GPYx banks\n ARM: S3C64XX: Fix section mismatch from cpufreq init\n ARM: EXYNOS4: Add keypad device to the SMDKV310\n ARM: EXYNOS4: Update clocks for keypad\n ARM: EXYNOS4: Update keypad base address\n ARM: EXYNOS4: Add keypad device helpers\n ARM: EXYNOS4: Add support for SATA on ARMLEX4210\n plat-nomadik: make GPIO interrupts work with cpuidle ApSleep\n mach-u300: define a dummy filter function for coh901318\n ...\n\nFix up various conflicts in\n - arch/arm/mach-exynos4/cpufreq.c\n - arch/arm/mach-mxs/gpio.c\n - drivers/net/Kconfig\n - drivers/tty/serial/Kconfig\n - drivers/tty/serial/Makefile\n - drivers/usb/gadget/fsl_mxc_udc.c\n - drivers/video/Kconfig\n" }, { "commit": "63a93699c6a58795b854ff573542a08367684dae", "tree": "057ab4cbde66862c51867dde030be69a2fa7073f", "parents": [ "16d8775700f1815076f879719ce14b33f50a3171", "21bd6d37cf23e643020bf28b41844ff0040c9393" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 16 19:05:40 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 16 19:05:40 2011 -0700" }, "message": "Merge branch \u0027remove\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027remove\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm:\n ARM: 6629/2: aaec2000: remove support for mach-aaec2000\n ARM: lh7a40x: remove unmaintained platform support\n\nFix up trivial conflicts in\n - arch/arm/mach-{aaec2000,lh7a40x}/include/mach/memory.h (removed)\n - drivers/usb/gadget/Kconfig (USB_[GADGET_]LH7A40X removed, others added)\n" }, { "commit": "16d8775700f1815076f879719ce14b33f50a3171", "tree": "8525e6e6f12b6acf7cf2746853cc65549f3dbf4c", "parents": [ "e34551339a195aa548eaf698523714a8fe7f1984", "05e34754518b6a90d5c392790c032575fab12d66" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 16 19:03:06 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 16 19:03:06 2011 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027for-linus\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm: (91 commits)\n ARM: 6806/1: irq: introduce entry and exit functions for chained handlers\n ARM: 6781/1: Thumb-2: Work around buggy Thumb-2 short branch relocations in gas\n ARM: 6747/1: P2V: Thumb2 support\n ARM: 6798/1: aout-core: zero thread debug registers in a.out core dump\n ARM: 6796/1: Footbridge: Fix I/O mappings for NOMMU mode\n ARM: 6784/1: errata: no automatic Store Buffer drain on Cortex-A9\n ARM: 6772/1: errata: possible fault MMU translations following an ASID switch\n ARM: 6776/1: mach-ux500: activate fix for errata 753970\n ARM: 6794/1: SPEAr: Append UL to device address macros.\n ARM: 6793/1: SPEAr: Remove unused *_SIZE macros from spear*.h files\n ARM: 6792/1: SPEAr: Replace SIZE macro\u0027s with SZ_4K macros\n ARM: 6791/1: SPEAr3xx: Declare device structures after shirq code\n ARM: 6790/1: SPEAr: Clock Framework: Rename usbd clock and align apb_clk entry\n ARM: 6789/1: SPEAr3xx: Rename sdio to sdhci\n ARM: 6788/1: SPEAr: Include mach/hardware.h instead of mach/spear.h\n ARM: 6787/1: SPEAr: Reorder #includes in .h \u0026 .c files.\n ARM: 6681/1: SPEAr: add debugfs support to clk API\n ARM: 6703/1: SPEAr: update clk API support\n ARM: 6679/1: SPEAr: make clk API functions more generic\n ARM: 6737/1: SPEAr: formalized timer support\n ...\n" }, { "commit": "05e34754518b6a90d5c392790c032575fab12d66", "tree": "318d321262269eff585573ab2acf04a2ff2b65f4", "parents": [ "bd1274dc005c2cee41771a7cc616f4709a6e6323", "b511d75d6150892e67c8ebfa9dc8eb37ebd02aa3" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 16 23:35:27 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 16 23:35:27 2011 +0000" }, "message": "Merge branch \u0027p2v\u0027 into devel\n\nConflicts:\n\tarch/arm/kernel/module.c\n\tarch/arm/mach-s5pv210/sleep.S\n" }, { "commit": "bd1274dc005c2cee41771a7cc616f4709a6e6323", "tree": "fcfe103a499ca9e3d8fa0ecbca5b7d0d274da5ca", "parents": [ "1f0090a1eaa1b750a2fc5c99c91b790d5322a1fd", "3ba6e69ad887f8a814267ed36fd4bfbddf8855a9" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 16 23:35:26 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 16 23:35:26 2011 +0000" }, "message": "Merge branch \u0027v6v7\u0027 into devel\n\nConflicts:\n\tarch/arm/include/asm/cacheflush.h\n\tarch/arm/include/asm/proc-fns.h\n\tarch/arm/mm/Kconfig\n" }, { "commit": "1f0090a1eaa1b750a2fc5c99c91b790d5322a1fd", "tree": "c685060f260410e6704c9dfd457ed8c347141f1d", "parents": [ "2472f3c8d8fc18b25b2cf1574c036e238187c0ff", "10a8c3839810ac9af1aec836d61b92e7a879f5fa" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 16 23:35:25 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 16 23:35:25 2011 +0000" }, "message": "Merge branch \u0027misc\u0027 into devel\n\nConflicts:\n\tarch/arm/Kconfig\n" }, { "commit": "2472f3c8d8fc18b25b2cf1574c036e238187c0ff", "tree": "485458b51ef0b5509376b56e6ff2e1b124f9c048", "parents": [ "d081377dfda42beab13d8b4af876571ce7661174", "31bb68a314e9a2c9fbe054441b18c0608585605e", "5dab26af1bacad9a7189d904fbc8b4fe8e95dd81", "4e8d76373c9fd7a1c1b401fc97ba01c0ecbb888f", "b6338bdc8305b27688a7feb8689e4ccfd42f0292", "f512626f5baf09c1d40d098462a986417f4e9790", "bf0c11183fc3a2acce56d2b53f2a117322bd3c3b", "941aefac4c243cf407d7665d3e64beb32d556acf", "f45b1149911cc4c3ab50e56c8844ad4ec04a4575", "981a95d37126cdf09e1dba3884305c2e25375bfb", "6e266b204b853b960ad038e62f31c1671f930b87", "21f47fbc5b18da4a3db680959aee887612ec9a72" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 16 23:35:17 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 16 23:35:17 2011 +0000" }, "message": "Merge branches \u0027at91\u0027, \u0027ep93xx\u0027, \u0027errata\u0027, \u0027footbridge\u0027, \u0027fncpy\u0027, \u0027gemini\u0027, \u0027irqdata\u0027, \u0027pm\u0027, \u0027sh\u0027, \u0027smp\u0027, \u0027spear\u0027, \u0027ux500\u0027 and \u0027via\u0027 into devel\n" }, { "commit": "10a8c3839810ac9af1aec836d61b92e7a879f5fa", "tree": "dbb67f0ed37857b92ee0098791d4d6e3d2a04d46", "parents": [ "6f685c5cdd29649cf8cc8f57c72791159f936e07" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Mon Mar 14 14:00:30 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Mar 15 09:42:28 2011 +0000" }, "message": "ARM: 6806/1: irq: introduce entry and exit functions for chained handlers\n\nSome chained IRQ handlers are written to cope with primary chips of\npotentially different flow types. Whether this a sensible thing to do\nis a point of contention.\n\nThis patch introduces entry/exit functions for chained handlers which\ninfer the flow type of the primary chip as fasteoi or level-type by\nchecking whether or not the -\u003eirq_eoi function pointer is present and\ncalling back to the primary chip as necessary. Other methods of flow\ncontrol are not considered.\n\nAcked-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "07d5ecae2940ddd77746e2fb597dcf57d3c2e277", "tree": "2755106df53db441230d1e5356a65bde0274f20c", "parents": [ "6e0aa9f8a8190e0879a29bd67aa606b51734a122" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 14 20:00:30 2011 +0100" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Mon Mar 14 21:10:26 2011 +0100" }, "message": "arm: Remove bogus comment in futex_atomic_cmpxchg_inatomic()\n\ncommit 522d7dec(futex: Remove redundant pagefault_disable in\nfutex_atomic_cmpxchg_inatomic()) added a bogus comment.\n\n/* Note that preemption is disabled by futex_atomic_cmpxchg_inatomic\n * call sites. */\n\nBogus in two aspects:\n\n1) pagefault_disable !\u003d preempt_disable even if the mechanism we use\n is the same\n\n2) we have a call site which deliberately does not disable pagefaults\n as it wants the possible fault to be handled - though that has been\n changed for consistency reasons now.\n\nSigh. I really should have seen that when committing the above. :(\n\nCatched-by-and-rightfully-ranted-at-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nLKML-Reference: \u003calpine.LFD.2.00.1103141126590.2787@localhost6.localdomain6\u003e\nCc: Michel Lespinasse \u003cwalken@google.com\u003e\nCc: Darren Hart \u003cdarren@dvhart.com\u003e\n" }, { "commit": "8688a1a8637c6b833b9b70148809db4538352d2e", "tree": "7b5d6c2d83c8bd1686811501c6287a650c40751b", "parents": [ "3afdb0f3528991de0833224f2dba60dc061e01fa", "f91f9cd505f92e4227ffda7e5799a33d4f34bf36" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Mar 12 20:33:51 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Mar 12 20:33:51 2011 +0000" }, "message": "Merge branch \u0027master\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tglx/linux-2.6-tcc into devel-stable\n" }, { "commit": "8d7718aa082aaf30a0b4989e1f04858952f941bc", "tree": "f006a565d138cec2b497c2bd619f570ad1a11f6e", "parents": [ "37a9d912b24f96a0591773e6e6c3642991ae5a70" ], "author": { "name": "Michel Lespinasse", "email": "walken@google.com", "time": "Thu Mar 10 18:50:58 2011 -0800" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Mar 11 12:23:31 2011 +0100" }, "message": "futex: Sanitize futex ops argument types\n\nChange futex_atomic_op_inuser and futex_atomic_cmpxchg_inatomic\nprototypes to use u32 types for the futex as this is the data type the\nfutex core code uses all over the place.\n\nSigned-off-by: Michel Lespinasse \u003cwalken@google.com\u003e\nCc: Darren Hart \u003cdarren@dvhart.com\u003e\nCc: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nCc: Matt Turner \u003cmattst88@gmail.com\u003e\nCc: Russell King \u003clinux@arm.linux.org.uk\u003e\nCc: David Howells \u003cdhowells@redhat.com\u003e\nCc: Tony Luck \u003ctony.luck@intel.com\u003e\nCc: Michal Simek \u003cmonstr@monstr.eu\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: \"James E.J. Bottomley\" \u003cjejb@parisc-linux.org\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Chris Metcalf \u003ccmetcalf@tilera.com\u003e\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nLKML-Reference: \u003c20110311025058.GD26122@google.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "37a9d912b24f96a0591773e6e6c3642991ae5a70", "tree": "5c4d5b9a52e2c533269e589115afbd25b6c8534b", "parents": [ "522d7decc0370070448a8c28982c8dfd8970489e" ], "author": { "name": "Michel Lespinasse", "email": "walken@google.com", "time": "Thu Mar 10 18:48:51 2011 -0800" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Mar 11 12:23:08 2011 +0100" }, "message": "futex: Sanitize cmpxchg_futex_value_locked API\n\nThe cmpxchg_futex_value_locked API was funny in that it returned either\nthe original, user-exposed futex value OR an error code such as -EFAULT.\nThis was confusing at best, and could be a source of livelocks in places\nthat retry the cmpxchg_futex_value_locked after trying to fix the issue\nby running fault_in_user_writeable().\n \nThis change makes the cmpxchg_futex_value_locked API more similar to the\nget_futex_value_locked one, returning an error code and updating the\noriginal value through a reference argument.\n \nSigned-off-by: Michel Lespinasse \u003cwalken@google.com\u003e\nAcked-by: Chris Metcalf \u003ccmetcalf@tilera.com\u003e [tile]\nAcked-by: Tony Luck \u003ctony.luck@intel.com\u003e [ia64]\nAcked-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nTested-by: Michal Simek \u003cmonstr@monstr.eu\u003e [microblaze]\nAcked-by: David Howells \u003cdhowells@redhat.com\u003e [frv]\nCc: Darren Hart \u003cdarren@dvhart.com\u003e\nCc: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nCc: Matt Turner \u003cmattst88@gmail.com\u003e\nCc: Russell King \u003clinux@arm.linux.org.uk\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: \"James E.J. Bottomley\" \u003cjejb@parisc-linux.org\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nLKML-Reference: \u003c20110311024851.GC26122@google.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n\n" }, { "commit": "522d7decc0370070448a8c28982c8dfd8970489e", "tree": "0f964a23a28b9dcf2d1fad3096f549c93c68b605", "parents": [ "c0c9ed15042ceac7c485813012a0a97316101b57" ], "author": { "name": "Michel Lespinasse", "email": "walken@google.com", "time": "Thu Mar 10 18:47:31 2011 -0800" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Mar 11 12:23:08 2011 +0100" }, "message": "futex: Remove redundant pagefault_disable in futex_atomic_cmpxchg_inatomic()\n\nkernel/futex.c disables page faults before calling\nfutex_atomic_cmpxchg_inatomic(), so there is no need to do it again\nwithin that function.\n \nSigned-off-by: Michel Lespinasse \u003cwalken@google.com\u003e\nCc: Darren Hart \u003cdarren@dvhart.com\u003e\nCc: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nCc: Matt Turner \u003cmattst88@gmail.com\u003e\nCc: Russell King \u003clinux@arm.linux.org.uk\u003e\nCc: David Howells \u003cdhowells@redhat.com\u003e\nCc: Tony Luck \u003ctony.luck@intel.com\u003e\nCc: Michal Simek \u003cmonstr@monstr.eu\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: \"James E.J. Bottomley\" \u003cjejb@parisc-linux.org\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Chris Metcalf \u003ccmetcalf@tilera.com\u003e\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nLKML-Reference: \u003c20110311024731.GB26122@google.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n\n" }, { "commit": "23bfdacf4eb525ff3404161429cedaa281c23e47", "tree": "82b850e1d22d617cc3e9e648325df38c4ed97c23", "parents": [ "6fa85e5ce311a8c57fe32cb6403961f7a897112d" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Thu Mar 10 14:03:01 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 10 15:16:29 2011 +0000" }, "message": "ARM: 6798/1: aout-core: zero thread debug registers in a.out core dump\n\nThe removal of the single-step emulation from ptrace on ARM means that\nthread_struct no longer has software breakpoint fields in its debug\nmember.\n\nThis patch fixes the a.out core dump code so that the debug registers\nare zeroed rather than trying to copy from non-existent fields.\n\nCc: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Bryan Wu \u003cbryan.wu@canonical.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "5dab26af1bacad9a7189d904fbc8b4fe8e95dd81", "tree": "246c70038035ee4a0505f2b043ecb3c73018b01b", "parents": [ "fcbdc5fe6ebe07d502c9b652cb63376bcc4227ac" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Fri Mar 04 12:38:54 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 09 21:40:18 2011 +0000" }, "message": "ARM: 6784/1: errata: no automatic Store Buffer drain on Cortex-A9\n\nOn revisions of the Cortex-A9 prior to r2p0, the Store Buffer does not\nhave any automatic draining mechanism and therefore a livelock may occur\nif an external agent continuously polls a memory location waiting to\nobserve an update.\n\nThis workaround defines cpu_relax() as smp_mb(), preventing correctly\nwritten polling loops from denying visibility of updates to memory.\n\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d7ed36a4ea84e3a850f9932e2058ceef987d1acd", "tree": "b4e8daf31024698e1b6be9ff6f8810be776f4c5c", "parents": [ "4bdb157749a0da065e532f2f46040c178075b06f" ], "author": { "name": "Santosh Shilimkar", "email": "santosh.shilimkar@ti.com", "time": "Wed Mar 02 08:03:22 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 09 00:18:47 2011 +0000" }, "message": "ARM: 6777/1: gic: Add hooks for architecture specific extensions\n\nFew architectures combine the GIC with an external interrupt\ncontroller. On such systems it may be necessary to update both\nthe GIC registers and the external controller\u0027s registers to control\nIRQ behavior.\n\nThis can be addressed in couple of possible methods.\n 1. Export common GIC routines along with \u0027struct irq_chip gic_chip\u0027\n and allow architectures to have custom function by override.\n 2. Provide architecture specific function pointer hooks\n within GIC library and leave platforms to add the necessary\n code as part of these hooks.\n\nFirst one might be non-intrusive but have few shortcomings like arch\nneeds to have there own custom gic library. Locks used should be\ncommon since it caters to same IRQs etc. Maintenance point of view\nalso it leads to multiple file fixes.\n\nThe second probably is cleaner and portable. It ensures that all the\ncommon GIC infrastructure is not touched and also provides archs to\naddress their specific issue.\n\nCc: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nSigned-off-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Colin Cross \u003cccross@android.com\u003e\nTested-by: Colin Cross \u003cccross@android.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "2839e06c95d12ada034cf9b63da60334c7c6358b", "tree": "9295f80025852f73fbf3c66740eae76df5d61314", "parents": [ "d239b1dc093d551046a909920b5310c1d1e308c1" ], "author": { "name": "Santosh Shilimkar", "email": "santosh.shilimkar@ti.com", "time": "Tue Mar 08 06:59:54 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 09 00:18:34 2011 +0000" }, "message": "ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corrupti\n\nPL310 implements the Clean \u0026 Invalidate by Way L2 cache maintenance\noperation (offset 0x7FC). This operation runs in background so that\nPL310 can handle normal accesses while it is in progress. Under very\nrare circumstances, due to this erratum, write data can be lost when\nPL310 treats a cacheable write transaction during a Clean \u0026 Invalidate\nby Way operation.\n\nWorkaround:\nDisable Write-Back and Cache Linefill (Debug Control Register)\nClean \u0026 Invalidate by Way (0x7FC)\nRe-enable Write-Back and Cache Linefill (Debug Control Register)\n\nThis patch also removes any OMAP dependency on PL310 Errata\u0027s\n\nSigned-off-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "71d8c5b11e3b5936ae6c2e0b1dd6f5c78b305b65", "tree": "c815434adc34cb7274ef6a0ee16cf8491fa0c03e", "parents": [ "0fff6b9a4e0aba233a2ff644316d29b0cb784e33", "53936c56dcaf1db818fe953ae05592a8b5e345b5" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Mar 06 08:42:55 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Mar 06 08:42:55 2011 +0000" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stable\n" }, { "commit": "868d172b8ac23070418ec6265195e88e8d5dbe92", "tree": "7e7b0b853c92c6ed96c8d61828ab0c4fe3cd4cb4", "parents": [ "e25bac968d41d994e5295f89547bdff6cb40588a" ], "author": { "name": "Eric Cooper", "email": "ecc@cmu.edu", "time": "Wed Feb 02 17:16:09 2011 -0500" }, "committer": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Thu Mar 03 16:26:55 2011 -0500" }, "message": "[ARM] add machine-specific hook to machine_kexec\n\nProvide the option to call a machine-specific function\nbefore kexec\u0027ing a new kernel.\n\nSigned-off-by: Eric Cooper \u003cecc@cmu.edu\u003e\nSigned-off-by: Nicolas Pitre \u003cnico@fluxnic.net\u003e\n" }, { "commit": "80f0aad77f3e1e9d9e518b09ac46963d628ae2be", "tree": "df195fff207483f4b10520ebcd3a500c1f703364", "parents": [ "3572bea8cbc57f0bef1e0f4580c01717df7026d8" ], "author": { "name": "Dave Martin", "email": "dave.martin@linaro.org", "time": "Fri Feb 25 17:54:52 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Feb 26 13:36:06 2011 +0000" }, "message": "ARM: 6766/1: Thumb-2: Reflect ARM/Thumb-2 configuration in module vermagic\n\nLoading Thumb-2 modules into an ARM kernel or vice-versa isn\u0027t\nguaranteed to work safely, since the kernel is not interworking-\naware everywhere.\n\nThis patch adds \"thumb2\" to the module vermagic when\nCONFIG_THUMB2_KERNEL is enabled, to help avoid accidental loading\nof modules into the wrong kernel.\n\nSigned-off-by: Dave Martin \u003cdave.martin@linaro.org\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "8f3112707fabc2f9f932a4ac1c5b92f3266e4662", "tree": "270f660b9021024fd93c8c95fff213140905550a", "parents": [ "97594b0f35c0708cb9551c070b9693a52ec24ebf" ], "author": { "name": "Nicolas Pitre", "email": "nicolas.pitre@linaro.org", "time": "Thu Feb 24 22:57:14 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Feb 26 13:33:47 2011 +0000" }, "message": "ARM: 6765/1: remove obsolete comment from asm/mach/arch.h\n\nSince commit 6fc31d54 this comment is no longer true.\n\nSigned-off-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "425fc47adb5bb69f76285be77a09a3341a30799e", "tree": "aa1fab1e90520f80573445c77b55db8446e3570c", "parents": [ "5637a126482026b37d426d76e1b18f748f309aaa" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Mon Feb 14 14:31:09 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Feb 23 17:24:22 2011 +0000" }, "message": "ARM: 6668/1: ptrace: remove single-step emulation code\n\nPTRACE_SINGLESTEP is a ptrace request designed to offer single-stepping\nsupport to userspace when the underlying architecture has hardware\nsupport for this operation.\n\nOn ARM, we set arch_has_single_step() to 1 and attempt to emulate hardware\nsingle-stepping by disassembling the current instruction to determine the\nnext pc and placing a software breakpoint on that location.\n\nUnfortunately this has the following problems:\n\n1.) Only a subset of ARMv7 instructions are supported\n2.) Thumb-2 is unsupported\n3.) The code is not SMP safe\n\nWe could try to fix this code, but it turns out that because of the above\nissues it is rarely used in practice. GDB, for example, uses PTRACE_POKETEXT\nand PTRACE_PEEKTEXT to manage breakpoints itself and does not require any\nkernel assistance.\n\nThis patch removes the single-step emulation code from ptrace meaning that\nthe PTRACE_SINGLESTEP request will return -EIO on ARM. Portable code must\ncheck the return value from a ptrace call and handle the failure gracefully.\n\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "aaa50048f6ce44af66ce0389d4cc6a8348333271", "tree": "a41e04a190420fb970981b8535db7cc9f6e583bd", "parents": [ "c191789c787f488fdb74de0ee55258f71a427704" ], "author": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Tue Jan 25 21:35:38 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Feb 23 17:24:17 2011 +0000" }, "message": "ARM: 6639/1: allow highmem on SMP platforms without h/w TLB ops broadcast\n\nIn commit e616c591405c168f6dc3dfd1221e105adfe49b8d, highmem support was\ndeactivated for SMP platforms without hardware TLB ops broadcast because\nusage of kmap_high_get() requires that IRQs be disabled when kmap_lock\nis locked which is incompatible with the IPI mechanism used by the\nsoftware TLB ops broadcast invoked through flush_all_zero_pkmaps().\n\nThe reason for kmap_high_get() is to ensure that the currently kmap\u0027d\npage usage count does not decrease to zero while we\u0027re using its\nexisting virtual mapping in an atomic context. With a VIVT cache this\nis essential to do due to cache coherency issues, but with a VIPT cache\nthis is only an optimization so not to pay the price of establishing a\nsecond mapping if an existing one can be used. However, on VIPT\nplatforms without hardware TLB maintenance we can give up on that\noptimization in order to be able to use highmem.\n\nFrom ARMv7 onwards the TLB ops are broadcasted in hardware, so let\u0027s\ndisable ARCH_NEEDS_KMAP_HIGH_GET only when CONFIG_SMP and\nCONFIG_CPU_TLB_V6 are defined.\n\nSigned-off-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nTested-by: Saeed Bishara \u003csaeed.bishara@gmail.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "2bbd7e9b74271b2d6a14b4840fc44afbea83774d", "tree": "7666eeaeefe43a616ece6bf189a3be8fa78e9c35", "parents": [ "459c1517f9873b198af7dcded8d8cc84749bbb69" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Jan 08 12:05:09 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Feb 23 17:24:12 2011 +0000" }, "message": "ARM: fix some sparse errors in generic ARM code\n\narch/arm/kernel/return_address.c:37:6: warning: symbol \u0027return_address\u0027 was not declared. Should it be static?\narch/arm/kernel/setup.c:76:14: warning: symbol \u0027processor_id\u0027 was not declared. Should it be static?\narch/arm/kernel/traps.c:259:1: warning: symbol \u0027die_lock\u0027 was not declared. Should it be static?\narch/arm/vfp/vfpmodule.c:156:6: warning: symbol \u0027vfp_raise_sigfpe\u0027 was not declared. Should it be static?\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "97594b0f35c0708cb9551c070b9693a52ec24ebf", "tree": "ef8c6d9197a1714331f247d1f9cf134033472865", "parents": [ "5a5af730536fbf15fc354980cba2a0400afa6b76" ], "author": { "name": "Uwe Kleine-König", "email": "u.kleine-koenig@pengutronix.de", "time": "Tue Feb 22 23:29:37 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Feb 23 16:19:21 2011 +0000" }, "message": "ARM: 6757/1: fix tlb.h induced linux/swap.h build failure\n\nCommit\n\n\t06824ba (ARM: tlb: delay page freeing for SMP and ARMv7 CPUs)\n\nintroduced a build failure for builds with CONFIG_SWAP\u003dn:\n\n\tIn file included from arch/arm/mm/init.c:27:\n\tarch/arm/include/asm/tlb.h: In function \u0027tlb_flush_mmu\u0027:\n\tarch/arm/include/asm/tlb.h:101: error: implicit declaration of function \u0027release_pages\u0027\n\tarch/arm/include/asm/tlb.h: In function \u0027tlb_remove_page\u0027:\n\tarch/arm/include/asm/tlb.h:165: error: implicit declaration of function \u0027page_cache_release\u0027\n\nas linux/swap.h doesn\u0027t include linux/pagemap.h but actually needs it\n(see comments in linux/swap.h as to why this is.)\n\nFix that by #including \u003clinux/pagemap.h\u003e in \u003casm/pgalloc.h\u003e as it\u0027s done\nby x86.\n\nSigned-off-by: Uwe Kleine-König \u003cu.kleine-koenig@pengutronix.de\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f6b0fa02e8b0708d17d631afce456524eadf87ff", "tree": "900fcd2149a03ba229bb29e982d3d6a5f3d3fcfc", "parents": [ "753790e713d80b50b867fa1ed32ec0eb5e82ae8e" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Feb 06 15:48:39 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Feb 22 17:11:23 2011 +0000" }, "message": "ARM: pm: add generic CPU suspend/resume support\n\nThis adds core support for saving and restoring CPU coprocessor\nregisters for suspend/resume support. This contains support for suspend\nwith ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.\nTested on Assabet and Tegra 2.\n\nTested-by: Colin Cross \u003cccross@android.com\u003e\nTested-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "58e9c47fa0dd76693b2c85c010c7430a4de77c6d", "tree": "8b315bd55179023cc22ec50b8933a3d881b0376a", "parents": [ "06824ba824b3e9f2fedb38bee79af0643198ed7f" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Feb 20 12:27:49 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Feb 21 19:29:28 2011 +0000" }, "message": "ARM: tlb: move noMMU tlb_flush() to asm/tlb.h\n\nThere\u0027s no need to noMMU to put tlb_flush() in asm/tlbflush.h - it\u0027s\npart of the tlb shootdown interface. Move it to asm/tlb.h instead, as\nper x86.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "06824ba824b3e9f2fedb38bee79af0643198ed7f", "tree": "ce6da1f5fd789a08dafec39e094b29cf6023a9af", "parents": [ "a9ad21fed09cb95d34af9474be0831525b30c4c6" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Feb 20 12:16:45 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Feb 21 19:29:28 2011 +0000" }, "message": "ARM: tlb: delay page freeing for SMP and ARMv7 CPUs\n\nWe need to delay freeing any mapped page on SMP and ARMv7 systems to\nensure that the data is not accessed by other CPUs, or is used for\nspeculative prefetch with ARMv7. This includes not only mapped pages\nbut also pages used for the page tables themselves.\n\nThis avoids races with the MMU/other CPUs accessing pages after they\u0027ve\nbeen freed but before we\u0027ve invalidated the TLB.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b8272a61c16decd4c8627fc1181bdd174c922c3f", "tree": "d539562c4fa117e151ffb7867cefff5c016d940f", "parents": [ "ac1556b37e9b06a41d7691dca0d50a28210488f9" ], "author": { "name": "Shiraz Hashim", "email": "shiraz.hashim@st.com", "time": "Wed Feb 16 07:40:29 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Feb 21 19:29:24 2011 +0000" }, "message": "ARM: 6722/1: SPEAr: sp810: switch to slow mode before reset\n\nIn sysctl_soft_reset(), switch to slow mode before resetting the system\nvia the system controller. This is required.\n\nReviewed-by: Stanley Miao \u003cstanley.miao@windriver.com\u003e\nSigned-off-by: Shiraz Hashim \u003cshiraz.hashim@st.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "885028e4ba4caf49d565c96481e1a05220ecb517", "tree": "45be55a3aa9cbd14bf924e00f974c43a35c573bc", "parents": [ "0cc9d5257857608ba85885b75fcada13d359b5d1" ], "author": { "name": "Srinidhi Kasagar", "email": "srinidhi.kasagar@stericsson.com", "time": "Thu Feb 17 07:03:51 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Feb 19 11:23:21 2011 +0000" }, "message": "ARM: 6741/1: errata: pl310 cache sync operation may be faulty\n\nThe effect of cache sync operation is to drain the store buffer and\nwait for all internal buffers to be empty. In normal conditions, store\nbuffer is able to merge the normal memory writes within its 32-byte\ndata buffers. Due to this erratum present in r3p0, the effect of cache\nsync operation on the store buffer still remains when the operation\ncompletes. This means that the store buffer is always asked to drain\nand this prevents it from merging any further writes.\n\nThis can severely affect performance on the write traffic esp. on\nNormal memory NC one.\n\nThe proposed workaround is to replace the normal offset of cache sync\noperation(0x730) by another offset targeting an unmapped PL310\nregister 0x740.\n\nSigned-off-by: srinidhi kasagar \u003csrinidhi.kasagar@stericsson.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "3a6b1676c6f27f7fad1a3d6fab5a95f90b1e7402", "tree": "7457d1896dae7e61bfad76f6d26e2d84a1b3ae7e", "parents": [ "4d901c4271951d110afb13ee9aa73d27a6c8e53d" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Feb 15 17:28:28 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 17 23:27:34 2011 +0000" }, "message": "ARM: 6675/1: use phys_addr_t instead of unsigned long in conversion code\n\nThe unsigned long datatype is not sufficient for mapping physical addresses\n\u003e\u003d 4GB.\n\nThis patch ensures that the address conversion code in asm/memory.h casts\nto the correct type when handling physical addresses. The internal v2p\nmacros only deal with lowmem addresses, so these do not need to be modified.\n\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "cada3c0841e1deaec4c0f92654610b028dc683ff", "tree": "9c6085c8b8447795ddc749315a31fd3906a6159d", "parents": [ "dc21af99fadcfa0ae65b52fd0895f85824f0c288" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jan 04 19:39:29 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 17 23:27:33 2011 +0000" }, "message": "ARM: P2V: extend to 16-bit translation offsets\n\nMSM\u0027s memory is aligned to 2MB, which is more than we can do with our\nexisting method as we\u0027re limited to the upper 8 bits. Extend this by\nusing two instructions to 16 bits, automatically selected when MSM is\nenabled.\n\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nTested-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "dc21af99fadcfa0ae65b52fd0895f85824f0c288", "tree": "d2d293d79fdb405f25ca7fb18aa16aba6ecea261", "parents": [ "5b7de4547b388d3949620e21d072e35b6f2638fa" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jan 04 19:09:43 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 17 23:27:32 2011 +0000" }, "message": "ARM: P2V: introduce phys_to_virt/virt_to_phys runtime patching\n\nThis idea came from Nicolas, Eric Miao produced an initial version,\nwhich was then rewritten into this.\n\nPatch the physical to virtual translations at runtime. As we modify\nthe code, this makes it incompatible with XIP kernels, but allows us\nto achieve this with minimal loss of performance.\n\nAs many translations are of the form:\n\n\tphysical \u003d virtual + (PHYS_OFFSET - PAGE_OFFSET)\n\tvirtual \u003d physical - (PHYS_OFFSET - PAGE_OFFSET)\n\nwe generate an \u0027add\u0027 instruction for __virt_to_phys(), and a \u0027sub\u0027\ninstruction for __phys_to_virt(). We calculate at run time (PHYS_OFFSET\n- PAGE_OFFSET) by comparing the address prior to MMU initialization with\nwhere it should be once the MMU has been initialized, and place this\nconstant into the above add/sub instructions.\n\nOnce we have (PHYS_OFFSET - PAGE_OFFSET), we can calculate the real\nPHYS_OFFSET as PAGE_OFFSET is a build-time constant, and save this for\nthe C-mode PHYS_OFFSET variable definition to use.\n\nAt present, we are unable to support Realview with Sparsemem enabled\nas this uses a complex mapping function, and MSM as this requires a\nconstant which will not fit in our math instruction.\n\nAdd a module version magic string for this feature to prevent\nincompatible modules being loaded.\n\nTested-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nTested-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f4117ac9e237b74afdf5e001d5ea26a4d15e9847", "tree": "dce3ccceda23d4bf620ec3d025a14773c7c938a8", "parents": [ "6fc31d54443bdc25a8166be15e3920a7e39d195d" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jan 04 18:07:14 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 17 23:26:55 2011 +0000" }, "message": "ARM: P2V: separate PHYS_OFFSET from platform definitions\n\nThis uncouple PHYS_OFFSET from the platform definitions, thereby\nfacilitating run-time computation of the physical memory offset.\n\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nAcked-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nAcked-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nAcked-by: Magnus Damm \u003cdamm@opensource.se\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nAcked-by: Jean-Christophe PLAGNIOL-VILLARD \u003cplagnioj@jcrosoft.com\u003e\nAcked-by: Wan ZongShun \u003cmcuos.com@gmail.com\u003e\nAcked-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nAcked-by: Eric Miao \u003ceric.y.miao@gmail.com\u003e\nAcked-by: Jiandong Zheng \u003cjdzheng@broadcom.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "0e25a5c98067286fc727cf142fc0dadf95790921", "tree": "2561e8b36242fbace98a2fe80047fb32aef6d150", "parents": [ "100b33c8bd8a3235fd0b7948338d6cbb3db3c63d" ], "author": { "name": "Rabin Vincent", "email": "rabin.vincent@stericsson.com", "time": "Tue Feb 08 09:24:36 2011 +0530" }, "committer": { "name": "Linus Walleij", "email": "linus.walleij@linaro.org", "time": "Thu Feb 17 13:55:45 2011 +0100" }, "message": "ARM: perf_event: allow platform-specific interrupt handler\n\nAllow a platform-specific IRQ handler to be specified via platform data.\nThis will be used to implement the single-irq workaround for the DB8500.\n\nSigned-off-by: Rabin Vincent \u003crabin.vincent@stericsson.com\u003e\nAcked-by: Lee Jones \u003clee.jones@linaro.org\u003e\nAcked-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\n" }, { "commit": "753790e713d80b50b867fa1ed32ec0eb5e82ae8e", "tree": "2d4244e4c21ed9512efd48dfd99bfddcbc85af02", "parents": [ "292ec42af7c6361435fe9df50cd59ec76f6741c6" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Feb 06 15:32:24 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Feb 12 11:52:21 2011 +0000" }, "message": "ARM: move cache/processor/fault glue to separate include files\n\nThis allows the cache/processor/fault glue to be more easily used\nfrom assembler code. Tested on Assabet and Tegra 2.\n\nTested-by: Colin Cross \u003cccross@android.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "292ec42af7c6361435fe9df50cd59ec76f6741c6", "tree": "376c6bdc9f615988c19f9597020a8cde99005543", "parents": [ "afe8a887550f7cc24eb16449670b93f6b43c32d8" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Feb 04 10:36:39 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Feb 11 12:29:18 2011 +0000" }, "message": "ARM: pm: add function to set WFI low-power mode for SMP CPUs\n\nAdd a function to set the SCU low-power mode for SMP CPUs. This\ncentralizes this functionality rather than having to expose the\nSCU register definitions to each platform.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "917692f5f7ec63de3b093c825913d68e910db282", "tree": "d4f2a59ca417c446450df0c1a84384fcef501c7f", "parents": [ "774c096bf9e49eebf7b5d2d9fdddf632c29ccea0" ], "author": { "name": "Dave Martin", "email": "dave.martin@linaro.org", "time": "Wed Feb 09 12:06:59 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 10 15:30:51 2011 +0000" }, "message": "ARM: 6655/1: Correct WFE() in asm/spinlock.h for Thumb-2\n\nThe content for ALT_SMP() in the definition of WFE() expands to 6\nbytes (IT cc ; WFEcc.W), which breaks the assumptions of the fixup\ncode, leading to lockups when the affected code gets run.\n\nThis patch works around the problem by explicitly using an\nIT + WFEcc.N pair.\n\nSigned-off-by: Dave Martin \u003cdave.martin@linaro.org\u003e\nAcked-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "774c096bf9e49eebf7b5d2d9fdddf632c29ccea0", "tree": "0189d866c91a8d8ca8bd574c17c6c65284594880", "parents": [ "3bc28c8edc4f5f78d9ec23fb0f20df29b7b3a072" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Jan 23 13:04:53 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Feb 02 21:23:33 2011 +0000" }, "message": "ARM: v6/v7 cache: allow cache calls to be optimized\n\nThe v6 cache call optimization was disabled to allow the optional block\ncache operations to be subsituted on CPUs which supported those\noperations. However, as that functionality was removed, we no longer\nneed to prevent this optimization being taken advantage of.\n\nThe v7 cache call optimization was just a copy of the v6, so also fix\nthat too.\n\nTested-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "37bc618fe2689a7f8de8fac82e72b00ecea4d43d", "tree": "22069ac77f14028b237703936385060c09b655f5", "parents": [ "a41297a0ffb43fda0a565bdd3ee405d16505820c" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 17 16:38:56 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Feb 02 21:23:29 2011 +0000" }, "message": "ARM: v6k: select TLS register code according to V6 variants\n\nIf CONFIG_CPU_V6 is enabled, we may or may not have the TLS register.\nUse the conditional code which copes with this variability. Otherwise,\nif CONFIG_CPU_32v6K is set, we know we have the TLS register on all\nsupported CPUs, so use it unconditionally.\n\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nTested-by: Sourav Poddar \u003csourav.poddar@ti.com\u003e\nTested-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "4ed67a53591db641543d57f31c182591a429dc93", "tree": "1e35ab3a934d96bb149d2bd9f10f70ca521cc361", "parents": [ "7db44c75a241c18d03e82540c5b825216d4c668b" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 17 15:42:42 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Feb 02 21:23:28 2011 +0000" }, "message": "ARM: v6k: select cmpxchg code sequences according to V6 variants\n\nIf CONFIG_CPU_V6 is enabled, we must avoid the byte/halfword/doubleword\nexclusive operations, which aren\u0027t implemented before V6K. Use the\ngeneric versions (or omit them) instead.\n\nIf CONFIG_CPU_V6 is not set, but CONFIG_CPU_32v6K is enabled, we have\nthe K extnesions, so use these new instructions.\n\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nTested-by: Sourav Poddar \u003csourav.poddar@ti.com\u003e\nTested-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "e399b1a4e1d205bdc816cb550d2064f2eb1ddc4c", "tree": "cf31e0aeafd972a8ea417dca1ff66c1e0315c907", "parents": [ "000d9c78eb5cd7f18e3d6a381d66e606bc9b8196" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 17 15:08:32 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Feb 02 21:23:26 2011 +0000" }, "message": "ARM: v6k: introduce CPU_V6K option\n\nIntroduce a CPU_V6K configuration option for platforms to select if they\nhave a V6K CPU core. This allows us to identify whether we need to\nsupport ARMv6 CPUs without the V6K SMP extensions at build time.\n\nCurrently CPU_V6K is just an alias for CPU_V6, and all places which\nreference CPU_V6 are replaced by (CPU_V6 || CPU_V6K).\n\nSelect CPU_V6K from platforms which are known to be V6K-only.\n\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nTested-by: Sourav Poddar \u003csourav.poddar@ti.com\u003e\nTested-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "000d9c78eb5cd7f18e3d6a381d66e606bc9b8196", "tree": "4a142d5c4d4b589ac696f3a6a932ba1965d29ed1", "parents": [ "6323f0ccedf756dfe5f46549cec69a2d6d97937b" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Jan 15 16:22:12 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Feb 02 21:23:25 2011 +0000" }, "message": "ARM: v6k: remove CPU_32v6K dependencies in asm/spinlock.h\n\nSMP requires at least the ARMv6K extensions to be present, so if we\u0027re\nrunning on SMP, the WFE and SEV instructions must be available.\n\nHowever, when we run on UP, the v6K extensions may not be available,\nand so we don\u0027t want WFE/SEV to be in the instruction stream. Use the\nSMP alternatives infrastructure to replace these instructions with NOPs\nif we build for SMP but run on UP.\n\nTested-by: Tony Lindgren \u003ctony@atomide.com\u003e\nTested-by: Sourav Poddar \u003csourav.poddar@ti.com\u003e\nTested-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "6323f0ccedf756dfe5f46549cec69a2d6d97937b", "tree": "091e3408c12bbce33ef5d708b6131132b9660d4d", "parents": [ "a16ede35a2659170c855c5d267776666c0630f1f" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Jan 16 18:02:17 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Feb 02 21:23:25 2011 +0000" }, "message": "ARM: bitops: switch set/clear/change bitops to use ldrex/strex\n\nSwitch the set/clear/change bitops to use the word-based exclusive\noperations, which are only present in a wider range of ARM architectures\nthan the byte-based exclusive operations.\n\nTested record:\n- Nicolas Pitre: ext3,rw,le\n- Sourav Poddar: nfs,le\n- Will Deacon: ext3,rw,le\n- Tony Lindgren: ext3+nfs,le\n\nReviewed-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nTested-by: Sourav Poddar \u003csourav.poddar@ti.com\u003e\nTested-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nTested-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "c1928022ef94662a88329e35fa0968b1be328b8e", "tree": "d3efe819340f08196c30fbd5908912e15cda01a7", "parents": [ "b0a2679d27408d97ce31e5f800b44227d3388b84" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Jan 30 11:29:40 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 31 10:53:42 2011 +0000" }, "message": "ARM: io: ensure inb/outb() et.al. are properly ordered on ARMv6+\n\nEnsure that the ISA/PCI IO space accessors are properly ordered on\nARMv6+ architectures. These should always be ordered with respect to\nall other accesses.\n\nThis also fixes __iormb() and __iowmb() not being visible to ioread/\niowrite if a platform defines its own MMIO accessors.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "5756e9dd0de6d5c307773f8f734c0684b3098fdd", "tree": "4a92eded1b93fd91d2c40bc5bb5cb0405daeed79", "parents": [ "6fb1b304255efc5c4c93874ac8c066272e257e28" ], "author": { "name": "Dave Martin", "email": "dave.martin@linaro.org", "time": "Wed Jan 26 18:34:26 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 27 11:48:58 2011 +0000" }, "message": "ARM: 6640/1: Thumb-2: Symbol manipulation macros for function body copying\n\nIn low-level board support code, there is sometimes a need to\ncopy a function body to another location at run-time.\n\nA straightforward call to memcpy doesn\u0027t work in Thumb-2,\nbecause bit 0 of external Thumb function symbols is set to 1,\nindicating that the function is Thumb. Without corrective\nmeasures, this will cause an off-by-one copy, and the copy\nmay be called using the wrong instruction set.\n\nThis patch adds an fncpy() macro to help with such copies.\n\nParticular care is needed, because C doesn\u0027t guarantee any\ndefined behaviour when casting a function pointer to any other\ntype. This has been observed to lead to strange optimisation\nside-effects when doing the arithmetic which is required in\norder to copy/move function bodies correctly in Thumb-2.\n\nThanks to Russell King and Nicolas Pitre for their input\non this patch.\n\nSigned-off-by: Dave Martin \u003cdave.martin@linaro.org\u003e\nTested-by: Jean Pihet \u003cj-pihet@ti.com\u003e\nTested-by: Tony Lindgren \u003ctony@atomide.com\u003e\nTested-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "05b112ff98070dc1f3293e8cd8e4c6f468d1084a", "tree": "18b5ddfc985a96c637e59ff3e5ce4672c277ff58", "parents": [ "03399c1cb4e2503e92d10c1ce38ac2e69b7d2380" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Tue Jan 25 11:18:25 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jan 25 21:18:03 2011 +0000" }, "message": "ARM: 6637/1: Make the argument to virt_to_phys() \"const volatile\"\n\nChanging the virt_to_phys() argument to \"const volatile void *\" avoids\ncompiler warnings in some situations where this function is used.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nAcked-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "baaece224570a935210a59257b5d9073e99843ea", "tree": "1b0af1903ce4a58122473cca2d128ae1f56726c0", "parents": [ "e5310f611d17ed4e92e0d4e46fd9f6fb40e66df3" ], "author": { "name": "Pawel Moll", "email": "pawel.moll@arm.com", "time": "Tue Jan 25 15:53:03 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jan 25 16:18:33 2011 +0000" }, "message": "ARM: 6635/2: Configure reference clock for Versatile Express timers\n\nTimers on Versatile Express mainboard are used as system clock/event\nsources. Driver assumes that they are clocked with 1MHz signal.\nOld V2M firmware apparently configured it by default, but on newer\nboards one can observe that \"sleep 1\" command takes over 30 seconds\nto finish, as the timers are fed with 32kHz instead...\n\nThis patch performs required magic and also removes code clearing\ntimer\u0027s control registers, as exactly the same operations are\nperformed by the timer driver few jiffies later.\n\nSigned-off-by: Pawel Moll \u003cpawel.moll@arm.com\u003e\nTested-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "82e6923e1862428b755ec306b3dbccf926849314", "tree": "e0be095c30c7cbfeff2a2096cf53e9c2f92fed13", "parents": [ "1bae4ce27c9c90344f23c65ea6966c50ffeae2f5" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jan 21 11:04:45 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 24 19:05:19 2011 +0000" }, "message": "ARM: lh7a40x: remove unmaintained platform support\n\nlh7a40x has only been receiving updates for updates to generic code.\nThe last involvement from the maintainer according to the git logs was\nin 2006. As such, it is a maintainence burden with no benefit.\n\nThis gets rid of two defconfigs.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "65e5d002b5ad220db2bf9557f53de5a98f7dab86", "tree": "93d36afd4b82a24e5b553766a574a6632fca3aff", "parents": [ "38567333a6dabd0f2b4150e9fb6dd8e3ba2985e5", "cb4d3eaebb96616085f5a46a7d7e004ddd955b09" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Jan 15 12:29:50 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Jan 15 12:29:50 2011 -0800" }, "message": "Merge branch \u0027fixes\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027fixes\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm:\n ARM: fix missing branch in __error_a\n ARM: fix /proc/$PID/stack on SMP\n ARM: Fix build regression on SA11x0, PXA, and H720x targets\n ARM: 6625/1: use memblock memory regions for \"System RAM\" I/O resources\n ARM: fix wrongly patched constants\n ARM: 6624/1: fix dependency for CONFIG_SMP_ON_UP\n ARM: 6623/1: Thumb-2: Fix out-of-range offset for Thumb-2 in proc-v7.S\n ARM: 6622/1: fix dma_unmap_sg() documentation\n ARM: 6621/1: bitops: remove condition code clobber for CLZ\n ARM: 6620/1: Change misleading warning when CONFIG_CMDLINE_FORCE is used\n ARM: 6619/1: nommu: avoid mapping vectors page when !CONFIG_MMU\n ARM: sched_clock: make minsec argument to clocks_calc_mult_shift() zero\n ARM: sched_clock: allow init_sched_clock() to be called early\n ARM: integrator: fix compile warning in cpu.c\n ARM: 6616/1: Fix ep93xx-fb init/exit annotations\n ARM: twd: fix display of twd frequency\n ARM: udelay: prevent math rounding resulting in short udelays\n" }, { "commit": "e163d529ad7ab449db36ee88dab16170de711f34", "tree": "d930e21edf1b5992066a9734524218eaa1f4bd24", "parents": [ "22eeb8f6e0214a83ac6958a29a83572137f174bb" ], "author": { "name": "Rabin Vincent", "email": "rabin@rab.in", "time": "Wed Jan 12 14:38:52 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jan 12 14:22:25 2011 +0000" }, "message": "ARM: 6621/1: bitops: remove condition code clobber for CLZ\n\nThe CLZ instruction does not alter the condition flags, so remove the\n\"cc\" clobber from the inline asm for fls().\n\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Rabin Vincent \u003crabin@rab.in\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "211baa7016894c02fc18693e21ca479cd08ac0c0", "tree": "0fea398c6288b46542fc1640adff697f9b1e07a5", "parents": [ "1aa023b8fda8096caf41c20427a0ef396d88eb0f" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jan 11 16:23:04 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jan 11 16:23:04 2011 +0000" }, "message": "ARM: sched_clock: allow init_sched_clock() to be called early\n\nsched_clock is supposed to be initialized early - in the recently added\ninit_early platform hook. However, in doing so we end up calling\nmod_timer() before the timer lists are initialized, resulting in an\noops.\n\nSplit the initialization in two - the part which the platform calls\nearly which starts things off. The addition of the timer can be\ndelayed until after we have more of the kernel initialized - when the\nnormal time sources are initialized.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "01539ba2a706ab7d35fc0667dff919ade7f87d63", "tree": "5a4bd0cf78007d06690fe4ac06bbd49a5a70bc47", "parents": [ "9e9bc9736756f25d6c47b4eba0ebf25b20a6f153", "dc69d1af9e8d9cbbabff88bb35a6782187a22229" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 06 19:13:58 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 06 19:13:58 2011 -0800" }, "message": "Merge branch \u0027omap-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6\n\n* \u0027omap-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (243 commits)\n omap2: Make OMAP2PLUS select OMAP_DM_TIMER\n OMAP4: hwmod data: Fix alignment and end of line in structurefields\n OMAP4: hwmod data: Move the DMA structures\n OMAP4: hwmod data: Move the smartreflex structures\n OMAP4: hwmod data: Fix missing SIDLE_SMART_WKUP in smartreflexsysc\n arm: omap: tusb6010: add name for MUSB IRQ\n arm: omap: craneboard: Add USB EHCI support\n omap2+: Initialize serial port for dynamic remuxing for n8x0\n omap2+: Add struct omap_board_data and use it for platform level serial init\n omap2+: Allow hwmod state changes to mux pads based on the state changes\n omap2+: Add support for hwmod specific muxing of devices\n omap2+: Add omap_mux_get_by_name\n OMAP2: PM: fix compile error when !CONFIG_SUSPEND\n MAINTAINERS: OMAP: hwmod: update hwmod code, data maintainership\n OMAP4: Smartreflex framework extensions\n OMAP4: hwmod: Add inital data for smartreflex modules.\n OMAP4: PM: Program correct init voltages for scalable VDDs\n OMAP4: Adding voltage driver support\n OMAP4: Register voltage PMIC parameters with the voltage layer\n OMAP3: PM: Program correct init voltages for VDD1 and VDD2\n ...\n\nFix up trivial conflict in arch/arm/plat-omap/Kconfig\n" }, { "commit": "404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34", "tree": "99119edc53fdca73ed7586829b8ee736e09440b3", "parents": [ "28cdac6690cb113856293bf79b40de33dbd8f974", "1051b9f0f9eab8091fe3bf98320741adf36b4cfa" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 06 22:33:32 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 06 22:33:32 2011 +0000" }, "message": "Merge branch \u0027devel-stable\u0027 into devel\n\nConflicts:\n\tarch/arm/mach-pxa/clock.c\n\tarch/arm/mach-pxa/clock.h\n" }, { "commit": "28cdac6690cb113856293bf79b40de33dbd8f974", "tree": "64cd8ca8376ccf9a12faee3588c15a5839f9a28b", "parents": [ "4073723acb9cdcdbe4df9c0e0c376c65d1697e43", "36bb94ba36f332de767cfaa3af6a5136435a3a9c" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 06 22:33:19 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 06 22:33:19 2011 +0000" }, "message": "Merge branch \u0027pgt\u0027 (early part) into devel\n" }, { "commit": "4073723acb9cdcdbe4df9c0e0c376c65d1697e43", "tree": "f41c17eac157b1223ce104845cf9b1e5a9e6a83d", "parents": [ "58daf18cdcab550262a5f4681e1f1e073e21965a", "4ec3eb13634529c0bc7466658d84d0bbe3244aea" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 06 22:32:52 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 06 22:32:52 2011 +0000" }, "message": "Merge branch \u0027misc\u0027 into devel\n\nConflicts:\n\tarch/arm/Kconfig\n\tarch/arm/common/Makefile\n\tarch/arm/kernel/Makefile\n\tarch/arm/kernel/smp.c\n" }, { "commit": "4ec3eb13634529c0bc7466658d84d0bbe3244aea", "tree": "b491daac2ccfc7b8ca88e171a43f66888463568a", "parents": [ "24056f525051a9e186af28904b396320e18bf9a0", "15095bb0fe779c0403091bda7adce5fb3bb9ca35" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 06 22:31:35 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 06 22:32:03 2011 +0000" }, "message": "Merge branch \u0027smp\u0027 into misc\n\nConflicts:\n\tarch/arm/kernel/entry-armv.S\n\tarch/arm/mm/ioremap.c\n" }, { "commit": "24056f525051a9e186af28904b396320e18bf9a0", "tree": "a8580f24820e21ad48333fce6b5f03be55edd561", "parents": [ "9eedd96301cad8ab58ee8c1e579677d0a75c2ba1" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 03 11:29:28 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 06 22:31:11 2011 +0000" }, "message": "ARM: DMA: add support for DMA debugging\n\nAdd ARM support for the DMA debug infrastructure, which allows the\nDMA API usage to be debugged.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "58daf18cdcab550262a5f4681e1f1e073e21965a", "tree": "2096324b947761a567dd451f33664f17ee1de2cd", "parents": [ "aa312be1987d43216e72ffce42bccf6bf81f62ed", "0af85dda39d9b673aca8c0ebae004ea70f3efc93" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jan 05 18:09:03 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jan 05 18:09:03 2011 +0000" }, "message": "Merge branch \u0027clksrc\u0027 into devel\n\nConflicts:\n\tarch/arm/mach-vexpress/v2m.c\n\tarch/arm/plat-omap/counter_32k.c\n\tarch/arm/plat-versatile/Makefile\n" }, { "commit": "31edf274f9aff1ccd39934a0b2fce38f4405c656", "tree": "fdc7bc445307ccb9648ca1a71375947c8ed59722", "parents": [ "3c0eee3fe6a3a1c745379547c7e7c904aa64f6d5", "ed60453fa8f8fc3d034dfdf10371a99cc6905626", "ac61d143ffe2a6db4d4bcf47c21a5159d6a1b644", "28257f7fdee0facc3b7f934e82c2485f27120d41", "b23065313297e750edd57ab6edfd36224826724e", "50005a8deb38e5e6456ebd94e57adb321d4589de", "cf562b4a550b3cd9d602a05bc27aaaaa376947b4", "3d09fbcd26851ffb2c40cec411b8e56db02520d1", "8a9618f5dfca35edb0d7ab6374ff586e2e9e989b" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jan 05 18:08:10 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jan 05 18:08:10 2011 +0000" }, "message": "Merge branches \u0027ftrace\u0027, \u0027gic\u0027, \u0027io\u0027, \u0027kexec\u0027, \u0027mod\u0027, \u0027sa11x0\u0027, \u0027sh\u0027 and \u0027versatile\u0027 into devel\n" }, { "commit": "04228460a3ded723b2da09141c76c45ddd712caf", "tree": "db7b9143b150ead1e9fec10760a1d5ff4045a5e7", "parents": [ "7c0ab43e6ab09d72dc8dbac2521b2f819ccc4026", "24c78557741395e038e83f25367cf2bfd7f582b8" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 03 22:55:21 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 03 22:55:21 2011 +0000" }, "message": "Merge branch \u0027fix\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6\n" }, { "commit": "823a2df258627b80df2e75056b850424a8eb5fed", "tree": "ad8b896ee3d99b91190290af2008a6e045805c7b", "parents": [ "82427de2c7c39ee7bcaa4cb0260b4e9b9ab19eb8" ], "author": { "name": "Mike Rapoport", "email": "mike@compulab.co.il", "time": "Wed Dec 29 09:06:26 2010 +0200" }, "committer": { "name": "Eric Miao", "email": "eric.y.miao@gmail.com", "time": "Mon Jan 03 23:18:32 2011 +0800" }, "message": "ARM: it8152: add IT8152_LAST_IRQ definition to fix build error\n\nThe commit 6ac6b817f3f4c23c5febd960d8deb343e13af5f3 (ARM: pxa: encode\nIRQ number into .nr_irqs) removed definition of ITE_LAST_IRQ which\ncaused the following build error:\n\nCC arch/arm/common/it8152.o\narch/arm/common/it8152.c: In function \u0027it8152_init_irq\u0027:\narch/arm/common/it8152.c:86: error: \u0027IT8152_LAST_IRQ\u0027 undeclared (first use in this function)\narch/arm/common/it8152.c:86: error: (Each undeclared identifier is reported only once\narch/arm/common/it8152.c:86: error: for each function it appears in.)\nmake[2]: *** [arch/arm/common/it8152.o] Error 1\n\nDefining the IT8152_LAST_IRQ in the arch/arm/include/hardware/it8152.c\nfixes the build.\n\nSigned-off-by: Mike Rapoport \u003cmike@compulab.co.il\u003e\nSigned-off-by: Eric Miao \u003ceric.y.miao@gmail.com\u003e\n" }, { "commit": "9eedd96301cad8ab58ee8c1e579677d0a75c2ba1", "tree": "87f5ebbbd5769516771bef37574b39464177f496", "parents": [ "3d29005ab8d828e36108ecc2338612ce3acdd86f" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 03 00:00:17 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 03 11:27:43 2011 +0000" }, "message": "ARM: DMA: Replace page_to_dma()/dma_to_page() with pfn_to_dma()/dma_to_pfn()\n\nReplace the page_to_dma() and dma_to_page() macros with their PFN\nequivalents. This allows us to map parts of memory which do not have\na struct page allocated to them to bus addresses. This will be used\ninternally by dma_alloc_coherent()/dma_alloc_writecombine().\n\nBuild tested on Versatile, OMAP1, IOP13xx and KS8695.\n\nTested-by: Janusz Krzysztofik \u003cjkrzyszt@tis.icnet.pl\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7c0ab43e6ab09d72dc8dbac2521b2f819ccc4026", "tree": "aa0896fc8b07d85c0d85edbd695f71025b39fa5d", "parents": [ "d13e5edd7284bedcf5952e1b6490e39ad843cb91" ], "author": { "name": "Axel Lin", "email": "axel.lin@gmail.com", "time": "Mon Jan 03 02:26:53 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 03 08:56:08 2011 +0000" }, "message": "ARM: 6605/1: Add missing include \"asm/memory.h\"\n\nThis patch fixes below build error by adding the missing asm/memory.h,\nwhich is needed for arch_is_coherent().\n\n$ make pxa3xx_defconfig; make\n CC init/do_mounts_rd.o\nIn file included from include/linux/list_bl.h:5,\n from include/linux/rculist_bl.h:7,\n from include/linux/dcache.h:7,\n from include/linux/fs.h:381,\n from init/do_mounts_rd.c:3:\ninclude/linux/bit_spinlock.h: In function \u0027bit_spin_unlock\u0027:\ninclude/linux/bit_spinlock.h:61: error: implicit declaration of function \u0027arch_is_coherent\u0027\nmake[1]: *** [init/do_mounts_rd.o] Error 1\nmake: *** [init] Error 2\n\nSigned-off-by: Axel Lin \u003caxel.lin@gmail.com\u003e\nAcked-by: Peter Huewe \u003cpeterhuewe@gmx.de\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "3d29005ab8d828e36108ecc2338612ce3acdd86f", "tree": "cadf8dcc7207039f3d6a372eef74bdc466eaad3e", "parents": [ "67cfa23ac9df810d1fbf3a06b7f408243350ecfe" ], "author": { "name": "Shiraz Hashim", "email": "shiraz.hashim@st.com", "time": "Thu Dec 23 11:32:41 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Dec 24 09:51:43 2010 +0000" }, "message": "ARM: 6541/1: move sev definition to common system.h include file\n\nsev is used to send wakeup event to other cores in ARMv6K and above.\nThis has been moved from platform specific part to standard common\nARM header file (asm/system.h). Also introduced wfi() and wfe().\n\nSigned-off-by: Shiraz Hashim \u003cshiraz.hashim@st.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "dec12e62c03d26bbc7a142f067215a3a43cce7d0", "tree": "e83d19c45b487ad17ceb43c743aad2ed5701be8d", "parents": [ "8ff1443c5439ecee7472b80cf12ecfc337e6ee98" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Dec 16 13:49:34 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Dec 24 09:49:52 2010 +0000" }, "message": "ARM: provide an early platform initialization hook\n\nThis allows platforms to hook into the initialization early to setup\nthings like scheduler clocks, etc.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "8ff1443c5439ecee7472b80cf12ecfc337e6ee98", "tree": "b6899444bc0b66a016d29271c5d70e8ad43db5ca", "parents": [ "cd544ce754ac2432ffcc0626ea802d2b30876b50" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 10:18:36 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Dec 24 09:49:51 2010 +0000" }, "message": "ARM: simplify early machine init hooks\n\nRather than storing each machine init hook separately, store a\npointer to the machine description record and dereference this\ninstead. This pointer is only available while the init sections\nare present, which is not a problem as we only use it from init\ncode.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "cd544ce754ac2432ffcc0626ea802d2b30876b50", "tree": "c1c678191e34ffb3c5bae173579191992ae530aa", "parents": [ "521086412ee423fbdfc7da81f257239c43f707b4" ], "author": { "name": "Magnus Damm", "email": "damm@opensource.se", "time": "Wed Dec 22 13:20:08 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Dec 24 09:47:36 2010 +0000" }, "message": "ARM: 6538/1: Subarch IRQ handler macros V3\n\nPer subarch interrupt handler macros V3.\n\nThis patch breaks out code from the irq_handler macro\ninto arch_irq_handler and arch_irq_handler_default.\n\nThe macros are put in the header file \"entry-macro-multi.S\"\n\nThe arch_irq_handler_default macro is designed to be\nused by irq_handler in entry-armv.S while arch_irq_handler\nis suitable for per-subarch use.\n\nSigned-off-by: Magnus Damm \u003cdamm@opensource.se\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "521086412ee423fbdfc7da81f257239c43f707b4", "tree": "88423e6db9544002ebec1494b82a3d91bfb57363", "parents": [ "4a50bfe365a977f634311504484342fbfffe855c" ], "author": { "name": "eric miao", "email": "eric.y.miao@gmail.com", "time": "Mon Dec 13 09:42:34 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Dec 24 09:47:34 2010 +0000" }, "message": "ARM: 6532/1: Allow machine to specify it\u0027s own IRQ handlers at run-time\n\nNormally different ARM platform has different way to decode the IRQ\nhardware status and demultiplex to the corresponding IRQ handler.\nThis is highly optimized by macro irq_handler in entry-armv.S, and\neach machine defines their own macro to decode the IRQ number.\nHowever, this prevents multiple machine classes to be built into a\nsingle kernel.\n\nBy allowing each machine to specify thier own handler, and making\nfunction pointer \u0027handle_arch_irq\u0027 to point to it at run time, this\ncan be solved. And introduce CONFIG_MULTI_IRQ_HANDLER to allow both\nsolutions to work.\n\nComparing with the highly optimized macro of irq_handler, the new\nfunction must be written with care not to lose too much performance.\nAnd the IPI stuff on SMP is expected to move to the provided arch\nIRQ handler as well.\n\nThe assembly code to invoke handle_arch_irq is optimized by Russell\nKing.\n\nSigned-off-by: Eric Miao \u003ceric.miao@canonical.com\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "537de3a67c0c86586eacffde40673b727242dc3a", "tree": "9de7b257fab75348a13e24a704935f95b732f00f", "parents": [ "09c85a440d113a8e6f32bc616423d7684970c37c" ], "author": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Wed Dec 22 04:52:05 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Dec 24 09:37:58 2010 +0000" }, "message": "ARM: 6536/1: Add missing SZ_{32,64,128}\n\n... and also remove misleading comment stating that this header is\nauto-generated.\n\nSigned-off-by: Stephen Warren \u003cswarren@nvidia.com\u003e\nAcked-by: Uwe Kleine-Knig \u003cu.kleine-koenig@pengutronix.de\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "112f38a4a31668eb6a7d91d128296a26afdf7c4b", "tree": "9f5ce228978cf13c9e23a4762b062733ff0cbcd5", "parents": [ "b5776c4a6d0afc13697e8452b9ebe1cc4d961b74" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 15 19:23:07 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 22 22:44:43 2010 +0000" }, "message": "ARM: sched_clock: provide common infrastructure for sched_clock()\n\nProvide common sched_clock() infrastructure for platforms to use to\ncreate a 64-bit ns based sched_clock() implementation from a counter\nrunning at a non-variable clock rate.\n\nThis implementation is based upon maintaining an epoch for the counter\nand an epoch for the nanosecond time. When we desire a sched_clock()\ntime, we calculate the number of counter ticks since the last epoch\nupdate, convert this to nanoseconds and add to the epoch nanoseconds.\n\nWe regularly refresh these epochs within the counter wrap interval.\nWe perform a similar calculation as above, and store the new epochs.\n\nWe read and write the epochs in such a way that sched_clock() can easily\n(and locklessly) detect when an update is in progress, and repeat the\nloading of these constants when they\u0027re known not to be stable. The\none caveat is that sched_clock() is not called in the middle of an\nupdate. We achieve that by disabling IRQs.\n\nFinally, if the clock rate is known at compile time, the counter to ns\nconversion factors can be specified, allowing sched_clock() to be tightly\noptimized. We ensure that these factors are correct by providing an\ninitialization function which performs a run-time check.\n\nAcked-by: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nTested-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nTested-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nTested-by: Mikael Pettersson \u003cmikpe@it.uu.se\u003e\nTested-by: Eric Miao \u003ceric.y.miao@gmail.com\u003e\nTested-by: Olof Johansson \u003colof@lixom.net\u003e\nTested-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "36bb94ba36f332de767cfaa3af6a5136435a3a9c", "tree": "45d1bd890b58658f4db58a033e619e511e3368f4", "parents": [ "9522d7e4cb5e0858122fc55d33a2c07728f0b10d" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Nov 16 08:40:36 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 22 11:05:35 2010 +0000" }, "message": "ARM: pgtable: provide RDONLY page table bit rather than WRITE bit\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9522d7e4cb5e0858122fc55d33a2c07728f0b10d", "tree": "49438ddcd5217da82cf9ebe79dda8577bc346456", "parents": [ "e926f4495e202500a6265987277fab217e235f08" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Nov 16 00:23:31 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 22 11:05:35 2010 +0000" }, "message": "ARM: pgtable: invert L_PTE_EXEC to L_PTE_XN\n\nThe hardware page tables use an XN bit \u0027execute never\u0027. Historically,\nwe\u0027ve had a Linux \u0027execute allow\u0027 bit, in the positive sense. Get rid\nof this artifact as future hardware will continue to have the XN sense.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "e926f4495e202500a6265987277fab217e235f08", "tree": "7ca0dc4c6976f1f1aba503a7cc29a13eb7c6b7cb", "parents": [ "af3813d6a5bf8d0f71b23d3ce458fa5f9916c6b7" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Nov 21 11:55:37 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 22 11:05:34 2010 +0000" }, "message": "ARM: pgtable: remove FIRST_USER_PGD_NR\n\nFIRST_USER_PGD_NR is now unnecessary, as this has been replaced by\nFIRST_USER_ADDRESS except in the architecture code. Fix up the last\nusage of FIRST_USER_PGD_NR, and remove the definition.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "614dd0585f376a25c638abbed9c5fbd21d7baece", "tree": "9bd2c8bb3523632901e3ddc3f9b1eba24e7671ab", "parents": [ "26bbf0b57a0848932f725076bcb1245ca696e8d3" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Nov 21 11:41:57 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 22 11:05:33 2010 +0000" }, "message": "ARM: pgtable: collect up identity mapping functions\n\nWe have two places where we create identity mappings - one when we bring\nsecondary CPUs online, and one where we setup some mappings for soft-\nreboot. Combine these two into a single implementation. Also collect\nthe identity mapping deletion function.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d30e45eeabefadc6039d7f876a59e5f5f6cb11c6", "tree": "9873141aac1042fe8b230aa525599135f5411e36", "parents": [ "f6e3354d02aa1f30672e3671098c12cb49c7da25" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Nov 16 00:16:01 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 22 11:05:32 2010 +0000" }, "message": "ARM: pgtable: switch order of Linux vs hardware page tables\n\nThis switches the ordering of the Linux vs hardware page tables in\neach page, thereby eliminating some of the arithmetic in the page\ntable walks. As we now place the Linux page table at the beginning\nof the page, we can deal with the offset in the pgt by simply masking\nit away, along with the other control bits.\n\nThis also makes the arithmetic all be positive, rather than a mixture.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "4584acc3ee236424b5d0b52f143d980cae3c2be5", "tree": "bc085d6c81a5ee5e721bfe90d84487156c2b5944", "parents": [ "f0c61d3d3c319def8feebb99682ae0223a41dffe", "c7d3e9e801d72e86eb8a0f311453192a84f14412", "b89cd71a159b5edca4c429687e4af01708eb1b26" ], "author": { "name": "Tony Lindgren", "email": "tony@atomide.com", "time": "Mon Dec 20 19:13:40 2010 -0800" }, "committer": { "name": "Tony Lindgren", "email": "tony@atomide.com", "time": "Mon Dec 20 19:13:40 2010 -0800" }, "message": "Merge branches \u0027devel-iommu-mailbox\u0027 and \u0027devel-l2x0\u0027 into omap-for-linus\n" }, { "commit": "10034aabca9032246762daaca3152f3e79380ea0", "tree": "32c0143b054ab6c5beeeb9726eaf86b87f2abd80", "parents": [ "e3d9c625f5e4158014e041f492b46e38ad10987e" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 14:28:02 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 15:09:16 2010 +0000" }, "message": "ARM: localtimer: clean up local timer on hot unplug\n\nWhen a CPU is hot unplugged, the generic tick code cleans up the\nclock event device, but fails to call down to the device\u0027s set_mode\nfunction to actually shut the device down.\n\nTo work around this, we\u0027ve historically had a local_timer_stop()\ncallback out of the hotplug code. However, this adds needless\ncomplexity when we have the clock event device itself available.\n\nExplicitly call the clock event device\u0027s set_mode function with\nCLOCK_EVT_MODE_UNUSED, so that the hardware can be cleanly shutdown\nwithout any special external callbacks. When/if the generic code\nis fixed, percpu_timer_stop() can be killed off.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ed3768a8d9dc2d345d4f27eb44ee1e4825056c08", "tree": "7ca8b45e83fa1eac70b285898e41332b28fe1626", "parents": [ "86e62b93368cffca9111996e3ed9e5b7bf6f0af3" ], "author": { "name": "Dave Martin", "email": "dave.martin@linaro.org", "time": "Wed Dec 01 15:39:23 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 15:09:12 2010 +0000" }, "message": "ARM: 6516/1: Allow SMP_ON_UP to work with Thumb-2 kernels.\n\n * __fixup_smp_on_up has been modified with support for the\n THUMB2_KERNEL case. For THUMB2_KERNEL only, fixups are split\n into halfwords in case of misalignment, since we can\u0027t rely on\n unaligned accesses working before turning the MMU on.\n\n No attempt is made to optimise the aligned case, since the\n number of fixups is typically small, and it seems best to keep\n the code as simple as possible.\n\n * Add a rotate in the fixup_smp code in order to support\n CPU_BIG_ENDIAN, as suggested by Nicolas Pitre.\n\n * Add an assembly-time sanity-check to ALT_UP() to ensure that\n the content really is the right size (4 bytes).\n\n (No check is done for ALT_SMP(). Possibly, this could be fixed\n by splitting the two uses ot ALT_SMP() (ALT_SMP...SMP_UP versus\n ALT_SMP...SMP_UP_B) into two macros. In the first case,\n ALT_SMP needs to expand to \u003e\u003d 4 bytes, not \u003d\u003d 4.)\n\n * smp_mpidr.h (which implements ALT_SMP()/ALT_UP() manually due\n to macro limitations) has not been modified: the affected\n instruction (mov) has no 16-bit encoding, so the correct\n instruction size is satisfied in this case.\n\n * A \"mode\" parameter has been added to smp_dmb:\n\n smp_dmb arm @ assumes 4-byte instructions (for ARM code, e.g. kuser)\n smp_dmb @ uses W() to ensure 4-byte instructions for ALT_SMP()\n\n This avoids assembly failures due to use of W() inside smp_dmb,\n when assembling pure-ARM code in the vectors page.\n\n There might be a better way to achieve this.\n\n * Kconfig: make SMP_ON_UP depend on\n (!THUMB2_KERNEL || !BIG_ENDIAN) i.e., THUMB2_KERNEL is now\n supported, but only if !BIG_ENDIAN (The fixup code for Thumb-2\n currently assumes little-endian order.)\n\nTested using a single generic realview kernel on:\n\tARM RealView PB-A8 (CONFIG_THUMB2_KERNEL\u003d{n,y})\n\tARM RealView PBX-A9 (SMP)\n\nSigned-off-by: Dave Martin \u003cdave.martin@linaro.org\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "86e62b93368cffca9111996e3ed9e5b7bf6f0af3", "tree": "554af0b864da59ddfe1bb49c88263f965ca32b59", "parents": [ "f36d340122ae8744e64af0a92a6f77b97542c0a4" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Nov 30 18:24:57 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 15:09:11 2010 +0000" }, "message": "ARM: SMP: remove smp_mpidr.h\n\nWith \"ARM: CPU hotplug: remove bug checks in platform_cpu_die()\", we\nnow do not use hard_smp_processor_id(), we no longer need to read the\nhardware processor ID. Remove the include providing this function.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "05c74a6cbcfb416286a947668ba32f63d99fe74a", "tree": "96f4dd3d5cbc67b14b93e9630f4f02becaa1a66a", "parents": [ "aec66ba1f75c2030cf66f5a21d1c81aa83aa5d95" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Dec 03 11:09:48 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 15:09:08 2010 +0000" }, "message": "ARM: SMP: consolidate the common parts of smp_prepare_cpus()\n\nThere is a certain amount of smp_prepare_cpus() which doesn\u0027t belong\nin the platform support code - that is, code which is invariant to the\nSMP implementation. Move this code into arch/arm/kernel/smp.c, and\nadd a platform_ prefix to the original function.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b54992fe1b4bad7b7488d58b8696e4e8974fdab0", "tree": "42c87b7a7f04627c841467ca65cf4e90f87ce2e2", "parents": [ "4a88abd7b48e8ec8084b1252d0f5ebdab43c2508" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Nov 15 14:46:46 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 15:08:01 2010 +0000" }, "message": "ARM: SMP: collect IPI and local timer IRQs for /proc/stat\n\nThe IPI and local timer interrupts weren\u0027t being properly accounted\nfor in /proc/stat. Collect them from the irq_stat structure, and\nreturn their sum.\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "4a88abd7b48e8ec8084b1252d0f5ebdab43c2508", "tree": "6f2bd56428c4a684c1bd4a06767e78128977c492", "parents": [ "f13cd4170ee789f63b3c9585c1ae34e028bd549d" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Nov 15 14:40:29 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 15:08:01 2010 +0000" }, "message": "ARM: SMP: provide individual IPI interrupt statistics\n\nThis separates out the individual IPI interrupt counts from the\ntotal IPI count, which allows better visibility of what IPIs are\nbeing used for.\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f13cd4170ee789f63b3c9585c1ae34e028bd549d", "tree": "5304bd2cec241d635a13f3d588e80bbc17997d5b", "parents": [ "cab8c6f3053c1b147bba825844c8e208f8b3b9f4" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Nov 15 14:33:51 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 15:07:32 2010 +0000" }, "message": "ARM: fix /proc/interrupts formatting\n\nAs per x86, align the initial column according to how many IRQs we\nhave. Also, provide an english explaination for the \u0027LOC:\u0027 and\n\u0027IPI:\u0027 lines.\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "cab8c6f3053c1b147bba825844c8e208f8b3b9f4", "tree": "ee11484788efc820b48f2348ec72df6e8356b7b5", "parents": [ "46c48f222f568decb881a552caa1c8f9c96c521e" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Nov 15 14:20:41 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 15:06:58 2010 +0000" }, "message": "ARM: SMP: move ipi_count into irq_stat structure\n\nMove the ipi_count into irq_stat, which allows the ipi_data structure\nto be entirely removed.\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "46c48f222f568decb881a552caa1c8f9c96c521e", "tree": "d84e79cfc44af8d99eb23e2aebee376feb55ef8a", "parents": [ "ec405ea9fe5fdeb40824edba7082803b3e98f176" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Nov 15 14:15:03 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 15:06:58 2010 +0000" }, "message": "ARM: SMP: provide accessors for irq_stat data\n\nProvide __inc_irq_stat() and __get_irq_stat() to increment and\nread the irq stat counters.\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ec405ea9fe5fdeb40824edba7082803b3e98f176", "tree": "62903c7d594e682d58aef61c84f9a16c1d327d95", "parents": [ "e3fbb087650df130788d8e3ac29875ee56819249" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Nov 15 13:38:06 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 15:06:57 2010 +0000" }, "message": "ARM: include local timer irq stats only when local timers configured\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "39af22a79232373764904576f31572f1db76af10", "tree": "20d31ab6a01b93dabe9c05277bcb1413e978648b", "parents": [ "b0c3844d8af6b9f3f18f31e1b0502fbefa2166be" ], "author": { "name": "Nicolas Pitre", "email": "nicolas.pitre@linaro.org", "time": "Wed Dec 15 15:14:45 2010 -0500" }, "committer": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Sun Dec 19 12:56:46 2010 -0500" }, "message": "ARM: get rid of kmap_high_l1_vipt()\n\nSince commit 3e4d3af501 \"mm: stack based kmap_atomic()\", it is no longer\nnecessary to carry an ad hoc version of kmap_atomic() added in commit\n7e5a69e83b \"ARM: 6007/1: fix highmem with VIPT cache and DMA\" to cope\nwith reentrancy.\n\nIn fact, it is now actively wrong to rely on fixed kmap type indices\n(namely KM_L1_CACHE) as kmap_atomic() totally ignores them now and a\nconcurrent instance of it may reuse any slot for any purpose.\n\nSigned-off-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "0aaa6f8f1da195ae1a993d3e9c80d600480cf947", "tree": "de9432838c0c7fe88cfc89c391c37929082b3eae", "parents": [ "b0c3844d8af6b9f3f18f31e1b0502fbefa2166be" ], "author": { "name": "Santosh Shilimkar", "email": "santosh.shilimkar@ti.com", "time": "Fri Nov 19 23:01:02 2010 +0530" }, "committer": { "name": "Tony Lindgren", "email": "tony@atomide.com", "time": "Sat Dec 18 09:30:15 2010 -0800" }, "message": "ARM: l2x0: Add aux control register bitfields\n\nThis patch adds the PL310 Auxiliary Control Register bitfields\nso that SOC\u0027s can use these bit fields to construct the AUXCTRL\nvalue to be passed/programmed instead of hardcoding it.\n\nSigned-off-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Tony Lindgren \u003ctony@atomide.com\u003e\n" }, { "commit": "2f841ed13b9f10037e25ddf417d01700ecd886d0", "tree": "123448d98b3be03ac90fbb6e32f224235063c8bf", "parents": [ "961ec6daa7b14f376c30d447a830fa4783a2112c", "8fbf397c3389c1dedfa9ee412715046ab28fd82d" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 18 14:27:55 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 18 14:27:55 2010 +0000" }, "message": "Merge branch \u0027hw-breakpoint\u0027 of git://repo.or.cz/linux-2.6/linux-wd into devel-stable\n" }, { "commit": "ac61d143ffe2a6db4d4bcf47c21a5159d6a1b644", "tree": "a0a5f36bc862c2163d4cc37333f46eb0257b3140", "parents": [ "7627dc802a98aebebc6a34e5b6558ea4717c968c" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 06 10:38:14 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Dec 14 19:21:52 2010 +0000" }, "message": "ARM: GIC: move enablement of PPI interrupts to gic.c\n\nAvoid adding nasty genirq-specific code to local timers to enable PPI\ninterrupts. Instead, provide a gic function to do this.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7627dc802a98aebebc6a34e5b6558ea4717c968c", "tree": "f1308e351f6f003a52b5939b7eece82f14a12c62", "parents": [ "bef8f9ee32511a28f1c9a7d3b8c51cdac030b564" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Dec 05 08:51:38 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Dec 14 19:21:47 2010 +0000" }, "message": "ARM: GIC: private a standard get_irqnr_preamble assembler macro\n\nProvide a standard get_irqnr_preamble assembler macro for platforms\nto use, which retrieves the base address of the GIC CPU interface\nfrom gic_cpu_base_addr. Allow platforms to override this by defining\nHAVE_GET_IRQNR_PREAMBLE.\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nTested-by: Abhijeet Dharmapurikar \u003cadharmap@codeaurora.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ff2e27ae0b17f53a6a289c87d325f706598f3788", "tree": "1288f491bce11b3d8a6d48604fd00d68bea6eb98", "parents": [ "384895330e0f3954d9478fd0853145f9c169df12" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 04 16:13:29 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Dec 14 19:21:42 2010 +0000" }, "message": "ARM: GIC: consolidate gic_cpu_base_addr to common GIC code\n\nEvery architecture using the GIC has a gic_cpu_base_addr pointer for\nGIC 0 for their entry assembly code to use to decode the cause of the\ncurrent interrupt. Move this into the common GIC code.\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nTested-by: Abhijeet Dharmapurikar \u003cadharmap@codeaurora.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "384895330e0f3954d9478fd0853145f9c169df12", "tree": "c90f70f4e070b640a1f1f2a76cf4acf864354093", "parents": [ "b580b899dd05a007ad232ee49a07b32d91876462" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 04 16:01:03 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Dec 14 19:21:40 2010 +0000" }, "message": "ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init\n\nWe don\u0027t need to re-pass the base address for the CPU interfaces to the\nGIC for secondary CPUs, as it will never be different from the boot CPU\n- and even if it was, we\u0027d overwrite the boot CPU\u0027s base address.\n\nGet rid of this argument, and rename to gic_secondary_init().\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nTested-by: Abhijeet Dharmapurikar \u003cadharmap@codeaurora.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b580b899dd05a007ad232ee49a07b32d91876462", "tree": "72def6f195ca02a5f9eb5e082930603b85349b0e", "parents": [ "e745a6676c76280f9721adeec79b08a0f2dfcc21" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 04 15:55:14 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Dec 14 19:21:30 2010 +0000" }, "message": "ARM: GIC: provide a single initialization function for boot CPU\n\nProvide gic_init() which initializes the GIC distributor and current\nCPU\u0027s GIC interface for the boot (or single) CPU.\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nTested-by: Abhijeet Dharmapurikar \u003cadharmap@codeaurora.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "28257f7fdee0facc3b7f934e82c2485f27120d41", "tree": "6b018506ca7fe825619f36f52922d83baf1bfde4", "parents": [ "a0b7bd0829194c03921915a68ee4a331ee394223" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 08 13:57:48 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 08 13:58:24 2010 +0000" }, "message": "ARM: io: simplify ioremap* and iounmap definitions\n\nWe don\u0027t need to repeat the same definitions of the ioremap*(),\nonce in terms of __arch_ioremap() and again in terms of __arm_ioremap().\nInstead, if the platform hasn\u0027t provided an __arch_ioremap, define\nthis to be __arm_ioremap, and only define the ioremap*() set using\n__arch_ioremap.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a0b7bd0829194c03921915a68ee4a331ee394223", "tree": "0d7a3dddfa6018ae1230b6082041a93ed21eb1b4", "parents": [ "cf7d7e5a1980d1116ee152d25dac382b112b9c17" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 08 13:49:04 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 08 13:57:04 2010 +0000" }, "message": "ARM: io: make iounmap() a simple macro\n\nDefining iounmap() with arguments prevents it from being used as a\nfunction pointer, causing platforms to work around this. Instead,\ndefine it to be a simple macro.\n\nDo the same for __arch_io(re|un)map too.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "161d1907607a5a562a152058c8daf1780ce7a00b", "tree": "0166cebedcd66a0f34c1d7cfcb51106add5b1019", "parents": [ "cf7d7e5a1980d1116ee152d25dac382b112b9c17" ], "author": { "name": "Magnus Damm", "email": "magnus.damm@gmail.com", "time": "Tue Nov 16 00:48:07 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Dec 07 09:20:24 2010 +0000" }, "message": "ARM: 6475/1: Introduce asm/hardware/entry-macro-gic.S\n\nThis patch is the identical GIC demux implementation\nmerge V3. Instead of implementing same code over and\nover simply share it in entry-macro-gic.S. The shared\ncode is based on the realview implementation.\n\nEach GIC demux instance still has to setup the base address\nof the controller using the get_irqnr_preamble macro. The\nrest of the GIC specific code can be shared.\n\nSigned-off-by: Magnus Damm \u003cdamm@opensource.se\u003e\nAcked-by: Srinidhi Kasagar \u003csrinidhi.kasagar@stericsson.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9ebb3cbcc39d4e61ae6751167086acfb5c201e6f", "tree": "4e88970d75cb2e7b3a5a2f1b50c58ab358d30339", "parents": [ "93a04a3416da12647c47840ebe2bb812fcb801d0" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Dec 01 14:12:13 2010 +0000" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Mon Dec 06 11:55:57 2010 +0000" }, "message": "ARM: hw_breakpoint: unify single-stepping code for watchpoints and breakpoints\n\nThe single-stepping code is currently different depending on whether\nwe are stepping over a breakpoint or a watchpoint. There is no good\nreason for this, so let\u0027s sort it out.\n\nThis patch adds functions for enabling/disabling single-step for\na particular hw_breakpoint and integrates this with the exception\nhandling code.\n\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "93a04a3416da12647c47840ebe2bb812fcb801d0", "tree": "bee210af11e5a3c4d7ff33f50916819b2190ea81", "parents": [ "0017ff42ac37ff6aeb87d0b006c5d32b9a39f5fc" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Mon Nov 29 16:56:01 2010 +0000" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Mon Dec 06 11:55:57 2010 +0000" }, "message": "ARM: hw_breakpoint: do not allocate new breakpoints with preemption disabled\n\nThe watchpoint single-stepping code calls register_user_hw_breakpoint to\nregister a mismatch breakpoint for stepping over the watchpoint. This is\nperformed with preemption disabled, which is unsafe as we may end up scheduling\nwhilst in_atomic(). Furthermore, using the perf API is rather overkill since\nwe are already in the hw-breakpoint backend and only require access to reserved\nbreakpoints anyway.\n\nThis patch reworks the watchpoint stepping code so that we don\u0027t require\nanother perf_event for the mismatch breakpoint. Instead, we hold a separate\narch_hw_breakpoint_ctrl struct inside the watchpoint which is used exclusively\nfor stepping. We can check whether or not stepping is enabled when installing\nor uninstalling the watchpoint and operate on the breakpoint accordingly.\n\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" } ], "next": "daf8741675562197d4fb4c4e9d773f53494203a5" }