)]}' { "log": [ { "commit": "c9f2946fbec88d4baa3a6d47eb3a8e6b08b05cd9", "tree": "2b18303a2a69cf0c9d0224daebda5e5fc34308d8", "parents": [ "1241140f5183db38393556832198a3b109bf9085" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Apr 30 22:54:27 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Apr 30 22:54:27 2006 -0700" }, "message": "[SPARC64]: Disable preemption during flush_tlb_pending().\n\nA context switch will force a call to flush_tlb_pending() (via\nswitch_to()), so if we test tlb_nr to be non-zero, then sleep, it\nwould become zero and later back at the original context we\u0027ll pass\nzero down into the TLB flushing code which should never see a nr\nargument of zero.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9df1dab1df58ef20ef7df9b8f39d86cf5d2d1949", "tree": "7f697e5cc595c906b4779f8301ef3eb58cfea728", "parents": [ "73c50a27a453a5ed0d21ff23bd67c1dd6d864cb8" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Mar 31 00:36:25 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Mar 31 23:03:36 2006 -0800" }, "message": "[SPARC64]: Align address in huge_pte_alloc().\n\nWe are about to fill in all HPAGE_SIZE\u0027s worth\nof PAGE_SIZE ptes, so we have to give the first\npte in that set else we scribble over random memory\nwhen we fill in the ptes.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "73c50a27a453a5ed0d21ff23bd67c1dd6d864cb8", "tree": "7a9857e2ed5dee8e334efadd16c5939650f757be", "parents": [ "6f25f3986af0353b0bdc220f79b89c997d0ceda4" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Mar 28 13:32:24 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Mar 31 23:03:35 2006 -0800" }, "message": "[SPARC64]: Document the instruction checks we do in do_sparc64_fault().\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7bebd83dbf096d0bf4b4bfbaf5d8844a05f5eafc", "tree": "ea583040c5d9fbd8d72e7b9bfa831c9f7b553a5e", "parents": [ "5d5d7727a8cde78f798ecf04bac8031eff536f9d" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 27 01:07:55 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 27 01:07:55 2006 -0800" }, "message": "[SPARC64]: Fix off-by-1 error in TSB grow check.\n\nThe worst part about this bug is what it would cause\na hugepage TSB to be allocated for every address space\nsince \"0 \u003e\u003d 0\".\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "fcab1e51796d8bcd1a7969ff52bd904d38748e00", "tree": "ed2429321d8d12e9ec93fa2c0aec31fdc3d7b267", "parents": [ "2e6e33bab6e1996a5dec9108fb467b52b841e7a8" ], "author": { "name": "Nick Piggin", "email": "npiggin@suse.de", "time": "Thu Mar 23 07:48:16 2006 +0100" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Thu Mar 23 07:15:21 2006 -0800" }, "message": "[PATCH] sparc64: fix set_page_count merge clash\n\nMerge clash will have broken sparc64. Synch up its online_page\nimplementation with powerpc, which was identical until the\nset_page_count removal.\n\nSigned-off-by: Nick Piggin \u003cnpiggin@suse.de\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "d04ef3a795b3b7b376a02713ed5e211e9ae1f917", "tree": "837da034751a2fc1be0fc5a105c218d41a498eb6", "parents": [ "36177ba655c238e33400cc2837a28720b62784bd", "dcc1e8dd88d4bc55e32a26dad7633d20ffe606d2" ], "author": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 22 10:56:57 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 22 10:56:57 2006 -0800" }, "message": "Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6\n\n* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6:\n [SPARC64]: Add a secondary TSB for hugepage mappings.\n [SPARC]: Respect vm_page_prot in io_remap_page_range().\n" }, { "commit": "42b88befd6e0dae1a5fe04c03925037fa890e1f3", "tree": "c234584f797e65e1bcd0d4675d56d1eb004d6681", "parents": [ "3915bcf38fe0b6d130b4bbde97804f29a0becf32" ], "author": { "name": "David Gibson", "email": "david@gibson.dropbear.id.au", "time": "Wed Mar 22 00:09:01 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 22 07:54:04 2006 -0800" }, "message": "[PATCH] hugepage: is_aligned_hugepage_range() cleanup\n\nQuite a long time back, prepare_hugepage_range() replaced\nis_aligned_hugepage_range() as the callback from mm/mmap.c to arch code to\nverify if an address range is suitable for a hugepage mapping.\nis_aligned_hugepage_range() stuck around, but only to implement\nprepare_hugepage_range() on archs which didn\u0027t implement their own.\n\nMost archs (everything except ia64 and powerpc) used the same\nimplementation of is_aligned_hugepage_range(). On powerpc, which\nimplements its own prepare_hugepage_range(), the custom version was never\nused.\n\nIn addition, \"is_aligned_hugepage_range()\" was a bad name, because it\nsuggests it returns true iff the given range is a good hugepage range,\nwhereas in fact it returns 0-or-error (so the sense is reversed).\n\nThis patch cleans up by abolishing is_aligned_hugepage_range(). Instead\nprepare_hugepage_range() is defined directly. Most archs use the default\nversion, which simply checks the given region is aligned to the size of a\nhugepage. ia64 and powerpc define custom versions. The ia64 one simply\nchecks that the range is in the correct address space region in addition to\nbeing suitably aligned. The powerpc version (just as previously) checks\nfor suitable addresses, and if necessary performs low-level MMU frobbing to\nset up new areas for use by hugepages.\n\nNo libhugetlbfs testsuite regressions on ppc64 (POWER5 LPAR).\n\nSigned-off-by: David Gibson \u003cdavid@gibson.dropbear.id.au\u003e\nSigned-off-by: Zhang Yanmin \u003cyanmin.zhang@intel.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Paul Mackerras \u003cpaulus@samba.org\u003e\nCc: William Lee Irwin III \u003cwli@holomorphy.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "7835e98b2e3c66dba79cb0ff8ebb90a2fe030c29", "tree": "405a96eade34845dabe2f125b6c5eb095846869d", "parents": [ "70dc991d66cac40fdb07346dba2b5d862d732c34" ], "author": { "name": "Nick Piggin", "email": "npiggin@suse.de", "time": "Wed Mar 22 00:08:40 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 22 07:54:02 2006 -0800" }, "message": "[PATCH] remove set_page_count() outside mm/\n\nset_page_count usage outside mm/ is limited to setting the refcount to 1.\nRemove set_page_count from outside mm/, and replace those users with\ninit_page_count() and set_page_refcounted().\n\nThis allows more debug checking, and tighter control on how code is allowed\nto play around with page-\u003e_count.\n\nSigned-off-by: Nick Piggin \u003cnpiggin@suse.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "dcc1e8dd88d4bc55e32a26dad7633d20ffe606d2", "tree": "a47592213d94f918867d3dd81bb91dac3e727dea", "parents": [ "14778d9072e53d2171f66ffd9657daff41acfaed" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Mar 22 00:49:59 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Mar 22 01:15:14 2006 -0800" }, "message": "[SPARC64]: Add a secondary TSB for hugepage mappings.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "14778d9072e53d2171f66ffd9657daff41acfaed", "tree": "3b60565ec1e957800fc3bf4743497202a24f8279", "parents": [ "e952f31bce6e9f64db01f607abc46529ba57ac9e" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Mar 21 02:29:39 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Mar 22 01:15:13 2006 -0800" }, "message": "[SPARC]: Respect vm_page_prot in io_remap_page_range().\n\nMake sure the callers do a pgprot_noncached() on\nvma-\u003evm_page_prot.\n\nPointed out by Hugh Dickens.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "f6b83f070e9b7ad9075f7cc5646260e56c7d0219", "tree": "48586ca4f4c75ee3862f63be332351e78f2d5476", "parents": [ "467418f3508b426adbc7df795ebf3baaed4fbefc" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Mar 20 01:17:17 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Mar 20 01:17:17 2006 -0800" }, "message": "[SPARC64]: Fix 2 bugs in huge page support.\n\n1) huge_pte_offset() did not check the page table hierarchy\n elements as being empty correctly, resulting in an OOPS\n\n2) Need platform specific hugetlb_get_unmapped_area() to handle\n the top-down vs. bottom-up address space allocation strategies.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "bb8646d8340fa7c1b66a037428e39f85f8738f0a", "tree": "931d4505a0ba65124b662f0f8b5935e0b154bd66", "parents": [ "88d7079458f87d6f2d2261b2f87b7b9416019f5e" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Mar 18 23:55:11 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:16:41 2006 -0800" }, "message": "[SPARC64]: Optimized TSB table initialization.\n\nWe only need to write an invalid tag every 16 bytes,\nso taking advantage of this can save many instructions\ncompared to the simple memset() call we make now.\n\nA prefetching implementation is implemented for sun4u\nand a block-init store version if implemented for Niagara.\n\nThe next trick is to be able to perform an init and\na copy_tsb() in parallel when growing a TSB table.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "88d7079458f87d6f2d2261b2f87b7b9416019f5e", "tree": "7e27074dcb05a795c15ed9455134c9e676b63aff", "parents": [ "9b4006dcf6a8c43bd482b9c1ec576f0ed270ef23" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Mar 18 19:16:23 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:16:40 2006 -0800" }, "message": "[SPARC64]: Allow CONFIG_MEMORY_HOTPLUG to build.\n\nonline_page() is straightforward, and then add a dummy\nremove_memory() that returns -EINVAL just like i386.\n\nThere is no point in implementing remove_memory() since\n__remove_pages() has no implementation either.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9b4006dcf6a8c43bd482b9c1ec576f0ed270ef23", "tree": "e04ac039a49f37ee5e8eca3fd654df0649a1806c", "parents": [ "b52439c22c63dbbefd5395f2151c0ef4f667e949" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Mar 18 18:12:42 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:16:39 2006 -0800" }, "message": "[SPARC64]: Use SLAB caches for TSB tables.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b52439c22c63dbbefd5395f2151c0ef4f667e949", "tree": "ff6671cab70dfaed00cf19367a6a71b1cda0cdf4", "parents": [ "05f9ca83596c7801549a2b4eba469d51baf5480f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Mar 17 23:40:47 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:16:38 2006 -0800" }, "message": "[SPARC64]: Don\u0027t kill the page allocator when growing a TSB.\n\nTry only lightly on \u003e 1 order allocations.\n\nIf a grow fails, we are under memory pressure, so do not try\nto grow the TSB for this address space any more.\n\nIf a \u003e 0 order TSB allocation fails on a new fork, retry using\na 0 order allocation.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7a1ac5264108fc3ed22d17a3cdd76212ed1666d1", "tree": "75378a1b470afa54900f1f15a5b41966d301520d", "parents": [ "a858f1ca726edc5eb7ed39722f7966d005f1c9ca" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Mar 16 02:02:32 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:16:33 2006 -0800" }, "message": "[SPARC64]: Fix and re-enable dynamic TSB sizing.\n\nThis is good for up to %50 performance improvement of some test cases.\nThe problem has been the race conditions, and hopefully I\u0027ve plugged\nthem all up here.\n\n1) There was a serious race in switch_mm() wrt. lazy TLB\n switching to and from kernel threads.\n\n We could erroneously skip a tsb_context_switch() and thus\n use a stale TSB across a TSB grow event.\n\n There is a big comment now in that function describing\n exactly how it can happen.\n\n2) All code paths that do something with the TSB need to be\n guarded with the mm-\u003econtext.lock spinlock. This makes\n page table flushing paths properly synchronize with both\n TSB growing and TLB context changes.\n\n3) TSB growing events are moved to the end of successful fault\n processing. Previously it was in update_mmu_cache() but\n that is deadlock prone. At the end of do_sparc64_fault()\n we hold no spinlocks that could deadlock the TSB grow\n sequence. We also have dropped the address space semaphore.\n\nWhile we\u0027re here, add prefetching to the copy_tsb() routine\nand put it in assembler into the tsb.S file. This piece of\ncode is quite time critical.\n\nThere are some small negative side effects to this code which\ncan be improved upon. In particular we grab the mm-\u003econtext.lock\neven for the tsb insert done by update_mmu_cache() now and that\u0027s\na bit excessive. We can get rid of that locking, and the same\nlock taking in flush_tsb_user(), by disabling PSTATE_IE around\nthe whole operation including the capturing of the tsb pointer\nand tsb_nentries value. That would work because anyone growing\nthe TSB won\u0027t free up the old TSB until all cpus respond to the\nTSB change cross call.\n\nI\u0027m not quite so confident in that optimization to put it in\nright now, but eventually we might be able to and the description\nis here for reference.\n\nThis code seems very solid now. It passes several parallel GCC\nbootstrap builds, and our favorite \"nut cruncher\" stress test which is\na full \"make -j8192\" build of a \"make allmodconfig\" kernel. That puts\nabout 256 processes on each cpu\u0027s run queue, makes lots of process cpu\nmigrations occur, causes lots of page table and TLB flushing activity,\nincurs many context version number changes, and it swaps the machine\nreal far out to disk even though there is 16GB of ram on this test\nsystem. :-)\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "17b0e199a10184d8c5bbbd79a4cee993bb1fb257", "tree": "c5cf39d072cf908e5b03216e1e1698bf85e86877", "parents": [ "d1112018b4bc82adf5c8a9c15a08954328f023ae" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Mar 08 15:57:03 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:14:23 2006 -0800" }, "message": "[SPARC64]: Fix 32-bit truncation which broke sparsemem.\n\nThe page-\u003eflags manipulations done by the D-cache dirty\nstate tracking was broken because the constants were not\nmarked with \"UL\" to make them 64-bit, which means we were\nclobbering the upper 32-bits of page-\u003eflags all the time.\n\nThis doesn\u0027t jive well with sparsemem which stores the\nsection and indexing information in the top 32-bits of\npage-\u003eflags.\n\nThis is yet another sparc64 bug which has been with us\nforever.\n\nWhile we\u0027re here, tidy up some things in bootmem_init()\nand paginig_init():\n\n1) Pass min_low_pfn to init_bootmem_node(), it\u0027s identical\n to (phys_base \u003e\u003e PAGE_SHIFT) but we should use consistent\n with the variable names we print in CONFIG_BOOTMEM_DEBUG\n\n2) max_mapnr, although no longer used, was being set\n inaccurately, we shouldn\u0027t subtract pfn_base any more.\n\n3) All the games with phys_base in the zones_*[] arrays\n we pass to free_area_init_node() are no longer necessary.\n\nThanks to Josh Grebe and Fabbione for the bug reports\nand testing. Fix also verified locally on an SB2500\nwhich had a memory layout that triggered the same problem.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d1112018b4bc82adf5c8a9c15a08954328f023ae", "tree": "4d94ef6c153f028cfaaff711cf7d4f07aa90e9b4", "parents": [ "ee29074d3bd23848905f52c515974e0cd0219faa" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Mar 08 02:16:07 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:14:22 2006 -0800" }, "message": "[SPARC64]: Move over to sparsemem.\n\nThis has been pending for a long time, and the fact\nthat we waste a ton of ram on some configurations\nkind of pushed things over the edge.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "ee29074d3bd23848905f52c515974e0cd0219faa", "tree": "d5306446b2e26d9e45f65467b4f3b3f3b0c8494c", "parents": [ "a77754b4d0731321db266c6c60ffcd7c62757da5" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 06 22:50:44 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:14:21 2006 -0800" }, "message": "[SPARC64]: Fix new context version SMP handling.\n\nDon\u0027t piggy back the SMP receive signal code to do the\ncontext version change handling.\n\nInstead allocate another fixed PIL number for this\nasynchronous cross-call. We can\u0027t use smp_call_function()\nbecause this thing is invoked with interrupts disabled\nand a few spinlocks held.\n\nAlso, fix smp_call_function_mask() to count \"cpus\" correctly.\nThere is no guarentee that the local cpu is in the mask\nyet that is exactly what this code was assuming.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a77754b4d0731321db266c6c60ffcd7c62757da5", "tree": "37cc4c6793e2b616791d42ee840e5a007a13eccb", "parents": [ "9132983ae140a8ca81e95e081d5a4c0dd7a7f670" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 06 19:59:50 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:14:20 2006 -0800" }, "message": "[SPARC64]: Bulletproof MMU context locking.\n\n1) Always spin_lock_init() in init_context(). The caller essentially\n clears it out, or copies the mm info from the parent. In both\n cases we need to explicitly initialize the spinlock.\n\n2) Always do explicit IRQ disabling while taking mm-\u003econtext.lock\n and ctx_alloc_lock.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "f7c00338cfeef125032aa12aa8ebeacf9e117e81", "tree": "3fc55d603a0c59aa8a4db63e4acc63b26170b7cb", "parents": [ "74ae998772041b62e9ad420d602e4f7dbb182cd6" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Mar 05 22:18:50 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:14:19 2006 -0800" }, "message": "[SPARC64]: Fix loop termination in mark_kpte_bitmap()\n\nIf we were aligned, but didn\u0027t have at least 256MB left\nto process, we would loop forever.\n\nThanks to fabbione for the report and testing the fix.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "74ae998772041b62e9ad420d602e4f7dbb182cd6", "tree": "8cbeb2ff56856d357647da6ab62562bac2fe87ad", "parents": [ "3cab0c3e8636d5005041aa52224f796c3a4ef872" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Mar 05 18:26:24 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:14:18 2006 -0800" }, "message": "[SPARC64]: Simplify TSB insert checks.\n\nDon\u0027t try to avoid putting non-base page sized entries\ninto the user TSB. It actually costs us more to check\nthis than it helps.\n\nEventually we\u0027ll have a multiple TSB scheme for user\nprocesses. Once a process starts using larger pages,\nwe\u0027ll allocate and use such a TSB.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7a591cfe4efef8a232e4938d44ae6693b319f6d7", "tree": "e6fbdfb34572f768788b773e3ce186e3924ab685", "parents": [ "2a3a5f5ddbefde498e87f10924d4bf741c5bf37f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 26 19:44:50 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:14:06 2006 -0800" }, "message": "[SPARC64]: Avoid dcache-dirty page state management on sun4v.\n\nIt is totally wasted work, since we have no D-cache aliasing\nissues on sun4v.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "2a3a5f5ddbefde498e87f10924d4bf741c5bf37f", "tree": "851003d4ff0b1619766d4fab883868f2b413ed62", "parents": [ "6cc80cfab8b2ce1919ad5862a43f6b7bcf163c80" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 26 19:31:49 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:14:05 2006 -0800" }, "message": "[SPARC64]: Bulletproof hypervisor TLB flushing.\n\nCheck TLB flush hypervisor calls for errors and report them.\n\nPass HV_MMU_ALL always for now, we can add back the optimization\nto avoid the I-TLB flush later.\n\nAlways explicitly page align the virtual address arguments.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "77b838fa1ef0ab02f75afc09834c60d87b86772f", "tree": "810bce2bf584b6259bd516daa0391cf1b3487ab4", "parents": [ "a0663a79ad4faebe1db4a56e2e767b120b12333a" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 23 21:40:15 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:14:01 2006 -0800" }, "message": "[SPARC64]: destroy_context() needs to disable interrupts.\n\nget_new_mmu_context() can be invoked from interrupt context\nnow for the new SMP version wrap handling.\n\nSo disable interrupt while taking ctx_alloc_lock in destroy_context()\nso we don\u0027t deadlock.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a0663a79ad4faebe1db4a56e2e767b120b12333a", "tree": "612a53e387a6aea6116f8a1637050fa13c6d9f80", "parents": [ "074d82cf688fe2dfa7ba4a2317c56f62d13fb522" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Feb 23 14:19:28 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:14:00 2006 -0800" }, "message": "[SPARC64]: Fix TLB context allocation with SMT style shared TLBs.\n\nThe context allocation scheme we use depends upon there being a 1\u003c--\u003e1\nmapping from cpu to physical TLB for correctness. Chips like Niagara\nbreak this assumption.\n\nSo what we do is notify all cpus with a cross call when the context\nversion number changes, and if necessary this makes them allocate\na valid context for the address space they are running at the time.\n\nStress tested with make -j1024, make -j2048, and make -j4096 kernel\nbuilds on a 32-strand, 8 core, T2000 with 16GB of ram.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b2bef4424cb4522f53e34d98d3deb0916478338b", "tree": "6c019c3b9e2e99706971694ae85952ef4034bfce", "parents": [ "0f05da6d577b80eb00f15994c86e4812ae60f1b9" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 23 01:55:55 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:58 2006 -0800" }, "message": "[SPARC64]: Export _PAGE_E and _PAGE_CACHE to modules.\n\nSBUS flash driver needs it.\n\nNoticed by Fabbione.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d7744a09504d5ae84edc8289a02254e1f2102410", "tree": "be0f245ee0725f2f066bf87d17d254ce1e7279bf", "parents": [ "9cc3a1ac9a819cadff05ca37bb7f208013a22035" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Feb 21 22:31:11 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:56 2006 -0800" }, "message": "[SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.\n\nIt can map all of the linear kernel mappings with zero TSB hash\nconflicts for systems with 16GB or less ram. In such cases, on\nSUN4V, once we load up this TSB the first time with all the\nmappings, we never take a linear kernel mapping TLB miss ever\nagain, the hypervisor handles them all.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9cc3a1ac9a819cadff05ca37bb7f208013a22035", "tree": "601fa49272b540b3a3e6cc3728db27c525b73721", "parents": [ "30c91d576e9ea41c963e7f28643219bda73b0ddc" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Feb 21 20:51:13 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:55 2006 -0800" }, "message": "[SPARC64]: Make use of Niagara 256MB PTEs for kernel mappings.\n\nWe use a bitmap, one bit for every 256MB of memory. If the\nbit is set we can use a 256MB PTE for linear mappings, else\nwe have to use a 4MB PTE.\n\nSUN4V support is there, and we can very easily add support\nfor Panther cpu 256MB PTEs in the future.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "0f15952ac8641bde1045162ffd4a7b474cc318b0", "tree": "f1837150e0e1589dda97f1780e99962bf6c905af", "parents": [ "f6c1fe529217788f095f6953c2b66bec1196ad3d" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 18 12:43:16 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:36 2006 -0800" }, "message": "[SPARC64]: Export a PAGE_SHARED symbol.\n\nFor drivers/media/*, noticed by Fabbione.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "8b234274418d6d79527c4ac3a72da446ca4cb35f", "tree": "ab4ab14fa7f1cab7889ecc2339f0261253a5d0e1", "parents": [ "7adb37fe80d06cbd40de9b225b12a3a9ec40b6bb" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 17 18:01:02 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:34 2006 -0800" }, "message": "[SPARC64]: More TLB/TSB handling fixes.\n\nThe SUN4V convention with non-shared TSBs is that the context\nbit of the TAG is clear. So we have to choose an \"invalid\"\nbit and initialize new TSBs appropriately. Otherwise a zero\nTAG looks \"valid\".\n\nMake sure, for the window fixup cases, that we use the right\nglobal registers and that we don\u0027t potentially trample on\nthe live global registers in etrap/rtrap handling (%g2 and\n%g6) and that we put the missing virtual address properly\nin %g5.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "12e126ad229abc718d05600027fcd5794c1e31e5", "tree": "1c28b8685a30c290956184485a997fc398f6d4f1", "parents": [ "52845cdb3b9c4c5fe1c2e295bd14457ff8dd6bcc" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 17 14:40:30 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:31 2006 -0800" }, "message": "[SPARC64]: Check for errors in hypervisor_tlb_lock().\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3f19a84e39619053f117bd5bb9183c5bfea7db45", "tree": "f40e0b3f5e0d5600304ea7496e30a33f6e8b51de", "parents": [ "c857e3fdbc306e95fdcaad1d8f3ea6bc8e7eea99" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 17 12:03:20 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:29 2006 -0800" }, "message": "[SPARC64]: Set associativity of kernel TSB descriptor correctly.\n\nIt should be 1, not 0.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3b3ab2eb9cf07ef1bc7a676c19aab994adb41a87", "tree": "174537e596cc7b20ecb2d75770476285af725051", "parents": [ "ebd8c56c5ae154e2c6cfb7453a76a4e7265b2377" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 17 09:54:42 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:25 2006 -0800" }, "message": "[SPARC64]: Use phys tsb address in tsb_insert() in SUN4V.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "de635d833f61ce0f2ad0b3431e6a3323a1c4fed5", "tree": "76559bb18ca6fe6ac4704b394b67a0e0eed842d5", "parents": [ "1daef08a12157923d90ec7a47ead8a97e0d243cc" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 15 21:01:31 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:07 2006 -0800" }, "message": "[SPARC64]: Fix flush_tsb_user() on SUN4V.\n\nNeeds to use physical addressing just like cheetah_plus.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1daef08a12157923d90ec7a47ead8a97e0d243cc", "tree": "bb7c395350abbb35b9dfce480127a31ddeb13b2c", "parents": [ "9d29a3fafd06534ad73427fee3c968c094d05b9b" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 15 20:35:10 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:06 2006 -0800" }, "message": "[SPARC64]: Fix comment typo in __flush_tlb_kernel_range.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "bf941d6cd62aa2022f0887e25e3d02c389b0bf9b", "tree": "56c8e87668d29ab96e0d84ba6aa5a62e64d9b827", "parents": [ "6c0f402f6cc62314ef83b975f3430350dcb6055f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 13 18:07:45 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:38 2006 -0800" }, "message": "[SPARC64]: Log faulting vaddr when bogus kernel PC detected.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "cf627156c450cd5a0741b31f55181db3400d4887", "tree": "e8f44d2509f5544ee5b5d583da3e10ac99ca3629", "parents": [ "ff02e0d26f139ad95ec3a7e94f88faccaa180dff" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 12 21:10:07 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:32 2006 -0800" }, "message": "[SPARC64]: Use inline patching for critical PTE operations.\n\nThis handles the SUN4U vs SUN4V PTE layout differences\nwith near zero performance cost.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "ff02e0d26f139ad95ec3a7e94f88faccaa180dff", "tree": "7a872c9792561c77c672ba640b80134c592d93c7", "parents": [ "221b2fb818c307e1cb47e036a1671ca554d9cd0a" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 12 17:07:51 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:31 2006 -0800" }, "message": "[SPARC64]: Move PTE field definitions back into asm/pgtable.h\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c4bce90ea2069e5a87beac806de3090ab32128d5", "tree": "3983a206c8060ef65ba17945d1c9f69e68d88b3d", "parents": [ "490384e752a43aa281ed533e9de2da36df25c337" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 11 21:57:54 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:25 2006 -0800" }, "message": "[SPARC64]: Deal with PTE layout differences in SUN4V.\n\nYes, you heard it right, they changed the PTE layout for\nSUN4V. Ho hum...\n\nThis is the simple and inefficient way to support this.\nIt\u0027ll get optimized, don\u0027t worry.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "490384e752a43aa281ed533e9de2da36df25c337", "tree": "ec087a27a481b9a63aeda6703971acf4adeab19b", "parents": [ "459b6e621e0e15315c25bac47fa7113e5818d45d" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 11 14:41:18 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:23 2006 -0800" }, "message": "[SPARC64]: Register kernel TSB with hypervisor.\n\nWe do this right after we take over the trap table from OBP.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "e92b92571c85dfa1cdc56e88566134c51ae1d12b", "tree": "fdd2bda36e563ea4df9c3f24dc5a3f330d50875c", "parents": [ "02fd473bd4844befc74f7ca67cd60891e0a2d890" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 11 10:19:37 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:19 2006 -0800" }, "message": "[SPARC64]: Handle hypervisor case correctly in copy_tsb().\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "12eaa328f9fb2d3fcb5afb682c762690d05a3cd8", "tree": "cce4e68b971757010a3e0bbf035fc65a381a3cd4", "parents": [ "18397944642cbca7fcd4a109b43ed5b4652e95b9" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 10 15:39:51 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:15 2006 -0800" }, "message": "[SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.\n\nThis is where the virtual address of the fault status\narea belongs.\n\nTo set it up we don\u0027t make a hypervisor call, instead\nwe call OBP\u0027s SUNW,set-trap-table with the real address\nof the fault status area as the second argument. And\nright before that call we write the virtual address into\nASI_SCRATCHPAD vaddr 0x0.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "164c220fa3947abbada65329d168f421b461a2a7", "tree": "1a10418ccf896f1f9209c2206bedf87915b63bfd", "parents": [ "dedacf623283cb24933ec9f7d5bf539f19173cd4" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 09 22:57:21 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:14 2006 -0800" }, "message": "[SPARC64]: Fix hypervisor call arg passing.\n\nFunction goes in %o5, args go in %o0 --\u003e %o5.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "618e9ed98aed924a1fc664eb6522db4a5e927043", "tree": "08ace6185b8f9709cb22a23d329def1dae622666", "parents": [ "aa9143b9719c07fb6f1f6207790c9c5086ae07e7" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 09 17:21:53 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:06 2006 -0800" }, "message": "[SPARC64]: Hypervisor TSB context switching.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d82ace7dc4073b090a55b9740700e32b9a9ae302", "tree": "d5aa8e10664b05bbfe31eacf95e2066c03cab102", "parents": [ "1d2f1f90a1e004b0c1b8a73ed4394a93f09104b3" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 09 02:52:44 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:03 2006 -0800" }, "message": "[SPARC64]: Detect sun4v early in boot process.\n\nWe look for \"SUNW,sun4v\" in the \u0027compatible\u0027 property\nof the root OBP device tree node.\n\nProtect every %ver register access, to make sure it is\nnot touched on sun4v, as %ver is hyperprivileged there.\n\nLock kernel TLB entries using hypervisor calls instead of\ncalls into OBP.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "8b11bd12aff76e02cdc2cbc9e439bba88d281223", "tree": "903ab8830616bfbe5a821e4359f642842c8060a4", "parents": [ "481295f982b21b1dbe71cbf41d3a93028fee30d1" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 22:13:05 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:56 2006 -0800" }, "message": "[SPARC64]: Patch up mmu context register writes for sun4v.\n\nsun4v uses ASI_MMU instead of ASI_DMMU\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "481295f982b21b1dbe71cbf41d3a93028fee30d1", "tree": "5b1af84a7f83021698bcf138c8875d7290e65282", "parents": [ "89a5264f065672a882f555228000614a6b2182b7" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 21:51:08 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:55 2006 -0800" }, "message": "[SPARC64]: Register per-cpu fault status area with sun4v hypervisor.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "df7d6aec96ab98cb182dd5138a85bdc363a9bf0d", "tree": "d71808a328639a32b16c53b24ce8a6b641f43ad2", "parents": [ "d257d5da39a78b32721ca84b2ba7f461f2f7ed7f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 00:00:16 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:53 2006 -0800" }, "message": "[SPARC64]: Rename gl_{1,2}insn_patch --\u003e sun4v_{1,2}insn_patch\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d257d5da39a78b32721ca84b2ba7f461f2f7ed7f", "tree": "ac28d377688ebe13a4d38e05f4ff65ba73d8652a", "parents": [ "840aaef8db32572b6d11e0d5cb5e6efcbc812000" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 06 23:44:37 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:52 2006 -0800" }, "message": "[SPARC64]: Initial sun4v TLB miss handling infrastructure.\n\nThings are a little tricky because, unlike sun4u, we have\nto:\n\n1) do a hypervisor trap to do the TLB load.\n2) do the TSB lookup calculations by hand\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "45fec05f805a113372c9a7ff4c653ac749f6921c", "tree": "36fc99d10656775acb8e9442719447d64ac30a03", "parents": [ "314981ac7177a933319e3c071a5cf0a579205e6e" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 05 22:27:28 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:50 2006 -0800" }, "message": "[SPARC64]: Sanitize %pstate writes for sun4v.\n\nIf we\u0027re just switching between different alternate global\nsets, nop it out on sun4v. Also, get rid of all of the\nalternate global save/restore in the OBP CIF trampoline code.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a43fe0e789f5445f5224511034f410adf11f153b", "tree": "cface7b6e616be616899da8c0762f904263c5985", "parents": [ "1633a53c79498455b16d051451f4e3f83ab4e7dd" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 04 03:10:53 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:40 2006 -0800" }, "message": "[SPARC64]: Add some hypervisor tlb_type checks.\n\nAnd more consistently check cheetah{,_plus} instead\nof assuming anything not spitfire is cheetah{,_plus}.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "52bf082f0a6e49e08ed99d4d9518c662dc735c7a", "tree": "7d6a27ea0ed9d66810952999cfa19afb4de66616", "parents": [ "766f861fbbd968a1850295ed6dec4504b4500dcc" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 04 03:08:37 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:38 2006 -0800" }, "message": "[SPARC64]: SUN4V hypervisor TLB flush support code.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "f4e841da30b4bcbb8f1cc20a01157a788ff58b21", "tree": "8f145f6902b694402ce6291a493caf3a2348717e", "parents": [ "7bec08e38a7d0f088994f6eec9b6374652ea71fb" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 02 16:16:24 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:34 2006 -0800" }, "message": "[SPARC64]: Turn off TSB growing for now.\n\nThere are several tricky races involved with growing the TSB. So just\nuse base-size TSBs for user contexts and we can revisit enabling this\nlater.\n\nOne part of the SMP problems is that tsb_context_switch() can see\npartially updated TSB configuration state if tsb_grow() is running in\nparallel. That\u0027s easily solved with a seqlock taken as a writer by\ntsb_grow() and taken as a reader to capture all the TSB config state\nin tsb_context_switch().\n\nThen there is flush_tsb_user() running in parallel with a tsb_grow().\nIn theory we could take the seqlock as a reader there too, and just\nresample the TSB pointer and reflush but that looks really ugly.\n\nLastly, I believe there is a case with threads that results in a TSB\nentry lock bit being set spuriously which will cause the next access\nto that TSB entry to wedge the cpu (since the TSB entry lock bit will\nnever clear). It\u0027s either copy_tsb() or some bug elsewhere in the TSB\nassembly.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "517af33237ecfc3c8a93b335365fa61e741ceca4", "tree": "58eff40eb4c517c4fd49fd347d38273ee1e1ee4b", "parents": [ "b0fd4e49aea8a460afab7bc67cd618e2d19291d4" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 01 15:55:21 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:32 2006 -0800" }, "message": "[SPARC64]: Access TSB with physical addresses when possible.\n\nThis way we don\u0027t need to lock the TSB into the TLB.\nThe trick is that every TSB load/store is registered into\na special instruction patch section. The default uses\nvirtual addresses, and the patch instructions use physical\naddress load/stores.\n\nWe can\u0027t do this on all chips because only cheetah+ and later\nhave the physical variant of the atomic quad load.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9954863975910a1b9372b7d5006a6cba43bdd288", "tree": "0a6d088d67e0a75ed6a15590c9811e1d6fa75576", "parents": [ "9bc657b28eba22e36efcdf3afa08100f92971eb4" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:34:34 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:28 2006 -0800" }, "message": "[SPARC64]: Kill swapper_pgd_zero, totally unused.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "2f7ee7c63f08b7f883b710a29d91c1891b81b8e1", "tree": "c0539482cecfd3cbc0b983a23058315811dc8b55", "parents": [ "a8b900d801697609d1b56cc9c110148c64678068" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:33:49 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:26 2006 -0800" }, "message": "[SPARC64]: Increase swapper_tsb size to 32K.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a8b900d801697609d1b56cc9c110148c64678068", "tree": "47602480aba29d17f8a79cc76dfe8af4d62f2599", "parents": [ "3487d1d4414fbfab5d98ec559e6f84f55520cb15" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:33:37 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:25 2006 -0800" }, "message": "[SPARC64]: Kill sole argument passed to setup_tba().\n\nNo longer used, and move extern declaration to a header file.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3487d1d4414fbfab5d98ec559e6f84f55520cb15", "tree": "b85ac7e9d8c07bd3c8a9d314d650b04cdf1ccc96", "parents": [ "6b6d017235acad3ee1681140795593723bb9b9df" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:33:25 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:24 2006 -0800" }, "message": "[SPARC64]: Kill PROM locked TLB entry preservation code.\n\nIt is totally unnecessary complexity. After we take over\nthe trap table, we handle all PROM tlb misses fully.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "4da808c352c290d3f762933d44d4ab90c2fd65f3", "tree": "da99326440777580a19c345a5b0d52fbf800042b", "parents": [ "4753eb2ac7022b999e5e484f1a5dc001dba22bd3" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:33:00 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:22 2006 -0800" }, "message": "[SPARC64]: Fix bogus flush instruction usage.\n\nSome of the trap code was still assuming that alternate\nglobal %g6 was hard coded with current_thread_info().\nLet\u0027s just consistently flush at KERNBASE when we need\na pipeline synchronization. That\u0027s locked into the TLB\nand will always work.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "4753eb2ac7022b999e5e484f1a5dc001dba22bd3", "tree": "138321ebd3b3c3aeb99517ec5158a65f556da774", "parents": [ "96c6e0d8e2a0eb1338751598be47fa1ffed91704" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:32:44 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:21 2006 -0800" }, "message": "[SPARC64]: Fix incorrect TSB lock bit handling.\n\nThe TSB_LOCK_BIT define is actually a special\nvalue shifted down by 32-bits for the assembler\ncode macros.\n\nIn C code, this isn\u0027t what we want.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b70c0fa1613c4f69b4a340a0e2bee387560ebbb1", "tree": "f7bf22ab75cb9118f5772353fef6efd923faa212", "parents": [ "bd40791e1d289d807b8580abe1f117e9c62894e4" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:32:04 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:19 2006 -0800" }, "message": "[SPARC64]: Preload TSB entries from update_mmu_cache().\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "bd40791e1d289d807b8580abe1f117e9c62894e4", "tree": "2b47e24c8dc0e668dfd7ba0e3879165180c49c65", "parents": [ "98c5584cfc47932c4f3ccf5eee2e0bae1447b85e" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:31:38 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:18 2006 -0800" }, "message": "[SPARC64]: Dynamically grow TSB in response to RSS growth.\n\nAs the RSS grows, grow the TSB in order to reduce the likelyhood\nof hash collisions and thus poor hit rates in the TSB.\n\nThis definitely needs some serious tuning.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "98c5584cfc47932c4f3ccf5eee2e0bae1447b85e", "tree": "c067ac8bfc081bbe0b3073374cb15708458e04ab", "parents": [ "09f94287f7260e03bbeab497e743691fafcc22c3" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:31:20 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:17 2006 -0800" }, "message": "[SPARC64]: Add infrastructure for dynamic TSB sizing.\n\nThis also cleans up tsb_context_switch(). The assembler\nroutine is now __tsb_context_switch() and the former is\nan inline function that picks out the bits from the mm_struct\nand passes it into the assembler code as arguments.\n\nsetup_tsb_parms() computes the locked TLB entry to map the\nTSB. Later when we support using the physical address quad\nload instructions of Cheetah+ and later, we\u0027ll simply use\nthe physical address for the TSB register value and set\nthe map virtual and PTE both to zero.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "09f94287f7260e03bbeab497e743691fafcc22c3", "tree": "ebdb365a7cfe25a1587a930d852f2eaa0e1e773a", "parents": [ "56fb4df6da76c35dca22036174e2d1edef83ff1f" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:31:06 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:16 2006 -0800" }, "message": "[SPARC64]: TSB refinements.\n\nMove {init_new,destroy}_context() out of line.\n\nDo not put huge pages into the TSB, only base page size translations.\nThere are some clever things we could do here, but for now let\u0027s be\ncorrect instead of fancy.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "56fb4df6da76c35dca22036174e2d1edef83ff1f", "tree": "b39f152ec9ed682edceca965a85680fd4bf736a7", "parents": [ "3c936465249f863f322154ff1aaa628b84ee5750" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 26 23:24:22 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:16 2006 -0800" }, "message": "[SPARC64]: Elminate all usage of hard-coded trap globals.\n\nUltraSPARC has special sets of global registers which are switched to\nfor certain trap types. There is one set for MMU related traps, one\nset of Interrupt Vector processing, and another set (called the\nAlternate globals) for all other trap types.\n\nFor what seems like forever we\u0027ve hard coded the values in some of\nthese trap registers. Some examples include:\n\n1) Interrupt Vector global %g6 holds current processors interrupt\n work struct where received interrupts are managed for IRQ handler\n dispatch.\n\n2) MMU global %g7 holds the base of the page tables of the currently\n active address space.\n\n3) Alternate global %g6 held the current_thread_info() value.\n\nSuch hardcoding has resulted in some serious issues in many areas.\nThere are some code sequences where having another register available\nwould help clean up the implementation. Taking traps such as\ncross-calls from the OBP firmware requires some trick code sequences\nwherein we have to save away and restore all of the special sets of\nglobal registers when we enter/exit OBP.\n\nWe were also using the IMMU TSB register on SMP to hold the per-cpu\narea base address, which doesn\u0027t work any longer now that we actually\nuse the TSB facility of the cpu.\n\nThe implementation is pretty straight forward. One tricky bit is\ngetting the current processor ID as that is different on different cpu\nvariants. We use a stub with a fancy calling convention which we\npatch at boot time. The calling convention is that the stub is\nbranched to and the (PC - 4) to return to is in register %g1. The cpu\nnumber is left in %g6. This stub can be invoked by using the\n__GET_CPUID macro.\n\nWe use an array of per-cpu trap state to store the current thread and\nphysical address of the current address space\u0027s page tables. The\nTRAP_LOAD_THREAD_REG loads %g6 with the current thread from this\ntable, it uses __GET_CPUID and also clobbers %g1.\n\nTRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load\nthe current processor\u0027s IRQ software state into %g6. It also uses\n__GET_CPUID and clobbers %g1.\n\nFinally, TRAP_LOAD_PGD_PHYS loads the physical address base of the\ncurrent address space\u0027s page tables into %g7, it clobbers %g1 and uses\n__GET_CPUID.\n\nMany refinements are possible, as well as some tuning, with this stuff\nin place.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3c936465249f863f322154ff1aaa628b84ee5750", "tree": "2bd7a229236f197d20a655133370e5d0c1bf886c", "parents": [ "05e28f9de65a38bb0c769080e91b6976e7e1e70c" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:30:27 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:14 2006 -0800" }, "message": "[SPARC64]: Kill pgtable quicklists and use SLAB.\n\nTaking a nod from the powerpc port.\n\nWith the per-cpu caching of both the page allocator and SLAB, the\npgtable quicklist scheme becomes relatively silly and primitive.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "05e28f9de65a38bb0c769080e91b6976e7e1e70c", "tree": "e1d3fcc1381ea6612ce4c082ca8596e84b637216", "parents": [ "74bf4312fff083ab25c3f357cc653ada7995e5f6" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:30:13 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:13 2006 -0800" }, "message": "[SPARC64]: No need to D-cache color page tables any longer.\n\nUnlike the virtual page tables, the new TSB scheme does not\nrequire this ugly hack.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "74bf4312fff083ab25c3f357cc653ada7995e5f6", "tree": "c23dea461e32485f4cd7ca4b8c33c632655eb906", "parents": [ "30d4d1ffed7098afe2641536d67eef150499da02" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:29:18 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:13 2006 -0800" }, "message": "[SPARC64]: Move away from virtual page tables, part 1.\n\nWe now use the TSB hardware assist features of the UltraSPARC\nMMUs.\n\nSMP is currently knowingly broken, we need to find another place\nto store the per-cpu base pointers. We hid them away in the TSB\nbase register, and that obviously will not work any more :-)\n\nAnother known broken case is non-8KB base page size.\n\nAlso noticed that flush_tlb_all() is not referenced anywhere, only\nthe internal __flush_tlb_all() (local cpu only) is used by the\nsparc64 port, so we can get rid of flush_tlb_all().\n\nThe kernel gets it\u0027s own 8KB TSB (swapper_tsb) and each address space\ngets it\u0027s own private 8K TSB. Later we can add code to dynamically\nincrease the size of per-process TSB as the RSS grows. An 8KB TSB is\ngood enough for up to about a 4MB RSS, after which the TSB starts to\nincur many capacity and conflict misses.\n\nWe even accumulate OBP translations into the kernel TSB.\n\nAnother area for refinement is large page size support. We could use\na secondary address space TSB to handle those.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "cab3f16febeaf1a60e38159ff578f609f9976544", "tree": "94fdc12b7ae46d285180be9fa8d03e7be6d63f71", "parents": [ "4168f7a31801bba6acc18662978d24ec850bbbd0" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Nov 29 13:59:03 2005 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Nov 29 13:59:03 2005 -0800" }, "message": "[SPARC64]: Fix \u003e8K I/O mappings.\n\nIncrement the PFN field of the PTE so that the tests\non vm_pfn in mm/memory.c match up. The TLB ignores these\nlower bits for larger page sizes, so it\u0027s OK to set things\nlike this.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "5cd9194a1b0b0fa219c31421ac64dfd38670ed49", "tree": "4cd74902103751f10aec30d5a4b0b9af51f42561", "parents": [ "6aab341e0a28aff100a09831c5300a2994b8b986" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Nov 28 14:02:10 2005 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Mon Nov 28 14:35:36 2005 -0800" }, "message": "[PATCH] sparc: convert IO remapping to VM_PFNMAP\n\nHere are the Sparc bits.\n\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "0b14c179a483e71ea41df2aa4a661760063115bd", "tree": "075fc303a3d2fd33f66c0af8f64064cff2b72b79", "parents": [ "664beed0190fae687ac51295694004902ddeb18e" ], "author": { "name": "Hugh Dickins", "email": "hugh@veritas.com", "time": "Mon Nov 21 21:32:15 2005 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Tue Nov 22 09:13:42 2005 -0800" }, "message": "[PATCH] unpaged: VM_UNPAGED\n\nAlthough we tend to associate VM_RESERVED with remap_pfn_range, quite a few\ndrivers set VM_RESERVED on areas which are then populated by nopage. The\nPageReserved removal in 2.6.15-rc1 changed VM_RESERVED not to free pages in\nzap_pte_range, without changing those drivers not to set it: so their pages\njust leak away.\n\nLet\u0027s not change miscellaneous drivers now: introduce VM_UNPAGED at the core,\nto flag the special areas where the ptes may have no struct page, or if they\nhave then it\u0027s not to be touched. Replace most instances of VM_RESERVED in\ncore mm by VM_UNPAGED. Force it on in remap_pfn_range, and the sparc and\nsparc64 io_remap_pfn_range.\n\nRevert addition of VM_RESERVED to powerpc vdso, it\u0027s not needed there. Is it\nneeded anywhere? It still governs the mm-\u003ereserved_vm statistic, and special\nvmas not to be merged, and areas not to be core dumped; but could probably be\neliminated later (the drivers are probably specifying it because in 2.4 it\nkept swapout off the vma, but in 2.6 we work from the LRU, which these pages\ndon\u0027t get on).\n\nUse the VM_SHM slot for VM_UNPAGED, and define VM_SHM to 0: it serves no\npurpose whatsoever, and should be removed from drivers when we clean up.\n\nSigned-off-by: Hugh Dickins \u003chugh@veritas.com\u003e\nAcked-by: William Irwin \u003cwli@holomorphy.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "84c1a13a30f21406f39e546684a78ebe9859e6d7", "tree": "296330a7d501eb349070363df28da70b10a62963", "parents": [ "940fdc6e1223f1323b88b7f1e7ae09a93a76b74d" ], "author": { "name": "Tobias Klauser", "email": "tklauser@nuerscht.ch", "time": "Wed Nov 09 12:03:42 2005 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Nov 09 12:03:42 2005 -0800" }, "message": "[SPARC64]: Use ARRAY_SIZE macro\n\nUse ARRAY_SIZE macro instead of sizeof(x)/sizeof(x[0]) and remove a\nduplicate of ARRAY_SIZE which is never used anyways.\n\nSigned-off-by: Tobias Klauser \u003ctklauser@nuerscht.ch\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "da1605465ebdb9dc25296a354394086cd559c243", "tree": "9006bcb3c3dc0952f41b0ddf0e7119b40f48b458", "parents": [ "d5a858bc148fe97996af9cf685cc124b70519adf" ], "author": { "name": "Hugh Dickins", "email": "hugh@veritas.com", "time": "Tue Nov 08 10:00:55 2005 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Nov 08 10:00:55 2005 -0800" }, "message": "[SPARC64] mm: update get_user_insn comment\n\nUpdate comment on get_user_insn to the more general \"pte lock\", which may\nor may not be the page_table_lock. Note vmtruncate handled like kswapd.\n\nSigned-off-by: Hugh Dickins \u003chugh@veritas.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b462705ac679f6195d1b23a752cda592d9107495", "tree": "c4d9be08f67b0ffdc66c3e170614bd03945f3c42", "parents": [ "c74df32c724a1652ad8399b4891bb02c9d43743a" ], "author": { "name": "Hugh Dickins", "email": "hugh@veritas.com", "time": "Sat Oct 29 18:16:24 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sat Oct 29 21:40:40 2005 -0700" }, "message": "[PATCH] mm: arches skip ptlock\n\nConvert those few architectures which are calling pud_alloc, pmd_alloc,\npte_alloc_map on a user mm, not to take the page_table_lock first, nor drop it\nafter. Each of these can continue to use pte_alloc_map, no need to change\nover to pte_alloc_map_lock, they\u0027re neither racy nor swappable.\n\nIn the sparc64 io_remap_pfn_range, flush_tlb_range then falls outside of the\npage_table_lock: that\u0027s okay, on sparc64 it\u0027s like flush_tlb_mm, and that has\nalways been called from outside of page_table_lock in dup_mmap.\n\nSigned-off-by: Hugh Dickins \u003chugh@veritas.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "b5810039a54e5babf428e9a1e89fc1940fabff11", "tree": "835836cb527ec9bd525f93eb7e016f3dfb8c8ae2", "parents": [ "f9c98d0287de42221c624482fd4f8d485c98ab22" ], "author": { "name": "Nick Piggin", "email": "nickpiggin@yahoo.com.au", "time": "Sat Oct 29 18:16:12 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sat Oct 29 21:40:39 2005 -0700" }, "message": "[PATCH] core remove PageReserved\n\nRemove PageReserved() calls from core code by tightening VM_RESERVED\nhandling in mm/ to cover PageReserved functionality.\n\nPageReserved special casing is removed from get_page and put_page.\n\nAll setting and clearing of PageReserved is retained, and it is now flagged\nin the page_alloc checks to help ensure we don\u0027t introduce any refcount\nbased freeing of Reserved pages.\n\nMAP_PRIVATE, PROT_WRITE of VM_RESERVED regions is tentatively being\ndeprecated. We never completely handled it correctly anyway, and is be\nreintroduced in future if required (Hugh has a proof of concept).\n\nOnce PageReserved() calls are removed from kernel/power/swsusp.c, and all\narch/ and driver code, the Set and Clear calls, and the PG_reserved bit can\nbe trivially removed.\n\nLast real user of PageReserved is swsusp, which uses PageReserved to\ndetermine whether a struct page points to valid memory or not. This still\nneeds to be addressed (a generic page_is_ram() should work).\n\nA last caveat: the ZERO_PAGE is now refcounted and managed with rmap (and\nthus mapcounted and count towards shared rss). These writes to the struct\npage could cause excessive cacheline bouncing on big systems. There are a\nnumber of ways this could be addressed if it is an issue.\n\nSigned-off-by: Nick Piggin \u003cnpiggin@suse.de\u003e\n\nRefcount bug fix for filemap_xip.c\n\nSigned-off-by: Carsten Otte \u003ccotte@de.ibm.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "fc2acab31be8e869b2d5f6de12f557f6f054f19c", "tree": "60cf419f5e88c3c46d39675a14649ea1e5849f03", "parents": [ "4d6ddfa9242bc3d27fb0f7248f6fdee0299c731f" ], "author": { "name": "Hugh Dickins", "email": "hugh@veritas.com", "time": "Sat Oct 29 18:16:03 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sat Oct 29 21:40:37 2005 -0700" }, "message": "[PATCH] mm: tlb_finish_mmu forget rss\n\nzap_pte_range has been counting the pages it frees in tlb-\u003efreed, then\ntlb_finish_mmu has used that to update the mm\u0027s rss. That got stranger when I\nadded anon_rss, yet updated it by a different route; and stranger when rss and\nanon_rss became mm_counters with special access macros. And it would no\nlonger be viable if we\u0027re relying on page_table_lock to stabilize the\nmm_counter, but calling tlb_finish_mmu outside that lock.\n\nRemove the mmu_gather\u0027s freed field, let tlb_finish_mmu stick to its own\nbusiness, just decrement the rss mm_counter in zap_pte_range (yes, there was\nsome point to batching the update, and a subsequent patch restores that). And\nforget the anal paranoia of first reading the counter to avoid going negative\n- if rss does go negative, just fix that bug.\n\nRemove the mmu_gather\u0027s flushes and avoided_flushes from arm and arm26: no use\nwas being made of them. But arm26 alone was actually using the freed, in the\nway some others use need_flush: give it a need_flush. arm26 seems to prefer\nspaces to tabs here: respect that.\n\nSigned-off-by: Hugh Dickins \u003chugh@veritas.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "4d6ddfa9242bc3d27fb0f7248f6fdee0299c731f", "tree": "da5b753df64e7163a35487005e50a3b90b0b0b9b", "parents": [ "15a23ffa2fc91cebdac44d4aee994f59d5c28dc0" ], "author": { "name": "Hugh Dickins", "email": "hugh@veritas.com", "time": "Sat Oct 29 18:16:02 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sat Oct 29 21:40:37 2005 -0700" }, "message": "[PATCH] mm: tlb_is_full_mm was obscure\n\ntlb_is_full_mm? What does that mean? The TLB is full? No, it means that the\nmm\u0027s last user has gone and the whole mm is being torn down. And it\u0027s an\ninline function because sparc64 uses a different (slightly better)\n\"tlb_frozen\" name for the flag others call \"fullmm\".\n\nAnd now the ptep_get_and_clear_full macro used in zap_pte_range refers\ndirectly to tlb-\u003efullmm, which would be wrong for sparc64. Rather than\ncorrect that, I\u0027d prefer to scrap tlb_is_full_mm altogether, and change\nsparc64 to just use the same poor name as everyone else - is that okay?\n\nSigned-off-by: Hugh Dickins \u003chugh@veritas.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "b4d1b825785847cddee6d104113da913f2ca8efb", "tree": "b491001940d86d6e3325300056aeda4158f6ef84", "parents": [ "f75884d28a6eae5a422d0454b982da3842f777af" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Oct 14 15:26:08 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Oct 14 15:26:08 2005 -0700" }, "message": "[SPARC64]: Fix powering off on SMP.\n\nDoing a \"SUNW,stop-self\" firmware call on the other cpus is not the\ncorrect thing to do when dropping into the firmware for a halt,\nreboot, or power-off.\n\nFor now, just do nothing to quiet the other cpus, as the system should\nbe quiescent enough. Later we may decide to implement smp_send_stop()\nlike the other SMP platforms do.\n\nBased upon a report from Christopher Zimmermann.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c9c10830740df1b5e7848d6fbb68c93a73e8f7cd", "tree": "b614058c3291ebccb996b27cee9b709956df7791", "parents": [ "d8e998c58a870770905495a1d45ebf7285b5b1c5" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Oct 12 12:22:46 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Oct 12 12:22:46 2005 -0700" }, "message": "[SPARC64]: Fix boot failures on SunBlade-150\n\nThe sequence to move over to the Linux trap tables from\nthe firmware ones needs to be more air tight. It turns\nout that to be %100 safe we do need to be able to translate\nOBP mappings in our TLB miss handlers early.\n\nIn order not to eat up a lot of kernel image memory with\nstatic page tables, just use the translations array in\nthe OBP TLB miss handlers. That solves the bulk of the\nproblem.\n\nFurthermore, to make sure the OBP TLB miss path will work\neven before the fixed MMU globals are loaded, explicitly\nload %g1 to TLB_SFSR at the beginning of the i-TLB and\nd-TLB miss handlers.\n\nTo ease the OBP TLB miss walking of the prom_trans[] array,\nwe sort it then delete all of the non-OBP entries in there\n(for example, there are entries for the kernel image itself\nwhich we\u0027re not interested in at all).\n\nWe also save about 32K of kernel image size with this change.\nNot a bad side effect :-)\n\nThere are still some reasons why trampoline.S can\u0027t use the\nsetup_trap_table() yet. The most noteworthy are:\n\n1) OBP boots secondary processors with non-bias\u0027d stack for\n some reason. This is easily fixed by using a small bootup\n stack in the kernel image explicitly for this purpose.\n\n2) Doing a firmware call via the normal C call prom_set_trap_table()\n goes through the whole OBP enter/exit sequence that saves and\n restores OBP and Linux kernel state in the MMUs. This path\n unfortunately does a \"flush %g6\" while loading up the OBP locked\n TLB entries for the firmware call.\n\n If we setup the %g6 in the trampoline.S code properly, that\n is in the PAGE_OFFSET linear mapping, but we\u0027re not on the\n kernel trap table yet so those addresses won\u0027t translate properly.\n\n One idea is to do a by-hand firmware call like we do in the\n early bootup code and elsewhere here in trampoline.S But this\n fails as well, as aparently the secondary processors are not\n booted with OBP\u0027s special locked TLB entries loaded. These\n are necessary for the firwmare to processes TLB misses correctly\n up until the point where we take over the trap table.\n\nThis does need to be resolved at some point.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9ad98c5b4461e7dfa3754963200993a68825eab4", "tree": "b7456cf49eaf034740fa7cb8b75e5b6ee01c9666", "parents": [ "782c3fd470abddf2525e34cf3131215a8f95e834" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Oct 05 15:12:00 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Oct 05 15:12:00 2005 -0700" }, "message": "[SPARC64]: Fix initrd when net booting.\n\nBy allocating early memory for the firmware page tables, we\ncan write over the beginning of the initrd image.\n\nSo what we do now is:\n\n1) Read in firmware translations table while still on the\n firmware\u0027s trap table.\n2) Switch to Linux trap table.\n3) Init bootmem.\n4) Build firmware page tables using __alloc_bootmem().\n\nAnd this keeps the initrd from being clobbered.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "0835ae0f27c0bfde67613d189ef6c537e004a6de", "tree": "ad5cad209eeb11bd1bf49a3b5cffa49618c717c8", "parents": [ "dd7205ed0f022a2a5e60eb7404e6c9f49d2301c3" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Oct 04 15:23:20 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Oct 04 15:23:20 2005 -0700" }, "message": "[SPARC64]: Replace cheetah+ code patching with variables.\n\nInstead of code patching to handle the page size fields in\nthe context registers, just use variables from which we get\nthe proper values.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "13edad7a5cef1c952459742482482a6b05e1a8a1", "tree": "4d1ddcbbb7fe5cda5e75c83e3d8511ed1642e201", "parents": [ "ed3ffaf7b5e0262cb860f106a6632933671cc88f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 29 17:58:26 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 29 17:58:26 2005 -0700" }, "message": "[SPARC64]: Rewrite convoluted physical memory probing.\n\nDelete all of the code working with sp_banks[] and replace\nwith clean acquisition and sorting of physical memory\nparameters from the firmware.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "10147570f9eaff3920f0c67bad7244c2eb958d4f", "tree": "213bdf97f2ac9d2dc3708db19da4ea41ca4f1606", "parents": [ "0836a0eb4073c3e0a09c5965833b9dec19f5abc7" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 28 21:46:43 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 28 21:46:43 2005 -0700" }, "message": "[SPARC64]: Kill all external references to sp_banks[]\n\nThus, we can mark sp_banks[] static in arch/sparc64/mm/init.c\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "0836a0eb4073c3e0a09c5965833b9dec19f5abc7", "tree": "d6538773d4bdc18a32e49c11e35138465f7739a1", "parents": [ "801ab3c731e77324c055769491711e620100dbfb" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 28 21:38:08 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 28 21:38:08 2005 -0700" }, "message": "[SPARC64]: Move phys_base, kern_{base,size}, and sp_banks[] init to paging_init\n\nAlso, move prom_probe_memory() into arch/sparc64/mm/init.c\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "efdc1e2083e04cc70721d55803889b346c1a3de2", "tree": "9f24fab33f795a69bb2dc43a8f3613392762ff02", "parents": [ "5fd29752f09cabff582f65c0ce35518db4c64937" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 28 21:06:47 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 28 21:06:47 2005 -0700" }, "message": "[SPARC64]: Simplify user fault fixup handling.\n\nInstead of doing byte-at-a-time user accesses to figure\nout where the fault occurred, read the saved fault_address\nfrom the current thread structure.\n\nFor the sake of defensive programming, if the fault_address\ndoes not fall into the user buffer range, simply assume the\nwhole area faulted. This will cause the fixup for\ncopy_from_user() to clear the entire kernel side buffer.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "8cf14af0a740fb7e9f94a203b5a989beb875d58f", "tree": "a7bec4d60c352e780d6a2b75e9b95e637e3a14f7", "parents": [ "705747ab87c96f1b4b8e73ba617c323d9087f6ac" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 28 20:21:11 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 28 20:21:11 2005 -0700" }, "message": "[SPARC64]: Convert to use generic exception table support.\n\nThe funny \"range\" exception table entries we had were only\nused by the compat layer socketcall assembly, and it wasn\u0027t\neven needed there.\n\nFor free we now get proper exception table sorting and fast\nbinary searching.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "0dc461069879b45a2d5333bd16990f8080a318fd", "tree": "d1f4b129750655352ac6a2ac1bee80fc95213a4f", "parents": [ "c5bd50a9533533d7b9ac3469fa679b2368e7e26c" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Sep 26 16:12:18 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Sep 26 16:12:18 2005 -0700" }, "message": "[SPARC64]: Do not do TLB pre-filling any more.\n\nIn order to do it correctly on UltraSPARC-III+ and later we\u0027d\nneed to add some complicated code to set the TAG access extension\nregister before loading the TLB.\n\nSince this optimization gives questionable gains, it\u0027s best to\njust remove it for now instead of adding the fix for Ultra-III+\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c5bd50a9533533d7b9ac3469fa679b2368e7e26c", "tree": "166aee9c0d1525ee8c4a7228015f2d4e37634c77", "parents": [ "80dc0d6b44ce0f01df58d8899e46612690ed7d81" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Sep 26 16:06:03 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Sep 26 16:06:03 2005 -0700" }, "message": "[SPARC64]: Simplify Spitfire D-cache page flush.\n\nIt tries to batch up the tag loads and comparisons, and\nthen the stores. And this is just complicated instead\nof efficient.\n\nAlso, make the symbol of the Cheetah version more grepable.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "56425306517ef28a9b480161cdb96d182172bc1d", "tree": "204cfbef0e5d86954f87b6b40d79d57f8157e5ea", "parents": [ "52f26deb7c67d5f34910660200b925c1a2b8df8c" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Sep 25 16:46:57 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Sep 25 16:46:57 2005 -0700" }, "message": "[SPARC64]: Add CONFIG_DEBUG_PAGEALLOC support.\n\nThe trick is that we do the kernel linear mapping TLB miss starting\nwith an instruction sequence like this:\n\n\tba,pt\t\t%xcc, kvmap_load\n\t xor\t\t%g2, %g4, %g5\n\nsucceeded by an instruction sequence which performs a full page table\nwalk starting at swapper_pg_dir.\n\nWe first take over the trap table from the firmware. Then, using this\nconstant PTE generation for the linear mapping area above, we build\nthe kernel page tables for the linear mapping.\n\nAfter this is setup, we patch that branch above into a \"nop\", which\nwill cause TLB misses to fall through to the full page table walk.\n\nWith this, the page unmapping for CONFIG_DEBUG_PAGEALLOC is trivial.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "898cf0ecb7959db97d71cbce19685ce73a28d47c", "tree": "321c4dcfd6a63fc9beda9663c9852422bfbce5a0", "parents": [ "1c9ea5db001142a96fec8fed0f92f26892a1b6ac" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Sep 23 11:59:44 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Sep 23 11:59:44 2005 -0700" }, "message": "[SPARC64]: Mark functions called by paging_init() as __init.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "bff06d552240ba7f5b49482a4865871d7bc03dc2", "tree": "ee760e252023bec338921296b12bb54987bedcac", "parents": [ "40fd3533c93f0062b6d1d8540961ef70fc8ab750" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 22 20:11:33 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 22 20:11:33 2005 -0700" }, "message": "[SPARC64]: Rewrite bootup sequence.\n\nInstead of all of this cpu-specific code to remap the kernel\nto the correct location, use portable firmware calls to do\nthis instead.\n\nWhat we do now is the following in position independant\nassembler:\n\n\tchosen_node \u003d prom_finddevice(\"/chosen\");\n\tprom_mmu_ihandle_cache \u003d prom_getint(chosen_node, \"mmu\");\n\tvaddr \u003d 4MB_ALIGN(current_text_addr());\n\tprom_translate(vaddr, \u0026paddr_high, \u0026paddr_low, \u0026mode);\n\tprom_boot_mapping_mode \u003d mode;\n\tprom_boot_mapping_phys_high \u003d paddr_high;\n\tprom_boot_mapping_phys_low \u003d paddr_low;\n\tprom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);\n\nand that replaces the massive amount of by-hand TLB probing and\nprogramming we used to do here.\n\nThe new code should also handle properly the case where the kernel\nis mapped at the correct address already (think: future kexec\nsupport).\n\nConsequently, the bulk of remap_kernel() dies as does the entirety\nof arch/sparc64/prom/map.S\n\nWe try to share some strings in the PROM library with the ones used\nat bootup, and while we\u0027re here mark input strings to oplib.h routines\nwith \"const\" when appropriate.\n\nThere are many more simplifications now possible. For one thing, we\ncan consolidate the two copies we now have of a lot of cpu setup code\nsitting in head.S and trampoline.S.\n\nThis is a significant step towards CONFIG_DEBUG_PAGEALLOC support.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "40fd3533c93f0062b6d1d8540961ef70fc8ab750", "tree": "89df38fa456ba31551cc7a803677da556ab1e912", "parents": [ "2bdb3cb265830aee823444d115a8a84eca2b934e" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 22 13:03:36 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 22 13:03:36 2005 -0700" }, "message": "[SPARC64]: Kill readjust_prom_translations()\n\nTesting shows that the prom_unmap() calls do absolutely\nnothing.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "2bdb3cb265830aee823444d115a8a84eca2b934e", "tree": "967596d2e3ab18772761dd1202d67803d0830c85", "parents": [ "5085b4a5492f4f8bd32d0cc5b1cad4bf522c2e1a" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 22 01:08:57 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 22 01:08:57 2005 -0700" }, "message": "[SPARC64]: Remove unnecessary paging_init() cruft.\n\nBecause we don\u0027t access the PAGE_OFFSET linear mappings\nany longer before we take over the trap table from the\nfirmware, we don\u0027t need to load dummy mappings there\ninto the TLB and we don\u0027t need the bootmap_base hack\nany longer either.\n\nWhile we are here, check for a larger than 8MB kernel\nand halt the boot with an error message. We know that\ndoesn\u0027t work, so instead of failing mysteriously we\nshould let the user know exactly what\u0027s wrong.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "5085b4a5492f4f8bd32d0cc5b1cad4bf522c2e1a", "tree": "ea8ecb5d0a99f577b6517fe13583d63d8a8e800e", "parents": [ "405599bd98b01d648becb020efb503abf19f9c9f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 22 00:45:41 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 22 00:45:41 2005 -0700" }, "message": "[SPARC64]: Do not allocate OBP page tables using bootmem\n\nJust allocate them physically starting from the end of\nthe kernel image. This incredibly simplifies our MM\nbootstrap in that we don\u0027t need any mappings in the linear\nPAGE_OFFSET area working in order to bootstrap ourselves and\ntake over the trap table from the firmware.\n\nMany further simplifications are possible now, and this also\nsets the stage for CONFIG_DEBUG_PAGEALLOC support.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "405599bd98b01d648becb020efb503abf19f9c9f", "tree": "ccf791e5a40f8c550103b0f7db054dca2973ae79", "parents": [ "b206fc4c0997ee858bc3ed35f157d7c3cda54cfd" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 22 00:12:35 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 22 00:12:35 2005 -0700" }, "message": "[SPARC64]: Break up inherit_prom_mappings() into it\u0027s constituent parts.\n\nThis thing was just a huge monolithic mess, so chop it up.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b206fc4c0997ee858bc3ed35f157d7c3cda54cfd", "tree": "c23da9880e719b5219d119fd1c966794ec66d4de", "parents": [ "1ac4f5ebaa496a23ab4a148c9864d7e30a6c6cd3" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 21 22:31:13 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 21 22:31:13 2005 -0700" }, "message": "[SPARC64]: Do not allocate prom translations using bootmem.\n\nUse __initdata instead.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1ac4f5ebaa496a23ab4a148c9864d7e30a6c6cd3", "tree": "1ab1e111f596b8c66c741e63f14d721cb1818c7a", "parents": [ "059deb693ec191e563ec69533d24f3feff0b78cd" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 21 21:49:32 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Sep 21 21:49:32 2005 -0700" }, "message": "[SPARC64]: Remove ktlb.S instruction patching.\n\nThis was kind of ugly, and actually buggy. The bug was that\nwe didn\u0027t handle a machine with memory starting \u003e 4GB. If\nthe \u0027prompmd\u0027 was allocated in physical memory \u003e 4GB we\u0027d\ncroak because the obp_iaddr_patch and obp_daddr_patch things\nonly supported a 32-bit physical address.\n\nSo fix this by just loading the appropriate values from two\nvariables in the kernel image, which is locked into the TLB\nand thus accesses to them can\u0027t cause a recursive TLB miss.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "83005161c84efa70f3d4dc193eb1024a40b650dc", "tree": "0a10b8658f115c857ad8fce078454e77dc5d5074", "parents": [ "05e14cb3bafabbf08216ab5566f3cd687eba9723" ], "author": { "name": "Prasanna S Panchamukhi", "email": "prasanna@in.ibm.com", "time": "Tue Sep 06 15:19:31 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Sep 07 16:58:00 2005 -0700" }, "message": "[PATCH] kprobes-prevent-possible-race-conditions-sparc64-changes fix\n\nThis patch adds flags \"ax\" to .kprobe.text section.\n\nSigned-off-by: Prasanna S Panchamukhi \u003cprasanna@in.ibm.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "05e14cb3bafabbf08216ab5566f3cd687eba9723", "tree": "6320a3e9193c474571401b2c279b1ee176c29c27", "parents": [ "1f7ad57b75ab0fba27455c7344a6ab7aa6bd90c5" ], "author": { "name": "Prasanna S Panchamukhi", "email": "prasanna@in.ibm.com", "time": "Tue Sep 06 15:19:30 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Sep 07 16:58:00 2005 -0700" }, "message": "[PATCH] Kprobes: prevent possible race conditions sparc64 changes\n\nThis patch contains the sparc64 architecture specific changes to prevent the\npossible race conditions.\n\nSigned-off-by: Prasanna S Panchamukhi \u003cprasanna@in.ibm.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" } ], "next": "a7a6cac204147634aba7487e4d618b028ff54c0d" }