)]}' { "log": [ { "commit": "6510d41954dc6a9c8b1dbca7eaca0f23195ca727", "tree": "868b5fac25c7c5b80cc5a88eaaab8bf3d693420d", "parents": [ "064106a91be5e76cb42c1ddf5d3871e3a1bd2a23" ], "author": { "name": "Harvey Harrison", "email": "harvey.harrison@gmail.com", "time": "Tue Apr 29 01:03:30 2008 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Apr 29 08:06:27 2008 -0700" }, "message": "kernel: Move arches to use common unaligned access\n\nUnaligned access is ok for the following arches:\ncris, m68k, mn10300, powerpc, s390, x86\n\nArches that use the memmove implementation for native endian, and\nthe byteshifting for the opposite endianness.\nh8300, m32r, xtensa\n\nPacked struct for native endian, byteshifting for other endian:\nalpha, blackfin, ia64, parisc, sparc, sparc64, mips, sh\n\nm86knommu is generic_be for Coldfire, otherwise unaligned access is ok.\n\nfrv, arm chooses endianness based on compiler settings, uses the byteshifting\nversions. Remove the unaligned trap handler from frv as it is now unused.\n\nv850 is le, uses the byteshifting versions for both be and le.\n\nRemove the now unused asm-generic implementation.\n\nSigned-off-by: Harvey Harrison \u003charvey.harrison@gmail.com\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\nCc: \u003clinux-arch@vger.kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "e122eaf69422e5d9ce93fc9786099098e3b9e1c4", "tree": "2300448ae2e0ea454619de01c3ca59715d861fe8", "parents": [ "a8e93ed8cb3d9aa22d192033009357526548c825" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Wed Jun 20 15:29:15 2007 +0200" }, "committer": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Wed Jul 18 20:45:51 2007 +0200" }, "message": "[AVR32] Remove optimization of unaligned word loads\n\nIf we let unaligned word loads bypass the generic unaligned handling,\ngcc may combine it with a swap.b instruction and turn it into a ldwsp\ninstruction, which does not work with unaligned addresses.\n\nRevert the optimization to prevent the RNDIS driver from crashing.\nHopefully we\u0027ll figure something out later (it may be better to do the\noptimization in gcc.)\n\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n" }, { "commit": "c6083cd61b5a64a1c73d1634744382f54cb99595", "tree": "4ad4409a074a9de87a03bc2162d27e326f2c0498", "parents": [ "8b4a40809e5330c9da5d20107d693d92d73b31dc" ], "author": { "name": "David Brownell", "email": "david-b@pacbell.net", "time": "Fri May 25 18:47:47 2007 -0700" }, "committer": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Wed Jul 18 20:45:50 2007 +0200" }, "message": "[AVR32] faster avr32 unaligned access\n\nUse a more conventional implementation for unaligned access, and include\nan AT32AP-specific optimization: the CPU will handle unaligned words.\n\nThe result is always faster and smaller for 8, 16, and 32 bit values.\nFor 64 bit quantities, it\u0027s presumably larger.\n\nSigned-off-by: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n" }, { "commit": "5f97f7f9400de47ae837170bb274e90ad3934386", "tree": "514451e6dc6b46253293a00035d375e77b1c65ed", "parents": [ "53e62d3aaa60590d4a69b4e07c29f448b5151047" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Mon Sep 25 23:32:13 2006 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Tue Sep 26 08:48:54 2006 -0700" }, "message": "[PATCH] avr32 architecture\n\nThis adds support for the Atmel AVR32 architecture as well as the AT32AP7000\nCPU and the AT32STK1000 development board.\n\nAVR32 is a new high-performance 32-bit RISC microprocessor core, designed for\ncost-sensitive embedded applications, with particular emphasis on low power\nconsumption and high code density. The AVR32 architecture is not binary\ncompatible with earlier 8-bit AVR architectures.\n\nThe AVR32 architecture, including the instruction set, is described by the\nAVR32 Architecture Manual, available from\n\nhttp://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf\n\nThe Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It\nfeatures a 7-stage pipeline, 16KB instruction and data caches and a full\nMemory Management Unit. It also comes with a large set of integrated\nperipherals, many of which are shared with the AT91 ARM-based controllers from\nAtmel.\n\nFull data sheet is available from\n\nhttp://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf\n\nwhile the CPU core implementation including caches and MMU is documented by\nthe AVR32 AP Technical Reference, available from\n\nhttp://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf\n\nInformation about the AT32STK1000 development board can be found at\n\nhttp://www.atmel.com/dyn/products/tools_card.asp?tool_id\u003d3918\n\nincluding a BSP CD image with an earlier version of this patch, development\ntools (binaries and source/patches) and a root filesystem image suitable for\nbooting from SD card.\n\nAlternatively, there\u0027s a preliminary \"getting started\" guide available at\nhttp://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links\nto the sources and patches you will need in order to set up a cross-compiling\nenvironment for avr32-linux.\n\nThis patch, as well as the other patches included with the BSP and the\ntoolchain patches, is actively supported by Atmel Corporation.\n\n[dmccr@us.ibm.com: Fix more pxx_page macro locations]\n[bunk@stusta.de: fix `make defconfig\u0027]\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nSigned-off-by: Adrian Bunk \u003cbunk@stusta.de\u003e\nSigned-off-by: Dave McCracken \u003cdmccr@us.ibm.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" } ] }