)]}'
{
  "log": [
    {
      "commit": "0c42bd0e425e9c8ddb7019fc446f7d915e36c5f6",
      "tree": "8d89f7b5907bed52847451ab37619e9516ed7c3c",
      "parents": [
        "b3c567e474b5ba4447b6e16063a3b0cffc22d205"
      ],
      "author": {
        "name": "Yong Wang",
        "email": "yong.y.wang@linux.intel.com",
        "time": "Fri Jul 30 16:23:03 2010 +0800"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Aug 04 14:12:05 2010 -0700"
      },
      "message": "dmaengine: Driver for Topcliff PCH DMA controller\n\nTopcliff PCH is the platform controller hub that is going to\nbe used in Intel\u0027s upcoming general embedded platforms. This\nadds the driver for Topcliff PCH DMA controller. The DMA\nchannels are strictly for device to host or host to device\ntransfers and cannot be used for generic memcpy.\n\nSigned-off-by: Yong Wang \u003cyong.y.wang@intel.com\u003e\n[kill GFP_ATOMIC, kill __raw_{read|write}l, locking fixlet]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "b3c567e474b5ba4447b6e16063a3b0cffc22d205",
      "tree": "fa5f4f72fcf12dc53a5e58b5359038864595fe3e",
      "parents": [
        "084a2ab9c258fb1efbb009f1bb1c6976da1f73f4"
      ],
      "author": {
        "name": "Vinod Koul",
        "email": "vinod.koul@intel.com",
        "time": "Wed Jul 21 13:28:10 2010 +0530"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 27 23:32:57 2010 -0700"
      },
      "message": "intel_mid: Add Mrst \u0026 Mfld DMA Drivers\n\nThis patch add DMA drivers for DMA controllers in Langwell chipset\nof Intel(R) Moorestown platform and DMA controllers in Penwell of\nIntel(R) Medfield platfrom\n\nThis patch adds support for Moorestown DMAC1 and DMAC2 controllers.\nIt also add support for Medfiled GP DMA and DMAC1 controllers.\nThese controllers supports memory to peripheral and peripheral to\nmemory transfers. It support only single block transfers.\n\nThis driver is based on Kernel DMA engine\nAnyone who wishes to use this controller should use DMA engine APIs\n\nThis controller exposes DMA_SLAVE capabilities and notifies the client drivers\nof DMA transaction completion\n\nConfig option required to be enabled CONFIG_INTEL_MID_DMAC\u003dy\n\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "b3040e40675ec2c43542331cd30d4ee3dae797e8",
      "tree": "a327c4a92118dd0e1c61b8455e744910cd121f57",
      "parents": [
        "6f68fbaafbaa033205cd131d3e1f3c4b914e9b78"
      ],
      "author": {
        "name": "Jassi Brar",
        "email": "jassi.brar@samsung.com",
        "time": "Sun May 23 20:28:19 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sun May 23 20:28:19 2010 -0700"
      },
      "message": "DMA: PL330: Add dma api driver\n\nAdd DMA Engine API driver for the PL330 DMAC.\nThis driver is supposed to be reusable by various\nplatforms that have one or more PL330 DMACs.\nAtm, DMA_SLAVE and DMA_MEMCPY capabilities have been\nimplemented.\n\nSigned-off-by: Jassi Brar \u003cjassi.brar@samsung.com\u003e\nReviewed-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\n[dan.j.williams@intel.com: missing slab.h and -\u003edevice_control() fixups]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "8d318a50b3d72e3daf94131f91e1ab799a8d5ad4",
      "tree": "ae36452931d2e836f725b3f91eebd7f4d9e27589",
      "parents": [
        "6a3cd3ea48584d14f60dce0b3c4e9e4428beb0fe"
      ],
      "author": {
        "name": "Linus Walleij",
        "email": "linus.walleij@stericsson.com",
        "time": "Tue Mar 30 15:33:42 2010 +0200"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Apr 14 14:49:20 2010 -0700"
      },
      "message": "DMAENGINE: Support for ST-Ericssons DMA40 block v3\n\nThis is a straightforward driver for the ST-Ericsson DMA40 DMA\ncontroller found in U8500, implemented akin to the existing\nCOH 901 318 driver.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Srinidh Kasagar \u003csrinidhi.kasagar@stericsson.com\u003e\nCc: STEricsson_nomadik_linux@list.st.com\nCc: Alessandro Rubini \u003crubini@unipv.it\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "de5d4453c5b224eefd02b6a141ed411a76d458af",
      "tree": "2c208ec52e52363b1f403b82b570b843e98d1384",
      "parents": [
        "84c8447c544bc7579097649273bc3f4e1b5de6af"
      ],
      "author": {
        "name": "Richard Röjfors",
        "email": "richard.rojfors@pelagicore.com",
        "time": "Thu Mar 25 19:44:21 2010 +0100"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Mar 25 17:18:43 2010 -0700"
      },
      "message": "dma: Add timb-dma\n\nAdds the support for the DMA engine withing the timberdale FPGA.\n\nThe DMA channels are strict device to host, or host to device\nand can not be used for generic memcpy.\n\nSigned-off-by: Richard Röjfors \u003crichard.rojfors@pelagicore.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "0fb6f739bb612bc989d295056877374b749e721b",
      "tree": "a7105b3d73736535b3bdb0f15f8f8c0869b81279",
      "parents": [
        "6c664a8915f5341c2e7f1df0bb4b9b4a88f6ad77"
      ],
      "author": {
        "name": "Piotr Ziecik",
        "email": "kosmo@semihalf.com",
        "time": "Fri Feb 05 03:42:52 2010 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Mar 01 22:16:42 2010 -0700"
      },
      "message": "dma: Add MPC512x DMA driver\n\nAdds initial version of MPC512x DMA driver.\nOnly memory to memory transfers are currenly supported.\n\nSigned-off-by: Piotr Ziecik \u003ckosmo@semihalf.com\u003e\nSigned-off-by: Wolfgang Denk \u003cwd@denx.de\u003e\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nCc: John Rigby \u003cjcrigby@gmail.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "6c664a8915f5341c2e7f1df0bb4b9b4a88f6ad77",
      "tree": "031bab9e62b2948ef3fc8a0a3223e8074bc201bb",
      "parents": [
        "f1acb878b6070941e844dfc4ca1b3b9e5a70426c"
      ],
      "author": {
        "name": "Linus Walleij",
        "email": "linus.walleij@stericsson.com",
        "time": "Tue Feb 09 22:34:54 2010 +0100"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Mar 01 22:13:20 2010 -0700"
      },
      "message": "Debugging options for the DMA engine subsystem\n\nThis adds Kconfig options for DEBUG and VERBOSE_DEBUG to the DMA\nengine subsystem, I got tired of editing the Makefile manually\neach time I want to debug things in here, modelled this on the\ndebug switches for other subsystems and works like a charm when\nworking on our DMA engines.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "12458ea06efd7b44281e68fe59c950ec7d59c649",
      "tree": "264df3c6fa054b7b866bb2eccca5f83e41044632",
      "parents": [
        "2e032b62c4c8560d6416ad3cc925cfc2a5eafb07"
      ],
      "author": {
        "name": "Anatolij Gustschin",
        "email": "agust@denx.de",
        "time": "Fri Dec 11 21:24:44 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Dec 11 21:24:44 2009 -0700"
      },
      "message": "ppc440spe-adma: adds updated ppc440spe adma driver\n\nThis patch adds new version of the PPC440SPe ADMA driver.\n\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "61f135b92f4758bc4d4767cd0a5d2da954e27f14",
      "tree": "388fdc08150e2f8fcb2859f70ca67cdd86616f36",
      "parents": [
        "b419148e567728f6af0c3b01965c1cc141e3e13a"
      ],
      "author": {
        "name": "Linus Walleij",
        "email": "linus.walleij@stericsson.com",
        "time": "Thu Nov 19 19:49:17 2009 +0100"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 23:45:19 2009 -0700"
      },
      "message": "Add COH 901 318 DMA block driver v5\n\nThis patch adds support for the ST-Ericsson COH 901 318 DMA block,\nfound in the U300 series platforms. It registers a DMA slave for\ndevice I/O and also a memcpy slave for memcpy.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "d8902adcc1a9fd484c8cb5e575152e32192c1ff8",
      "tree": "305109ce60db5ea9710dddce9db8a23f65ff4572",
      "parents": [
        "9134d02bc0af4a8747d448d1f811ec5f8eb96df6"
      ],
      "author": {
        "name": "Nobuhiro Iwamatsu",
        "email": "iwamatsu.nobuhiro@renesas.com",
        "time": "Mon Sep 07 03:26:23 2009 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:56:02 2009 -0700"
      },
      "message": "dmaengine: sh: Add Support SuperH DMA Engine driver\n\nThis supported all DMA channels, and it was tested in SH7722,\nSH7780, SH7785 and SH7763.\nThis can not use with SH DMA API.\n\nSigned-off-by: Nobuhiro Iwamatsu \u003ciwamatsu.nobuhiro@renesas.com\u003e\nReviewed-by: Matt Fleming \u003cmatt@console-pimps.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "e12c4fa377ffda2490476caae17f24daaf9c9bd7",
      "tree": "aa7a19d8f7f931709a8a835a4b0d441f83d759fd",
      "parents": [
        "a348a7e6fdbcd2d5192a09719a479bb238fde727",
        "4b652f0db3be891c7b76b109c3b55003b920fc96"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:52:57 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:52:57 2009 -0700"
      },
      "message": "Merge branch \u0027ioat\u0027 into dmaengine\n"
    },
    {
      "commit": "a348a7e6fdbcd2d5192a09719a479bb238fde727",
      "tree": "5ff94185f4e5a810777469d7fe7832a8ec2d3430",
      "parents": [
        "808347f6a31792079e345ec865e9cfcb6e8ae6b2",
        "28d0325ce6e0a52f53d8af687e6427fee59004d3"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 14:32:24 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 14:32:24 2009 -0700"
      },
      "message": "Merge commit \u0027v2.6.31-rc1\u0027 into dmaengine\n"
    },
    {
      "commit": "584ec22759c06cdfc189c03a727f20038526245b",
      "tree": "54f4ebb99c3f66f62aeb38d091d1840d88e2ee57",
      "parents": [
        "07a2039b8eb0af4ff464efd3dfd95de5c02648c6"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:32:12 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:32:12 2009 -0700"
      },
      "message": "ioat: move to drivers/dma/ioat/\n\nWhen first created the ioat driver was the only inhabitant of\ndrivers/dma/.  Now, it is the only multi-file (more than a .c and a .h)\ndriver in the directory.  Moving it to an ioat/ subdirectory allows the\nnaming convention to be cleaned up, and allows for future splitting of\nthe source files by hardware version (v1, v2, and v3).\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "dc78baa2b90b289590911b40b6800f77d0dc935a",
      "tree": "db54dedb1e13a413190ad637ccaf6f5557dc9c10",
      "parents": [
        "f1aef8b6e6abf32a3a269542f95a19e2cb319f6c"
      ],
      "author": {
        "name": "Nicolas Ferre",
        "email": "nicolas.ferre@atmel.com",
        "time": "Fri Jul 03 19:24:33 2009 +0200"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Jul 22 22:41:27 2009 -0700"
      },
      "message": "dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller\n\nThis AHB DMA Controller (aka HDMA or DMAC on AT91 systems) is availlable on\nat91sam9rl chip. It will be used on other products in the future.\n\nThis first release covers only the memory-to-memory tranfer type. This is the\nonly tranfer type supported by this chip.  On other products, it will be used\nalso for peripheral DMA transfer (slave API support to come).\n\nI used dmatest client without problem in different configurations to test it.\n\nFull documentation for this controller can be found in the SAM9RL datasheet:\nhttp://www.atmel.com/dyn/products/product_card.asp?part_id\u003d4243\n\nSigned-off-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "ea76f0b3759283ec3cc06c86e266bf0fa6a981d2",
      "tree": "36719ab69e7d94cc59c909526022219376807313",
      "parents": [
        "a43da03ca4719276b9601730627d20b2a71fb6ba"
      ],
      "author": {
        "name": "Atsushi Nemoto",
        "email": "anemo@mba.ocn.ne.jp",
        "time": "Thu Apr 23 00:40:30 2009 +0900"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Wed Jun 17 11:06:25 2009 +0100"
      },
      "message": "DMA: TXx9 Soc DMA Controller driver\n\nThis patch adds support for the integrated DMAC of the TXx9 family.\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "5296b56d1b2000b60fb966be161c1f8fb629786b",
      "tree": "18277748caa9ba43610f76a310d34a3b2155e1a5",
      "parents": [
        "ef560682a97491f62ef538931a4861b57d66c52c"
      ],
      "author": {
        "name": "Guennadi Liakhovetski",
        "email": "lg@denx.de",
        "time": "Mon Jan 19 15:36:21 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Jan 19 15:36:21 2009 -0700"
      },
      "message": "i.MX31: Image Processing Unit DMA and IRQ drivers\n\ni.MX3x SoCs contain an Image Processing Unit, consisting of a Control\nModule (CM), Display Interface (DI), Synchronous Display Controller (SDC),\nAsynchronous Display Controller (ADC), Image Converter (IC), Post-Filter\n(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).\nCM contains, among other blocks, an Interrupt Generator (IG) and a Clock\nand Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are\nsupported over dmaengine and irq-chip APIs respectively.\n\nIDMAC is a specialised DMA controller, its DMA channels cannot be used for\ngeneral-purpose operations, even though it might be possible to configure\na memory-to-memory channel for memcpy operation. This driver will not work\nwith generic dmaengine clients, clients, wishing to use it must use\nrespective wrapper structures, they also must specify which channels they\nrequire, as channels are hard-wired to specific IPU functions.\n\nAcked-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "3bfb1d20b547a5071d01344581eac5846ea84491",
      "tree": "3cdbd3b5d59c93f257573cc894db2a000698f02b",
      "parents": [
        "dc0ee6435cb92ccc81b14ff28d163fecc5a7f120"
      ],
      "author": {
        "name": "Haavard Skinnemoen",
        "email": "haavard.skinnemoen@atmel.com",
        "time": "Tue Jul 08 11:59:42 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 08 11:59:42 2008 -0700"
      },
      "message": "dmaengine: Driver for the Synopsys DesignWare DMA controller\n\nThis adds a driver for the Synopsys DesignWare DMA controller (aka\nDMACA on AVR32 systems.) This DMA controller can be found integrated\non the AT32AP7000 chip and is primarily meant for peripheral DMA\ntransfer, but can also be used for memory-to-memory transfers.\n\nThis patch is based on a driver from David Brownell which was based on\nan older version of the DMA Engine framework. It also implements the\nproposed extensions to the DMA Engine API for slave DMA operations.\n\nThe dmatest client shows no problems, but there may still be room for\nimprovement performance-wise. DMA slave transfer performance is\ndefinitely \"good enough\"; reading 100 MiB from an SD card running at ~20\nMHz yields ~7.2 MiB/s average transfer rate.\n\nFull documentation for this controller can be found in the Synopsys\nDW AHB DMAC Databook:\n\nhttp://www.synopsys.com/designware/docs/iip/DW_ahb_dmac/latest/doc/dw_ahb_dmac_db.pdf\n\nThe controller has lots of implementation options, so it\u0027s usually a\ngood idea to check the data sheet of the chip it\u0027s intergrated on as\nwell. The AT32AP7000 data sheet can be found here:\n\nhttp://www.atmel.com/dyn/products/datasheets.asp?family_id\u003d682\n\n\nChanges since v4:\n  * Use client_count instead of dma_chan_is_in_use()\n  * Add missing include\n  * Unmap buffers unless client told us not to\n\nChanges since v3:\n  * Update to latest DMA engine and DMA slave APIs\n  * Embed the hw descriptor into the sw descriptor\n  * Clean up and update MODULE_DESCRIPTION, copyright date, etc.\n\nChanges since v2:\n  * Dequeue all pending transfers in terminate_all()\n  * Rename dw_dmac.h -\u003e dw_dmac_regs.h\n  * Define and use controller-specific dma_slave data\n  * Fix up a few outdated comments\n  * Define hardware registers as structs (doesn\u0027t generate better\n    code, unfortunately, but it looks nicer.)\n  * Get number of channels from platform_data instead of hardcoding it\n    based on CONFIG_WHATEVER_CPU.\n  * Give slave clients exclusive access to the channel\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e,\nSigned-off-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "4a776f0aa922a552460192c07b56f4fe9cd82632",
      "tree": "ae6c2fef63e40fcdcac22483f3aa35eab95e64de",
      "parents": [
        "ff7b04796d9866327ea76e1393f1e902ef032f84"
      ],
      "author": {
        "name": "Haavard Skinnemoen",
        "email": "hskinnemoen@atmel.com",
        "time": "Tue Jul 08 11:58:45 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 08 11:58:45 2008 -0700"
      },
      "message": "dmatest: Simple DMA memcpy test client\n\nThis client tests DMA memcpy using various lengths and various offsets\ninto the source and destination buffers. It will initialize both\nbuffers with a repeatable pattern and verify that the DMA engine copies\nthe requested region and nothing more. It will also verify that the\nbytes aren\u0027t swapped around, and that the source buffer isn\u0027t modified.\n\nThe dmatest module can be configured to test a specific device, a\nspecific channel. It can also test multiple channels at the same time,\nand it can start multiple threads competing for the same channel.\n\nChanges since v2:\n  * Support testing multiple channels at the same time\n  * Support testing with multiple threads competing for the same channel\n  * Use counting test patterns in order to catch byte ordering issues\n\nChanges since v1:\n  * Remove extra dashes around \"help\"\n  * Remove \"default n\" from Kconfig\n  * Turn TEST_BUF_SIZE into a module parameter\n  * Return DMA_NAK instead of DMA_DUP\n  * Print unhandled events\n  * Support testing specific channels and devices\n  * Move to the end of the Makefile\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "ff7b04796d9866327ea76e1393f1e902ef032f84",
      "tree": "42fd30c8e2051e7c6acc15da363960647030d3d3",
      "parents": [
        "ebabe2762607147d28aa395ea6df2a0ee7f795a1"
      ],
      "author": {
        "name": "Saeed Bishara",
        "email": "saeed@marvell.com",
        "time": "Tue Jul 08 11:58:36 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 08 11:58:36 2008 -0700"
      },
      "message": "dmaengine: DMA engine driver for Marvell XOR engine\n\nThe XOR engine found in Marvell\u0027s SoCs and system controllers\nprovides XOR and DMA operation, iSCSI CRC32C calculation, memory\ninitialization, and memory ECC error cleanup operation support.\n\nThis driver implements the DMA engine API and supports the following\ncapabilities:\n- memcpy\n- xor\n- memset\n\nThe XOR engine can be used by DMA engine clients implemented in the\nkernel, one of those clients is the RAID module.  In that case, I\nobserved 20% improvement in the raid5 write throughput, and 40%\ndecrease in the CPU utilization when doing array construction, those\nresults obtained on an 5182 running at 500Mhz.\n\nWhen enabling the NET DMA client, the performance decreased, so\nmeanwhile it is recommended to keep this client off.\n\nSigned-off-by: Saeed Bishara \u003csaeed@marvell.com\u003e\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "173acc7ce8538f1f3040791dc622a92aadc12cf4",
      "tree": "f408e415851cf3343af6077287984169958951ad",
      "parents": [
        "976dde010e513a9c7c3117a32b7b015f84b37430"
      ],
      "author": {
        "name": "Zhang Wei",
        "email": "wei.zhang@freescale.com",
        "time": "Sat Mar 01 07:42:48 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Mar 04 10:16:46 2008 -0700"
      },
      "message": "dmaengine: add driver for Freescale MPC85xx DMA controller\n\nThe driver implements DMA engine API for Freescale MPC85xx DMA controller,\nwhich could be used by devices in the silicon.  The driver supports the\nBasic mode of Freescale MPC85xx DMA controller.  The MPC85xx processors\nsupported include MPC8540/60, MPC8555, MPC8548, MPC8641 and so on.\n\nThe MPC83xx(MPC8349, MPC8360) are also supported.\n\n[kamalesh@linux.vnet.ibm.com: build fix]\n[dan.j.williams@intel.com: merge mm fixes, rebase on async_tx-2.6.25]\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by: Ebony Zhu \u003cebony.zhu@freescale.com\u003e\nAcked-by: Kumar Gala \u003cgalak@gate.crashing.org\u003e\nCc: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Paul Mackerras \u003cpaulus@samba.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "2ed6dc34f9ed39bb8e4c81ea1056f0ba56315841",
      "tree": "e3f6ca7961f9c4e34453d06e584c0bc98ec630d7",
      "parents": [
        "7589670f37736bcc119ebfbd69aafea6d585d1d4"
      ],
      "author": {
        "name": "Shannon Nelson",
        "email": "shannon.nelson@intel.com",
        "time": "Tue Oct 16 01:27:42 2007 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Tue Oct 16 09:43:09 2007 -0700"
      },
      "message": "I/OAT: Add DCA services\n\nAdd code to connect to the DCA driver and provide cpu tags for use by\ndrivers that would like to use Direct Cache Access hints.\n\n    [Adrian Bunk]                Several Kconfig cleanup items\n    [Andrew Morten, Chris Leech] Fix for using cpu_physical_id() even when\n\t\t\t         built for uni-processor\n\nSigned-off-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "8ab89567da0cea9bae2c1b5dad47b51c424479e4",
      "tree": "95ac8bc77b2e8d9f1dec97f6fd7128760e27561f",
      "parents": [
        "43d6e369d43ff175e1e0e80caaedb1e53829247c"
      ],
      "author": {
        "name": "Shannon Nelson",
        "email": "shannon.nelson@intel.com",
        "time": "Tue Oct 16 01:27:39 2007 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Tue Oct 16 09:43:09 2007 -0700"
      },
      "message": "I/OAT: Split PCI startup from DMA handling code\n\nSplit the general PCI startup from the DMA handling code in order to\nprepare for adding support for DCA services and future versions of the\nioatdma device.\n\n    [Rusty Russell] Removal of __unsafe() usage.\n\nSigned-off-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "1fda5f4e96225c3ed0baded942704c0ae399da23",
      "tree": "a16dbd8a674b8da8e5aed5cabcd497e63e3af754",
      "parents": [
        "223758c77a67b1eb383a92b35d67de29502a9f55"
      ],
      "author": {
        "name": "Shannon Nelson",
        "email": "shannon.nelson@intel.com",
        "time": "Tue Oct 16 01:27:37 2007 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Tue Oct 16 09:43:09 2007 -0700"
      },
      "message": "I/OAT: Rename the source file\n\nRename the ioatdma.c file in preparation for splitting into multiple files,\nwhich will allow for easier adding new functionality.\n\nSigned-off-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "c211092313b90f898dec61f35207fc282d1eadc3",
      "tree": "30df0c81f207d0babb3fe56a17419f37e71e973a",
      "parents": [
        "f6dff381af01006ffae3c23cd2e07e30584de0ec"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 02 13:52:26 2007 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Jul 13 08:06:18 2007 -0700"
      },
      "message": "dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines\n\nThe Intel(R) IOP series of i/o processors integrate an Xscale core with\nraid acceleration engines.  The capabilities per platform are:\n\niop219:\n (2) copy engines\niop321:\n (2) copy engines\n (1) xor and block fill engine\niop33x:\n (2) copy and crc32c engines\n (1) xor, xor zero sum, pq, pq zero sum, and block fill engine\niop34x (iop13xx):\n (2) copy, crc32c, xor, xor zero sum, and block fill engines\n (1) copy, crc32c, xor, xor zero sum, pq, pq zero sum, and block fill engine\n\nThe driver supports the features of the async_tx api:\n* asynchronous notification of operation completion\n* implicit (interupt triggered) handling of inter-channel transaction\n  dependencies\n\nThe driver adapts to the platform it is running by two methods.\n1/ #include \u003casm/arch/adma.h\u003e which defines the hardware specific\n   iop_chan_* and iop_desc_* routines as a series of static inline\n   functions\n2/ The private platform data attached to the platform_device defines the\n   capabilities of the channels\n\n20070626: Callbacks are run in a tasklet.  Given the recent discussion on\nLKML about killing tasklets in favor of workqueues I did a quick conversion\nof the driver.  Raid5 resync performance dropped from 50MB/s to 30MB/s, so\nthe tasklet implementation remains until a generic softirq interface is\navailable.\n\nChangelog:\n* fixed a slot allocation bug in do_iop13xx_adma_xor that caused too few\nslots to be requested eventually leading to data corruption\n* enabled the slot allocation routine to attempt to free slots before\nreturning -ENOMEM\n* switched the cleanup routine to solely use the software chain and the\nstatus register to determine if a descriptor is complete.  This is\nnecessary to support other IOP engines that do not have status writeback\ncapability\n* make the driver iop generic\n* modified the allocation routines to understand allocating a group of\nslots for a single operation\n* added a null xor initialization operation for the xor only channel on\niop3xx\n* support xor operations on buffers larger than the hardware maximum\n* split the do_* routines into separate prep, src/dest set, submit stages\n* added async_tx support (dependent operations initiation at cleanup time)\n* simplified group handling\n* added interrupt support (callbacks via tasklets)\n* brought the pending depth inline with ioat (i.e. 4 descriptors)\n* drop dma mapping methods, suggested by Chris Leech\n* don\u0027t use inline in C files, Adrian Bunk\n* remove static tasklet declarations\n* make iop_adma_alloc_slots easier to read and remove chances for a\n  corrupted descriptor chain\n* fix locking bug in iop_adma_alloc_chan_resources, Benjamin Herrenschmidt\n* convert capabilities over to dma_cap_mask_t\n* fixup sparse warnings\n* add descriptor flush before iop_chan_enable\n* checkpatch.pl fixes\n* gpl v2 only correction\n* move set_src, set_dest, submit to async_tx methods\n* move group_list and phys to async_tx\n\nCc: Russell King \u003crmk@arm.linux.org.uk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "de5506e155276d385712c2aa1c2d9a27cd4ed947",
      "tree": "219c30dab27b9aef2597d8735dfc19db8454849e",
      "parents": [
        "db21733488f84a596faaad0d05430b3f51804692"
      ],
      "author": {
        "name": "Chris Leech",
        "email": "christopher.leech@intel.com",
        "time": "Tue May 23 17:50:37 2006 -0700"
      },
      "committer": {
        "name": "David S. Miller",
        "email": "davem@sunset.davemloft.net",
        "time": "Sat Jun 17 21:25:46 2006 -0700"
      },
      "message": "[I/OAT]: Utility functions for offloading sk_buff to iovec copies\n\nProvides for pinning user space pages in memory, copying to iovecs,\nand copying from sk_buffs including fragmented and chained sk_buffs.\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n"
    },
    {
      "commit": "0bbd5f4e97ff9c057b385a1886b4aed1fb0300f1",
      "tree": "0c3d8528c31e8291fb78c2e7a287910987ed2888",
      "parents": [
        "c13c8260da3155f2cefb63b0d1b7dcdcb405c644"
      ],
      "author": {
        "name": "Chris Leech",
        "email": "christopher.leech@intel.com",
        "time": "Tue May 23 17:35:34 2006 -0700"
      },
      "committer": {
        "name": "David S. Miller",
        "email": "davem@sunset.davemloft.net",
        "time": "Sat Jun 17 21:18:46 2006 -0700"
      },
      "message": "[I/OAT]: Driver for the Intel(R) I/OAT DMA engine\n\nAdds a new ioatdma driver\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n"
    },
    {
      "commit": "c13c8260da3155f2cefb63b0d1b7dcdcb405c644",
      "tree": "ecfe02fa44a423a948f5fb5ad76497da2bb7a402",
      "parents": [
        "427abfa28afedffadfca9dd8b067eb6d36bac53f"
      ],
      "author": {
        "name": "Chris Leech",
        "email": "christopher.leech@intel.com",
        "time": "Tue May 23 17:18:44 2006 -0700"
      },
      "committer": {
        "name": "David S. Miller",
        "email": "davem@sunset.davemloft.net",
        "time": "Sat Jun 17 21:18:43 2006 -0700"
      },
      "message": "[I/OAT]: DMA memcpy subsystem\n\nProvides an API for offloading memory copies to DMA devices\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n"
    }
  ]
}