)]}' { "log": [ { "commit": "1cfd2bda8c486ae0e7a8005354758ebb68172bca", "tree": "76ce15f377d8d6eb3ae4aa8b8b0b415457e38d36", "parents": [ "b57bdda58cda0aaf6def042d101dd85977a286ed", "763e9db9994e27a7d2cb3701c8a097a867d0e0b4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 06 11:44:36 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 06 11:44:36 2010 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (30 commits)\n PCI: update for owner removal from struct device_attribute\n PCI: Fix warnings when CONFIG_DMI unset\n PCI: Do not run NVidia quirks related to MSI with MSI disabled\n x86/PCI: use for_each_pci_dev()\n PCI: use for_each_pci_dev()\n PCI: MSI: Restore read_msi_msg_desc(); add get_cached_msi_msg_desc()\n PCI: export SMBIOS provided firmware instance and label to sysfs\n PCI: Allow read/write access to sysfs I/O port resources\n x86/PCI: use host bridge _CRS info on ASRock ALiveSATA2-GLAN\n PCI: remove unused HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_{SIZE|BOUNDARY}\n PCI: disable mmio during bar sizing\n PCI: MSI: Remove unsafe and unnecessary hardware access\n PCI: Default PCIe ASPM control to on and require !EMBEDDED to disable\n PCI: kernel oops on access to pci proc file while hot-removal\n PCI: pci-sysfs: remove casts from void*\n ACPI: Disable ASPM if the platform won\u0027t provide _OSC control for PCIe\n PCI hotplug: make sure child bridges are enabled at hotplug time\n PCI hotplug: shpchp: Removed check for hotplug of display devices\n PCI hotplug: pciehp: Fixed return value sign for pciehp_unconfigure_device\n PCI: Don\u0027t enable aspm before drivers have had a chance to veto it\n ...\n" }, { "commit": "ea5f9fc5899660dd26c1ccf3fab183bd041140ee", "tree": "b0d0517ee4064cfb587651b195ee5d2be864a8cc", "parents": [ "8cc2bfd87fdd2f4a31f39c86f59df4b4be2c0adc" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Tue Jun 22 17:03:03 2010 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 30 09:29:34 2010 -0700" }, "message": "PCI: Default PCIe ASPM control to on and require !EMBEDDED to disable\n\nThe CONFIG_PCIEASPM option is confusing and potentially dangerous. ASPM is\na hardware mediated feature rather than one under direct OS control, and\neven if the config option is disabled the system firmware may have turned\non ASPM on various bits of hardware. This can cause problems later -\nvarious hardware that claims to support ASPM does a poor job of it and may\nhang or cause other difficulties. The kernel is able to recognise this in\nmany cases and disable the ASPM functionality, but only if CONFIG_PCIEASPM\nis enabled.\n\nGiven that in its default configuration this option will either leave the\nhardware as it was originally or disable hardware functionality that may\ncause problems, it should by default y. The only reason to disable it\nought to be to reduce code size, so make it dependent on CONFIG_EMBEDDED.\n\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nCc: lrodriguez@atheros.com\nCc: maximlevitsky@gmail.com\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "41cd766b065970ff6f6c89dd1cf55fa706c84a3d", "tree": "f52a7346daaaad331dbd260f0e21bcf9d108b2e6", "parents": [ "4302e0fb7fa5b071e30f3cfb68e85155b3d69d9b" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Wed Jun 09 16:05:07 2010 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 30 09:29:15 2010 -0700" }, "message": "PCI: Don\u0027t enable aspm before drivers have had a chance to veto it\n\nThe aspm code will currently set the configured aspm policy before drivers\nhave had an opportunity to indicate that their hardware doesn\u0027t support it.\nUnfortunately, putting some hardware in L0 or L1 can result in the hardware\nno longer responding to any requests, even after aspm is disabled. It makes\nmore sense to leave aspm policy at the BIOS defaults at initial setup time,\nreconfiguring it after pci_enable_device() is called. This allows the\ndriver to blacklist individual devices beforehand.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f6735590e9f441762ab5afeff64ded99e5b19a68", "tree": "58e15ba0d4c00195da9e9b199b7fc73de7f51e64", "parents": [ "73cd3b43f08cc9a9bcb168994b8e9ebd983ff573" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu May 27 11:21:11 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 30 09:29:10 2010 -0700" }, "message": "PCI aerdrv: fix annoying warnings\n\nSome compiler generates following warnings:\n\n In function \u0027aer_isr\u0027:\n warning: \u0027e_src.id\u0027 may be used uninitialized in this function\n warning: \u0027e_src.status\u0027 may be used uninitialized in this function\n\nAvoid status flag \"int ret\" and return constants instead, so that\ngcc sees the return value matching \"it is initialized\" better.\n\nAcked-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c125e96f044427f38d106fab7bc5e4a5e6a18262", "tree": "d9bbd40cc933fe522dbdf8ca2f7edf7b6f2f7ca4", "parents": [ "b14e033e17d0ea0ba12668d0d2f371cd31586994" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Jul 05 22:43:53 2010 +0200" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Jul 19 01:58:48 2010 +0200" }, "message": "PM: Make it possible to avoid races between wakeup and system sleep\n\nOne of the arguments during the suspend blockers discussion was that\nthe mainline kernel didn\u0027t contain any mechanisms making it possible\nto avoid races between wakeup and system suspend.\n\nGenerally, there are two problems in that area. First, if a wakeup\nevent occurs exactly when /sys/power/state is being written to, it\nmay be delivered to user space right before the freezer kicks in, so\nthe user space consumer of the event may not be able to process it\nbefore the system is suspended. Second, if a wakeup event occurs\nafter user space has been frozen, it is not generally guaranteed that\nthe ongoing transition of the system into a sleep state will be\naborted.\n\nTo address these issues introduce a new global sysfs attribute,\n/sys/power/wakeup_count, associated with a running counter of wakeup\nevents and three helper functions, pm_stay_awake(), pm_relax(), and\npm_wakeup_event(), that may be used by kernel subsystems to control\nthe behavior of this attribute and to request the PM core to abort\nsystem transitions into a sleep state already in progress.\n\nThe /sys/power/wakeup_count file may be read from or written to by\nuser space. Reads will always succeed (unless interrupted by a\nsignal) and return the current value of the wakeup events counter.\nWrites, however, will only succeed if the written number is equal to\nthe current value of the wakeup events counter. If a write is\nsuccessful, it will cause the kernel to save the current value of the\nwakeup events counter and to abort the subsequent system transition\ninto a sleep state if any wakeup events are reported after the write\nhas returned.\n\n[The assumption is that before writing to /sys/power/state user space\nwill first read from /sys/power/wakeup_count. Next, user space\nconsumers of wakeup events will have a chance to acknowledge or\nveto the upcoming system transition to a sleep state. Finally, if\nthe transition is allowed to proceed, /sys/power/wakeup_count will\nbe written to and if that succeeds, /sys/power/state will be written\nto as well. Still, if any wakeup events are reported to the PM core\nby kernel subsystems after that point, the transition will be\naborted.]\n\nAdditionally, put a wakeup events counter into struct dev_pm_info and\nmake these per-device wakeup event counters available via sysfs,\nso that it\u0027s possible to check the activity of various wakeup event\nsources within the kernel.\n\nTo illustrate how subsystems can use pm_wakeup_event(), make the\nlow-level PCI runtime PM wakeup-handling code use it.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nAcked-by: markgross \u003cmarkgross@thegnar.org\u003e\nReviewed-by: Alan Stern \u003cstern@rowland.harvard.edu\u003e\n" }, { "commit": "b27759f880018b0cd43543dc94c921341b64b5ec", "tree": "486e63a80e0f11d93f9f8ee3a5780b5030154cd0", "parents": [ "7e27d6e778cd87b6f2415515d7127eba53fe5d02" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Fri Jun 18 17:04:22 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jun 18 09:36:37 2010 -0700" }, "message": "PCI/PM: Do not use native PCIe PME by default\n\nCommit c7f486567c1d0acd2e4166c47069835b9f75e77b\n(PCI PM: PCIe PME root port service driver) causes the native PCIe\nPME signaling to be used by default, if the BIOS allows the kernel to\ncontrol the standard configuration registers of PCIe root ports.\nHowever, the native PCIe PME is coupled to the native PCIe hotplug\nand calling pcie_pme_acpi_setup() makes some BIOSes expect that\nthe native PCIe hotplug will be used as well. That, in turn, causes\nproblems to appear on systems where the PCIe hotplug driver is not\nloaded. The usual symptom, as reported by Jaroslav Kameník and\nothers, is that the ACPI GPE associated with PCIe hotplug keeps\nfiring continuously causing kacpid to take substantial percentage\nof CPU time.\n\nTo work around this issue, change the default so that the native\nPCIe PME signaling is only used if directly requested with the help\nof the pcie_pme\u003d command line switch.\n\nFixes https://bugzilla.kernel.org/show_bug.cgi?id\u003d15924 , which is\na listed regression from 2.6.33.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nReported-by: Jaroslav Kameník \u003cjaroslav@kamenik.cz\u003e\nTested-by: Antoni Grzymala \u003cantekgrzymala@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9a90e09854a3c7cc603ab8fc9163f77bb1f66cfa", "tree": "c8c5f767dd2351c9db440f003cc14401583bafd3", "parents": [ "d372e7fe4698bde3a00b718f7901a0025dda47ef", "d3b383338f105f50724c10a7d81b04a3930e886b" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 28 14:42:18 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 28 14:42:18 2010 -0700" }, "message": "Merge branch \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6\n\n* \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: (27 commits)\n ACPI: Don\u0027t let acpi_pad needlessly mark TSC unstable\n drivers/acpi/sleep.h: Checkpatch cleanup\n ACPI: Minor cleanup eliminating redundant PMTIMER_TICKS to NS conversion\n ACPI: delete unused c-state promotion/demotion data strucutures\n ACPI: video: fix acpi_backlight\u003dvideo\n ACPI: EC: Use kmemdup\n drivers/acpi: use kasprintf\n ACPI, APEI, EINJ injection parameters support\n Add x64 support to debugfs\n ACPI, APEI, Use ERST for persistent storage of MCE\n ACPI, APEI, Error Record Serialization Table (ERST) support\n ACPI, APEI, Generic Hardware Error Source memory error support\n ACPI, APEI, UEFI Common Platform Error Record (CPER) header\n Unified UUID/GUID definition\n ACPI Hardware Error Device (PNP0C33) support\n ACPI, APEI, PCIE AER, use general HEST table parsing in AER firmware_first setup\n ACPI, APEI, Document for APEI\n ACPI, APEI, EINJ support\n ACPI, APEI, HEST table parsing\n ACPI, APEI, APEI supporting infrastructure\n ...\n" }, { "commit": "affb72c3a8984ba55e055b0a0228c3ea1a056758", "tree": "a6d4c9051110c03f9222bde9c3dcea7822f8570c", "parents": [ "ea8c071cad789b1919355fc7a67182a5c9994e6b" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Tue May 18 14:35:16 2010 +0800" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed May 19 22:40:14 2010 -0400" }, "message": "ACPI, APEI, PCIE AER, use general HEST table parsing in AER firmware_first setup\n\nNow, a dedicated HEST tabling parsing code is used for PCIE AER\nfirmware_first setup. It is rebased on general HEST tabling parsing\ncode of APEI. The firmware_first setup code is moved from PCI core to\nAER driver too, because it is only AER related.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andi Kleen \u003cak@linux.intel.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "caa5afbd4831c649b951ae1227a7985f47547e31", "tree": "5000986023ae83933a94795ab1bc22519f9d4e80", "parents": [ "f6d3780061283039de33b402c35c3bf9322afe14" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:23:17 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:40 2010 -0700" }, "message": "PCI: aerdrv: trivial cleanup for aerdrv_core.c\n\nStyle cleanup for pci_{en,dis}able_pcie_error_reporting().\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f6d3780061283039de33b402c35c3bf9322afe14", "tree": "67ec48ba847e45e372d20f93facb658c4d6f2b4f", "parents": [ "89713422a768458a0d375f0c2f3586cd5ccde6a1" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:22:11 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:39 2010 -0700" }, "message": "PCI: aerdrv: trivial cleanup for aerdrv.c\n\nSkip zero-ing in aer_alloc_rpc() since it is allocated by kzalloc().\nThe closing comment marker \"*/\" is recommended for kernel-doc comments.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "89713422a768458a0d375f0c2f3586cd5ccde6a1", "tree": "c446440123602cdb5320617ac7a8c2dbf514ff41", "parents": [ "517cae3829ae8cc3033c24f60e64eb251b2f0d14" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:21:27 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:38 2010 -0700" }, "message": "PCI: aerdrv: introduce default_downstream_reset_link\n\nI noticed that when I inject a fatal error to an endpoint via\naer-inject, aer_root_reset() is called as reset_link for a\ndownstream port at upstream of the endpoint:\n\n pcieport 0000:00:06.0: AER: Uncorrected (Fatal) error received: id\u003d5401\n :\n pcieport 0000:52:02.0: Root Port link has been reset\n\nIt externally appears to be working, but internally issues some\naccesses to PCI_ERR_ROOT_COMMAND/STATUS registers that is for\nroot port so not available on downstream port.\n\nThis patch introduces default_downstream_reset_link that is\na version of aer_root_reset() with no accesses to root port\u0027s\nregister. It is used for downstream ports that has no reset_link\nfunction its specific.\n\nThis patch also updates related description in pcieaer-howto.txt.\nSome minor fixes are included.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "517cae3829ae8cc3033c24f60e64eb251b2f0d14", "tree": "90f54b8aa311e16e3549bda1e1d7148bd631ddd9", "parents": [ "4f7ccf6a6085eefd2517b8c7090608c64b01ab67" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:20:43 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:38 2010 -0700" }, "message": "PCI: aerdrv: rework find_aer_service\n\nThe structure find_aer_service_data is no longer useful.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Jin Dongming \u003cjin.dongming@np.css.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4f7ccf6a6085eefd2517b8c7090608c64b01ab67", "tree": "41d6a5d595bb14cc537333e278f1a3ed4fc19cc4", "parents": [ "e167bfcaa4cd44b4c66206a3c06b2aafb3f1260e" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:19:48 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:37 2010 -0700" }, "message": "PCI: aerdrv: remove is_downstream\n\nThe pcie-\u003eport of port service device points the port associated\nthe service with. The find_aer_service iterates over children of\ngiven port udev.\n\nSo it is clear that the pcie-\u003eport of port service of given port\nudev must always point the udev.\n\nTherefore we can know the type of udev without checking its children.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e167bfcaa4cd44b4c66206a3c06b2aafb3f1260e", "tree": "cc21ae9a6f9efb3271b130e4e69ade52e71be871", "parents": [ "f647a44f5725b0e6c8211096f4b49900164123ee" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:18:26 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:37 2010 -0700" }, "message": "PCI: aerdrv: remove magical ROOT_ERR_STATUS_MASKS\n\nMake it clear that we only interest in 2 *_RCV bits.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f647a44f5725b0e6c8211096f4b49900164123ee", "tree": "dc5e677d978435159dd62e1faf0824fb01e44aa0", "parents": [ "17e21854bd59862f4ee47d1c7e828549f782711b" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:17:33 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:34 2010 -0700" }, "message": "PCI: aerdrv: redefine PCI_ERR_ROOT_*_SRC\n\nThe Error Source Identification Register (Offset 34h) is 4 byte\nwhich contains a couple of 2 byte field, \"[15:0] ERR_COR Source\nIdentification\" and \"[31:16] ERR_FATAL/NONFATAL Source Identification.\"\n\nThis patch defines PCI_ERR_ROOT_ERR_SRC to make dword access sensible.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "17e21854bd59862f4ee47d1c7e828549f782711b", "tree": "b1d7db096b4fa24e0522aa33de2710d2039924d0", "parents": [ "88da13bfabbffb8f89574eb168b9da9a0abc693f" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:16:52 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:33 2010 -0700" }, "message": "PCI: aerdrv: rework do_recovery\n\nMove dev_printks for debug into do_recovery().\nThis allows do_recovery() to return void.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "88da13bfabbffb8f89574eb168b9da9a0abc693f", "tree": "0d618bd5c2ddab8ba03d9b0c21b3998f2928d282", "parents": [ "7c4ec94f72cefec1c1b42219469794a34864a1ee" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:16:16 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:33 2010 -0700" }, "message": "PCI: aerdrv: rework get_e_source()\n\nCurrent get_e_source() returns pointer to an element of array.\nHowever since it also progress consume counter, it is possible\nthat the element is overwritten by newly produced data before\nthe element is really consumed.\n\nThis patch changes get_e_source() to copy contents of the element\nto address pointed by its caller. Once copied the element in\narray can be consumed.\n\nAnd relocate this function to more innocuous place.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7c4ec94f72cefec1c1b42219469794a34864a1ee", "tree": "349c45d1e61680926af565d234fa852cc88c17ed", "parents": [ "4a0c096efd4383fc98aa40e195363f600ba814f8" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:15:08 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:16 2010 -0700" }, "message": "PCI: aerdrv: rework aer_isr_one_error()\n\nDivide tricky for-loop into readable if-blocks.\n\nThe logic to set multi_error_valid (to force walking pci bus\nhierarchy to find 2nd~ error devices) is changed too, to check\nMULTI_{,_UN}COR_RCV bit individually and to force walk only when\nit is required.\n\nAnd rework setting e_info-\u003eseverity for uncorrectable, not to use\nmagic numbers.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4a0c096efd4383fc98aa40e195363f600ba814f8", "tree": "61f7f4aa18e7905b227f2de3622dd43403fc0551", "parents": [ "bd17d4742d5a8cbedd41a1d44c0cdee84a532363" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:14:17 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:15 2010 -0700" }, "message": "PCI: aerdrv: rework add_error_device\n\nStop iteration if we cannot register any more.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bd17d4742d5a8cbedd41a1d44c0cdee84a532363", "tree": "5df159b4dbd4ce1eaae5799ecc227e8e368c359e", "parents": [ "c887275e6a5b857b72c798e4a6019160a860e2ef" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:13:41 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:15 2010 -0700" }, "message": "PCI: aerdrv: remove compare_device_id\n\nInline too-simple subroutine only used here.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c887275e6a5b857b72c798e4a6019160a860e2ef", "tree": "8e8629859adcb9fcaacfd334f408d2949e1840b3", "parents": [ "98ca3964fe8da0d742331af80952443af5cff464" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:12:21 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:14 2010 -0700" }, "message": "PCI: aerdrv: introduce is_error_source\n\nTake core part of find_device_iter() to make a new function\nis_error_source() that checks given device has report an error\nor not.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "98ca3964fe8da0d742331af80952443af5cff464", "tree": "35c1b803496ca97322d88754de804117114a7c11", "parents": [ "843f4697eea576c24f057bbdb199115bbb6b10bc" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:11:42 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:14 2010 -0700" }, "message": "PCI: aerdrv: rework find_source_device\n\nReturn bool to indicate that the source device is found or not.\nThis allows us to skip calling aer_process_err_devices() if we can.\n\nAnd move dev_printk for debug into this function.\n\nv2: return bool instead of int\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "843f4697eea576c24f057bbdb199115bbb6b10bc", "tree": "889c40b06c3ca033733cf90f93184ec7917f9076", "parents": [ "460d298d521910483dcdc09920ca4c4a63b16730" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:10:53 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:13 2010 -0700" }, "message": "PCI: aerdrv: make aer_{en,dis}able_rootport static\n\nThese functions are only called from init/remove path of aerdrv,\nso move them from aerdrv_core.c to aerdrv.c, to make them static.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "460d298d521910483dcdc09920ca4c4a63b16730", "tree": "271ff70a7fa27992055de90da9dfeefd7ea5d0f4", "parents": [ "c6d34eddecb34fd84f9fb2ea26a63cfde5662f49" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:10:03 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:13 2010 -0700" }, "message": "PCI: aerdrv: cleanup inconsistent functions\n\nThis cleanup solves some minor naming issues by removing unuseful\nfunction aer_delete_rootport() and by renaming disable_root_aer()\nto aer_disable_rootport().\n\n- Inconsistent location of alloc \u0026 free:\n The struct rpc is allocated in aer_alloc_rpc() at aerdrv.c\n while it is implicitly freed in aer_delete_rootport() at\n aerdrv_core.c.\n\n- Inconsistent function name:\n It makes a bit confusion that aer_delete_rootport() is seemed\n to be paired with aer_enable_rootport(), i.e. there is neither\n \"add\" against \"delete\" nor \"disable\" against \"enable\".\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c6d34eddecb34fd84f9fb2ea26a63cfde5662f49", "tree": "a80ed52485693d649158621edcd8bd2d9431d3c9", "parents": [ "d4dfd7278eade24c4aa4b36b8df981fab04f2f26" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:09:13 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:12 2010 -0700" }, "message": "PCI: aerdrv: RsvdP of PCI_ERR_ROOT_COMMAND\n\nHandle preserved bits properly.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4352aa5bbf1d0080c2dcf904ce1e4be0a1cb5937", "tree": "cf30890e45bd359380a610444bd36ca7d96528dc", "parents": [ "73a0e614580fb650846be1e9315f6b7b6069b9cc" ], "author": { "name": "Alexander Duyck", "email": "alexander.h.duyck@intel.com", "time": "Thu Mar 25 13:03:30 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Apr 08 09:24:11 2010 -0700" }, "message": "PCI aerdrv: use correct bit defines and add 2ms delay to aer_root_reset\n\nWhile testing completion timeouts I found that hardware was not recovering.\nIt looks like the hot reset was never being propagated to the endpoint\ndevices on the bus due to the fact that we were clearing the bit too\nquickly.\n\nThe documentation I have states that we should be transmitting hot reset\nTS1s for 2ms. To achieve this I have added a 2ms delay from the time we\nset the secondary bus reset bit to the time we clear it. In addition I\nchanged the define used for the secondary bus reset bit to match the\nregister define that was being used.\n\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Alexander Duyck \u003calexander.h.duyck@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05", "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1", "parents": [ "ed391f4ebf8f701d3566423ce8f17e614cde9806" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Mar 24 17:04:11 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Mar 30 22:02:32 2010 +0900" }, "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files. percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed. Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability. As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n only the necessary includes are there. ie. if only gfp is used,\n gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n blocks and try to put the new include such that its order conforms\n to its surrounding. It\u0027s put in the include block which contains\n core kernel includes, in the same order that the rest are ordered -\n alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n because the file doesn\u0027t have fitting include block), it prints out\n an error message indicating which .h file needs to be added to the\n file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n and ~3000 slab.h inclusions. The script emitted errors for ~400\n files.\n\n2. Each error was manually checked. Some didn\u0027t need the inclusion,\n some needed manual addition while adding it to implementation .h or\n embedding .c file was more appropriate for others. This step added\n inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n editing them as sprinkling gfp.h and slab.h inclusions around .h\n files could easily lead to inclusion dependency hell. Most gfp.h\n inclusion directives were ignored as stuff from gfp.h was usually\n wildly available and often used in preprocessor macros. Each\n slab.h inclusion directive was examined and added manually as\n necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my\n distributed build env didn\u0027t work with gcov compiles) and a few\n more options had to be turned off depending on archs to make things\n build (like ipr on powerpc/64 which failed due to missing writeq).\n\n * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n * powerpc and powerpc64 SMP allmodconfig\n * sparc and sparc64 SMP allmodconfig\n * ia64 SMP allmodconfig\n * s390 SMP allmodconfig\n * alpha SMP allmodconfig\n * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n" }, { "commit": "a1e4d72cd3024999bfb6703092ea271438805c89", "tree": "853a289d73ad9ffb04038fc493d209e980a3ef9b", "parents": [ "09c09bc618a4ceec387c57542031b4fc35826e16" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Feb 08 19:16:33 2010 +0100" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Fri Feb 26 20:39:12 2010 +0100" }, "message": "PM: Allow PCI devices to suspend/resume asynchronously\n\nSet power.async_suspend for all PCI devices and PCIe port services,\nso that they can be suspended and resumed in parallel with other\ndevices they don\u0027t depend on in a known way (i.e. devices which are\nnot their parents or children).\n\nThis only affects the \"regular\" suspend and resume stages, which\nmeans in particular that the restoration of the PCI devices\u0027 standard\nconfiguration registers during resume will still be carried out\nsynchronously (at the \"early\" resume stage).\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\n" }, { "commit": "b16694f70c40ea8d539cdc93a422039771e85870", "tree": "2ac80b596bff438d84c13224076aa474a3c8053c", "parents": [ "6cbf82148ff286ec22a55be6836c3a5bffc489c1" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Feb 22 14:13:39 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:21:21 2010 -0800" }, "message": "PCIe PME: use pci_pcie_cap()\n\nUse pci_pcie_cap() instead of pci_find_capability() to get PCIe\ncapability offset. This reduces redundant search in PCI configuration\nspace.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "552be54cc4232dc5acc49ccb372129d6f1b6923f", "tree": "65739c06da3ce6a68dfe8fa27d4438d0eb8166d4", "parents": [ "b67ea76172d4b1922c4b3c46c8ea8e9fec1ff38c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Feb 22 14:12:24 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:21:10 2010 -0800" }, "message": "PCIe PME: use pci_is_pcie()\n\nUse pci_is_pcie() instead of looking at obsolete is_pcie field in\nstruct pci_dev.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c39fae1416d59fd565606793f090cebe3720d50d", "tree": "f53b3dc3202706c328c2306f168058ec2e9ae859", "parents": [ "c7f486567c1d0acd2e4166c47069835b9f75e77b" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:40:07 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:20:39 2010 -0800" }, "message": "PCI PM: Make it possible to force using INTx for PCIe PME signaling\n\nApparently, some machines may have problems with PCI run-time power\nmanagement if MSIs are used for the native PCIe PME signaling. In\nparticular, on the MSI Wind U-100 PCIe PME interrupts are not\ngenerated by a PCIe root port after a resume from suspend to RAM, if\nthe system wake-up was triggered by a PME from the device attached to\nthis port. [It doesn\u0027t help to free the interrupt on suspend and\nrequest it back on resume, even if that is done along with disabling\nthe MSI and re-enabling it, respectively.] However, if INTx\ninterrupts are used for this purpose on the same machine, everything\nworks just fine.\n\nFor this reason, add a kernel command line switch allowing one to\nrequest that MSIs be not used for the native PCIe PME signaling,\nintroduce a DMI table allowing us to blacklist machines that need\nthis switch to be set by default and put the MSI Wind U-100 into this\ntable.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c7f486567c1d0acd2e4166c47069835b9f75e77b", "tree": "5552890ac80fc53f61dd9c53a6211610375efa1f", "parents": [ "58ff463396ad00828e922d50998787e97fd32512" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:39:08 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:20:31 2010 -0800" }, "message": "PCI PM: PCIe PME root port service driver\n\nPCIe native PME detection mechanism is based on interrupts generated\nby root ports or event collectors every time a PCIe device sends a\nPME message upstream.\n\nOnce a PME message has been sent by an endpoint device and received\nby its root port (or event collector in the case of root complex\nintegrated endpoints), the Requester ID from the message header is\nregistered in the root port\u0027s Root Status register. At the same\ntime, the PME Status bit of the Root Status register is set to\nindicate that there\u0027s a PME to handle. If PCIe PME interrupt is\nenabled for the root port, it generates an interrupt once the PME\nStatus has been set. After receiving the interrupt, the kernel can\nidentify the PCIe device that generated the PME using the Requester\nID from the root port\u0027s Root Status register. [For details, see PCI\nExpress Base Specification, Rev. 2.0.]\n\nImplement a driver for the PCIe PME root port service working in\naccordance with the above description.\n\nBased on a patch from Shaohua Li \u003cshaohua.li@intel.com\u003e.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bd1f46deba615971a58193afd0202878cadf19a7", "tree": "1a197e82ad0f6314f0ff0507c04030aaad933c7c", "parents": [ "61c39bb354a1f791ba6f562b766a72e508a036ee" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Fri Jan 22 14:06:53 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 25 10:42:52 2010 -0800" }, "message": "PCI: fix nested spinlock hang in aer_inject\n\nThe aer_inject module hangs in aer_inject() when checking the device\u0027s\nerror masks. The hang is due to a recursive use of the aer_inject lock.\nThe aer_inject() routine grabs the lock while processing the error and then\ncalls pci_read_config_dword to read the masks. The pci_read_config_dword\nroutine is earlier overridden by pci_read_aer, which among other things,\ngrabs the aer_inject lock.\n\nFixed by moving the pci_read_config_dword calls to read the masks to before\nthe lock is taken.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b49bfd32901625e4adcfee011d2b32a43b4db67d", "tree": "2a83d0d739df23b96b094de83880defc05ea0a6a", "parents": [ "1ae861e652b5457e7fa98ccbc55abea1e207916e" ], "author": { "name": "Youquan,Song", "email": "youquan.song@linux.intel.com", "time": "Thu Dec 17 08:22:48 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 15:52:49 2010 -0800" }, "message": "PCIe AER: prevent AER injection if hardware masks error reporting\n\nThe Correcteable/Uncorrectable Error Mask Registers are used by PCIe AER\ndriver which will controls the reporting of individual errors to PCIe RC\nvia PCIe error messages.\n\nIf hardware masks special error reporting to RC, the aer_inject driver\nshould not inject aer error.\n\nAcked-by: Andi Kleen \u003cak@linux.intel.com\u003e\nSigned-off-by: Youquan, Song \u003cyouquan.song@intel.com\u003e\nAcked-by: Ying, Huang \u003cying.huang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "46256f83d0d066f99ffde547f27473dfd2a78009", "tree": "b70c070f59d510d3d0e974009199a1c175d753d3", "parents": [ "40da4186a53e59d801130156ecb89fc5830ff227" ], "author": { "name": "Youquan,Song", "email": "youquan.song@linux.intel.com", "time": "Fri Dec 11 18:42:35 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 08:31:46 2010 -0800" }, "message": "PCI: AER: fix aer inject result in kernel oops\n\nIf the BIOS does not export _OSC to allow OS take over the PCIe AER, the\npcie aer driver will not initialize the aer service. However, the\naer_inject driver does not check this scenario, which results in a kernel\noops when injecting an aer error into OS. For example:\n\nBUG: unable to handle kernel NULL pointer dereference at 0000000000000350\nIP: [\u003cffffffff812e08f7\u003e] _spin_lock_irqsave+0xc/0x23\nPGD 155c41067 PUD 157fe0067 PMD 0\nOops: 0002 [#1] SMP\nPid: 5119, comm: aer-inject Not tainted 2.6.32-rc8-mce #2\nRIP: 0010:[\u003cffffffff812e08f7\u003e] [\u003cffffffff812e08f7\u003e] _spin_lock_irqsave+0xc/0x23\nRSP: 0018:ffff880157f81e28 EFLAGS: 00010096\nRAX: 0000000000000296 RBX: 0000000000000000 RCX: 0000000000000100\nRDX: 0000000000010000 RSI: 0000000000000246 RDI: 0000000000000350\nRBP: ffff880157f81e28 R08: 0000000000000004 R09: ffff880157f81dac\nR10: ffff88015a666f60 R11: ffff88015a666f40 R12: ffff88015758cc00\nR13: 0000000000000350 R14: 0000000000000000 R15: 0000000000000100\nFS: 00007f4d4a66e6f0(0000) GS:ffff8800282e0000(0000) knlGS:0000000000000000\nCS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b\nCR2: 0000000000000350 CR3: 000000015661a000 CR4: 00000000000006e0\nDR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000\nDR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400\nProcess aer-inject (pid: 5119, threadinfo ffff880157f80000, task ffff8801585f4340)\nStack:\n ffff880157f81e78 ffffffff811b1615 ffff880157f81e78 ffffffff81222823\nCall Trace:\n [\u003cffffffff811b1615\u003e] aer_irq+0x38/0x117\n [\u003cffffffff81222823\u003e] ? device_for_each_child+0x5f/0x6f\n [\u003cffffffffa00967bf\u003e] aer_inject_write+0x409/0x45e [aer_inject]\n [\u003cffffffff810eb80e\u003e] vfs_write+0xae/0x16a\n [\u003cffffffff810eb98e\u003e] sys_write+0x47/0x6e\n [\u003cffffffff8100ba2b\u003e] system_call_fastpath+0x16/0x1b\nRIP [\u003cffffffff812e08f7\u003e] _spin_lock_irqsave+0xc/0x23\n RSP \u003cffff880157f81e28\u003e\nCR2: 0000000000000350\n\nSo check the _OSC before assuming that AER is available to the OS.\n\nSigned-off-by: Youquan, Song \u003cyouquan.song@intel.com\u003e\nAcked-by: Ying, Huang \u003cying.huang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "40da4186a53e59d801130156ecb89fc5830ff227", "tree": "8eab64b223ca9657a65fb0650f10dce68ff6420f", "parents": [ "45d28b097280a78893ce25a5d0db41e6a2717853" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Tue Dec 15 11:38:04 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 08:29:37 2010 -0800" }, "message": "PCI: pcie portdrv: style cleanup\n\nNo change in logic.\n\nBefore:\n drivers/pci/pcie/portdrv_core.c:\n total: 7 errors, 2 warnings, 508 lines checked\n drivers/pci/pcie/portdrv_pci.c:\n total: 4 errors, 2 warnings, 300 lines checked\n\nAfter:\n drivers/pci/pcie/portdrv_core.c:\n total: 0 errors, 0 warnings, 506 lines checked\n drivers/pci/pcie/portdrv_pci.c:\n total: 0 errors, 0 warnings, 299 lines checked\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7e8af37a9a71b479f58d2fd5f0ddaa6780c51f11", "tree": "c83fc67ebf0df900bf7ac3c30cd282f28a13b8a6", "parents": [ "45e829ea412760d2404d7dfc42528df46aedbf62" ], "author": { "name": "Stefan Assmann", "email": "sassmann@redhat.com", "time": "Thu Dec 03 18:00:10 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:54 2009 -0800" }, "message": "PCI: change PCI nomenclature in drivers/pci/ (non-comment changes)\n\nChanging occurrences of variants of PCI-X and PCIe to the PCI-SIG\nterms listed in the \"Trademark and Logo Usage Guidelines\".\nhttp://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf\n\nPatch is limited to drivers/pci/ and changes concern non-comment parts or\nanything that might be visible to the user.\n\nSigned-off-by: Stefan Assmann \u003csassmann@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "45e829ea412760d2404d7dfc42528df46aedbf62", "tree": "869581b5828f9eb16a5ce38231b58a80a30be67c", "parents": [ "5714868812b563ba8816c1d974f4f07c76941c30" ], "author": { "name": "Stefan Assmann", "email": "sassmann@redhat.com", "time": "Thu Dec 03 06:49:24 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:53 2009 -0800" }, "message": "PCI: change PCI nomenclature in drivers/pci/ (comment changes)\n\nChanging occurrences of variants of PCI-X and PCIe to the PCI-SIG\nterms listed in the \"Trademark and Logo Usage Guidelines\".\nhttp://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf\n\nPatch is limited to drivers/pci/ and changes concern comments only.\n\nSigned-off-by: Stefan Assmann \u003csassmann@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "471452104b8520337ae2fb48c4e61cd4896e025d", "tree": "8594ae4a8362014e3cccf72a4e8834cdbb610bdd", "parents": [ "0ead0f84e81a41c3e98aeceab04af8ab1bb08d1f" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Mon Dec 14 18:00:08 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Dec 15 08:53:25 2009 -0800" }, "message": "const: constify remaining dev_pm_ops\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "b26a34aa4792b3db2500b8a98cb7702765c1a92e", "tree": "2a34bad3bce325dabc1a3aafbe225c62cee3dd77", "parents": [ "638bba08282fb50ba4ebde073ad70551b929e0f2" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Fri Nov 06 11:25:13 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:09:59 2009 -0800" }, "message": "PCI: fix BUG_ON triggered by logical PCIe root port removal\n\nThis problem happened when removing PCIe root port using PCI logical\nhotplug operation.\n\nThe immediate cause of this problem is that the pointer to invalid\ndata structure is passed to pcie_update_aspm_capable() by\npcie_aspm_exit_link_state(). When pcie_aspm_exit_link_state() received\na pointer to root port link, it unconfigures the root port link and\nfrees its data structure at first. At this point, there are not links\nto configure under the root port and the data structure for root port\nlink is already freed. So pcie_aspm_exit_link_state() must not call\npcie_update_aspm_capable() and pcie_config_aspm_path().\n\nThis patch fixes the problem by changing pcie_aspm_exit_link_state()\nnot to call pcie_update_aspm_capable() and pcie_config_aspm_path() if\nthe specified link is root port link.\n\n------------[ cut here ]------------\nkernel BUG at drivers/pci/pcie/aspm.c:606!\ninvalid opcode: 0000 [#1] SMP DEBUG_PAGEALLOC\nlast sysfs file: /sys/devices/pci0000:40/0000:40:13.0/remove\nCPU 1\nModules linked in: shpchp\nPid: 9345, comm: sysfsd Not tainted 2.6.32-rc5 #98 ProLiant DL785 G6\nRIP: 0010:[\u003cffffffff811df69b\u003e] [\u003cffffffff811df69b\u003e] pcie_update_aspm_capable+0x15/0xbe\nRSP: 0018:ffff88082a2f5ca0 EFLAGS: 00010202\nRAX: 0000000000000e77 RBX: ffff88182cc3e000 RCX: ffff88082a33d006\nRDX: 0000000000000001 RSI: ffffffff811dff4a RDI: ffff88182cc3e000\nRBP: ffff88082a2f5cc0 R08: ffff88182cc3e000 R09: 0000000000000000\nR10: ffff88182fc00180 R11: ffff88182fc00198 R12: ffff88182cc3e000\nR13: 0000000000000000 R14: ffff88182cc3e000 R15: ffff88082a2f5e20\nFS: 00007f259a64b6f0(0000) GS:ffff880864600000(0000) knlGS:0000000000000000\nCS: 0010 DS: 0018 ES: 0018 CR0: 000000008005003b\nCR2: 00007feb53f73da0 CR3: 000000102cc94000 CR4: 00000000000006e0\nDR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000\nDR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400\nProcess sysfsd (pid: 9345, threadinfo ffff88082a2f4000, task ffff88082a33cf00)\nStack:\n ffff88182cc3e000 ffff88182cc3e000 0000000000000000 ffff88082a33cf00\n\u003c0\u003e ffff88082a2f5cf0 ffffffff811dff52 ffff88082a2f5cf0 ffff88082c525168\n\u003c0\u003e ffff88402c9fd2f8 ffff88402c9fd2f8 ffff88082a2f5d20 ffffffff811d7db2\nCall Trace:\n [\u003cffffffff811dff52\u003e] pcie_aspm_exit_link_state+0xf5/0x11e\n [\u003cffffffff811d7db2\u003e] pci_stop_bus_device+0x76/0x7e\n [\u003cffffffff811d7d67\u003e] pci_stop_bus_device+0x2b/0x7e\n [\u003cffffffff811d7e4f\u003e] pci_remove_bus_device+0x15/0xb9\n [\u003cffffffff811dcb8c\u003e] remove_callback+0x29/0x3a\n [\u003cffffffff81135aeb\u003e] sysfs_schedule_callback_work+0x15/0x6d\n [\u003cffffffff81072790\u003e] worker_thread+0x19d/0x298\n [\u003cffffffff8107273b\u003e] ? worker_thread+0x148/0x298\n [\u003cffffffff81135ad6\u003e] ? sysfs_schedule_callback_work+0x0/0x6d\n [\u003cffffffff810765c0\u003e] ? autoremove_wake_function+0x0/0x38\n [\u003cffffffff810725f3\u003e] ? worker_thread+0x0/0x298\n [\u003cffffffff8107629e\u003e] kthread+0x7d/0x85\n [\u003cffffffff8102eafa\u003e] child_rip+0xa/0x20\n [\u003cffffffff8102e4bc\u003e] ? restore_args+0x0/0x30\n [\u003cffffffff81076221\u003e] ? kthread+0x0/0x85\n [\u003cffffffff8102eaf0\u003e] ? child_rip+0x0/0x20\nCode: 89 e5 8a 50 48 31 c0 c0 ea 03 83 e2 07 e8 b2 de fe ff c9 48 98 c3 55 48 89 e5 41 56 49 89 fe 41 55 41 54 53 48 83 7f 10 00 74 04 \u003c0f\u003e 0b eb fe 48 8b 05 da 7d 63 00 4c 8d 60 e8 4c 89 e1 eb 24 4c\nRIP [\u003cffffffff811df69b\u003e] pcie_update_aspm_capable+0x15/0xbe\n RSP \u003cffff88082a2f5ca0\u003e\n---[ end trace 6ae0f65bdeab8555 ]---\n\nReported-by: Alex Chiang \u003cachiang@hp.com\u003e\nTested-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "638bba08282fb50ba4ebde073ad70551b929e0f2", "tree": "ba517f15b67b9f5329d6167df27d6198d1a798b0", "parents": [ "6cdfd995a65a52e05b99e3a72a9b979abe73b312" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Thu Dec 03 10:28:25 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:03:19 2009 -0800" }, "message": "PCI: remove ifdefed pci_cleanup_aer_correct_error_status\n\nThe pci_cleanup_aer_correct_error_status() function has been\n#if 0\u0027d out since 2.6.25. Time to remove the dead code.\n\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6cdfd995a65a52e05b99e3a72a9b979abe73b312", "tree": "37b4f67ea9c156710976ad47ec79431c1320551b", "parents": [ "575939cf548951dde8df0786899ea5a91bb669b2" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Thu Dec 03 10:28:20 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:03:11 2009 -0800" }, "message": "PCI: unconditionally clear AER uncorr status register during cleanup\n\nThe current implementation of pci_cleanup_aer_uncorrect_error_status\nonly clears either fatal or non-fatal error status bits depending\non the state of the I/O channel. This implementation will then often\nleave some bits set after PCI error recovery completes. The uncleared bit\nsettings will then be falsely reported the next time an AER interrupt is\ngenerated for that hierarchy. An easy way to illustrate this issue is to\nuse the aer-inject module to simultaneously inject both an uncorrectable\nnon-fatal and uncorrectable fatal error. One of the errors will not be\ncleared.\n\nThis patch resolves this issue by unconditionally clearing all bits in\nthe AER uncorrectable status register. All settings and corrective action\nstrategies are saved and determined before\npci_cleanup_aer_uncorrect_error_status is called, so this change should not\naffect errory handling functionality.\n\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f9f45604edcf87ac86a9d68ca54106c5fb743719", "tree": "1983255e2df44203e0ae7ce8d3aa2c1c9c67b548", "parents": [ "694f88ef7ada0d99e304f687ba92e268a594358b" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:06:51 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:24 2009 -0800" }, "message": "PCI: portdrv: remove redundant definitions\n\nRemove unnecessary definitions from portdrv.h and use generic\ndefinitions instead.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "694f88ef7ada0d99e304f687ba92e268a594358b", "tree": "f7095c20f3a6111947a0edaa99dfddd366dbf4b2", "parents": [ "40717c39b1e6c064f48a263a27e58642221e8661" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:06:15 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:19 2009 -0800" }, "message": "PCI: portdrv: remove unnecessary struct pcie_port_data\n\nRemove \u0027port_type\u0027 field in struct pcie_port_data(), because we can\nget port type information from struct pci_dev. With this change, this\npatch also does followings:\n\n - Remove struct pcie_port_data because it no longer has any field.\n - Remove portdrv private definitions about port type (PCIE_RC_PORT,\n PCIE_SW_UPSTREAM_PORT and PCIE_SW_DOWNSTREAM_PORT), and use generic\n definitions instead.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "40717c39b1e6c064f48a263a27e58642221e8661", "tree": "62c92897f5370900b5cfd6769bfa193ae1a61320", "parents": [ "fbb5de70bbe13ecbebb04226dd6d52b1258dc247" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:05:35 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:10 2009 -0800" }, "message": "PCI: portdrv: minor cleanup for pcie_port_device_register\n\nMinor cleanups for pcie_port_device_register().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fbb5de70bbe13ecbebb04226dd6d52b1258dc247", "tree": "0298455195db5d154718fad4cc411125080a9e3a", "parents": [ "1ce5e83063bf388a2c9fa1e3d4d3122146ad305d" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:05:01 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:06 2009 -0800" }, "message": "PCI: portdrv: add missing irq cleanup\n\nAdd missing service irqs cleanup in the error code path of\npcie_port_device_register().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1ce5e83063bf388a2c9fa1e3d4d3122146ad305d", "tree": "10528a2c8dd991a7c6ad6e55058469d96aa335d5", "parents": [ "dc5351784eb36f1fec4efa88e01581be72c0b711" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:04:30 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:59 2009 -0800" }, "message": "PCI: portdrv: enable device before irq initialization\n\nCall pci_enable_device() before initializing service irqs, because\nlegacy interrupt is initialized in pci_enable_device() on some\narchitectures.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dc5351784eb36f1fec4efa88e01581be72c0b711", "tree": "b91a30f23149bbf7d243c63f68af43bc0e46dc6f", "parents": [ "d013598d9a46befebdfd37195829ce411e4878ea" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:04:00 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:51 2009 -0800" }, "message": "PCI: portdrv: cleanup service irqs initialization\n\nThis patch cleans up the service irqs initialization as follows:\n\n - Remove \u0027irq_mode\u0027 field in pcie_port_data and related definitions,\n which is not needed because we can get the same information from\n \u0027is_msix\u0027, \u0027is_msi\u0027 and \u0027pin\u0027 fields in struct pci_dev.\n\n - Change the name of \u0027vectors\u0027 argument of assign_interrupt_mode() to\n \u0027irqs\u0027 because it holds irq numbers actually. People might confuse\n it with CPU vector or MSI/MSI-X vector.\n\n - Change function name assign_interrupt_mode() to init_service_irqs()\n becasuse we no longer have \u0027irq_mode\u0027 data structure, and new name\n is more straightforward (IMO).\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d013598d9a46befebdfd37195829ce411e4878ea", "tree": "92d461ff66a29cbf9b23af2570de4a99ad9a16c6", "parents": [ "9e5d0b16dada536dfe2f1e893b6ad0225ff8a2c9" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:03:27 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:44 2009 -0800" }, "message": "PCI: portdrv: check capabilities first\n\nMove capability check capability to the beginning of\npcie_port_device_register() prevents redundant execution path.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9e5d0b16dada536dfe2f1e893b6ad0225ff8a2c9", "tree": "1861e7d3d52a5aeb91284ca6b1e310811adb2eb3", "parents": [ "2dd60e96b4d52bccd2dd585e776a3449d7b34b8f" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:02:51 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:37 2009 -0800" }, "message": "PCI: portdrv: move PME capability check\n\nNo reason to check PME capability outside get_port_device_capability().\nDo it in get_port_device_capability().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2dd60e96b4d52bccd2dd585e776a3449d7b34b8f", "tree": "917f339b7542be53ec3b64c12a221d5e6700eec1", "parents": [ "52a0f24beabe9e89223e367c65a0156dff17265c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:02:13 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:26 2009 -0800" }, "message": "PCI: portdrv: remove redundant pcie type calculation\n\nPCIe port type is already stored in \u0027pcie_type\u0027 field of struct\npci_dev. So we don\u0027t need to get it from pci configuration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "52a0f24beabe9e89223e367c65a0156dff17265c", "tree": "d6249304150228dcb15052781cb9f26afae05be4", "parents": [ "898294c97500b1cdff6edce52fd34e024eb070ec" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:01:28 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:18 2009 -0800" }, "message": "PCI: portdrv: cleanup pcie_device registration\n\nIn the current port bus driver implementation, pcie_device allocation,\ninitialization and registration are done in separated functions. Doing\nthose in one function make the code simple and easier to read.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "898294c97500b1cdff6edce52fd34e024eb070ec", "tree": "0f5faec54c06f3775c164b48a1c48659c6ceeb4c", "parents": [ "59353ea30e65ab3ae181d6175e3212e1361c3787" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:00:53 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:12 2009 -0800" }, "message": "PCI: portdrv: remove redundant pcie_port_device_probe\n\nWe don\u0027t need pcie_port_device_probe() because we can get pci\ndevice/port type using pci_is_pcie() and \u0027pcie_type\u0027 fields in struct\npci_dev. Remove pcie_port_device_probe().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b44d7db36480a3b27e78141fc9d6597aa577744b", "tree": "76780c8f3ed3644fafa3e8c38b8d5608bed83be3", "parents": [ "8b06477dc4fcdfc21442ad334d3f3e335225ea0c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:37:24 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:17 2009 -0800" }, "message": "PCIe AER: use pci_is_pcie()\n\nChanges for PCIe AER driver to use pci_is_pcie() instead of checking\npci_dev-\u003eis_pcie.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8b06477dc4fcdfc21442ad334d3f3e335225ea0c", "tree": "77a614b6b702e884944f2bf7e2b44bef922e4633", "parents": [ "5f4d91a1228ac85c75b099efd36fff1a3407335c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:36:52 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:17 2009 -0800" }, "message": "PCIe ASPM: use pci_is_pcie()\n\nChange for PCIe ASPM driver to use pci_is_pcie() instead of checking\npci_dev-\u003eis_pcie.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "db9538a7495e33f3571c0e791c7678bc0c6ef50f", "tree": "690c5977a83e5c7f0423870dd208784afcd4b159", "parents": [ "dba90dfe48e2e00e79a15c95940730b6926ee176" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:33:30 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:14 2009 -0800" }, "message": "PCIe ASPM: use pci_pcie_cap()\n\nUse pci_pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCIe ASPM driver. This avoids unnecessary search in PCI\nconfiguration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dba90dfe48e2e00e79a15c95940730b6926ee176", "tree": "af32687abec213653a6432842a8962adcf3a9e8c", "parents": [ "39a53062cb5b2ceca6035f3ed67317672f0bcf3b" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:32:42 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:13 2009 -0800" }, "message": "PCIe port bus: use pci_pcie_cap()\n\nUse pci_pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCI Express Port Bus driver. This avoids unnecessary serarch\nin PCI configuration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "39a53062cb5b2ceca6035f3ed67317672f0bcf3b", "tree": "cafbfa800f85c28abad3504787555009ebd97dd0", "parents": [ "06a1cbafb253c4c60d6a54a994887f5fbceabcc0" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:31:38 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:13 2009 -0800" }, "message": "PCIe AER: use pci_pcie_cap()\n\nUse pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCIe AER driver. This avoids unnecessary search in PCI\nconfiguration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "476f644edf7c22b47e6a118e4a1e138112a5ef14", "tree": "bafecfc91290c5d3eb70d3bf7c7561b61bc97c66", "parents": [ "1d0243559497b9cab00099c49a5ba3222cd6576f" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Oct 12 13:14:15 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:38 2009 -0800" }, "message": "PCI: fix memory leak in aer_inject\n\nFixed probable typo in aer_inject cleanup code resulting in a memory\nleak.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1d0243559497b9cab00099c49a5ba3222cd6576f", "tree": "36a0e7707770e5f97df28aa8ec0a92b7307d16aa", "parents": [ "cc5d153a0ca794e3781ef34c76f32ad3e991b13d" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Oct 12 13:14:10 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:38 2009 -0800" }, "message": "PCI: use better error return values in aer_inject\n\nReplaced some error return values in aer_inject. Use -ENODEV when we\ncan\u0027t find a device and -ENOTTY when the device does not support PCIe AER.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "cc5d153a0ca794e3781ef34c76f32ad3e991b13d", "tree": "61feef82ec34c5f6489abe6db95fae8d03a43d0b", "parents": [ "3c299dc22635e500214707aa28be119ff2b3901c" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Oct 12 13:14:05 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:37 2009 -0800" }, "message": "PCI: add support for PCI domains to aer_inject\n\nAdd support for PCI domains (segments) to aer_inject.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0584396157ad2d008e2cc76b4ed6254151183a25", "tree": "8860a033938b1a01cccf9a203208f741758724ac", "parents": [ "8792e11f1c54bcba34412f03959e70ee217f2231" ], "author": { "name": "Matt Domsch", "email": "Matt_Domsch@dell.com", "time": "Mon Nov 02 11:51:24 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:25 2009 -0800" }, "message": "PCI: PCIe AER: honor ACPI HEST FIRMWARE FIRST mode\n\nFeedback from Hidetoshi Seto and Kenji Kaneshige incorporated. This\ncorrectly handles PCI-X bridges, PCIe root ports and endpoints, and\nprints debug messages when invalid/reserved types are found in the\nHEST. PCI devices not in domain/segment 0 are not represented in\nHEST, thus will be ignored.\n\nToday, the PCIe Advanced Error Reporting (AER) driver attaches itself\nto every PCIe root port for which BIOS reports it should, via ACPI\n_OSC.\n\nHowever, _OSC alone is insufficient for newer BIOSes. Part of ACPI\n4.0 is the new APEI (ACPI Platform Error Interfaces) which is a way\nfor OS and BIOS to handshake over which errors for which components\neach will handle. One table in ACPI 4.0 is the Hardware Error Source\nTable (HEST), where BIOS can define that errors for certain PCIe\ndevices (or all devices), should be handled by BIOS (\"Firmware First\nmode\"), rather than be handled by the OS.\n\nDell PowerEdge 11G server BIOS defines Firmware First mode in HEST, so\nthat it may manage such errors, log them to the System Event Log, and\npossibly take other actions. The aer driver should honor this, and\nnot attach itself to devices noted as such.\n\nFurthermore, Kenji Kaneshige reminded us to disallow changing the AER\nregisters when respecting Firmware First mode. Platform firmware is\nexpected to manage these, and if changes to them are allowed, it could\nbreak that firmware\u0027s behavior.\n\nThe HEST parsing code may be replaced in the future by a more\nfeature-rich implementation. This patch provides the minimum needed\nto prevent breakage until that implementation is available.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Matt Domsch \u003cMatt_Domsch@dell.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2caa731819a633bec5a56736e64c562b7e193666", "tree": "e93f5c50c33c7cf5a9cc3ea29dd1d868b4f14d5c", "parents": [ "589bf8d52b5bbb580962438ad9403ec6853bc12b", "30fc24b5cbc55f9e6c686e2710cc812419bddc0c" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Oct 12 14:38:34 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Oct 12 14:38:34 2009 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n PCI: Prevent AER driver from being loaded on non-root port PCIE devices\n PCI: get larger bridge ranges when space is available\n PCI: pci.c: fix kernel-doc notation\n PCI quirk: TI XIO200a erroneously reports support for fast b2b transfers\n PCI PM: Read device power state from register after updating it\n PCI: remove pci_assign_resource_fixed()\n PCI: PCIe portdrv: remove \"-driver\" from driver name\n" }, { "commit": "d43c36dc6b357fa1806800f18aa30123c747a6d1", "tree": "339ce510073ecbe9b3592008f7dece7b277035ef", "parents": [ "69585dd69e663a40729492c7b52eb82477a2027a" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Wed Oct 07 17:09:06 2009 +0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Oct 11 11:20:58 2009 -0700" }, "message": "headers: remove sched.h from interrupt.h\n\nAfter m68k\u0027s task_thread_info() doesn\u0027t refer to current,\nit\u0027s possible to remove sched.h from interrupt.h and not break m68k!\nMany thanks to Heiko Carstens for allowing this.\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\n" }, { "commit": "30fc24b5cbc55f9e6c686e2710cc812419bddc0c", "tree": "58a6ca580ab9fef9081e4921775b9b2c33ca0ab2", "parents": [ "308cf8e13f42f476dfd6552aeff58fdc0788e566" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Oct 07 09:28:56 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Oct 07 09:28:56 2009 -0700" }, "message": "PCI: Prevent AER driver from being loaded on non-root port PCIE devices\n\nA bug was seen on boards using a PLX 8518 switch device which advertises\nAER on each of it\u0027s transparent bridges. The AER driver was loaded for\neach bridge and this driver tried to access the AER source ID register\nwhenever an interrupt occured on the shared PCI INTX lines. The source\nID register does not exist on non root port PCIE device\u0027s which\nadvertise AER and trying to access this register causes a unsupported\nrequest error on the bridge. Thus, when the next interrupt occurs,\nanother error is found and the non existent source ID register is\naccessed again, and so it goes on.\n\nThe result is a spammed dmesg with unsupported request PCI express\nerrors on the bridge device that the AER driver is loaded against.\n\nReported-by: Malcolm Crossley \u003cmalcolm.crossley2@gefanuc.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nTested-by: Malcolm Crossley \u003cmalcolm.crossley2@gefanuc.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e3fb20f9c8783d6e27cf84389a9606e410733eef", "tree": "ece2a369a2c95148a622e7e2faf56fdd20d0c716", "parents": [ "0eca52a92735f43462165efe00a7e394345fb38e" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Oct 05 16:47:34 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Oct 06 09:41:48 2009 -0700" }, "message": "PCI: PCIe portdrv: remove \"-driver\" from driver name\n\nNo need to include \"-driver\" in the driver name.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nCC: Tom Long Nguyen \u003ctom.l.nguyen@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3e77a3f7895e9c20756dc250282afa12f6d259a3", "tree": "fe9a701f8c7d86841846b52326fbec89c8e42c29", "parents": [ "7557b5d63259d55f716e62e528978d4866318515" ], "author": { "name": "Andi Kleen", "email": "andi@firstfloor.org", "time": "Wed Sep 16 22:40:22 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:05:27 2009 -0700" }, "message": "PCI: Disable AER with pci\u003dnomsi\n\nWhen booting with pci\u003dnomsi aer causes lost interrupts and\nlockdep inversions.\n\nSo check if MSIs are not disabled before initializing the aer\ndriver.\n\nSigned-off-by: Andi Kleen \u003cak@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7557b5d63259d55f716e62e528978d4866318515", "tree": "a7de26e15fe8d551f7b853d9ecd47403f31b13db", "parents": [ "ab86e5765d41a5eb4239a1c04d613db87bea5ed8" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Sep 16 17:29:59 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:05:16 2009 -0700" }, "message": "PCI ASPM: support L1 only\n\nThe definition of the ASPM support field in the Link Capabilities\nRegister had been changed by the \"ASPM optionality ECN\" as follows:\n\n\u003cBefore\u003e\n\t00b\tReserved\n\t01b\tL0s Supported\n\t10b\tReserved\n\t11b\tL0s and L1 Supported\n\n\u003cAfter\u003e\n\t00b\tNo ASPM Support\n\t01b\tL0s Supported\n\t10b\tL1 Supported\n\t11b\tL0s and L1 Supported\n\nCurrent linux ASPM driver doesn\u0027t enable ASPM if the support field is\n00b or 10b. So there is no impact about 00b. But current linux ASPM\ndriver doesn\u0027t enable L1 if the support field is 10b. With this patch,\n10b (L1 support) is handled properly.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e9d8288871efa0d98a1d1d1f17976b5b00a0234d", "tree": "d446e04d904afeb5bda9598ec526d9beef2c5e95", "parents": [ "7f53866932fd08add06ee2f93ead129949158490" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Sep 14 22:25:11 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 13:38:55 2009 -0700" }, "message": "PCI / PCIe portdrv: Fix pcie_portdrv_slot_reset()\n\nAfter commit c82f63e411f1b58427c103bd95af2863b1c96dd1\n(PCI: check saved state before restore) pcie_portdrv_slot_reset()\nmay not work correctly if dev-\u003eerror_state is equal to\npci_channel_io_frozen, because dev-\u003estate_saved need not be set at\nthat time. Fix this issue by setting dev-\u003estate_saved before\npci_restore_state() is called in pcie_portdrv_slot_reset().\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9965976a38f66fc170fc0528b3115bf1a8a58b0a", "tree": "9814ad7063145c84b05499efbb52ca8bb5f66340", "parents": [ "0baed8da1ed91b664759f6c7f955b3a804457389" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Sep 11 08:46:07 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Sep 11 08:46:07 2009 -0700" }, "message": "PCI: pcie portdrv: remove unused variable\n\nRemove unused port_data variable left over from the MCH hotplug quirk\ncleanup.\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0ba379ec0fb182a87b8891c5754abbcd9c035b4f", "tree": "d2678b52e9e92a654f1997a9b6e891f47351c782", "parents": [ "b1c089b7caf18905bd1d87136cf7b8c837254932" ], "author": { "name": "Eric W. Biederman", "email": "ebiederm@xmission.com", "time": "Sun Sep 06 21:48:35 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:06:49 2009 -0700" }, "message": "PCI: Simplify hotplug mch quirk.\n\nThere is a very old quirk for the intel E7502 E7320 and E7525 memory\ncontroller hubs that disables usage of msi interrupts on pcie hotplug\nbridges of those devices, and disables changing the affinity of irqs.\n\nToday all we have to do to disable msi on a specific device is to set\ndev-\u003eno_msi, which is much more straightforward than the previous\nlogic.\n\nThe re-running of this fixup after pci hotplug happens below these\ndevices is totally bogus. All of the state we change is pure software\nstate and we don\u0027t change the hardware at all. Which means hotplug on\nthe lower devices doesn\u0027t have a chance to change this state. So we\ncan safely remove the special case from the pciehp driver and the pcie\nportdriver.\n\nI suspect the special case was someone\u0027s expermental debug code that\nslipped in. Certainly it isn\u0027t mentioned in commit\n6fb8880a61510295aece04a542767161f624dffe aka BKrev:\n41966101LJ_ogfOU0m2aE6teZfQnuQ where the code first appears.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: \"Eric W. Biederman\" \u003cebiederm@xmission.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b1c089b7caf18905bd1d87136cf7b8c837254932", "tree": "52859a8cdd9479c31d8c013f8cb2145cfb5a1a8b", "parents": [ "79e4b89be81b5e53bc4cb51788ca7a45cadb4ef3" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:16:59 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:50:13 2009 -0700" }, "message": "PCI: pcie, aer: report all error before recovery\n\nThis patch is required not to lost error records by action invoked on\nerror recovery, such as slot reset etc.\n\nFollowing sample (real machine + dummy record injected by aer-inject)\nshows that record of 28:00.1 could not be retrieved by recovery of 28:00.0:\n\n- Before:\n\npcieport-driver 0000:00:02.0: AER: Multiple Uncorrected (Non-Fatal) error received: id\u003d2801\ne1000e 0000:28:00.0: PCIE Bus Error: severity\u003dUncorrected (Non-Fatal), type\u003dTransaction Layer, id\u003d2800(Receiver ID)\ne1000e 0000:28:00.0: device [8086:1096] error status/mask\u003d00001000/00100000\ne1000e 0000:28:00.0: [12] Poisoned TLP (First)\ne1000e 0000:28:00.0: TLP Header: 00000000 00000001 00000002 00000003\ne1000e 0000:28:00.0: broadcast error_detected message\ne1000e 0000:28:00.0: broadcast slot_reset message\ne1000e 0000:28:00.0: setting latency timer to 64\ne1000e 0000:28:00.0: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)\ne1000e 0000:28:00.0: PME# disabled\ne1000e 0000:28:00.0: PME# disabled\ne1000e 0000:28:00.1: setting latency timer to 64\ne1000e 0000:28:00.1: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)\ne1000e 0000:28:00.1: PME# disabled\ne1000e 0000:28:00.1: PME# disabled\ne1000e 0000:28:00.0: broadcast resume message\ne1000e 0000:28:00.0: AER driver successfully recovered\ne1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX\n\n- After:\n\npcieport-driver 0000:00:02.0: AER: Multiple Uncorrected (Non-Fatal) error received: id\u003d2801\ne1000e 0000:28:00.0: PCIE Bus Error: severity\u003dUncorrected (Non-Fatal), type\u003dTransaction Layer, id\u003d2800(Receiver ID)\ne1000e 0000:28:00.0: device [8086:1096] error status/mask\u003d00001000/00100000\ne1000e 0000:28:00.0: [12] Poisoned TLP (First)\ne1000e 0000:28:00.0: TLP Header: 00000000 00000001 00000002 00000003\ne1000e 0000:28:00.1: PCIE Bus Error: severity\u003dUncorrected (Non-Fatal), type\u003dTransaction Layer, id\u003d2801(Receiver ID)\ne1000e 0000:28:00.1: device [8086:1096] error status/mask\u003d00081000/00100000\ne1000e 0000:28:00.1: [12] Poisoned TLP (First)\ne1000e 0000:28:00.1: [19] ECRC\ne1000e 0000:28:00.1: TLP Header: 00000000 00000001 00000002 00000003\ne1000e 0000:28:00.1: Error of this Agent(2801) is reported first\ne1000e 0000:28:00.0: broadcast error_detected message\ne1000e 0000:28:00.0: broadcast slot_reset message\ne1000e 0000:28:00.0: setting latency timer to 64\ne1000e 0000:28:00.0: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)\ne1000e 0000:28:00.0: PME# disabled\ne1000e 0000:28:00.0: PME# disabled\ne1000e 0000:28:00.1: setting latency timer to 64\ne1000e 0000:28:00.1: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)\ne1000e 0000:28:00.1: PME# disabled\ne1000e 0000:28:00.1: PME# disabled\ne1000e 0000:28:00.0: broadcast resume message\ne1000e 0000:28:00.0: AER driver successfully recovered\ne1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "79e4b89be81b5e53bc4cb51788ca7a45cadb4ef3", "tree": "846f21ae6628559b68778d2e438ac3503c76ca79", "parents": [ "273024ded7b364e1305a31bf4eb197870284f279" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:16:45 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:50:05 2009 -0700" }, "message": "PCI: pcie, aer: change error print format\n\nUse dev_printk like format.\n\nSample (real machine + dummy error injected by aer-inject):\n\n- Before:\n\n+------ PCI-Express Device Error ------+\nError Severity : Corrected\nPCIE Bus Error type : Data Link Layer\nBad TLP :\nReceiver ID : 2800\nVendorID\u003d8086h, DeviceID\u003d1096h, Bus\u003d28h, Device\u003d00h, Function\u003d00h\n+------ PCI-Express Device Error ------+\nError Severity : Corrected\nPCIE Bus Error type : Data Link Layer\nBad TLP :\nBad DLLP :\nReceiver ID : 2801\nVendorID\u003d8086h, DeviceID\u003d1096h, Bus\u003d28h, Device\u003d00h, Function\u003d01h\nError of this Agent(2801) is reported first\n\n- After:\n\npcieport-driver 0000:00:02.0: AER: Multiple Corrected error received: id\u003d2801\ne1000e 0000:28:00.0: PCIE Bus Error: severity\u003dCorrected, type\u003dData Link Layer, id\u003d2800(Receiver ID)\ne1000e 0000:28:00.0: device [8086:1096] error status/mask\u003d00000040/00000000\ne1000e 0000:28:00.0: [ 6] Bad TLP\ne1000e 0000:28:00.1: PCIE Bus Error: severity\u003dCorrected, type\u003dData Link Layer, id\u003d2801(Receiver ID)\ne1000e 0000:28:00.1: device [8086:1096] error status/mask\u003d000000c0/00000000\ne1000e 0000:28:00.1: [ 6] Bad TLP\ne1000e 0000:28:00.1: [ 7] Bad DLLP\ne1000e 0000:28:00.1: Error of this Agent(2801) is reported first\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "273024ded7b364e1305a31bf4eb197870284f279", "tree": "f3aee59e082b25f8920c6c7d6a3d6ea741325c71", "parents": [ "3472a18773bc6661ea7f8de2b4172db7e00b67e6" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:16:20 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:49:56 2009 -0700" }, "message": "PCI: pcie, aer: flags to bits\n\nCompact struct and codes.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3472a18773bc6661ea7f8de2b4172db7e00b67e6", "tree": "fdfc96e3014f8f76b7d3e58cb915880771d809bc", "parents": [ "e7a0d92b19f438011ad76c41755b56ec2ef05f64" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:16:00 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:49:36 2009 -0700" }, "message": "PCI: pcie, aer: remove unused macros\n\nCleanup.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e7a0d92b19f438011ad76c41755b56ec2ef05f64", "tree": "f09cc40211ccf8c1b695d6394d9c184ea12b943d", "parents": [ "0d90c3ac0bb89acfbf481c8b06749b00eade6545" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:13:42 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:49:26 2009 -0700" }, "message": "PCI: pcie, aer: report multiple/first error on a device\n\nMultiple bits might be set in the Uncorrectable Error Status\nregister. But aer_print_error_source() only report a error of\nthe lowest bit set in the error status register.\n\nSo print strings for all bits unmasked and set.\n\nAnd check First Error Pointer to mark the error occured first.\nThis FEP is not valid when the corresponing bit of the Uncorrectable\nError Status register is not set, or unimplemented or undefined.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0d90c3ac0bb89acfbf481c8b06749b00eade6545", "tree": "1f8bb597f08231c1f715fa6d6c72fa21089c1fef", "parents": [ "24dbb7beb2a207f423006c46830dfaacca5a1139" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:12:25 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:49:07 2009 -0700" }, "message": "PCI: pcie, aer: refer mask state in mask register properly\n\nERR_{,UN}CORRECTABLE_ERROR_MASK are set of error bits which linux know,\nset of PCI_ERR_COR_* and PCI_ERR_UNC_* defined in linux/pci_regs.h.\nThis masks make aerdrv not to report errors of unknown bit, while aerdrv\nhave ability to report such undefined errors as \"Unknown Error Bit %2d\".\n\nOTOH aerdrv_errprint does not have any check of setting in mask register.\nSo it could report masked wrong error by finding bit in status without\nknowing that the bit is masked in the mask register.\n\nThis patch changes aerdrv to use mask state in mask register propely\ninstead of defined/hardcoded ERR_{,UN}CORRECTABLE_ERROR_MASK.\nThis change prevents aerdrv from reporting masked error, and also enable\nreporting unknown errors.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "24dbb7beb2a207f423006c46830dfaacca5a1139", "tree": "2a2b7b85c11eb784c691c0857c59e8a6053004ae", "parents": [ "0d465f23502e0810443c90a9cf1cf5686c4af4f2" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:11:29 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:48:19 2009 -0700" }, "message": "PCI: pcie, aer: remove spinlock in aerdrv_errprint.c\n\nThe static buffer errmsg_buff[] is used only for building error\nmessage in fixed format, and is protected by a spinlock.\n\nThis patch removes this buffer and the spinlock.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0d465f23502e0810443c90a9cf1cf5686c4af4f2", "tree": "7b40a9655387f20895e491ed6d0ad25bc2c66e4c", "parents": [ "1b4ffcf8432f7945e0bd0571f10a2f2bd1dbd850" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:10:40 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:47:46 2009 -0700" }, "message": "PCI: pcie, aer: fix report of multiple errors\n\nThe flag AER_MULTI_ERROR_VALID_FLAG in info-\u003eflag does mean that the\nroot port receives multiple error messages. Error messages can be\nposted from different devices, so it does not mean that each reported\ndevice has multiple errors.\n\nIf there are multiple error devices and the root port has valid error\nsource ID, it would be nice to report which device is the error source\nreported first.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1b4ffcf8432f7945e0bd0571f10a2f2bd1dbd850", "tree": "1b95d1740ed46c89c28501e1d947c3c173f75436", "parents": [ "f15857569613a982568be88d034555d88eead0aa" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:09:58 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:47:32 2009 -0700" }, "message": "PCI: pcie, aer: init struct aer_err_info for reuse\n\nIn case of multiple errors, struct aer_err_info would be reused among\nall reported devices. So the info-\u003estatus should be initialized before\nrecycled. Otherwise error of one device might be reported as the error\nof another device. Also info-\u003eflags has similar problem on reporting\nTLP header.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f15857569613a982568be88d034555d88eead0aa", "tree": "a4d10a5e0f9013c2289226b80f2ee97b4107801d", "parents": [ "bd8fedd045d1d3f4e1f5daca179b0a49949ab538" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:08:59 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:47:16 2009 -0700" }, "message": "PCI: pcie, aer: rework MASK macros in aerdrv_errprint.c\n\nDefinitions of MASK macros in aerdrv_errprint.c are tricky and unsafe.\n\nFor example, AER_AGENT_TRANSMITTER_MASK(_sev, _stat) does work like:\n static inline func(int _sev, int _stat)\n {\n if (_sev \u003d\u003d AER_CORRECTABLE)\n return (_stat \u0026 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER));\n else\n return (_stat \u0026 PCI_ERR_COR_REP_ROLL);\n }\nIn case of else path here, for uncorrectable errors, testing bits in\n_stat by PCI_ERR_COR_* does not make sense because _stat should have only\nPCI_ERR_UNC_* bits originated in uncorrectable error status register.\nBut at this time this is safe because uncorrectable error using bit\nposition same to PCI_ERR_COR_REP_ROLL(\u003d bit position 8) is not defined.\nLikewise, AER_AGENT_COMPLETER_MASK is always PCI_ERR_UNC_COMP_ABORT but\nit works because bit 15 of correctable error status is not defined.\n\nIt means that these MASK macros will turn to be wrong once if new error\nis defined. (In fact, bit 15 of correctable is now defined in PCIe 2.1)\n\nThis patch changes these MASK macros to be more strict, not to return\nPCI_ERR_COR_* bits for uncorrectable error status and vise versa.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bd8fedd045d1d3f4e1f5daca179b0a49949ab538", "tree": "85d6c0739f0c461b9976a0ae1b3f2800751a4d33", "parents": [ "c9a918838c07cbef934c8ef818d8f0e719015c3a" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:08:14 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:46:54 2009 -0700" }, "message": "PCI: pcie, aer: AER_PR for printing in aerdrv_errprint.c\n\nAdd workaround macro to reduce the number of checkpatch warning:\n WARNING: printk() should include KERN_ facility level\n\nBefore:\n total: 0 errors, 10 warnings, 247 lines checked\nAfter:\n total: 0 errors, 1 warnings, 243 lines checked\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c9a918838c07cbef934c8ef818d8f0e719015c3a", "tree": "fa0978d67632a15fdd014f448ac099ab1ec8df75", "parents": [ "b439b1d4e3ae3c36ed94ed233119ff0d145af257" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:07:29 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:46:18 2009 -0700" }, "message": "PCI: pcie, aer: checkpatch style cleanup in pcie/aer/*\n\nBefore:\n drivers/pci/pcie/aer/aer_inject.c\n total: 4 errors, 4 warnings, 473 lines checked\n drivers/pci/pcie/aer/aerdrv.c\n total: 5 errors, 2 warnings, 333 lines checked\n drivers/pci/pcie/aer/aerdrv.h\n total: 1 errors, 0 warnings, 139 lines checked\n drivers/pci/pcie/aer/aerdrv_core.c\n total: 4 errors, 3 warnings, 872 lines checked\n drivers/pci/pcie/aer/aerdrv_errprint.c\n total: 12 errors, 11 warnings, 248 lines checked\n\nAfter:\n drivers/pci/pcie/aer/aer_inject.c\n total: 0 errors, 0 warnings, 466 lines checked\n drivers/pci/pcie/aer/aerdrv.c\n total: 0 errors, 0 warnings, 335 lines checked\n drivers/pci/pcie/aer/aerdrv.h\n total: 0 errors, 0 warnings, 139 lines checked\n drivers/pci/pcie/aer/aerdrv_core.c\n total: 0 errors, 0 warnings, 869 lines checked\n drivers/pci/pcie/aer/aerdrv_errprint.c\n total: 0 errors, 10 warnings, 247 lines checked\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ac18018a414a90d841ea81d38fecb913c0ec1880", "tree": "21eeedf2a160f50ae6f6bcba1ef7d5ee5d6cbfb4", "parents": [ "b7206cbf024dd43c42f9585e2017db1c1facd566" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 11:02:13 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:49 2009 -0700" }, "message": "PCI ASPM: support per direction l0s management\n\nThe L0s state can be managed separately for each direction (upstream\ndirection and downstream direction) of the link. But in the current\nimplementation, those are mixed up. With this patch, L0s for each\ndirection are managed separately.\n\nTo maintain three states (upstream direction L0s, downstream L0s and\nL1), \u0027aspm_support\u0027, \u0027aspm_enabled\u0027, \u0027aspm_capable\u0027, \u0027aspm_disable\u0027\nand \u0027aspm_default\u0027 fields in struct pcie_link_state are changed to\n3-bit from 2-bit. The \u0027latency\u0027 field is separated to two \u0027latency_up\u0027\nand \u0027latency_dw\u0027 fields to maintain exit latencies for each direction\nof the link. For L0, \u0027latency_up.l0\u0027 and \u0027latency_dw.l0\u0027 are used to\nconfigure upstream direction L0s and downstream direction L0s\nrespectively. For L1, larger value of \u0027latency_up.l1\u0027 and\n\u0027latency_dw.l1\u0027 is considered as L1 exit latency.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b7206cbf024dd43c42f9585e2017db1c1facd566", "tree": "cf84dccb916f90e445c08b244939a25203874aec", "parents": [ "07d92760d2ee542fe932f4e8b5807dd98481d1fd" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 11:01:37 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:48 2009 -0700" }, "message": "PCI ASPM: support partial aspm enablement\n\nIn the current implementation, ASPM L0s/L1 is disabled for all links\nin the hierarchy if one of the link doesn\u0027t meet latency requirement.\nBut we can partially enable ASPM L0s/L1 on sub-tree in the hierarchy.\nThis patch allows partial L0s/L1 enablement in the hierarchy. And it\nalso reduce the calculation cost of ASPM configuration very much.\n\nIn the previous implementation, all links were enabled with the same\nstate. With this patch, enabled state for each link is determined\nsimply as follows (the \u0027requested\u0027 is from policy_to_aspm_state()).\n\n enabled \u003d requested \u0026 (link-\u003easpm_capable \u0026 link-\u003easpm_disable)\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "07d92760d2ee542fe932f4e8b5807dd98481d1fd", "tree": "47d94230d73567b16f9c9a307d1c8f08eff47184", "parents": [ "f1c0ca29ae72bc0c10282eada66c8a792ee98482" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 11:00:25 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:47 2009 -0700" }, "message": "PCI ASPM: introduce capable flag\n\nIntroduce \u0027aspm_capable\u0027 field to maintain the capable ASPM setting of\nthe link. By the \u0027aspm_capable\u0027, we don\u0027t need to recheck latency\nevery time ASPM policy is changed.\n\nEach bit in \u0027aspm_capable\u0027 is associated to ASPM state (L0S/L1). The\nbit is set if the associated ASPM state is supported by the link and\nit satisfies the latency requirement (i.e. exit latency \u003c endpoint\nacceptable latency). The \u0027aspm_capable\u0027 is updated when\n\n - an endpoint device is added (boot time or hot-plug time)\n - an endpoint device is removed (hot-unplug time)\n - PCI power state is changed.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f1c0ca29ae72bc0c10282eada66c8a792ee98482", "tree": "4629fc8c5f0a8537376636b997f6a62dddc63ac2", "parents": [ "fc87e919c0ce8e213edf2ffca17f384f059873d3" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 10:59:52 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:46 2009 -0700" }, "message": "PCI ASPM: introduce disable flag\n\nIntroduce \u0027aspm_disable\u0027 flag to manage disabled ASPM state more\nrobust way.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fc87e919c0ce8e213edf2ffca17f384f059873d3", "tree": "0bd3d67b0320c486e9ec1c846569c3a72baf6bc7", "parents": [ "8a339e7321f10dc2f28928ffadb69b6c7c2d5c3b" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 10:58:46 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:45 2009 -0700" }, "message": "PCI ASPM: fix possible null pointer dereference\n\nFix possible NULL dereference in pcie_aspm_exit_link_state(). This\npatch also cleanup some code.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8a339e7321f10dc2f28928ffadb69b6c7c2d5c3b", "tree": "b89669aed567cced569a0eb1fcb557268f608cee", "parents": [ "b127bd55d9cd9d5b40278b30645669d6d46933bc" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 10:58:09 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:45 2009 -0700" }, "message": "PCI ASPM: remove redundant list check\n\nRemove the following check in __pcie_aspm_config_link() because it\nnerver be true.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b127bd55d9cd9d5b40278b30645669d6d46933bc", "tree": "93aed7b6e6d0f164ee2678f36fe87c9a68ba5114", "parents": [ "6f1186be4feb3364d3a52cbea81e43e4d5296196" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 10:57:31 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:44 2009 -0700" }, "message": "PCI ASPM: do not clear enabled field by support field\n\nWe must not clear bits in \u0027aspm_enabled\u0027 using \u0027aspm_support\u0027, or\n\u0027aspm_enabled\u0027 and \u0027aspm_default\u0027 might be different from the actual\nstate. In addtion, \u0027aspm_default\u0027 should be intialized even if\n\u0027aspm_support\u0027 is 0.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "50e5628a4ac465a52f0d4ca6567343be029731a0", "tree": "f5c083d0b80ed3fc782921d7885200cddf04fcc8", "parents": [ "0d07348931daef854aca8c834a89f1a99ba4ff2b" ], "author": { "name": "Joe Perches", "email": "joe@perches.com", "time": "Sun Jun 28 09:26:40 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jun 29 12:10:35 2009 -0700" }, "message": "PCI ECRC: Remove unnecessary semicolons\n\nAcked-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5c92ffb1ecc7f13267cdef5dda8a838937912c93", "tree": "50a5ffeea038549e1195d80f10b183f55c45e4ef", "parents": [ "3647584d9ef35c9ec4abefdbea29959c26c54f13" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:23:57 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:23 2009 -0700" }, "message": "PCI ASPM: remove get_root_port_link\n\nBy having a pointer to the root port link, we can remove loops in\nget_root_port_link() to search the root port link.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3647584d9ef35c9ec4abefdbea29959c26c54f13", "tree": "107167bb680a15c1581dfb3f05737cfe514c6c29", "parents": [ "efdf8288819df67d608a186f9d17a7d4051f3c1f" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:23:09 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:22 2009 -0700" }, "message": "PCI ASPM: cleanup pcie_aspm_sanity_check\n\nMinor cleanup for pcie_aspm_sanity_check().\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "efdf8288819df67d608a186f9d17a7d4051f3c1f", "tree": "3d781654102cafc726bbc1894070260364eac3af", "parents": [ "5e0eaa7d3679c3ef8618803bc9311270e5816641" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:22:26 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:22 2009 -0700" }, "message": "PCI ASPM: remove has_switch field\n\nWe don\u0027t need the \u0027has_switch\u0027 field in the struct pcie_link_state.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5e0eaa7d3679c3ef8618803bc9311270e5816641", "tree": "895538798c0fd42aa499ac78ed0cb40a8fec27fa", "parents": [ "7ab709910323a8af20722c066267516b3e7680a2" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:21:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:21 2009 -0700" }, "message": "PCI ASPM: cleanup calc_Lx_latency\n\nCleanup for calc_L0S_latency() and calc_L1_latency().\n\n - Separate exit latency and acceptable latency calculation.\n - Some minor cleanups.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7ab709910323a8af20722c066267516b3e7680a2", "tree": "d35af8b1894b3813ef1fc7a6aea13fa9dbda78b9", "parents": [ "430842e29d396928989c0a45e05025e988004d79" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:20:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:20 2009 -0700" }, "message": "PCI ASPM: cleanup pcie_aspm_get_cap_device\n\nMinor cleanup for pcie_aspm_get_cap_device().\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "430842e29d396928989c0a45e05025e988004d79", "tree": "ecdfed05c82324784fabf42f5f008efa1d3c6dc5", "parents": [ "f7ea3d7fc03753b08e267fece19c56383e6b856f" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:20:10 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:19 2009 -0700" }, "message": "PCI ASPM: cleanup clkpm checks\n\nIn the current ASPM implementation, callers of pcie_set_clock_pm() check\nClock PM capability of the link or current Clock PM state of the link.\nThis check should be done in pcie_set_clock_pm() itself.\n\nThis patch moves those checks into pcie_set_clock_pm(). It also\nintroduces pcie_set_clkpm_nocheck() that is equivalent to old\npcie_set_clock_pm(), for the caller who wants to change Clocl PM state\nregardless of the Clock PM capability or current Clock PM state. In\naddition, this patch changes the function name from\npcie_set_clock_pm() to pcie_set_clkpm() for consistency.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f7ea3d7fc03753b08e267fece19c56383e6b856f", "tree": "2ff13c579b8e7dedf3a088b93982e25a3647bdf1", "parents": [ "8d349ace9a5c2a8404bcf4a371fe170480ffbebb" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:19:00 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:18 2009 -0700" }, "message": "PCI ASPM: cleanup __pcie_aspm_check_state_one\n\nClean up and simplify __pcie_aspm_check_state_one().\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8d349ace9a5c2a8404bcf4a371fe170480ffbebb", "tree": "6495378f6b3255752cd04af22e653ece36c7d8b7", "parents": [ "5aa63583cbec27482c6f1d761a0509f59b7969a8" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:18:22 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:15 2009 -0700" }, "message": "PCI ASPM: cleanup initialization\n\nClean up ASPM initialization by refactoring some functionality, renaming\nfunctions, and moving things around.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5aa63583cbec27482c6f1d761a0509f59b7969a8", "tree": "a989edcd7e85199aee66eff2f087dfd6d94176bb", "parents": [ "5cde89d80172a393e49077d2450545b97ac8d972" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:17:44 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:26 2009 -0700" }, "message": "PCI ASPM: cleanup change input argument of aspm functions\n\nIn the current ASPM implementation, there are many functions that\ntake a pointer to struct pci_dev corresponding to the upstream component\nof the link as a parameter. But, since those functions handle PCI\nexpress link state, a pointer to struct pcie_link_state is more\nsuitable than a pointer to struct pci_dev. Changing a parameter to a\npointer to struct pcie_link_state makes ASPM code much simpler and\neasier to read. This patch also contains some minor cleanups. This patch\ndoesn\u0027t have any functional change.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" } ], "next": "5cde89d80172a393e49077d2450545b97ac8d972" }