)]}'
{
  "log": [
    {
      "commit": "ec8c0446b6e2b67b5c8813eb517f4bf00efa99a9",
      "tree": "e7c12d7c486c958a5e38888b41cfcd6a558f1aff",
      "parents": [
        "bcd022801ee514e28c32837f0b3ce18c775f1a7b"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Tue Dec 12 17:14:57 2006 +0000"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.osdl.org",
        "time": "Wed Dec 13 09:27:08 2006 -0800"
      },
      "message": "[PATCH] Optimize D-cache alias handling on fork\n\nVirtually index, physically tagged cache architectures can get away\nwithout cache flushing when forking.  This patch adds a new cache\nflushing function flush_cache_dup_mm(struct mm_struct *) which for the\nmoment I\u0027ve implemented to do the same thing on all architectures\nexcept on MIPS where it\u0027s a no-op.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "26ef5c09576496dfd08d2b36ec1d08a6f917a0eb",
      "tree": "6a0bc875966eb00dc04dc2fdf7deeac96262698b",
      "parents": [
        "e130bedb7ce718a8eb6b56a3806b96281f618111"
      ],
      "author": {
        "name": "David Gibson",
        "email": "david@gibson.dropbear.id.au",
        "time": "Thu Nov 10 11:50:16 2005 +1100"
      },
      "committer": {
        "name": "Paul Mackerras",
        "email": "paulus@samba.org",
        "time": "Thu Nov 10 13:09:22 2005 +1100"
      },
      "message": "[PATCH] powerpc: Merge cacheflush.h and cache.h\n\nThe ppc32 and ppc64 versions of cacheflush.h were almost identical.\nThe two versions of cache.h are fairly similar, except for a bunch of\nregister definitions in the ppc32 version which probably belong better\nelsewhere.  This patch, therefore, merges both headers.  Notable\npoints:\n\t- there are several functions in cacheflush.h which exist only\non ppc32 or only on ppc64.  These are handled by #ifdef for now, but\nthese should probably be consolidated, along with the actual code\nbehind them later.\n\t- Confusingly, both ppc32 and ppc64 have a\nflush_dcache_range(), but they\u0027re subtly different: it uses dcbf on\nppc32 and dcbst on ppc64, ppc64 has a flush_inval_dcache_range() which\nuses dcbf.  These too should be merged and consolidated later.\n\t- Also flush_dcache_range() was defined in cacheflush.h on\nppc64, and in cache.h on ppc32.  In the merged version it\u0027s in\ncacheflush.h\n\t- On ppc32 flush_icache_range() is a normal function from\nmisc.S.  On ppc64, it was wrapper, testing a feature bit before\ncalling __flush_icache_range() which does the actual flush.  This\npatch takes the ppc64 approach, which amounts to no change on ppc32,\nsince CPU_FTR_COHERENT_ICACHE will never be set there, but does mean\nrenaming flush_icache_range() to __flush_icache_range() in\narch/ppc/kernel/misc.S and arch/powerpc/kernel/misc_32.S\n\t- The PReP register info from asm-ppc/cache.h has moved to\narch/ppc/platforms/prep_setup.c\n\t- The 8xx register info from asm-ppc/cache.h has moved to a\nnew asm-powerpc/reg_8xx.h, included from reg.h\n\t- flush_dcache_all() was defined on ppc32 (only), but was\nnever called (although it was exported).  Thus this patch removes it\nfrom cacheflush.h and from ARCH\u003dpowerpc (misc_32.S) entirely.  It\u0027s\nleft in ARCH\u003dppc for now, with the prototype moved to ppc_ksyms.c.\n\nBuilt for Walnut (ARCH\u003dppc), 32-bit multiplatform (pmac, CHRP and PReP\nARCH\u003dppc, pmac and CHRP ARCH\u003dpowerpc).  Built and booted on POWER5\nLPAR (ARCH\u003dpowerpc and ARCH\u003dppc64).\n\nBuilt for 32-bit powermac (ARCH\u003dppc and ARCH\u003dpowerpc).  Built and\nbooted on POWER5 LPAR (ARCH\u003dpowerpc and ARCH\u003dppc64).  Built and booted\non G5 (ARCH\u003dpowerpc)\n\nSigned-off-by: David Gibson \u003cdavid@gibson.dropbear.id.au\u003e\nSigned-off-by: Paul Mackerras \u003cpaulus@samba.org\u003e\n"
    }
  ]
}