)]}' { "log": [ { "commit": "c768e67625688517c23f46b31a46e1f7d2de1c71", "tree": "5b3e970fed1fd5eea71a8254c210f967b816e669", "parents": [ "f248dc626e95a2b61fed3631df49aef23f1736b8" ], "author": { "name": "Hartley Sweeten", "email": "hartleys@visionengravers.com", "time": "Wed Oct 21 02:27:01 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 21 13:09:37 2009 +0100" }, "message": "ARM: 5769/1: CPU_ARM920T: remove dead Maverick EP9312 URL\n\nRemove the URL listed for Maverick EP9312 since it is not available\nand modify the help text appropriately.\n\nSigned-off-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nAcked-by: Ryan Mallon \u003cryan@bluewatersys.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "787b2faadc4356b6c2c71feb42fb944fece9a12f", "tree": "e3acab624bb2de248a2e4f1e6293024200c8dc8c", "parents": [ "edc72786d208e77db94f84dcb0d166c0d23d82f7" ], "author": { "name": "Nitin Gupta", "email": "ngupta@vflare.org", "time": "Mon Oct 12 14:20:23 2009 +0530" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 12 17:52:26 2009 +0100" }, "message": "ARM: force dcache flush if dcache_dirty bit set\n\nOn ARM, update_mmu_cache() does dcache flush for a page only if\nit has a kernel mapping (page_mapping(page) !\u003d NULL). The correct\nbehavior would be to force the flush based on dcache_dirty bit only.\n\nOne of the cases where present logic would be a problem is when\na RAM based block device[1] is used as a swap disk. In this case,\nwe would have in-memory data corruption as shown in steps below:\n\ndo_swap_page()\n{\n - Allocate a new page (if not already in swap cache)\n - Issue read from swap disk\n - Block driver issues flush_dcache_page()\n - flush_dcache_page() simply sets PG_dcache_dirty bit and does not\n actually issue a flush since this page has no user space mapping yet.\n - Now, if swap disk is almost full, this newly read page is removed\n from swap cache and corrsponding swap slot is freed.\n - Map this page anonymously in user space.\n - update_mmu_cache()\n - Since this page does not have kernel mapping (its not in page/swap\n cache and is mapped anonymously), it does not issue dcache flush\n even if dcache_dirty bit is set by flush_dcache_page() above.\n\n \u003cuser now gets stale data since dcache was never flushed\u003e\n}\n\nSame problem exists on mips too.\n\n[1] example:\n - brd (RAM based block device)\n - ramzswap (RAM based compressed swap device)\n\nSigned-off-by: Nitin Gupta \u003cngupta@vflare.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "6a5e293f1b34920c69a932ce37b4a4714a428dc7", "tree": "d5d85081d906126cdd539d297fa2ef2eb07b1f61", "parents": [ "e9ac829185c5d17787d78c13c05a40c39d660239" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Oct 11 16:29:48 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Oct 11 16:29:48 2009 +0100" }, "message": "ARM: Add kmap_atomic type debugging\n\nSeemingly this support was missed when highmem was added, so\nDEBUG_HIGHMEM wouldn\u0027t have checked the kmap_atomic type.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "3257f43d9296ed7adcc84e48f6ddf5313cf29266", "tree": "97cfb5a7bcd2d21452a7716c4daa8ea512fc1ab7", "parents": [ "32cfb1b16f2b68d2296536811cadfffe26a06c1b" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Tue Oct 06 17:57:22 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 07 13:13:00 2009 +0100" }, "message": "ARM: 5747/1: Fix the start_pg value in free_memmap()\n\nIf sparsemem is enabled, the start_pfn passed to the free_memmap()\nfunction corresponds to an area of memory not known to the kernel and\npfn_to_page returns a wrong value. The (start_pfn - 1), however, is\nknown to the kernel.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "32cfb1b16f2b68d2296536811cadfffe26a06c1b", "tree": "6872f034656cc4ffb80ba51f9b29c35bb8da9f9e", "parents": [ "cc1ad4a69667be885ac6036a315066854ef8c871" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Tue Oct 06 17:57:09 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 07 13:12:59 2009 +0100" }, "message": "ARM: 5746/1: Handle possible translation errors in ARMv6/v7 coherent_user_range\n\nThis is needed because applications using the sys_cacheflush system call\ncan pass a memory range which isn\u0027t mapped yet even though the\ncorresponding vma is valid. The patch also adds unwinding annotations\nfor correct backtraces from the coherent_user_range() functions.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "1d2127123db9b1821959c2b8b7473dd7ffcdf527", "tree": "17134cbb3a6d7a077e5f05877964b1258d1f30c8", "parents": [ "e89e04fcdce6146cab3a34d4073f8a1714b457ec" ], "author": { "name": "Imre Deak", "email": "imre.deak@nokia.com", "time": "Mon Oct 05 13:40:44 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 05 17:55:55 2009 +0100" }, "message": "ARM: 5742/1: ARM: add debug check for invalid kernel page faults\n\nAccording to the following in arch/arm/mm/fault.c page faults from\nkernel mode are invalid if mmap_sem is already held and there is\nno exception handler defined for the faulting instruction:\n\n/*\n * As per x86, we may deadlock here. However, since the kernel only\n * validly references user space from well defined areas of the code,\n * we can bug out early if this is from code which shouldn\u0027t.\n */\nif (!down_read_trylock(\u0026mm-\u003emmap_sem)) {\n\tif (!user_mode(regs) \u0026\u0026 !search_exception_tables(regs-\u003eARM_pc))\n\t\tgoto no_context;\n\nSince mmap_sem can be held at arbitrary times by another thread this\nalso means that any page faults from kernel mode are invalid if no\nexception handler is defined for them, regardless whether mmap_sem is\nheld at the time of fault.\n\nTo easier detect code that can trigger the above error, add a check\nalso for the case where mmap_sem is acquired. As this has an overhead\nmake it a VM debug check.\n\nSigned-off-by: Imre Deak \u003cimre.deak@nokia.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d25ef8b86e6a58f5476bf6e4a8da730b335f68fa", "tree": "2d7773ed145ace0f93d7a11ee9f738a4df4be14f", "parents": [ "4fb2847437d871fe579f820ceb18031db3359901" ], "author": { "name": "Kirill A. Shutemov", "email": "kirill@shutemov.name", "time": "Fri Sep 25 13:40:49 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Oct 02 22:34:32 2009 +0100" }, "message": "ARM: 5728/1: Proper prefetch abort handling on ARMv6 and ARMv7\n\nCurrently, on ARMv6 and ARMv7, if an application tries to execute\ncode (or garbage) on non-executable page it hangs. It caused by\nincorrect prefetch abort handling. Now every prefetch abort\nprocesses as a translation fault.\n\nTo fix this we have to analyze instruction fault status register\nto figure out reason why we\u0027ve got the abort and process it\naccordingly.\n\nTo make IFSR different from DFSR we set bit 31 which is reserved in\nboth IFSR and DFSR.\n\nThis patch also tries to protect from future hangs on unexpected\nexceptions. An application will be killed if unexpected exception\ntype was received.\n\nSigned-off-by: Kirill A. Shutemov \u003ckirill@shutemov.name\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "4fb2847437d871fe579f820ceb18031db3359901", "tree": "e2015dbc54178dd114eb0c41fa5a29d89dd15b41", "parents": [ "6806bfe18fca92e2001538b84cab5f63c5ea4bed" ], "author": { "name": "Kirill A. Shutemov", "email": "kirill@shutemov.name", "time": "Fri Sep 25 13:39:47 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Oct 02 22:34:32 2009 +0100" }, "message": "ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()\n\nInstruction fault status register, IFSR, was introduced on ARMv6 to\nprovide status information about the last insturction fault. It\nneeded for proper prefetch abort handling.\n\nNow we have three prefetch abort model:\n\n * legacy - for CPUs before ARMv6. They doesn\u0027t provide neither\n IFSR nor IFAR. We simulate IFSR with section translation fault\n status for them to generalize code;\n * ARMv6 - provides IFSR, but not IFAR;\n * ARMv7 - provides both IFSR and IFAR.\n\nSigned-off-by: Kirill A. Shutemov \u003ckirill@shutemov.name\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "6806bfe18fca92e2001538b84cab5f63c5ea4bed", "tree": "5279f344e2da4fd87dadd5a2e39142175807f1e7", "parents": [ "31abdb744179159f8b605f56da5b197b188e1689" ], "author": { "name": "Greg Ungerer", "email": "gerg@snapgear.com", "time": "Fri Oct 02 00:45:28 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Oct 02 22:32:34 2009 +0100" }, "message": "ARM: 5740/1: fix valid_phys_addr_range() range check\n\nCommit 1522ac3ec95ff0230e7aa516f86b674fdf72866c\n(\"Fix virtual to physical translation macro corner cases\")\nbreaks the end of memory check in valid_phys_addr_range().\nThe modified expression results in the apparent /dev/mem size\nbeing 2 bytes smaller than what it actually is.\n\nThis patch reworks the expression to correctly check the address,\nwhile maintaining use of a valid address to __pa().\n\nSigned-off-by: Greg Ungerer \u003cgerg@uclinux.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "e616c591405c168f6dc3dfd1221e105adfe49b8d", "tree": "e2e7642873628746aba95dd22d90da26935383ab", "parents": [ "9a0f6b4646a0acaf7f06fd2e02f10f303fe85d8f" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 27 20:55:43 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Sep 28 18:06:20 2009 +0100" }, "message": "ARM: Don\u0027t allow highmem on SMP platforms without h/w TLB ops broadcast\n\nWe suffer an unfortunate combination of \"features\" which makes highmem\nsupport on platforms without hardware TLB maintainence broadcast difficult:\n\n- we need kmap_high_get() support for DMA cache coherence\n- this requires kmap_high() to take a spinlock with IRQs disabled\n- kmap_high() occasionally calls flush_all_zero_pkmaps() to clear\n out old mappings\n- flush_all_zero_pkmaps() calls flush_tlb_kernel_range(), which\n on s/w IPI\u0027d systems eventually calls smp_call_function_many()\n- smp_call_function_many() must not be called with IRQs disabled:\n\nWARNING: at kernel/smp.c:380 smp_call_function_many+0xc4/0x240()\nModules linked in:\nBacktrace:\n[\u003cc00306f0\u003e] (dump_backtrace+0x0/0x108) from [\u003cc0286e6c\u003e] (dump_stack+0x18/0x1c)\n r6:c007cd18 r5:c02ff228 r4:0000017c\n[\u003cc0286e54\u003e] (dump_stack+0x0/0x1c) from [\u003cc0053e08\u003e] (warn_slowpath_common+0x50/0x80)\n[\u003cc0053db8\u003e] (warn_slowpath_common+0x0/0x80) from [\u003cc0053e50\u003e] (warn_slowpath_null+0x18/0x1c)\n r7:00000003 r6:00000001 r5:c1ff4000 r4:c035fa34\n[\u003cc0053e38\u003e] (warn_slowpath_null+0x0/0x1c) from [\u003cc007cd18\u003e] (smp_call_function_many+0xc4/0x240)\n[\u003cc007cc54\u003e] (smp_call_function_many+0x0/0x240) from [\u003cc007cec0\u003e] (smp_call_function+0x2c/0x38)\n[\u003cc007ce94\u003e] (smp_call_function+0x0/0x38) from [\u003cc005980c\u003e] (on_each_cpu+0x1c/0x38)\n[\u003cc00597f0\u003e] (on_each_cpu+0x0/0x38) from [\u003cc0031788\u003e] (flush_tlb_kernel_range+0x50/0x58)\n r6:00000001 r5:00000800 r4:c05f3590\n[\u003cc0031738\u003e] (flush_tlb_kernel_range+0x0/0x58) from [\u003cc009c600\u003e] (flush_all_zero_pkmaps+0xc0/0xe8)\n[\u003cc009c540\u003e] (flush_all_zero_pkmaps+0x0/0xe8) from [\u003cc009c6b4\u003e] (kmap_high+0x8c/0x1e0)\n[\u003cc009c628\u003e] (kmap_high+0x0/0x1e0) from [\u003cc00364a8\u003e] (kmap+0x44/0x5c)\n[\u003cc0036464\u003e] (kmap+0x0/0x5c) from [\u003cc0109dfc\u003e] (cramfs_readpage+0x3c/0x194)\n[\u003cc0109dc0\u003e] (cramfs_readpage+0x0/0x194) from [\u003cc0090c14\u003e] (__do_page_cache_readahead+0x1f0/0x290)\n[\u003cc0090a24\u003e] (__do_page_cache_readahead+0x0/0x290) from [\u003cc0090ce4\u003e] (ra_submit+0x30/0x38)\n[\u003cc0090cb4\u003e] (ra_submit+0x0/0x38) from [\u003cc0089384\u003e] (filemap_fault+0x3dc/0x438)\n r4:c1819988\n[\u003cc0088fa8\u003e] (filemap_fault+0x0/0x438) from [\u003cc009d21c\u003e] (__do_fault+0x58/0x43c)\n[\u003cc009d1c4\u003e] (__do_fault+0x0/0x43c) from [\u003cc009e8cc\u003e] (handle_mm_fault+0x104/0x318)\n[\u003cc009e7c8\u003e] (handle_mm_fault+0x0/0x318) from [\u003cc0033c98\u003e] (do_page_fault+0x188/0x1e4)\n[\u003cc0033b10\u003e] (do_page_fault+0x0/0x1e4) from [\u003cc0033ddc\u003e] (do_translation_fault+0x7c/0x84)\n[\u003cc0033d60\u003e] (do_translation_fault+0x0/0x84) from [\u003cc002b474\u003e] (do_DataAbort+0x40/0xa4)\n r8:c1ff5e20 r7:c0340120 r6:00000805 r5:c1ff5e54 r4:c03400d0\n[\u003cc002b434\u003e] (do_DataAbort+0x0/0xa4) from [\u003cc002bcac\u003e] (__dabt_svc+0x4c/0x60)\n...\n\nSo we disable highmem support on these systems.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "041d785f807c8e92e11cc1bd2b3438f7823e63d2", "tree": "91364697e90a0a6af75c3313bf703e79f62f87c9", "parents": [ "d80ade7b323152672bf66e74ec11c324332f6d1e" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 27 17:40:42 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Sep 28 18:06:20 2009 +0100" }, "message": "ARM: Fix warning: unused variable \u0027highmem\u0027\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "baea7b946f00a291b166ccae7fcfed6c01530cc6", "tree": "4aa275fbdbec9c7b9b4629e8bee2bbecd3c6a6af", "parents": [ "ae19ffbadc1b2100285a5b5b3d0a4e0a11390904", "94e0fb086fc5663c38bbc0fe86d698be8314f82f" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Sep 24 21:22:33 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Sep 24 21:22:33 2009 +0100" }, "message": "Merge branch \u0027origin\u0027 into for-linus\n\nConflicts:\n\tMAINTAINERS\n" }, { "commit": "56f8ba83a52b9f9e3711eff8e54168ac14aa288f", "tree": "e030f7f3a191384268d86863ca43237a137e8f51", "parents": [ "a6a01063de6298c60f2506dc7659403e02b4b224" ], "author": { "name": "Rusty Russell", "email": "rusty@rustcorp.com.au", "time": "Thu Sep 24 09:34:49 2009 -0600" }, "committer": { "name": "Rusty Russell", "email": "rusty@rustcorp.com.au", "time": "Thu Sep 24 09:34:49 2009 +0930" }, "message": "cpumask: use mm_cpumask() wrapper: arm\n\nMakes code futureproof against the impending change to mm-\u003ecpu_vm_mask.\n\nIt\u0027s also a chance to use the new cpumask_ ops which take a pointer\n(the older ones are deprecated, but there\u0027s no hurry for arch code).\n\nSigned-off-by: Rusty Russell \u003crusty@rustcorp.com.au\u003e\n" }, { "commit": "ae19ffbadc1b2100285a5b5b3d0a4e0a11390904", "tree": "3c2086ab67398a019089a47ca3f362a4bc6db74f", "parents": [ "34e84f39a27d059a3e6ec6e8b94aafa702e6f220", "9173a8ef24a6b1b8031507b35b8ffe5f85a87692" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 22 20:54:53 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 22 21:01:40 2009 +0100" }, "message": "Merge branch \u0027master\u0027 into for-linus\n" }, { "commit": "cc013a88906bad9d2832d6316de1c7dbc1c2a794", "tree": "c47d1bc76cf9bbf94c328ca6e15ac99ddbab7603", "parents": [ "73d7c33e81aed92ac185950a20407c1a2ea65a83" ], "author": { "name": "Geert Uytterhoeven", "email": "Geert.Uytterhoeven@sonycom.com", "time": "Mon Sep 21 17:02:36 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Sep 22 07:17:34 2009 -0700" }, "message": "arches: drop superfluous casts in nr_free_pages() callers\n\nCommit 96177299416dbccb73b54e6b344260154a445375 (\"Drop free_pages()\")\nmodified nr_free_pages() to return \u0027unsigned long\u0027 instead of \u0027unsigned\nint\u0027. This made the casts to \u0027unsigned long\u0027 in most callers superfluous,\nso remove them.\n\n[akpm@linux-foundation.org: coding-style fixes]\nSigned-off-by: Geert Uytterhoeven \u003cGeert.Uytterhoeven@sonycom.com\u003e\nReviewed-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nAcked-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\nAcked-by: Kyle McMartin \u003ckyle@mcmartin.ca\u003e\nAcked-by: WANG Cong \u003cxiyou.wangcong@gmail.com\u003e\nCc: Richard Henderson \u003crth@twiddle.net\u003e\nCc: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nCc: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nCc: Mikael Starvik \u003cstarvik@axis.com\u003e\nCc: \"Luck, Tony\" \u003ctony.luck@intel.com\u003e\nCc: Hirokazu Takata \u003ctakata@linux-m32r.org\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: David Howells \u003cdhowells@redhat.com\u003e\nAcked-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Chris Zankel \u003czankel@tensilica.com\u003e\nCc: Michal Simek \u003cmonstr@monstr.eu\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "df297bf6c7933e7b021cdc1bf3f9e319ea3a7e9c", "tree": "9ef6353c4100c83176c4e7b5ef3933dc342f91df", "parents": [ "d374bf14a5ff18133bd6a6cc00f189949f7ba8fb" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 20 13:18:47 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 20 16:53:40 2009 +0100" }, "message": "ARM: Add support for checking access permissions on prefetch aborts\n\nARMv6 introduces non-executable mappings, which can cause prefetch aborts\nwhen an attempt is made to execute from such a mapping. Currently, this\ncauses us to loop in the page fault handler since we don\u0027t correctly\ncheck for proper permissions.\n\nFix this by checking that VMAs have VM_EXEC set for prefetch aborts.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d374bf14a5ff18133bd6a6cc00f189949f7ba8fb", "tree": "d04f40327d5575f5f848695a97099527475a2634", "parents": [ "bf4569922b97824f33e5d08d0bbe4b34fe43e4cd" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 20 12:53:01 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 20 16:53:40 2009 +0100" }, "message": "ARM: Separate out access error checking\n\nSince we get notified separately about prefetch aborts, which may be\npermission faults, we need to check for appropriate access permissions\nwhen handling a fault. This patch prepares us for doing this by\nseparating out the access error checking.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "bf4569922b97824f33e5d08d0bbe4b34fe43e4cd", "tree": "09d3bc1252c44c70a9f4090486daa1329189da0c", "parents": [ "b42c6344b091db680fd1ec7a0483e8b6796f802b" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 20 12:52:19 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 20 12:55:50 2009 +0100" }, "message": "ARM: Ensure correct might_sleep() check in pagefault path\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b42c6344b091db680fd1ec7a0483e8b6796f802b", "tree": "37b25ae64b025dfbf041630e4d4b26b63b0a217f", "parents": [ "c88d6aa71bd2ad7b4da2f281bd64ada65d533d83" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 20 12:47:40 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 20 12:55:49 2009 +0100" }, "message": "ARM: Update page fault handling for new OOM techniques\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "c88d6aa71bd2ad7b4da2f281bd64ada65d533d83", "tree": "dbc0f5ad6f48abddde2072300b0e4617d7d46cd4", "parents": [ "4275c13ca8859af8a1390856c82173bcdfc32938" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 20 12:41:58 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 20 12:55:49 2009 +0100" }, "message": "ARM: Provide definitions and helpers for decoding the FSR register\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "40d743b8c16a8cf6e30c1d941aa6147f9550ea75", "tree": "9fcdf9a06b18a275253048d1ea7c9803cec38845", "parents": [ "7da18afa423f167e7ef3c9728e584d8bf05bd55a", "83e686ea0291ee93b87dcdc00b96443b80de56c9" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Sep 19 13:47:57 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Sep 19 13:47:57 2009 +0100" }, "message": "Merge branch \u0027for-rmk\u0027 of git://linux-arm.org/linux-2.6\n" }, { "commit": "bc581770cfdd8c17ea17d324dc05e2f9c599e7ca", "tree": "c6d2c2eb82d8a6c6851de0ecc7d8c0e63e026266", "parents": [ "18240904960a39e582ced8ba8ececb10b8c22dd3" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Sep 15 17:30:37 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 15 22:11:05 2009 +0100" }, "message": "ARM: 5580/2: ARM TCM (Tightly-Coupled Memory) support v3\n\nThis adds the TCM interface to Linux, when active, it will\ndetect and report TCM memories and sizes early in boot if\npresent, introduce generic TCM memory handling, provide a\ngeneric TCM memory pool and select TCM memory for the U300\nplatform.\n\nSee the Documentation/arm/tcm.txt for documentation.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "910a17e57ab6cd22b300bde4ce5f633f175c7ccd", "tree": "2a1dea95ca2d50192216500d90d9b0358af1dc1d", "parents": [ "59fcf48fdebe65e4774d2c7ec76b7845d281749a" ], "author": { "name": "Kirill A. Shutemov", "email": "kirill@shutemov.name", "time": "Tue Sep 15 10:23:53 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 15 22:06:38 2009 +0100" }, "message": "ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size\n\nCurrently kernel believes that all ARM CPUs have L1_CACHE_SHIFT \u003d\u003d 5.\nIt\u0027s not true at least for CPUs based on Cortex-A8.\n\nList of CPUs with cache line size !\u003d 32 should be expanded later.\n\nSigned-off-by: Kirill A. Shutemov \u003ckirill@shutemov.name\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "2f82af08fcc7dc01a7e98a49a5995a77e32a2925", "tree": "d505fe5936881b137b82b59360646a6988e506ba", "parents": [ "f199fd990639f93d07d8e104b0a66aabaf01d67d" ], "author": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Mon Sep 14 03:25:28 2009 -0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Sep 15 09:37:12 2009 -0700" }, "message": "Nicolas Pitre has a new email address\n\nDue to problems at cam.org, my nico@cam.org email address is no longer\nvalid. FRom now on, nico@fluxnic.net should be used instead.\n\nSigned-off-by: Nicolas Pitre \u003cnico@fluxnic.net\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "87d721ad7a37b7650dd710c88dd5c6a5bf9fe996", "tree": "869d633803eb7c429624d3bd16a6117816849763", "parents": [ "ddd559b13f6d2fe3ad68c4b3f5235fd3c2eae4e3", "b7cfda9fc3d7aa60cffab5367f2a72a4a70060cd" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Sep 12 12:04:37 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Sep 12 12:04:37 2009 +0100" }, "message": "Merge branch \u0027master\u0027 into devel\n" }, { "commit": "ddd559b13f6d2fe3ad68c4b3f5235fd3c2eae4e3", "tree": "d827bca3fc825a0ac33efbcd493713be40fcc812", "parents": [ "cf7a2b4fb6a9b86779930a0a123b0df41aa9208f", "f17a1f06d2fa93f4825be572622eb02c4894db4e" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Sep 12 12:02:26 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Sep 12 12:02:26 2009 +0100" }, "message": "Merge branch \u0027devel-stable\u0027 into devel\n\nConflicts:\n\tMAINTAINERS\n\tarch/arm/mm/fault.c\n" }, { "commit": "701038144945ef98c5817f43079952fa38c35999", "tree": "88782f6ac8e4df1f7f8f738659adedd7108e8cae", "parents": [ "4abf27add86e5b7c37dca1fb4dd9a740b4332a84", "c2b455474e4c6bc8bab6506e2a08dbd5ad50d74d" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Sep 12 11:50:52 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Sep 12 11:50:52 2009 +0100" }, "message": "Merge branch \u0027nomadik\u0027 into devel-stable\n" }, { "commit": "b7cfda9fc3d7aa60cffab5367f2a72a4a70060cd", "tree": "a52c6cdbbc7973a4904ec499a607732832e4ca38", "parents": [ "5eb38f44839ec1aade167b125d86d265c886c195" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Sep 07 15:06:42 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Sep 12 11:48:09 2009 +0100" }, "message": "ARM: Fix pfn_valid() for sparse memory\n\nOn OMAP platforms, some people want to declare to segment up the memory\nbetween the kernel and a separate application such that there is a hole\nin the middle of the memory as far as Linux is concerned. However,\nthey want to be able to mmap() the hole.\n\nThis currently causes problems, because update_mmu_cache() thinks that\nthere are valid struct pages for the \"hole\". Fix this by making\npfn_valid() slightly more expensive, by checking whether the PFN is\ncontained within the meminfo array.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nTested-by: Khasim Syed Mohammed \u003ckhasim@ti.com\u003e\n" }, { "commit": "7929eb9cf643ae416e5081b2a6fa558d37b9854c", "tree": "c4cbaa5ccdd1c929eba802374d80191b6f90e16c", "parents": [ "c47a830c08a26a7c210ae16a0ffe3f56ba86ea69" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Thu Sep 03 21:45:59 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Sep 04 19:20:07 2009 +0100" }, "message": "ARM: 5691/1: fix cache aliasing issues between kmap() and kmap_atomic() with highmem\n\nLet\u0027s suppose a highmem page is kmap\u0027d with kmap(). A pkmap entry is\nused, the page mapped to it, and the virtual cache is dirtied. Then\nkunmap() is used which does virtually nothing except for decrementing a\nusage count.\n\nThen, let\u0027s suppose the _same_ page gets mapped using kmap_atomic().\nIt is therefore mapped onto a fixmap entry instead, which has a\ndifferent virtual address unaware of the dirty cache data for that page\nsitting in the pkmap mapping.\n\nFortunately it is easy to know if a pkmap mapping still exists for that\npage and use it directly with kmap_atomic(), thanks to kmap_high_get().\n\nAnd actual testing with a printk in the added code path shows that this\ncondition is actually met *extremely* frequently. Seems that we\u0027ve been\nquite lucky that things have worked so well with highmem so far.\n\nCc: stable@kernel.org\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "13f96d8f4c5a3f6a6b5e578d08869d79d690e0b2", "tree": "fe33eb0bce77b41d9e7a491b1241db6a70a93df2", "parents": [ "37d0892c5a94e208cf863e3b7bac014edee4346d" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Tue Sep 01 22:01:27 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Sep 02 11:33:24 2009 +0100" }, "message": "ARM: 5687/1: fix an oops with highmem\n\nIn xdr_partial_copy_from_skb() there is that sequence:\n\n\t\tkaddr \u003d kmap_atomic(*ppage, KM_SKB_SUNRPC_DATA);\n\t\t[...]\n\t\tflush_dcache_page(*ppage);\n\t\tkunmap_atomic(kaddr, KM_SKB_SUNRPC_DATA);\n\nMixing flush_dcache_page() and kmap_atomic() is a bit odd,\nespecially since kunmap_atomic() must deal with cache issues\nalready. OTOH the non-highmem case must use flush_dcache_page()\nas kunmap_atomic() becomes a no op with no cache maintenance.\n\nProblem is that with highmem the implementation of kmap_atomic()\ndoesn\u0027t set page-\u003evirtual, and page_address(page) returns 0 in\nthat case. Here flush_dcache_page() calls __flush_dcache_page()\nwhich calls __cpuc_flush_dcache_page(page_address(page)) resulting\nin a kernel oops.\n\nNone of the kmap_atomic() implementations uses set_page_address().\nHence we can assume page_address() is always expected to return 0 in\nthat case. Let\u0027s conditionally call __cpuc_flush_dcache_page() only\nwhen the page address is non zero, and perform that test only when\nhighmem is configured.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "65cec8e3db606608fd1f8dfc4a1c7c37bfba9173", "tree": "b1e0ecd6380afa2286fffada08cddbd388640343", "parents": [ "369842658a36bcea28ecb643ba4bdb53919330dd" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Aug 17 20:02:06 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Aug 17 20:02:06 2009 +0100" }, "message": "ARM: implement highpte\n\nAdd the ARM implementation of highpte, which allows PTE tables to be\nplaced in highmem. Unfortunately, we do not offer highpte support\nwhen support for L2 cache is enabled.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "dde5828f56cb2c1aa70365c476e6830482127258", "tree": "c5765e13e62d9356a0059d08dba7334202707948", "parents": [ "3b3119fc549c93df60316d28bdd77c2de3986588" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Aug 15 12:36:00 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Aug 15 12:36:00 2009 +0100" }, "message": "ARM: Fix broken highmem support\n\nCurrently, highmem is selectable, and you can request an increased\nvmalloc area. However, none of this has any effect on the memory\nlayout since a patch in the highmem series was accidentally dropped.\nMoreover, even if you did want highmem, all memory would still be\nregistered as lowmem, possibly resulting in overflow of the available\nvirtual mapping space.\n\nThe highmem boundary is determined by the highest allowed beginning\nof the vmalloc area, which depends on its configurable minimum size\n(see commit 60296c71f6c5063e3c1f1d2619ca0b60940162e7 for details on\nthis).\n\nWe should create mappings and initialize bootmem only for low memory,\nwhile the zone allocator must still be told about highmem.\n\nCurrently, memory nodes which are completely located in high memory\nare not supported. This is not a huge limitation since systems\nrelying on highmem support are unlikely to have discontiguous memory\nwith large holes.\n\n[ A similar patch was meant to be merged before commit 5f0fbf9ecaf3\n and be available in Linux v2.6.30, however some git rebase screw-up\n of mine dropped the first commit of the series, and that goofage\n escaped testing somehow as well. -- Nico ]\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nReviewed-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "412bb0a6224f96661c042a109c4978649c00ed52", "tree": "21cff4cf9f97c4cdbd293704ead2a422e4245c37", "parents": [ "bdaaaec39792ee0035d6c5a5ad2520991e090a3c" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:37:09 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:37:09 2009 +0100" }, "message": "Include linux/sched.h in arch/arm/mm/fault.c\n\nWhen building with !MMU, task_struct is not defined. Just include the\nrelevant file.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "bdaaaec39792ee0035d6c5a5ad2520991e090a3c", "tree": "8e7b5f10c1d7c7e85c6f62304f18c16948681dea", "parents": [ "8bdca0ac2b1ec35091941c57b4202f7096291c5b" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:35:06 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:35:06 2009 +0100" }, "message": "nommu: Do not set PRRR and NMRR in proc-v7.S if !MMU\n\nARMv7-R profile CPUs do not have these registers.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "8b79d5f217d7fc7d6b85ee5b10899f2bd20b64ed", "tree": "0419d82bb5c582425e94b45fdb4baec20c5ab8e4", "parents": [ "b32f3afe3c5c4ddd1c414d41845470a99c88475f" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:35:04 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:35:04 2009 +0100" }, "message": "nommu: Add #ifdef CONFIG_MMU around the PTE sanity checks\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "b32f3afe3c5c4ddd1c414d41845470a99c88475f", "tree": "bbf8cac97feba4c1f82e15f9a24d7119fd8131d8", "parents": [ "ab6494f0c96f8953c7ad3e35301b2de2db3add57" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:35:03 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:35:03 2009 +0100" }, "message": "nommu: Include asm/setup.h in arch/arm/mm/nommu.c\n\nThis is needed for the struct meminfo definition.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "ab6494f0c96f8953c7ad3e35301b2de2db3add57", "tree": "08ffb48cb7ce1ec66dc5deeddf7cf4b890882410", "parents": [ "2732f4b6f11689fa08e2db5689fc652d608936b5" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:35:02 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:35:02 2009 +0100" }, "message": "nommu: Add noMMU support to the DMA API\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "09529f7a1a010cc364267fc5895a71c3853eb82c", "tree": "67c02ab7314c48766812065a199c2277f7fe6688", "parents": [ "16c79651a5ee1ad7e4fca65a7c5309dfca89ed28" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:34:55 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:34:55 2009 +0100" }, "message": "nommu: Fix the fault processing for the MMU-less case\n\nThe patch adds the necessary ifdefs around functions that only make\nsense when the MMU is enabled.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n\n\n" }, { "commit": "347c8b70b1d5256e445e54e736f88d21877616cf", "tree": "513ae480cdb8eb46ec68aab77ab78c5d8b3a205b", "parents": [ "b86040a59feb255a8193173caa4d5199464433d5" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:32:56 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri Jul 24 12:32:56 2009 +0100" }, "message": "Thumb-2: Implement the unified arch/arm/mm support\n\nThis patch adds the ARM/Thumb-2 unified support to the arch/arm/mm/*\nfiles.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "f7a55fa6ecef8be6d15bd79a803e44a3187ce9d6", "tree": "92ef2f51f2564abc7e40cdc9f1ef2db966e28c0b", "parents": [ "ee0049d49ad2556222a7b3127be2dae11982f7b3" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Jul 11 16:51:40 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Jul 11 16:55:52 2009 +0100" }, "message": "[ARM] remove L_PTE_BUFFERABLE and L_PTE_CACHEABLE\n\nThese old symbols are meaningless now that we have memory type\nsupport implemented. The entire memory type field needs to be\nmodified rather than just a few bits twiddled.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ba9b42e4ff5eb68f9c946378229d7e45299d7151", "tree": "fd078d8765d9dc39a9ee6e4de27b26d9a3101015", "parents": [ "66d9e2102af038bcd3286a6efce83e1877e5997b" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Jul 05 10:50:37 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Jul 05 15:25:00 2009 +0100" }, "message": "[ARM] export __cpu_flush_dcache_page\n\nNow required for libsas:\n\n Kernel: arch/arm/boot/Image is ready\n Kernel: arch/arm/boot/zImage is ready\n Building modules, stage 2.\n MODPOST 1096 modules\nERROR: \"xscale_flush_kern_dcache_page\" [drivers/scsi/libsas/libsas.ko] undefined!\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "0b260fd4b0eb7c90f9258bfa6317ae553319b5da", "tree": "8b5a53a421c220a34b2f3850478b067bd419f6cb", "parents": [ "725b1f9d86822246e5a1237bf97d2783857d8a3a" ], "author": { "name": "Alessandro Rubini", "email": "rubini@gnudd.com", "time": "Thu Jul 02 15:29:43 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 02 21:20:47 2009 +0100" }, "message": "[ARM] 5587/1: nomadik: add l2cc\n\nSigned-off-by: Alessandro Rubini \u003crubini@unipv.it\u003e\nAcked-by: Andrea Gallo \u003candrea.gallo@stericsson.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9e268beb92ee3a853b3946e84b10358207e2085f", "tree": "dec36344c8b16d53e56763aa174dd7ea806b653f", "parents": [ "2e8b5a09ebf1f98f02c1988a48415e89d4c25168", "9ccdac3662dbf3c75e8f8851a214bdf7d365a4bd" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 14:56:13 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 14:56:13 2009 -0700" }, "message": "Merge branch \u0027devel\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027devel\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm: (49 commits)\n [ARM] idle: clean up pm_idle calling, obey hlt_counter\n [ARM] S3C: Fix gpio-config off-by-one bug\n [ARM] S3C64XX: add to_irq() support for EINT() GPIO\n [ARM] S3C64XX: clock.c: fix typo in usb-host clock ctrlbit\n [ARM] S3C64XX: fix HCLK gate defines\n [ARM] Update mach-types\n [ARM] wire up rt_tgsigqueueinfo and perf_counter_open\n OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons\n OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL\n OMAP3: Add support for DPLL3 divisor values higher than 2\n OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers\n OMAP3 SRAM: add more comments on the SRAM code\n OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change\n OMAP3 clock: add a short delay when lowering CORE clk rate\n OMAP3 clock: initialize SDRC timings at kernel start\n OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize\n [ARM] Add old Feroceon support to compressed/head.S\n [ARM] 5559/1: Limit the stack unwinding caused by a kthread exit\n [ARM] 5558/1: Add extra checks to ARM unwinder to avoid tracing corrupt stacks\n [ARM] 5557/1: Discard some ARM.ex*.*exit.text sections when !HOTPLUG or !HOTPLUG_CPU\n ...\n" }, { "commit": "d06063cc221fdefcab86589e79ddfdb7c0e14b63", "tree": "00ccaf8c1992b57a4445d78b9eae25fde0b3ab31", "parents": [ "30c9f3a9fae79517bca595826a19c6855fbb6d32" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Apr 10 09:01:23 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Jun 21 13:08:22 2009 -0700" }, "message": "Move FAULT_FLAG_xyz into handle_mm_fault() callers\n\nThis allows the callers to now pass down the full set of FAULT_FLAG_xyz\nflags to handle_mm_fault(). All callers have been (mechanically)\nconverted to the new calling convention, there\u0027s almost certainly room\nfor architectures to clean up their code and then add FAULT_FLAG_RETRY\nwhen that support is added.\n\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "c2860d43f5dfab599fc1308ab61b1d3e30801ceb", "tree": "16c350b23b657c2bb22123d86010cc4e725a2e39", "parents": [ "41184f6a5ef0d88529904d54f06f88b67fb76f4a" ], "author": { "name": "George G. Davis", "email": "gdavis@mvista.com", "time": "Thu Jun 04 17:16:04 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jun 19 16:35:34 2009 +0100" }, "message": "[ARM] 5540/1: 32-bit Thumb-2 {ld,st}{m,rd} alignment fault fixup support\n\nFrom: Min Zhang \u003cmzhang@mvista.com\u003e\n\nAdd alignment fault fixup support for 32-bit Thumb-2 LDM, LDRD, POP,\nPUSH, STM and STRD instructions. Alignment fault fixup support for\nthe remaining 32-bit Thumb-2 load/store instruction cases is not\nincluded since ARMv6 and later processors include hardware support\nfor loads and stores of unaligned words and halfwords.\n\nSigned-off-by: Min Zhang \u003cmzhang@mvista.com\u003e\nSigned-off-by: George G. Davis \u003cgdavis@mvista.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "187f81b3d8d315c35c73ac0d05b15a04a0ac3ce7", "tree": "e0b806f06470b57ffbdeaba550ab5eba2052427e", "parents": [ "1d89b30cc9be41af87881682ec82e2c107849dbe", "d78ff0a50aac6a1bfe445969dd963e6486e49f56" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Jun 18 23:09:52 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jun 18 23:09:52 2009 +0100" }, "message": "Merge branch \u0027for-rmk\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel\n" }, { "commit": "e6c3f4b89bf3698a6994d30de7a16ae395a81dab", "tree": "ea97f93b3b68e8be3c71d1a5bf2a40a17b7b8301", "parents": [ "303f2d7dc8eddc65de27d97eab0fc1c04ec4d2e1" ], "author": { "name": "Tomas \u0027Sleep_Walker\u0027 Cech", "email": "sleep_walker@suse.cz", "time": "Mon May 18 15:24:14 2009 +0200" }, "committer": { "name": "Eric Miao", "email": "eric.y.miao@gmail.com", "time": "Tue Jun 16 21:03:34 2009 +0800" }, "message": "[ARM] pxa/treo680: initial support\n\nSigned-off-by: Tomáš Čech \u003csleep_walker@suse.cz\u003e\nAcked-by: Marek Vasut \u003cmarek.vasut@gmail.com\u003e\nSigned-off-by: Eric Miao \u003ceric.miao@marvell.com\u003e\n" }, { "commit": "2cf4d4514d5b43c1f3b64bd0ec8b9853bde8f1dc", "tree": "e35a625496acc6ac852846d40b8851186b9d1ac4", "parents": [ "44b7532b8b464f606053562400719c9c21276037", "ce53895a5d24e0ee19fb92f56c17323fb4c9ab27" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Jun 14 13:42:43 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Jun 14 13:42:43 2009 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027for-linus\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm: (417 commits)\n MAINTAINERS: EB110ATX is not ebsa110\n MAINTAINERS: update Eric Miao\u0027s email address and status\n fb: add support of LCD display controller on pxa168/910 (base layer)\n [ARM] 5552/1: ep93xx get_uart_rate(): use EP93XX_SYSCON_PWRCNT and EP93XX_SYSCON_PWRCN\n [ARM] pxa/sharpsl_pm: zaurus needs generic pxa suspend/resume routines\n [ARM] 5544/1: Trust PrimeCell resource sizes\n [ARM] pxa/sharpsl_pm: cleanup of gpio-related code.\n [ARM] pxa/sharpsl_pm: drop set_irq_type calls\n [ARM] pxa/sharpsl_pm: merge pxa-specific code into generic one\n [ARM] pxa/sharpsl_pm: merge the two sharpsl_pm.c since it\u0027s now pxa specific\n [ARM] sa1100: remove unused collie_pm.c\n [ARM] pxa: fix the conflicting non-static declarations of global_gpios[]\n [ARM] 5550/1: Add default configure file for w90p910 platform\n [ARM] 5549/1: Add clock api for w90p910 platform.\n [ARM] 5548/1: Add gpio api for w90p910 platform\n [ARM] 5551/1: Add multi-function pin api for w90p910 platform.\n [ARM] Make ARM_VIC_NR depend on ARM_VIC\n [ARM] 5546/1: ARM PL022 SSP/SPI driver v3\n ARM: OMAP4: SMP: Update defconfig for OMAP4430\n ARM: OMAP4: SMP: Enable SMP support for OMAP4430\n ...\n" }, { "commit": "b7c11ec9f1c9f4272f032215ddb0b65d64b22ecc", "tree": "c65b81ef9ae5076d2137034accfa2610f45a13de", "parents": [ "06099961002a813324d057a91695af7c72939da6", "7666c17e2b0986a079da46122d8658544416c2cf" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Jun 14 11:01:44 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Jun 14 11:01:44 2009 +0100" }, "message": "Merge branch \u0027u300\u0027 into devel\n\nConflicts:\n\tarch/arm/Makefile\nUpdates:\n\tarch/arm/mach-u300/core.c\n\tarch/arm/mach-u300/timer.c\n" }, { "commit": "42578c82e0f1810a07ebe29cb05e874893243d8c", "tree": "e2a3811677d3594e891fc82c940438f6b6abc3e0", "parents": [ "2631182bf93919577730e6a6c4345308db590057", "85d6943af50537d3aec58b967ffbd3fec88453e9" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Jun 11 15:35:00 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jun 11 15:35:00 2009 +0100" }, "message": "Merge branch \u0027for-rmk\u0027 of git://linux-arm.org/linux-2.6 into devel\n\nConflicts:\n\tarch/arm/Kconfig\n\tarch/arm/kernel/smp.c\n\tarch/arm/mach-realview/Makefile\n\tarch/arm/mach-realview/platsmp.c\n" }, { "commit": "1946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7", "tree": "d6cb6a56623d39021e30bb6d1892bfda7edb123a", "parents": [ "eb5f4ca9536ba297c98721ecbbdf41ec5b987bd5" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Jun 01 12:50:33 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jun 02 22:36:20 2009 +0100" }, "message": "[ARM] ARMv7 errata: only apply fixes when running on applicable CPU\n\nCurrently, whenever an erratum workaround is enabled, it will be\napplied whether or not the erratum is relevent for the CPU. This\npatch changes this - we check the variant and revision fields in the\nmain ID register to determine which errata to apply.\n\nWe also avoid re-applying erratum 460075 if it has already been applied.\nApplying this fix in non-secure mode results in the kernel failing to\nboot (or even do anything.)\n\nThis fixes booting on some ARMv7 based platforms which otherwise\nsilently fail.\n\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a22f277bba321474a01691ae66d5952926459f44", "tree": "a3d60526be57064fa3e31159f2c196c6d260c598", "parents": [ "4dd9e742df98f8f600b4302d3adbb087a68237f7" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun May 31 15:02:58 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun May 31 15:12:25 2009 +0100" }, "message": "[ARM] Kconfig: remove \u0027default n\u0027\n\nKconfig entries default to n, so there\u0027s no need for this to be\nexplicitly specified.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "26584853a44c58f3d6ac7360d697a2ddcd1a3efa", "tree": "a47156d781c6207d316746a056a81ca82b90d452", "parents": [ "ee8c9571191e588ede9a220ded807e33c4897d91" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Sat May 30 14:00:18 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Sat May 30 14:00:18 2009 +0100" }, "message": "Add core support for ARMv6/v7 big-endian\n\nStarting with ARMv6, the CPUs support the BE-8 variant of big-endian\n(byte-invariant). This patch adds the core support:\n\n- setting of the BE-8 mode via the CPSR.E register for both kernel and\n user threads\n- big-endian page table walking\n- REV used to rotate instructions read from memory during fault\n processing as they are still little-endian format\n- Kconfig and Makefile support for BE-8. The --be8 option must be passed\n to the final linking stage to convert the instructions to\n little-endian\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "23d1c515d8fc6d74bea442a4b687c3b5b8627ec4", "tree": "d257dedacef94e47006d7daca00e698296e9fa38", "parents": [ "213fb2a8ee81ec106b9b370a07ccad575e9d3748" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Sat May 30 14:00:16 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Sat May 30 14:00:16 2009 +0100" }, "message": "ARMv7: Document the PRRR and NMRR registers setting\n\nThis patch adds a comment to the proc-v7.S file for the setting of the\nPRRR and NMRR registers. It also sets the PRRR[13:12] bits to 0\n(corresponding to the reserved TEX[0]CB encoding 110) to be consistent\nwith the documentation.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "213fb2a8ee81ec106b9b370a07ccad575e9d3748", "tree": "ae439bbb35cfa5c96b8d658ea97359c761117e09", "parents": [ "d71e1352e240dea32d481ad8d662e8de4406ac7e" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Sat May 30 14:00:16 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Sat May 30 14:00:16 2009 +0100" }, "message": "ARMv7: Enable the SWP instruction\n\nThe SWP instruction has been deprecated starting with the ARMv6\narchitecture. On ARMv7 processors with the multiprocessor extensions\n(like Cortex-A9), this instruction is disabled by default but it can be\nenabled by setting bit 10 in the System Control register. Note that\nsetting this bit is safe even if the ARMv7 processor has the SWP\ninstruction enabled by default.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "ba3c02636a0743a62cb50b920d36e1c046ab88cf", "tree": "4b715a804a9e2121fe87ab6b694dbc90679c7ca2", "parents": [ "faa7bc51c11d5bbe440ac04710fd7a3208782000" ], "author": { "name": "Tony Thompson", "email": "Anthony.Thompson@arm.com", "time": "Sat May 30 14:00:15 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Sat May 30 14:00:15 2009 +0100" }, "message": "ARMv7: Mark the PTWs inner WBWA on SMP and WB on UP\n\nThere are additional bits to set for the ARMv7 SMP extensions in the\nTTBR registers. The IRGN bits order is counter-intuitive but it allows\nsoftware built for the ARMv7 base architecture to run on an\nimplementation with the MP extensions.\n\nSigned-off-by: Tony Thompson \u003cAnthony.Thompson@arm.com\u003e\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "faa7bc51c11d5bbe440ac04710fd7a3208782000", "tree": "8aaa4e8e2fbb14b421988762fa90a3dbe6fa76e7", "parents": [ "da055eb52ec067d51dc08c7e86baf92dd5c01599" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Sat May 30 14:00:14 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Sat May 30 14:00:14 2009 +0100" }, "message": "Check whether the TLB operations need broadcasting on SMP systems\n\nARMv7 SMP hardware can handle the TLB maintenance operations\nbroadcasting in hardware so that the software can avoid the costly IPIs.\nThis patch adds the necessary checks (the MMFR3 CPUID register) to avoid\nthe broadcasting if already supported by the hardware.\n\n(this patch is based on the work done by Tony Thompson @ ARM)\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "1b504bbe7a4a6c251cdc9dcba1fab72234827945", "tree": "f747a26e44efb9420a2ac9a0f2c95f7004f3b826", "parents": [ "412b400278ed0f71712387d0b9b31cbdd8a18efc" ], "author": { "name": "Colin Tuckley", "email": "colin.tuckley@arm.com", "time": "Sat May 30 13:56:12 2009 +0100" }, "committer": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Sat May 30 13:56:12 2009 +0100" }, "message": "RealView: Add support for the RealView/PBX platform\n\nThis is a RealView platform supporting core tiles with ARM11MPCore,\nCortex-A8 or Cortex-A9 (multicore) processors. It has support for MMC,\nCompactFlash, PCI-E.\n\nSigned-off-by: Colin Tuckley \u003ccolin.tuckley@arm.com\u003e\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "56a459314a982bae75b9bce64bcca853d378ca7e", "tree": "07d9121fb08229ebe2ac2f4420cec70434c7bbba", "parents": [ "fc05505b77f7900a1bb74fb3f3a4343dee4265a4", "5c651ffaee6f07aa1f5e6d0763845a2ee606b6bd" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon May 25 10:15:59 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon May 25 10:20:21 2009 +0100" }, "message": "Merge branch \u0027iommu\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git into devel\n" }, { "commit": "69d3a84a646d6ad6cd693a7a3d5b9af414113d2c", "tree": "3fe2ec29cc83ff07ae0d07df6b51c52a59a3944e", "parents": [ "066aa9c1e3d0af52619fe26f05810990ff381d8c" ], "author": { "name": "Hiroshi DOYU", "email": "Hiroshi.DOYU@nokia.com", "time": "Wed Jan 28 21:32:08 2009 +0200" }, "committer": { "name": "Hiroshi DOYU", "email": "Hiroshi.DOYU@nokia.com", "time": "Tue May 19 08:23:49 2009 +0300" }, "message": "omap iommu: simple virtual address space management\n\nThis patch provides a device drivers, which has a omap iommu, with\naddress mapping APIs between device virtual address(iommu), physical\naddress and MPU virtual address.\n\nThere are 4 possible patterns for iommu virtual address(iova/da) mapping.\n\n |iova/\t\t\t mapping\t\tiommu_\t\tpage\n | da\tpa\tva\t(d)-(p)-(v)\t\tfunction\ttype\n ---------------------------------------------------------------------------\n 1 | c\t\tc\tc\t 1 - 1 - 1\t _kmap() / _kunmap()\ts\n 2 | c\t\tc,a\tc\t 1 - 1 - 1\t_kmalloc()/ _kfree()\ts\n 3 | c\t\td\tc\t 1 - n - 1\t _vmap() / _vunmap()\ts\n 4 | c\t\td,a\tc\t 1 - n - 1\t_vmalloc()/ _vfree()\tn*\n\n \u0027iova\u0027:\tdevice iommu virtual address\n \u0027da\u0027:\talias of \u0027iova\u0027\n \u0027pa\u0027:\tphysical address\n \u0027va\u0027:\tmpu virtual address\n\n \u0027c\u0027:\tcontiguous memory area\n \u0027d\u0027:\tdicontiguous memory area\n \u0027a\u0027:\tanonymous memory allocation\n \u0027()\u0027:\toptional feature\n\n \u0027n\u0027:\ta normal page(4KB) size is used.\n \u0027s\u0027:\tmultiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used.\n\n \u0027*\u0027:\tnot yet, but feasible.\n\nSigned-off-by: Hiroshi DOYU \u003cHiroshi.DOYU@nokia.com\u003e\n" }, { "commit": "2142babac999a5ba169348892a8e3ac222bec7a4", "tree": "eb862396a9864b34e2335b7cc0c6114c56f9ec1a", "parents": [ "bb402c4fb5bba4edf5b8c72b3db8760e60df4876", "0516e4643cd22fc9f535aef02ad1de66c382c93b" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat May 02 16:40:20 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat May 02 16:40:20 2009 -0700" }, "message": "Merge master.kernel.org:/home/rmk/linux-2.6-arm\n\n* master.kernel.org:/home/rmk/linux-2.6-arm: (45 commits)\n [ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data\n [ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created\n [ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch\n [ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail\n davinci: DM644x: NAND: update partitioning\n davinci: update DM644x support in preparation for more SoCs\n davinci: DM644x: rename board file\n davinci: update pin-multiplexing support\n davinci: serial: generalize for more SoCs\n davinci: DM355 IRQ Definitions\n davinci: DM646x: add interrupt number and priorities\n davinci: PSC: Clear bits in MDCTL reg before setting new bits\n davinci: gpio bugfixes\n davinci: add EDMA driver\n davinci: timers: use clk_get_rate()\n [ARM] pxa/littleton: add missing da9034 touchscreen support\n [ARM] pxa/zylonite: configure GPIO18/19 correctly, used by 2 GPIO expanders\n [ARM] pxa/zylonite: fix the issue of unused SDATA_IN_1 pin get AC97 not working\n [ARM] pxa: make ads7846 on corgi and spitz to sync on HSYNC\n [ARM] pxa: remove unused CPU_FREQ_PXA Kconfig symbol\n ...\n" }, { "commit": "0516e4643cd22fc9f535aef02ad1de66c382c93b", "tree": "8b82945aa5f1ef825656aed2580cacafcd829ac3", "parents": [ "855c551f5b8cc3815d58e1056c1f1e7c461e2d24" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Apr 30 17:06:20 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Apr 30 20:13:00 2009 +0100" }, "message": "[ARM] 5489/1: ARM errata: Data written to the L2 cache can be overwritten with stale data\n\nThis patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It\nconfigures the L2 cache auxiliary control register so that the Write\nAllocate mode for the L2 cache is disabled.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "855c551f5b8cc3815d58e1056c1f1e7c461e2d24", "tree": "c2a84666b3a86c3e5cb5272ed42b802f9411ec33", "parents": [ "7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Apr 30 17:06:15 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Apr 30 20:12:59 2009 +0100" }, "message": "[ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created\n\nThis patch adds a workaround for the 458693 Cortex-A8 (r2p0)\nerratum. It sets the corresponding bits in the auxiliary control\nregister so that the PLD instruction becomes a NOP.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47", "tree": "1f092413fbe0c91350e7861638dec7bb475c8435", "parents": [ "9cba3ccc8fe77b67aff2db8f5827d7cb752ce11f" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Apr 30 17:06:09 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Apr 30 20:12:50 2009 +0100" }, "message": "[ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch\n\nThis patch adds the workaround for the 430973 Cortex-A8 (r1p0..r1p2)\nerratum. The BTAC/BTB is now flushed at every context switch.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9cba3ccc8fe77b67aff2db8f5827d7cb752ce11f", "tree": "cb73cbaa3c197180b7f9d829561121197a8c69db", "parents": [ "10993374f84cc1c4100aea9eca7fa154518ffc5e" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Apr 30 17:06:03 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Apr 30 20:12:47 2009 +0100" }, "message": "[ARM] 5488/1: ARM errata: Invalidation of the Instruction Cache operation can fail\n\nThis patch implements the recommended workaround for erratum 411920\n(ARM1136, ARM1156, ARM1176).\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d98aac7592114241f378bc8d5b3e424cced7ded2", "tree": "2d052df037411e94478d5ee4ff43402a45fd8fe4", "parents": [ "bb3cee2b35d2b9edab71997bd06040ff37483e08" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Mon Apr 27 10:21:46 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Apr 28 22:44:29 2009 +0100" }, "message": "[ARM] 5480/1: U300-v5 integrate into the ARM architecture\n\nThis hooks the U300 support into Kbuild and makes a small hook\nin mmu.c for supporting an odd memory alignment with shared memory\non these systems.\n\nThis is rebased to RMK:s GIT HEAD. This patch tries to add the\nKconfig option in alphabetic order by option text and the Makefile\nentry after config symbol.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "991da17ec0b9f396154c8120ffd10e5d7d7aa361", "tree": "e53b6ce7d3482afb516e806bfc69966a6af0b7c0", "parents": [ "df1f6d200c1e20788184251c49f349b38d90889c" ], "author": { "name": "Tim Abbott", "email": "tabbott@MIT.EDU", "time": "Mon Apr 27 14:02:22 2009 -0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Apr 27 19:51:58 2009 -0700" }, "message": "arm: Use __INIT macro instead of .text.init.\n\narm is placing some code in the .text.init section, but it does not\nreference that section in its linker scripts.\n\nThis change moves this code from the .text.init section to the\n.init.text section, which is presumably where it belongs.\n\nSigned-off-by: Tim Abbott \u003ctabbott@mit.edu\u003e\nAcked-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nAcked-by: Sam Ravnborg \u003csam@ravnborg.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "81854f82c5c1a203b2f5c94f6aa2ed8b8e19f025", "tree": "2eac472ee815f31cfeca6ab396c6cd6347dc2871", "parents": [ "8c8aa5fa3060abc17e8a07d15f575485f6a0c0b8" ], "author": { "name": "Marek Vasut", "email": "marek.vasut@gmail.com", "time": "Sat Mar 28 12:37:42 2009 +0100" }, "committer": { "name": "Eric Miao", "email": "eric.miao@marvell.com", "time": "Sat Apr 04 10:26:34 2009 +0800" }, "message": "[ARM] pxa: Add support for suspend on PalmTX, T5 and LD\n\nSigned-off-by: Marek Vasut \u003cmarek.vasut@gmail.com\u003e\nSigned-off-by: Eric Miao \u003ceric.miao@marvell.com\u003e\n" }, { "commit": "fe68e68f6a379d317a87ae24de050a65b11ea1fb", "tree": "7e6099b993d9385eae4e7a892271c3fd38a7c207", "parents": [ "01a24d2b9309676ec2e7069cd19f5b1c4a1505e0" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Wed Apr 01 13:53:48 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Apr 01 22:15:57 2009 +0100" }, "message": "[ARM] 5439/1: Do not clear bit 10 of DFSR during abort handling on ARMv6\n\nBecause of an ARM1136 erratum (326103), the current v6_early_abort\nfunction needs to set the correct FSR[11] value which determines whether\nthe data abort was caused by a read or write. For legacy reasons (bit 10\nnot handled by software), bit 10 was also cleared masking out imprecise\naborts on ARMv6 CPUs. This patch removes the clearing of bit 10 of FSR.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f000328ac10f23f4841b83ddc60eceb3ba0ac176", "tree": "bcd9597eb25e0285f3d9a61c6203e8ec92d8cdfb", "parents": [ "d75de08727018659cd7e060cf0018eaf53e49aaf" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Fri Mar 27 14:22:26 2009 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sat Mar 28 22:39:30 2009 -0400" }, "message": "[ARM] Kirkwood: small L2 code cleanup\n\nStrictly speaking, a MCR instruction does not produce any output.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "d75de08727018659cd7e060cf0018eaf53e49aaf", "tree": "355e43af6605aeff23102af26615c9a679306407", "parents": [ "c31f403de62415c738ddc9e673cf8e722c82f861" ], "author": { "name": "Maxime Bizon", "email": "mbizon@freebox.fr", "time": "Fri Mar 27 18:42:19 2009 +0100" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sat Mar 28 22:39:30 2009 -0400" }, "message": "[ARM] Kirkwood: invalidate L2 cache before enabling it\n\nI get random oopses on my Kirkwood board at startup when L2 cache is\nenabled. FYI I\u0027m using Marvell uboot version 3.4.16\n\nEach boot produces the same oops, but anything that changes the kernel\nsize (even only changing initramfs) makes the oops different.\n\nI noticed that nothing invalidates the L2 cache before enabling it,\ndoing so fixes my problem.\n\nSigned-off-by: Maxime Bizon \u003cmbizon@freebox.fr\u003e\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "9759d22c8348343b0da4e25d6150c41712686c14", "tree": "338b185f11d705258888a8f2318a3a3b7ea0968d", "parents": [ "ed40d0c472b136682b2fcba05f89762859c7374f", "f0bba9f934517533acbda7329be93f55d5a01c03" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sat Mar 28 20:30:18 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Mar 28 20:30:18 2009 +0000" }, "message": "Merge branch \u0027master\u0027 into devel\n\nConflicts:\n\tarch/arm/include/asm/elf.h\n\tarch/arm/kernel/module.c\n" }, { "commit": "f0bba9f934517533acbda7329be93f55d5a01c03", "tree": "8b70d9651e235d44a175154146cf50597665549d", "parents": [ "803c78e4da28d7d7cb0642caf643b9289ae7838a" ], "author": { "name": "Mikael Pettersson", "email": "mikpe@it.uu.se", "time": "Sat Mar 28 19:18:05 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Mar 28 20:21:20 2009 +0000" }, "message": "[ARM] 5435/1: fix compile warning in sanity_check_meminfo()\n\nCompiling recent 2.6.29-rc kernels for ARM gives me the following warning:\n\narch/arm/mm/mmu.c: In function \u0027sanity_check_meminfo\u0027:\narch/arm/mm/mmu.c:697: warning: comparison between pointer and integer\n\nThis is because commit 3fd9825c42c784a59b3b90bdf073f49d4bb42a8d\n\"[ARM] 5402/1: fix a case of wrap-around in sanity_check_meminfo()\"\nin 2.6.29-rc5-git4 added a comparison of a pointer with PAGE_OFFSET,\nwhich is an integer.\n\nFixed by casting PAGE_OFFSET to void *.\n\nSigned-off-by: Mikael Pettersson \u003cmikpe@it.uu.se\u003e\nAcked-by: Nicolas Pitre \u003cnico@cam.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "542f869f1826f092606efd0c4c771f070d1314f5", "tree": "9c9d265ab0c87ea7862ccb70933f33d3d7011334", "parents": [ "e8b374bb6c888a70530d800c9e2fcd153e2c325d", "839e642f3dda44a35c6a91780bff41d84c288022" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Mar 26 23:10:11 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 26 23:10:11 2009 +0000" }, "message": "Merge branch \u0027for-rmk\u0027 of git://gitorious.org/linux-gemini/mainline into devel\n\nConflicts:\n\tarch/arm/mm/Kconfig\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "28853ac8fe5221de74a14f1182d7b2b383dfd85c", "tree": "dcfd9b20028e5a3a9504e26d2c9060f4746fc83a", "parents": [ "bba7d0b9ba0f04d25145de8170a17a3a07bbfdde" ], "author": { "name": "Paulius Zaleckas", "email": "paulius.zaleckas@teltonika.lt", "time": "Wed Mar 25 13:10:01 2009 +0200" }, "committer": { "name": "Paulius Zaleckas", "email": "paulius.zaleckas@teltonika.lt", "time": "Wed Mar 25 13:10:01 2009 +0200" }, "message": "ARM: Add support for FA526 v2\n\nAdds support for Faraday FA526 core. This core is used at least by:\nCortina Systems Gemini and Centroid family\nCavium Networks ECONA family\nGrain Media GM8120\nPixelplus ImageARM\nProlific PL-1029\nFaraday IP evaluation boards\n\nv2:\n- move TLB_BTB to separate patch\n- update copyrights\n\nSigned-off-by: Paulius Zaleckas \u003cpaulius.zaleckas@teltonika.lt\u003e\n" }, { "commit": "fbf2b1f9cfdb4e4b5d042839142ed19ff5d46679", "tree": "3a17c02aa0cf9bdbed9aa479739974aa2416ecac", "parents": [ "9a38e989b8ce04923f919fc2a8a24eb07fb484e2", "053a96ca11a9785a7e63fc89eed4514a6446ec58" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Tue Mar 24 22:47:45 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Mar 24 22:47:45 2009 +0000" }, "message": "Merge branch \u0027highmem\u0027 into devel\n" }, { "commit": "9a38e989b8ce04923f919fc2a8a24eb07fb484e2", "tree": "6b99638dc32b99420ada46ca8d1373ad7aa5a208", "parents": [ "7d83f8fca517b123cf0136503a9e50974f65ec49", "5fa82eb8ff06cd3ac4d64c6875922ae1dfa003c5" ], "author": { "name": "root", "email": "root@dyn-67.arm.linux.org.uk", "time": "Tue Mar 24 22:04:25 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Mar 24 22:04:25 2009 +0000" }, "message": "Merge branch \u0027devel\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel\n" }, { "commit": "49cbe78637eb0503f45fc9b556ec08918a616534", "tree": "96de29959c5ef512d8f1e0bea7eae2245b7cc3f9", "parents": [ "f8dec04d33b94a4cfa9358fd9666c01480bb164d" ], "author": { "name": "Eric Miao", "email": "eric.miao@marvell.com", "time": "Tue Jan 20 14:15:18 2009 +0800" }, "committer": { "name": "Eric Miao", "email": "eric.miao@marvell.com", "time": "Mon Mar 23 10:11:34 2009 +0800" }, "message": "[ARM] pxa: add base support for Marvell\u0027s PXA168 processor line\n\n\"\"\"The Marvell® PXA168 processor is the first in a family of application\nprocessors targeted at mass market opportunities in computing and consumer\ndevices. It balances high computing and multimedia performance with low\npower consumption to support extended battery life, and includes a wealth\nof integrated peripherals to reduce overall BOM cost .... \"\"\"\n\nSee http://www.marvell.com/featured/pxa168.jsp for more information.\n\n 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core,\n there are many enhancements like instructions for flushing the\n whole D-cache, and so on\n\n 2. Clock reuses Russell\u0027s common clkdev, and added the basic support\n for UART1/2.\n\n 3. Devices are a bit different from the \u0027mach-pxa\u0027 way, the platform\n devices are now dynamically allocated only when necessary (i.e.\n when pxa_register_device() is called). Description for each device\n are stored in an array of \u0027struct pxa_device_desc\u0027. Now that:\n\n a. this array of device description is marked with __initdata and\n can be freed up system is fully up\n\n b. which means board code has to add all needed devices early in\n his initializing function\n\n c. platform specific data can now be marked as __initdata since\n they are allocated and copied by platform_device_add_data()\n\n 4. only the basic UART1/2/3 are added, more devices will come later.\n\nSigned-off-by: Jason Chagas \u003cchagas@marvell.com\u003e\nSigned-off-by: Eric Miao \u003ceric.miao@marvell.com\u003e\n" }, { "commit": "7d83f8fca517b123cf0136503a9e50974f65ec49", "tree": "92ed1faaf112e98e29a00efc99e1a4e6c79e6a8e", "parents": [ "be093beb608edf821b45fe00a8a080fb5c6ed4af", "569106c70e49ad67c69fa7d43a2a5218e63a4619" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Mar 19 23:10:40 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 19 23:10:40 2009 +0000" }, "message": "Merge branch \u0027master\u0027 of git://git.marvell.com/orion into devel\n\nConflicts:\n\n\tarch/arm/mach-mx1/devices.c\n" }, { "commit": "3f973e22160257c5bda85815be5b1540d391a671", "tree": "c453cc200f3cd71bd28195e9959034aa673a7693", "parents": [ "3902a15e784e9b1efa8e6ad246489c609e0ef880" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Tue Nov 04 00:48:42 2008 -0500" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:22 2009 -0400" }, "message": "[ARM] ignore high memory with VIPT aliasing caches\n\nVIPT aliasing caches have issues of their own which are not yet handled.\nUsage of discard_old_kernel_data() in copypage-v6.c is not highmem ready,\nkmap/fixmap stuff doesn\u0027t take account of cache colouring, etc.\nIf/when those issues are handled then this could be reverted.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "3902a15e784e9b1efa8e6ad246489c609e0ef880", "tree": "8b674544cc2b3381fa9481d2e1e60eb99ef62a71", "parents": [ "1bb772679ffb0ba1ff1d40d8c6b855ab029f177d" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Thu Sep 18 22:55:47 2008 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:21 2009 -0400" }, "message": "[ARM] xsc3: add highmem support to L2 cache handling code\n\nOn xsc3, L2 cache ops are possible only on virtual addresses. The code\nis rearranged so to have a linear progression requiring the least amount\nof pte setups in the highmem case. To protect the virtual mapping so\ncreated, interrupts must be disabled currently up to a page worth of\naddress range.\n\nThe interrupt disabling is done in a way to minimize the overhead within\nthe inner loop. The alternative would consist in separate code for\nthe highmem and non highmem compilation which is less preferable.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "1bb772679ffb0ba1ff1d40d8c6b855ab029f177d", "tree": "c76eb84a6f8df764f0c8e13d84964968c3ab10b7", "parents": [ "58edb515724f9e63e569536d01ac8d8f8ddb367a" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Fri Sep 12 16:11:51 2008 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:21 2009 -0400" }, "message": "[ARM] Feroceon: add highmem support to L2 cache handling code\n\nThe choice is between looping over the physical range and performing\nsingle cache line operations, or to map highmem pages somewhere, as\ncache range ops are possible only on virtual addresses.\n\nBecause L2 range ops are much faster, we go with the later by factoring\nthe physical-to-virtual address conversion and use a fixmap entry for it\nin the HIGHMEM case.\n\nPossible future optimizations to avoid the pte setup cost:\n\n - do the pte setup for highmem pages only\n\n - determine a threshold for doing a line-by-line processing on physical\n addresses when the range is small\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "43377453af83b8ff8c1c731da1508bd6b84ebfea", "tree": "42a55f4d1856ced05d9e21f8619005e8b76694c3", "parents": [ "3297e760776af18a26bf30046cbaaae2e730c5c2" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Thu Mar 12 22:52:09 2009 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:21 2009 -0400" }, "message": "[ARM] introduce dma_cache_maint_page()\n\nThis is a helper to be used by the DMA mapping API to handle cache\nmaintenance for memory identified by a page structure instead of a\nvirtual address. Those pages may or may not be highmem pages, and\nwhen they\u0027re highmem pages, they may or may not be virtually mapped.\nWhen they\u0027re not mapped then there is no L1 cache to worry about. But\neven in that case the L2 cache must be processed since unmapped highmem\npages can still be L2 cached.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "3835f6cb645bdb9a58aa6e062fe1d5777f1a9748", "tree": "de3429794bb06cab351a7909da7c8c33bfa38567", "parents": [ "d73cd42893f4cdc06e6829fea2347bb92cb789d1" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Wed Sep 17 15:21:55 2008 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:21 2009 -0400" }, "message": "[ARM] mem_init(): make highmem pages available for use\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "d73cd42893f4cdc06e6829fea2347bb92cb789d1", "tree": "fddff067f2b09aa13741bc9d05956429616e986a", "parents": [ "5f0fbf9ecaf354fa4bbf266fffdea2ea3d14a0ed" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Mon Sep 15 16:44:55 2008 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:20 2009 -0400" }, "message": "[ARM] kmap support\n\nThe kmap virtual area borrows a 2MB range at the top of the 16MB area\nbelow PAGE_OFFSET currently reserved for kernel modules and/or the\nXIP kernel. This 2MB corresponds to the range covered by 2 consecutive\nsecond-level page tables, or a single pmd entry as seen by the Linux\npage table abstraction. Because XIP kernels are unlikely to be seen\non systems needing highmem support, there shouldn\u0027t be any shortage of\nVM space for modules (14 MB for modules is still way more than twice the\ntypical usage).\n\nBecause the virtual mapping of highmem pages can go away at any moment\nafter kunmap() is called on them, we need to bypass the delayed cache\nflushing provided by flush_dcache_page() in that case.\n\nThe atomic kmap versions are based on fixmaps, and\n__cpuc_flush_dcache_page() is used directly in that case.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "5f0fbf9ecaf354fa4bbf266fffdea2ea3d14a0ed", "tree": "9f0c59760b2bec510519118ddb17d4b15db473f5", "parents": [ "1522ac3ec95ff0230e7aa516f86b674fdf72866c" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Tue Sep 16 13:05:53 2008 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Sun Mar 15 21:01:20 2009 -0400" }, "message": "[ARM] fixmap support\n\nThis is the minimum fixmap interface expected to be implemented by\narchitectures supporting highmem.\n\nWe have a second level page table already allocated and covering\n0xfff00000-0xffffffff because the exception vector page is located\nat 0xffff0000, and various cache tricks already use some entries above\n0xffff0000. Therefore the PTEs covering 0xfff00000-0xfffeffff are free\nto be used.\n\nHowever the XScale cache flushing code already uses virtual addresses\nbetween 0xfffe0000 and 0xfffeffff.\n\nSo this reserves the 0xfff00000-0xfffdffff range for fixmap stuff.\n\nThe Documentation/arm/memory.txt information is updated accordingly,\nincluding the information about the actual top of DMA memory mapping\nregion which didn\u0027t match the code.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\n" }, { "commit": "97fb44eb6bc01f4ffed4300e475aa15e44877375", "tree": "481ed6efd0babe7185cae04f2fd295426b36411d", "parents": [ "e4707dd3e9d0cb57597b6568a5e51fea5d6fca41", "148854c65ea8046b045672fd49f4333aefaa3ab5" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Fri Mar 13 21:44:51 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Mar 13 21:44:51 2009 +0000" }, "message": "Merge branch \u0027for-rmk\u0027 of git://git.pengutronix.de/git/imx/linux-2.6 into devel\n\nConflicts:\n\n\tarch/arm/mach-at91/gpio.c\n" }, { "commit": "cb88214d726b337d49c1f65cbc5e5ac85837b11b", "tree": "286cb0b63eeb16c4c3f3f728813cabc2298dc730", "parents": [ "9536ff33619e13fcc4bd16354faea97dba244f73" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Sun Feb 08 02:00:50 2009 +0100" }, "committer": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Fri Mar 13 10:34:29 2009 +0100" }, "message": "[ARM] MX31/MX35: Add l2x0 cache support\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\n" }, { "commit": "1522ac3ec95ff0230e7aa516f86b674fdf72866c", "tree": "77444039536e70b3e9fbb38f686104cb5054aba3", "parents": [ "305b07680f6c6a7e59f996c5bd85f009caff5bb1" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Thu Mar 12 17:03:48 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 12 23:09:09 2009 +0000" }, "message": "[ARM] Fix virtual to physical translation macro corner cases\n\nThe current use of these macros works well when the conversion is\nentirely linear. In this case, we can be assured that the following\nholds true:\n\n\t__va(p + s) - s \u003d __va(p)\n\nHowever, this is not always the case, especially when there is a\nnon-linear conversion (eg, when there is a 3.5GB hole in memory.)\nIn this case, if \u0027s\u0027 is the size of the region (eg, PAGE_SIZE) and\n\u0027p\u0027 is the final page, the above is most definitely not true.\n\nSo, we must ensure that __va() and __pa() are only used with valid\nkernel direct mapped RAM addresses. This patch tweaks the code\nto achieve this.\n\nTested-by: Charles Moschel \u003cfred99@carolina.rr.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "446c92b2901bedb3725d29b4e73def8aba623ffc", "tree": "5669761e042f8321214ca5a975fec536fa5f0efd", "parents": [ "9311c593f24f28de2a339da602644f0f7ae0fc60" ], "author": { "name": "Uwe Kleine-König", "email": "u.kleine-koenig@pengutronix.de", "time": "Thu Mar 12 18:03:16 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 12 21:33:03 2009 +0000" }, "message": "[ARM] 5421/1: ftrace: fix crash due to tracing of __naked functions\n\nThis is a fix for the following crash observed in 2.6.29-rc3:\nhttp://lkml.org/lkml/2009/1/29/150\n\nOn ARM it doesn\u0027t make sense to trace a naked function because then\nmcount is called without stack and frame pointer being set up and there\nis no chance to restore the lr register to the value before mcount was\ncalled.\n\nReported-by: Matthias Kaehlcke \u003cmatthias@kaehlcke.net\u003e\nTested-by: Matthias Kaehlcke \u003cmatthias@kaehlcke.net\u003e\n\nCc: Abhishek Sagar \u003csagar.abhishek@gmail.com\u003e\nCc: Steven Rostedt \u003crostedt@home.goodmis.org\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Uwe Kleine-König \u003cu.kleine-koenig@pengutronix.de\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "e4707dd3e9d0cb57597b6568a5e51fea5d6fca41", "tree": "c76a6cb54e4f90a8deebf380bf8fe8a5f6eb2750", "parents": [ "6dc4a47a0cf423879b505af0e29997fca4088630" ], "author": { "name": "Paul Walmsley", "email": "paul@pwsan.com", "time": "Thu Mar 12 20:11:43 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 12 19:25:02 2009 +0000" }, "message": "[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type\n\nThis patch adds a Non-cacheable Normal ARM executable memory type,\nMT_MEMORY_NONCACHED.\n\nOn OMAP3, this is used for rapid dynamic voltage/frequency scaling in\nthe VDD2 voltage domain. OMAP3\u0027s SDRAM controller (SDRC) is in the\nVDD2 voltage domain, and its clock frequency must change along with\nvoltage. The SDRC clock change code cannot run from SDRAM itself,\nsince SDRAM accesses are paused during the clock change. So the\ncurrent implementation of the DVFS code executes from OMAP on-chip\nSRAM, aka \"OCM RAM.\"\n\nIf the OCM RAM pages are marked as Cacheable, the ARM cache controller\nwill attempt to flush dirty cache lines to the SDRC, so it can fill\nthose lines with OCM RAM instruction code. The problem is that the\nSDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU\nsubsystem to hang.\n\nTI\u0027s original solution to this problem was to mark the OCM RAM\nsections as Strongly Ordered memory, thus preventing caching. This is\noverkill: since the memory is marked as non-bufferable, OCM RAM writes\nbecome needlessly slow. The idea of \"Strongly Ordered SRAM\" is also\nconceptually disturbing. Previous LAKML list discussion is here:\n\nhttp://www.spinics.net/lists/arm-kernel/msg54312.html\n\nThis memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future\npatch.\n\nCc: Richard Woodruff \u003cr-woodruff2@ti.com\u003e\nSigned-off-by: Paul Walmsley \u003cpaul@pwsan.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "25ef4a67e78e1322d55f0a38783537ed89addc02", "tree": "030221d967bba0ab8d5274159063f839e6f503cc", "parents": [ "c8532db7f2661b63f658b9a08cf4053a3e6abb78" ], "author": { "name": "Seth Forshee", "email": "seth.forshee@gmail.com", "time": "Mon Mar 02 22:39:36 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Mar 03 12:11:25 2009 +0000" }, "message": "[ARM] 5416/1: Use unused address in v6_early_abort\n\nThe target of the strex instruction to clear the exlusive monitor\nis currently the top of the stack. If the store succeeeds this\ncorrupts r0 in pt_regs. Use the next stack location instead of\nthe current one to prevent any chance of corrupting an in-use\naddress.\n\nSigned-off-by: Seth Forshee \u003cseth.forshee@gmail.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "3fd9825c42c784a59b3b90bdf073f49d4bb42a8d", "tree": "ae0910729307786e5393b66373239c4dee48303f", "parents": [ "fd4b9b3650076ffadbdd6e360eb198f5d61747c0" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Wed Feb 18 22:29:22 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 19 09:49:45 2009 +0000" }, "message": "[ARM] 5402/1: fix a case of wrap-around in sanity_check_meminfo()\n\nIn the non highmem case, if two memory banks of 1GB each are provided,\nthe second bank would evade suppression since its virtual base would\nbe 0. Fix this by disallowing any memory bank which virtual base\naddress is found to be lower than PAGE_OFFSET.\n\nReported-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "08e445bd6a98fa09befe0cf6d67705324f913fc6", "tree": "34308727da79a6a36fc52ebe5b5d960b2bafaf6d", "parents": [ "ecbab71c521819716e204659dfe72fc39d00630a" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Fri Jan 16 23:02:54 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jan 28 16:55:00 2009 +0000" }, "message": "[ARM] 5366/1: fix shared memory coherency with VIVT L1 + L2 caches\n\nWhen there are multiple L1-aliasing userland mappings of the same physical\npage, we currently remap each of them uncached, to prevent VIVT cache\naliasing issues. (E.g. writes to one of the mappings not being immediately\nvisible via another mapping.) However, when we do this remapping, there\ncould still be stale data in the L2 cache, and an uncached mapping might\nbypass L2 and go straight to RAM. This would cause reads from such\nmappings to see old data (until the dirty L2 line is eventually evicted.)\n\nThis issue is solved by forcing a L2 cache flush whenever the shared page\nis made L1 uncacheable.\n\nIdeally, we would make L1 uncacheable and L2 cacheable as L2 is PIPT. But\nFeroceon does not support that combination, and the TEX\u003d5 C\u003d0 B\u003d0 encoding\nfor XSc3 doesn\u0027t appear to work in practice.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "24f11ec001920f1cfaeeed8e8b55725d900bbb56", "tree": "bb7a1007374c9ce9f60962c22f8bccb31bd6cb44", "parents": [ "fb22d72782b023cda5e9876d3381f30932a64f91" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Jan 25 17:36:34 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Jan 25 17:36:34 2009 +0000" }, "message": "[ARM] fix section-based ioremap\n\nTomi Valkeinen reports:\n Running with latest linux-omap kernel on OMAP3 SDP board, I have\n problem with iounmap(). It looks like iounmap() does not properly\n free large areas. Below is a test which fails for me in 6-7 loops.\n\n\tfor (i \u003d 0; i \u003c 200; ++i) {\n\t\tvaddr \u003d ioremap(paddr, size);\n\t\tif (!vaddr) {\n\t\t\tprintk(\"couldn\u0027t ioremap\\n\");\n\t\t\tbreak;\n\t\t}\n\t\tiounmap(vaddr);\n\t}\n\nThe changes to vmalloc.c weren\u0027t reflected in the ARM ioremap\nimplementation. Turns out the fix is rather simple.\n\nTested-by: Tomi Valkeinen \u003ctomi.valkeinen@nokia.com\u003e\nTested-by: Matt Gerassimoff \u003cmgeras@gmail.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7dd8c4f3526b16edb1a3f4edb4665a8fa6e632d8", "tree": "12b54dbe73f40a701d52dd7f97ad2a11e86f032e", "parents": [ "953a7e8476bbd7367cebdb868c326ba42968bc13" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Jan 18 16:24:19 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Jan 24 11:41:17 2009 +0000" }, "message": "[ARM] fix StrongARM-11x0 page copy implementation\n\nWhich had the \u0027from\u0027 and \u0027to\u0027 pages reversed.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "98007c230eb1e85ff5d49b4a697835680483dafd", "tree": "a5074e8b1330de2f8ff8b4a6a3ce3a31a5f0f702", "parents": [ "d672d2fc13242f9284345cb7e4c5a32cd5edefa3" ], "author": { "name": "Nicolas Pitre", "email": "nico@cam.org", "time": "Fri Jan 09 15:28:55 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jan 12 13:51:03 2009 +0000" }, "message": "[ARM] 5364/1: allow flush_ioremap_region() to be used from modules\n\nWithout this, the pxa2xx-flash driver cannot be used as a module.\n\nReported-by: Chris Lawrence \u003cchrisdl@netspace.net.au\u003e\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9c93af1ede9418bb3f1b9dd442faf91ba796a0ff", "tree": "a5185e6af336e3c00343e7791517b70f00d0c2df", "parents": [ "0e8f989a253b1bf85ea1c8d7987d67c054f4af91" ], "author": { "name": "David Howells", "email": "dhowells@redhat.com", "time": "Thu Jan 08 12:04:47 2009 +0000" }, "committer": { "name": "David Howells", "email": "dhowells@redhat.com", "time": "Thu Jan 08 12:04:47 2009 +0000" }, "message": "NOMMU: Rename ARM\u0027s struct vm_region\n\nRename ARM\u0027s struct vm_region so that I can introduce my own global version\nfor NOMMU. It\u0027s feasible that the ARM version may wish to use my global one\ninstead.\n\nThe NOMMU vm_region struct defines areas of the physical memory map that are\nunder mmap. This may include chunks of RAM or regions of memory mapped\ndevices, such as flash. It is also used to retain copies of file content so\nthat shareable private memory mappings of files can be made. As such, it may\nbe compatible with what is described in the banner comment for ARM\u0027s vm_region\nstruct.\n\nSigned-off-by: David Howells \u003cdhowells@redhat.com\u003e\n" }, { "commit": "c613bbba6f39c8804f1f26e96fb68a117cc9e282", "tree": "85fbc24f26b61ce4e7a908d18952e3abc1f5cd10", "parents": [ "cd4348339c21f4a15c01f3f120e92b3224a0a7da", "80eee6bca4069c48247005aa07cb5e8e86042aa3" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Wed Dec 17 20:04:45 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Dec 17 20:04:45 2008 +0000" }, "message": "Merge branch \u0027mxc-pu-imxfb\u0027 of git://pasiphae.extern.pengutronix.de/git/imx/linux-2.6 into devel\n" }, { "commit": "7e1548a597ef7e26d5d62f8be3be6da9e101b26c", "tree": "fe6cbf4d9a3c1afdba04fb276fef0f932403727c", "parents": [ "1f7f569c0ae6e619504095eabf796edd712d943d", "2619bc327417f549f1c89d5ef9b4a4aa768f41a2" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Mon Dec 15 22:13:26 2008 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 15 22:13:26 2008 +0000" }, "message": "Merge branch \u0027omap3-upstream\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into devel\n" } ], "next": "67306da610a3e4824192e92888634d3d8700bfc1" }