)]}' { "log": [ { "commit": "fb7ebfe4108e2cdfa2bb88e57148087717463dfa", "tree": "e18690b45566b6c4df7598524bdbeb71fbd80ba1", "parents": [ "cda57bf9348fdbf4b8a830d6f9eb7da81df2f486" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Wed Jan 04 15:50:02 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:15:21 2012 -0800" }, "message": "PCI: Increase resource array mask bit size in pcim_iomap_regions()\n\nDEVICE_COUNT_RESOURCE will be bigger than 16 when SRIOV supported is enabled.\n\nLet them pass with int just like pci_enable_resources().\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "cda57bf9348fdbf4b8a830d6f9eb7da81df2f486", "tree": "428e754d5064cb4da55c6896a274f9c716d27af6", "parents": [ "aecab53f45b84fbc7d6848957f9d83e1c3548b17" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Wed Jan 04 15:49:45 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:15:14 2012 -0800" }, "message": "PCI: DEVICE_COUNT_RESOURCE should be equal to PCI_NUM_RESOURCES\n\nSave some bytes for device resource array.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "118faafaf987f521832843d36c6be580983f9a6b", "tree": "56e9146fa7b4777f29977989884f912a68432e9f", "parents": [ "7ec303a7247a46a7a88a4f890466fd12dbdd5dc6" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:28:24 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:11:15 2012 -0800" }, "message": "PCI: remove pci_create_bus()\n\nAll users of pci_create_bus() have been converted to pci_create_root_bus(),\nso remove it.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "de4b2f76d69673cea08be952dcb4df2f4c81c6e3", "tree": "c4ad7b48299c2916117367641dfe1fa09325d8e1", "parents": [ "a2ebb827958a4ab3577443f89037f229683c644a" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:25:55 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:53 2012 -0800" }, "message": "PCI: convert pci_scan_bus() to use pci_create_root_bus()\n\nI plan to deprecate pci_scan_bus_parented(), so use pci_create_root_bus()\ndirectly instead. pci_scan_bus() itself will be removed as soon as all\ncallers are gone, so this is just an interim step.\n\nv2: export pci_scan_bus\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a2ebb827958a4ab3577443f89037f229683c644a", "tree": "c1e44c472315f75c8ba9d147e3712db1e9017a1e", "parents": [ "166c6370754a0a92386e2ffb0eeb06e50ac8588d" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:25:50 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:52 2012 -0800" }, "message": "PCI: add pci_scan_root_bus() that accepts resource list\n\n\"Early\" and \"header\" quirks often use incorrect bus resources because they\nsee the default resources assigned by pci_create_bus(), before the\narchitecture fixes them up (typically in pcibios_fixup_bus()). Regions\nreserved by these quirks end up with the wrong parents.\n\nHere\u0027s the standard path for scanning a PCI root bus:\n\n pci_scan_bus or pci_scan_bus_parented\n pci_create_bus \u003c-- A create with default resources\n pci_scan_child_bus\n pci_scan_slot\n pci_scan_single_device\n pci_scan_device\n pci_setup_device\n pci_fixup_device(early) \u003c-- B\n pci_device_add\n pci_fixup_device(header) \u003c-- C\n pcibios_fixup_bus \u003c-- D fill in correct resources\n\nEarly and header quirks at B and C use the default (incorrect) root bus\nresources rather than those filled in at D.\n\nThis patch adds a new pci_scan_root_bus() function that sets the bus\nresources correctly from a supplied list of resources.\n\nI intend to remove pci_scan_bus() and pci_scan_bus_parented() after\nfixing all callers.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "166c6370754a0a92386e2ffb0eeb06e50ac8588d", "tree": "c9bbbf23a0508cd93d546ecbfdb9fcd423a1e461", "parents": [ "a9d9f5276cb3fa08351e8837ab9398bfd8e69a2e" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:25:45 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:51 2012 -0800" }, "message": "PCI: add pci_create_root_bus() that accepts resource list\n\npci_create_bus() assigns ioport_resource and iomem_resource as the default\nbus resources, i.e., the entire address space. Architectures fix these\nlater, typically in pcibios_fixup_bus() or after pci_scan_bus_parented()\nreturns, but code that runs in the interim sees incorrect resource\ninformation.\n\nThis patch adds a new pci_create_root_bus() that sets the bus resources\ncorrectly from a supplied list of resources.\n\nI intend to remove pci_create_bus() after changing all callers.\n\nBased on original patch by Deng-Cheng Zhu.\n\nReference: http://www.spinics.net/lists/mips/msg41654.html\nReference: https://lkml.org/lkml/2011/8/26/88\nSigned-off-by: Deng-Cheng Zhu \u003cdczhu@mips.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "45ca9e9730c5acdb482dd95799fd8ac834481897", "tree": "b73836ea44c0b3537ededd0c86653edfcfabb5c3", "parents": [ "afd24ece5c76af87f6fc477f2747b83a764f161c" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:25:35 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:50 2012 -0800" }, "message": "PCI: add helpers for building PCI bus resource lists\n\nWe\u0027d like to supply a list of resources when we create a new PCI bus,\ne.g., the root bus under a PCI host bridge. These are helpers for\nconstructing that list.\n\nThese are exported because the plan is to replace this exported interface:\n pci_scan_bus_parented()\nwith this one:\n pci_add_resource(resources, ...)\n pci_scan_root_bus(..., resources)\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "96c5590058d7fded14f43af2ab521436cecf3125", "tree": "673577f86b1ee8886c27cc86333fdfdc6cc783ac", "parents": [ "9cdce18d6f0baae53f012fb3f50e66e7ff24c509" ], "author": { "name": "Myron Stowe", "email": "mstowe@redhat.com", "time": "Fri Oct 28 15:48:38 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:42 2012 -0800" }, "message": "PCI: Pull PCI \u0027latency timer\u0027 setup up into the core\n\nThe \u0027latency timer\u0027 of PCI devices, both Type 0 and Type 1,\nis setup in architecture-specific code [see: \u0027pcibios_set_master()\u0027].\nThere are two approaches being taken by all the architectures - check\nif the \u0027latency timer\u0027 is currently set between 16 and 255 and if not\nbring it within bounds, or, do nothing (and then there is the\ngratuitously different PA-RISC implementation).\n\nThere is nothing architecture-specific about PCI\u0027s \u0027latency timer\u0027 so\nthis patch pulls its setup functionality up into the PCI core by\ncreating a generic \u0027pcibios_set_master()\u0027 function using the \u0027__weak\u0027\nattribute which can be used by all architectures as a default which,\nif necessary, can then be over-ridden by architecture-specific code.\n\nNo functional change.\n\nSigned-off-by: Myron Stowe \u003cmyron.stowe@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "cfce9fb808d7d25f6ea18a804eb71b08c7d777c1", "tree": "5266c63ab2a128a65ef830aee2e2ec1020aad4a4", "parents": [ "2502dbdfc878a801b5e6d0b6901c334f4051ca39" ], "author": { "name": "Myron Stowe", "email": "mstowe@redhat.com", "time": "Fri Oct 28 15:47:35 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:35 2012 -0800" }, "message": "PCI: add declaration for pcibios_set_master() to pci core\n\nCurrently, pcibios_set_master() is implemented in architecture-\nspecific code. There is nothing architecture-specific about PCI\u0027s\n\u0027latency timer\u0027.\n\nThis patch adds a declaration for pcibios_set_master() to PCI\u0027s core\nin preperation for pulling the function itself up into the core.\nWithout the addition of this declaration, subsequent patches that\nremove inline definitions of pcibios_set_master() would be removing\nthe only declaration of such.\n\nNo functional change.\n\nSigned-off-by: Myron Stowe \u003cmyron.stowe@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a2e27787f893621c5a6b865acf6b7766f8671328", "tree": "b7398b80a56b1e25e4758dfc9ed2af2df27458f3", "parents": [ "fb51ccbf217c1c994607b6519c7d85250928553d" ], "author": { "name": "Jan Kiszka", "email": "jan.kiszka@siemens.com", "time": "Fri Nov 04 09:46:00 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:34 2012 -0800" }, "message": "PCI: Introduce INTx check \u0026 mask API\n\nThese new PCI services allow to probe for 2.3-compliant INTx masking\nsupport and then use the feature from PCI interrupt handlers. The\nservices are properly synchronized with concurrent config space access\nvia sysfs or on device reset.\n\nThis enables generic PCI device drivers like uio_pci_generic or KVM\u0027s\ndevice assignment to implement the necessary kernel-side IRQ handling\nwithout any knowledge about device-specific interrupt status and control\nregisters.\n\nAcked-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Jan Kiszka \u003cjan.kiszka@siemens.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fb51ccbf217c1c994607b6519c7d85250928553d", "tree": "d08ba9a0278da0e75b6c6714e9453e46068e27b4", "parents": [ "ae5cd86455381282ece162966183d3f208c6fad7" ], "author": { "name": "Jan Kiszka", "email": "jan.kiszka@siemens.com", "time": "Fri Nov 04 09:45:59 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:33 2012 -0800" }, "message": "PCI: Rework config space blocking services\n\npci_block_user_cfg_access was designed for the use case that a single\ncontext, the IPR driver, temporarily delays user space accesses to the\nconfig space via sysfs. This assumption became invalid by the time\npci_dev_reset was added as locking instance. Today, if you run two loops\nin parallel that reset the same device via sysfs, you end up with a\nkernel BUG as pci_block_user_cfg_access detect the broken assumption.\n\nThis reworks the pci_block_user_cfg_access to a sleeping service\npci_cfg_access_lock and an atomic-compatible variant called\npci_cfg_access_trylock. The former not only blocks user space access as\nbefore but also waits if access was already locked. The latter service\njust returns false in this case, allowing the caller to resolve the\nconflict instead of raising a BUG.\n\nAdaptions of the ipr driver were originally written by Brian King.\n\nAcked-by: Brian King \u003cbrking@linux.vnet.ibm.com\u003e\nAcked-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Jan Kiszka \u003cjan.kiszka@siemens.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "da8d1c8ba4dcb16d60be54b233deca9a7cac98dc", "tree": "ac4713f9dd29aab4d4d5b167cf61081aeb2ccdb4", "parents": [ "8b6a5af92c03b363df050da906480085b6cd6e00" ], "author": { "name": "Neil Horman", "email": "nhorman@tuxdriver.com", "time": "Thu Oct 06 14:08:18 2011 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:25 2012 -0800" }, "message": "PCI/sysfs: add per pci device msi[x] irq listing (v5)\n\nThis patch adds a per-pci-device subdirectory in sysfs called:\n/sys/bus/pci/devices/\u003cdevice\u003e/msi_irqs\n\nThis sub-directory exports the set of msi vectors allocated by a given\npci device, by creating a numbered sub-directory for each vector beneath\nmsi_irqs. For each vector various attributes can be exported.\nCurrently the only attribute is called mode, which tracks the\noperational mode of that vector (msi vs. msix)\n\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "466b3ddfbcf4f5ce402a77397630a0fa9ea9ce6b", "tree": "b6cc96d109e5ba389e3825064714232e2bc314dd", "parents": [ "0d52f54e2ef64c189dedc332e680b2eb4a34590a" ], "author": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Sun Oct 30 16:35:08 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Oct 31 10:23:57 2011 -0700" }, "message": "PCI: Fix compile errors with PCI_ATS and !PCI_IOV\n\nThe ats and sroiv members of \u0027struct pci_dev\u0027 are required\nfor the ATS code already, even without IOV support compiled\nin. So depend on ATS here. This is fine with PCI_IOV too\nbecause it selects PCI_ATS. Also the prototypes for ATS\nneed to be available for PCI_ATS.\n\nReported-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nSigned-off-by: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0e59e7e7feb5a12938fbf9135147eeda3238c6c4", "tree": "dbe994369ca9cad6893f0fd710f75791bc84b816", "parents": [ "46b51ea2099fa2082342e52b8284aa828429b80b", "a513a99a7cebfb452839cc09c9c0586f72d96414" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Oct 28 14:20:44 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Oct 28 14:20:44 2011 -0700" }, "message": "Merge branch \u0027next-rebase\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci\n\n* \u0027next-rebase\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci:\n PCI: Clean-up MPS debug output\n pci: Clamp pcie_set_readrq() when using \"performance\" settings\n PCI: enable MPS \"performance\" setting to properly handle bridge MPS\n PCI: Workaround for Intel MPS errata\n PCI: Add support for PASID capability\n PCI: Add implementation for PRI capability\n PCI: Export ATS functions to modules\n PCI: Move ATS implementation into own file\n PCI / PM: Remove unnecessary error variable from acpi_dev_run_wake()\n PCI hotplug: acpiphp: Prevent deadlock on PCI-to-PCI bridge remove\n PCI / PM: Extend PME polling to all PCI devices\n PCI quirk: mmc: Always check for lower base frequency quirk for Ricoh 1180:e823\n PCI: Make pci_setup_bridge() non-static for use by arch code\n x86: constify PCI raw ops structures\n PCI: Add quirk for known incorrect MPSS\n PCI: Add Solarflare vendor ID and SFC4000 device IDs\n" }, { "commit": "379021d5c0899fcf9410cae4ca7a59a5a94ca769", "tree": "9c91ffb80fcb143b94c20922cb27d60d2c7e6654", "parents": [ "3e309cdf07c930f29a4e0f233e47d399bea34c68" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Oct 03 23:16:33 2011 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Oct 14 09:05:31 2011 -0700" }, "message": "PCI / PM: Extend PME polling to all PCI devices\n\nThe land of PCI power management is a land of sorrow and ugliness,\nespecially in the area of signaling events by devices. There are\ndevices that set their PME Status bits, but don\u0027t really bother\nto send a PME message or assert PME#. There are hardware vendors\nwho don\u0027t connect PME# lines to the system core logic (they know\nwho they are). There are PCI Express Root Ports that don\u0027t bother\nto trigger interrupts when they receive PME messages from the devices\nbelow. There are ACPI BIOSes that forget to provide _PRW methods for\ndevices capable of signaling wakeup. Finally, there are BIOSes that\ndo provide _PRW methods for such devices, but then don\u0027t bother to\ncall Notify() for those devices from the corresponding _Lxx/_Exx\nGPE-handling methods. In all of these cases the kernel doesn\u0027t have\na chance to receive a proper notification that it should wake up a\ndevice, so devices stay in low-power states forever. Worse yet, in\nsome cases they continuously send PME Messages that are silently\nignored, because the kernel simply doesn\u0027t know that it should clear\nthe device\u0027s PME Status bit.\n\nThis problem was first observed for \"parallel\" (non-Express) PCI\ndevices on add-on cards and Matthew Garrett addressed it by adding\ncode that polls PME Status bits of such devices, if they are enabled\nto signal PME, to the kernel. Recently, however, it has turned out\nthat PCI Express devices are also affected by this issue and that it\nis not limited to add-on devices, so it seems necessary to extend\nthe PME polling to all PCI devices, including PCI Express and planar\nones. Still, it would be wasteful to poll the PME Status bits of\ndevices that are known to receive proper PME notifications, so make\nthe kernel (1) poll the PME Status bits of all PCI and PCIe devices\nenabled to signal PME and (2) disable the PME Status polling for\ndevices for which correct PME notifications are received.\n\nTested-by: Sarah Sharp \u003csarah.a.sharp@linux.intel.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e24442733ee486c99d03fe2ecd98924d1bc14c51", "tree": "799b7789febb8491115c97f5a136042d26a81cff", "parents": [ "72da0b07b1b497927758a2102b856ce41e4ba81e" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Sun Sep 11 14:08:38 2011 -0300" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Oct 14 09:05:29 2011 -0700" }, "message": "PCI: Make pci_setup_bridge() non-static for use by arch code\n\nThe \"powernv\" platform of the powerpc architecture needs to assign PCI\nresources using a specific algorithm to fit some HW constraints of\nthe IBM \"IODA\" architecture (related to the ability to create error\nhandling domains that encompass specific segments of MMIO space).\n\nFor doing so, it wants to call pci_setup_bridge() from architecture\nspecific resource management in order to configure bridges after all\nresources have been assigned. So make it non-static.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "88c5100c28b02c4b2b2c6f6fafbbd76d90f698b9", "tree": "08c4399e0341f7eb0ccb24e15f2cab687275c2a4", "parents": [ "8083f0fc969d9b5353061a7a6f963405057e26b1", "3ee72ca99288f1de95ec9c570e43f531c8799f06" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Oct 07 13:38:43 2011 -0400" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Oct 07 13:38:43 2011 -0400" }, "message": "Merge branch \u0027master\u0027 of github.com:davem330/net\n\nConflicts:\n\tnet/batman-adv/soft-interface.c\n" }, { "commit": "5f39e6705faade2e89d119958a8c51b9b6e2c53c", "tree": "e9d69f2f465daeca7cdc452a3b19d702f15e98b0", "parents": [ "05faadcf59507e8eea57ffbeea9cbb14c9a2ab3d" ], "author": { "name": "Jon Mason", "email": "mason@myri.com", "time": "Mon Oct 03 09:50:20 2011 -0500" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Oct 04 09:52:28 2011 -0700" }, "message": "PCI: Disable MPS configuration by default\n\nAdd the ability to disable PCI-E MPS turning and using the BIOS\nconfigured MPS defaults. Due to the number of issues recently\ndiscovered on some x86 chipsets, make this the default behavior.\n\nAlso, add the option for peer to peer DMA MPS configuration. Peer to\npeer DMA is outside the scope of this patch, but MPS configuration could\nprevent it from working by having the MPS on one root port different\nthan the MPS on another. To work around this, simply make the system\nwide MPS the smallest possible value (128B).\n\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nAcked-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "fb7a6d4e7da219f895d156cad00e2b6373e2494f", "tree": "79f5f36386124f010533b67f0414c4bf86527770", "parents": [ "230dec61313dc5f5720311d0b492f69f5466b0a4", "8c838d7384c6e5c0583ec6bbb2e6f6dba19feda1" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Sep 23 13:56:44 2011 -0400" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Sep 23 13:56:44 2011 -0400" }, "message": "Merge git://github.com/Jkirsher/net-next\n" }, { "commit": "6777829cfe1c4ed78319ad40aaee60254222da76", "tree": "03e55538247c4b2fbdc837984922a0ac8753b253", "parents": [ "9c9b1f24f2aa31a3cea94939edc551f68ebadc89" ], "author": { "name": "Greg Rose", "email": "gregory.v.rose@intel.com", "time": "Fri Jul 22 05:46:07 2011 +0000" }, "committer": { "name": "Jeff Kirsher", "email": "jeffrey.t.kirsher@intel.com", "time": "Fri Sep 23 09:05:44 2011 -0700" }, "message": "pci: Add flag indicating device has been assigned by KVM\n\nDevice drivers that create and destroy SR-IOV virtual functions via\ncalls to pci_enable_sriov() and pci_disable_sriov can cause catastrophic\nfailures if they attempt to destroy VFs while they are assigned to\nguest virtual machines. By adding a flag for use by the KVM module\nto indicate that a device is assigned a device driver can check that\nflag and avoid destroying VFs while they are assigned and avoid system\nfailures.\n\nCC: Ian Campbell \u003cijc@hellion.org.uk\u003e\nCC: Konrad Wilk \u003ckonrad.wilk@oracle.com\u003e\nSigned-off-by: Greg Rose \u003cgregory.v.rose@intel.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Jeff Kirsher \u003cjeffrey.t.kirsher@intel.com\u003e\n" }, { "commit": "2bbc6942273b5b3097bd265d82227bdd84b351b2", "tree": "34d846f34a94dbe7b0c4800cb8efc3cf2e07ad74", "parents": [ "be768912a49b10b68e96fbd8fa3cab0adfbd3091" ], "author": { "name": "Ram Pai", "email": "linuxram@us.ibm.com", "time": "Mon Jul 25 13:08:39 2011 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Aug 01 11:50:15 2011 -0700" }, "message": "PCI : ability to relocate assigned pci-resources\n\nCurrently pci-bridges are allocated enough resources to satisfy their immediate\nrequirements. Any additional resource-requests fail if additional free space,\ncontiguous to the one already allocated, is not available. This behavior is not\nreasonable since sufficient contiguous resources, that can satisfy the request,\nare available at a different location.\n\nThis patch provides the ability to expand and relocate a allocated resource.\n\n\tv2: Changelog: Fixed size calculation in pci_reassign_resource()\n\tv3: Changelog : Split this patch. The resource.c changes are already\n\t\t\tupstream. All the pci driver changes are in here.\n\nSigned-off-by: Ram Pai \u003clinuxram@us.ibm.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b03e7495a862b028294f59fc87286d6d78ee7fa1", "tree": "836fbfc2b0e34f034cb273c4d065baba3a65178c", "parents": [ "5f66d2b58ca879e70740c82422354144845d6dd3" ], "author": { "name": "Jon Mason", "email": "mason@myri.com", "time": "Wed Jul 20 15:20:54 2011 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Aug 01 11:49:16 2011 -0700" }, "message": "PCI: Set PCI-E Max Payload Size on fabric\n\nOn a given PCI-E fabric, each device, bridge, and root port can have a\ndifferent PCI-E maximum payload size. There is a sizable performance\nboost for having the largest possible maximum payload size on each PCI-E\ndevice. However, if improperly configured, fatal bus errors can occur.\nThus, it is important to ensure that PCI-E payloads sends by a device\nare never larger than the MPS setting of all devices on the way to the\ndestination.\n\nThis can be achieved two ways:\n\n- A conservative approach is to use the smallest common denominator of\n the entire tree below a root complex for every device on that fabric.\n\nThis means for example that having a 128 bytes MPS USB controller on one\nleg of a switch will dramatically reduce performances of a video card or\n10GE adapter on another leg of that same switch.\n\nIt also means that any hierarchy supporting hotplug slots (including\nexpresscard or thunderbolt I suppose, dbl check that) will have to be\nentirely clamped to 128 bytes since we cannot predict what will be\nplugged into those slots, and we cannot change the MPS on a \"live\"\nsystem.\n\n- A more optimal way is possible, if it falls within a couple of\n constraints:\n* The top-level host bridge will never generate packets larger than the\n smallest TLP (or if it can be controlled independently from its MPS at\n least)\n* The device will never generate packets larger than MPS (which can be\n configured via MRRS)\n* No support of direct PCI-E \u003c-\u003e PCI-E transfers between devices without\n some additional code to specifically deal with that case\n\nThen we can use an approach that basically ignores downstream requests\nand focuses exclusively on upstream requests. In that case, all we need\nto care about is that a device MPS is no larger than its parent MPS,\nwhich allows us to keep all switches/bridges to the max MPS supported by\ntheir parent and eventually the PHB.\n\nIn this case, your USB controller would no longer \"starve\" your 10GE\nEthernet and your hotplug slots won\u0027t affect your global MPS.\nAdditionally, the hotplugged devices themselves can be configured to a\nlarger MPS up to the value configured in the hotplug bridge.\n\nTo choose between the two available options, two PCI kernel boot args\nhave been added to the PCI calls. \"pcie_bus_safe\" will provide the\nformer behavior, while \"pcie_bus_perf\" will perform the latter behavior.\nBy default, the latter behavior is used.\n\nNOTE: due to the location of the enablement, each arch will need to add\ncalls to this function. This patch only enables x86.\n\nThis patch includes a number of changes recommended by Benjamin\nHerrenschmidt.\n\nTested-by: Jordan_Hargrave@dell.com\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f85f19de90a9997583bb26e6f1f9297a4e152c18", "tree": "2dfe61dab6c39ca202f114cb68c68978da1624e3", "parents": [ "b993fdbc7fe26f96b59003a3552c418a71aa0a9f", "7b87c9df5602efd6c7edeb291bbd104d49a6babf" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jul 29 23:35:05 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jul 29 23:35:05 2011 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n PCI: remove printks about disabled bridge windows\n PCI: fold pci_calc_resource_flags() into decode_bar()\n PCI: treat mem BAR type \"11\" (reserved) as 32-bit, not 64-bit, BAR\n PCI: correct pcie_set_readrq write size\n PCI: pciehp: change wait time for valid configuration access\n x86/PCI: Preserve existing pci\u003dbfsort whitelist for Dell systems\n PCI: ARI is a PCIe v2 feature\n x86/PCI: quirks: Use pci_dev-\u003erevision\n PCI: Make the struct pci_dev * argument of pci_fixup_irqs const.\n PCI hotplug: cpqphp: use pci_dev-\u003evendor\n PCI hotplug: cpqphp: use pci_dev-\u003esubsystem_{vendor|device}\n x86/PCI: config space accessor functions should not ignore the segment argument\n PCI: Assign values to \u0027pci_obff_signal_type\u0027 enumeration constants\n x86/PCI: reduce severity of host bridge window conflict warnings\n PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI\n PCI: PCIe AER: add aer_recover_queue\n x86/PCI: select direct access mode for mmconfig option\n PCI hotplug: Rename is_ejectable which also exists in dock.c\n" }, { "commit": "60063497a95e716c9a689af3be2687d261f115b4", "tree": "6ce0d68db76982c53df46aee5f29f944ebf2c320", "parents": [ "148817ba092f9f6edd35bad3c6c6b8e8f90fe2ed" ], "author": { "name": "Arun Sharma", "email": "asharma@fb.com", "time": "Tue Jul 26 16:09:06 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Jul 26 16:49:47 2011 -0700" }, "message": "atomic: use \u003clinux/atomic.h\u003e\n\nThis allows us to move duplicated code in \u003casm/atomic.h\u003e\n(atomic_inc_not_zero() for now) to \u003clinux/atomic.h\u003e\n\nSigned-off-by: Arun Sharma \u003casharma@fb.com\u003e\nReviewed-by: Eric Dumazet \u003ceric.dumazet@gmail.com\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: David Miller \u003cdavem@davemloft.net\u003e\nCc: Eric Dumazet \u003ceric.dumazet@gmail.com\u003e\nAcked-by: Mike Frysinger \u003cvapier@gentoo.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "6d16d6d9bb6f93e6f8506cfb3e91795d6443d54f", "tree": "92a1c9e4b645fa6d1fffedaeb56141b66f847320", "parents": [ "431bf99d26157d56689e5de65bd27ce9f077fc3f", "b395fb36d59e17b9335805c10fa30fc51c8a94c6" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jul 22 16:39:42 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jul 22 16:39:42 2011 -0700" }, "message": "Merge branch \u0027core-iommu-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027core-iommu-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n iommu/core: Fix build with INTR_REMAP\u003dy \u0026\u0026 CONFIG_DMAR\u003dn\n iommu/amd: Don\u0027t use MSI address range for DMA addresses\n iommu/amd: Move missing parts to drivers/iommu\n iommu: Move iommu Kconfig entries to submenu\n x86/ia64: intel-iommu: move to drivers/iommu/\n x86: amd_iommu: move to drivers/iommu/\n msm: iommu: move to drivers/iommu/\n drivers: iommu: move to a dedicated folder\n x86/amd-iommu: Store device alias as dev_data pointer\n x86/amd-iommu: Search for existind dev_data before allocting a new one\n x86/amd-iommu: Allow dev_data-\u003ealias to be NULL\n x86/amd-iommu: Use only dev_data in low-level domain attach/detach functions\n x86/amd-iommu: Use only dev_data for dte and iotlb flushing routines\n x86/amd-iommu: Store ATS state in dev_data\n x86/amd-iommu: Store devid in dev_data\n x86/amd-iommu: Introduce global dev_data_list\n x86/amd-iommu: Remove redundant device_flush_dte() calls\n iommu-api: Add missing header file\n\nFix up trivial conflicts (independent additions close to each other) in\ndrivers/Makefile and include/linux/pci.h\n" }, { "commit": "d5341942d784134f2997b3ff82cd63cf71d1f932", "tree": "355ad81a15d031bbfe7dd94ee6696d8889c926d0", "parents": [ "05d3ac267a9d10af6ca370afe21802333aad1d5c" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Jun 10 15:30:21 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 22 08:26:06 2011 -0700" }, "message": "PCI: Make the struct pci_dev * argument of pci_fixup_irqs const.\n\nAside of the usual motivation for constification, this function has a\nhistory of being abused a hook for interrupt and other fixups so I turned\nthis function const ages ago in the MIPS code but it should be done\ntreewide.\n\nDue to function pointer passing in varous places a few other functions\nhad to be constified as well.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nTo: Anton Vorontsov \u003cavorontsov@mvista.com\u003e\nTo: Chris Metcalf \u003ccmetcalf@tilera.com\u003e\nTo: Colin Cross \u003cccross@android.com\u003e\nAcked-by: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nTo: Eric Miao \u003ceric.y.miao@gmail.com\u003e\nTo: Erik Gilling \u003ckonkers@android.com\u003e\nAcked-by: Guan Xuetao \u003cgxt@mprc.pku.edu.cn\u003e\nTo: \"H. Peter Anvin\" \u003chpa@zytor.com\u003e\nTo: Imre Kaloz \u003ckaloz@openwrt.org\u003e\nTo: Ingo Molnar \u003cmingo@redhat.com\u003e\nTo: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nTo: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nTo: Krzysztof Halasa \u003ckhc@pm.waw.pl\u003e\nTo: Lennert Buytenhek \u003ckernel@wantstofly.org\u003e\nTo: Matt Turner \u003cmattst88@gmail.com\u003e\nTo: Nicolas Pitre \u003cnico@fluxnic.net\u003e\nTo: Olof Johansson \u003colof@lixom.net\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nTo: Richard Henderson \u003crth@twiddle.net\u003e\nTo: Russell King \u003clinux@arm.linux.org.uk\u003e\nTo: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: linux-alpha@vger.kernel.org\nCc: linux-arm-kernel@lists.infradead.org\nCc: linux-kernel@vger.kernel.org\nCc: linux-mips@linux-mips.org\nCc: linux-pci@vger.kernel.org\nCc: linux-sh@vger.kernel.org\nCc: linux-tegra@vger.kernel.org\nCc: sparclinux@vger.kernel.org\nCc: x86@kernel.org\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "688398bb7b9c6ac115da7749ea808d3ef69e029f", "tree": "b9c0124b53e37be90204a9e335540f0530cf651d", "parents": [ "43d786ed4df4c54cb8802a523748a7d78130a2cb" ], "author": { "name": "Myron Stowe", "email": "mstowe@redhat.com", "time": "Thu Jul 07 15:00:36 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 22 08:25:40 2011 -0700" }, "message": "PCI: Assign values to \u0027pci_obff_signal_type\u0027 enumeration constants\n\n\u0027pci_obff_signal_type\u0027 is passed between drivers and the kernel API.\nThis patch explicitly assigns values to the enumeration type\u0027s constants\nwhich aids in detecting any future changes or additions that would break\nthe kernel\u0027s ABI.\n\nNo functional change.\n\nSigned-off-by: Myron Stowe \u003cmyron.stowe@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "166e9278a3f98bab29ebb3d685a81cfb11b98be0", "tree": "f8f3e8a28c5d96d9053567d6a9ef8e04e7b298dd", "parents": [ "29b68415e335ba9e0eb6057f9405aa4d9c23efe4" ], "author": { "name": "Ohad Ben-Cohen", "email": "ohad@wizery.com", "time": "Fri Jun 10 21:42:27 2011 +0300" }, "committer": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Tue Jun 21 10:49:30 2011 +0200" }, "message": "x86/ia64: intel-iommu: move to drivers/iommu/\n\nThis should ease finding similarities with different platforms,\nwith the intention of solving problems once in a generic framework\nwhich everyone can use.\n\nNote: to move intel-iommu.c, the declaration of pci_find_upstream_pcie_bridge()\nhas to move from drivers/pci/pci.h to include/linux/pci.h. This is handled\nin this patch, too.\n\nAs suggested, also drop DMAR\u0027s EXPERIMENTAL tag while we\u0027re at it.\n\nCompile-tested on x86_64.\n\nSigned-off-by: Ohad Ben-Cohen \u003cohad@wizery.com\u003e\nSigned-off-by: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\n" }, { "commit": "ef3b4f8cc20e80c767e47b848fb7512770ab80d7", "tree": "dc3550170335564b7644e1db62658a56d2c7ff8e", "parents": [ "64099d981c9916ec4a485b3ffbb89fa877fc595f" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Mon Apr 11 11:34:33 2011 +1000" }, "committer": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Wed Jun 08 09:08:57 2011 +1000" }, "message": "pci/of: Consolidate pci_bus_to_OF_node()\n\nThe generic code always get the device-node in the right place now\nso a single implementation will work for all archs\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nAcked-by: Michal Simek \u003cmonstr@monstr.eu\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "64099d981c9916ec4a485b3ffbb89fa877fc595f", "tree": "363409e3a5bafdbbfbeffe6f93f1c2338f1c893b", "parents": [ "3d5fe5a65af9c0b609d6e26b8d63fe5923c4e512" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Thu Apr 07 13:09:47 2011 +1000" }, "committer": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Wed Jun 08 09:08:43 2011 +1000" }, "message": "pci/of: Consolidate pci_device_to_OF_node()\n\nAll archs do more or less the same thing now, move it into\na single generic place.\n\nI chose pci.h rather than of_pci.h to avoid having to change\nall call-sites to include the later.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Michal Simek \u003cmonstr@monstr.eu\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "98d9f30c820d509145757e6ecbc36013aa02f7bc", "tree": "dd5da915d991352ced56ed849612029339f64198", "parents": [ "1fa7b6a29c61358cc2ca6f64cef4aa0e1a7ca74c" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Mon Apr 11 11:37:07 2011 +1000" }, "committer": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Wed Jun 08 09:08:17 2011 +1000" }, "message": "pci/of: Match PCI devices to OF nodes dynamically\n\npowerpc has two different ways of matching PCI devices to their\ncorresponding OF node (if any) for historical reasons. The ppc64 one\ndoes a scan looking for matching bus/dev/fn, while the ppc32 one does a\nscan looking only for matching dev/fn on each level in order to be\nagnostic to busses being renumbered (which Linux does on some\nplatforms).\n\nThis removes both and instead moves the matching code to the PCI core\nitself. It\u0027s the most logical place to do it: when a pci_dev is created,\nwe know the parent and thus can do a single level scan for the matching\ndevice_node (if any).\n\nThe benefit is that all archs now get the matching for free. There\u0027s one\nhook the arch might want to provide to match a PHB bus to its device\nnode. A default weak implementation is provided that looks for the\nparent device device node, but it\u0027s not entirely reliable on powerpc for\nvarious reasons so powerpc provides its own.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Michal Simek \u003cmonstr@monstr.eu\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "98b98d316349e9a028e632629fe813d07fa5afdd", "tree": "caaf6a662a86c5e2a418f0929ca05f0748803ac5", "parents": [ "0d66cba1ac3ad38614077443d604d6a09cec99de", "931474c4c30633400ff0dff8fb452ae20e01d067" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue May 24 12:06:40 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue May 24 12:06:40 2011 -0700" }, "message": "Merge branch \u0027drm-core-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6\n\n* \u0027drm-core-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (169 commits)\n drivers/gpu/drm/radeon/atom.c: fix warning\n drm/radeon/kms: bump kms version number\n drm/radeon/kms: properly set num banks for fusion asics\n drm/radeon/kms/atom: move dig phy init out of modesetting\n drm/radeon/kms/cayman: fix typo in register mask\n drm/radeon/kms: fix typo in spread spectrum code\n drm/radeon/kms: fix tile_config value reported to userspace on cayman.\n drm/radeon/kms: fix incorrect comparison in cayman setup code.\n drm/radeon/kms: add wait idle ioctl for eg-\u003ecayman\n drm/radeon/cayman: setup hdp to invalidate and flush when asked\n drm/radeon/evergreen/btc/fusion: setup hdp to invalidate and flush when asked\n agp/uninorth: Fix lockups with radeon KMS and \u003e1x.\n drm/radeon/kms: the SS_Id field in the LCD table if for LVDS only\n drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices\n drm/radeon/kms: fixup eDP connector handling\n drm/radeon/kms: bail early for eDP in hotplug callback\n drm/radeon/kms: simplify hotplug handler logic\n drm/radeon/kms: rewrite DP handling\n drm/radeon/kms/atom: add support for setting DP panel mode\n drm/radeon/kms: atombios.h updates for DP panel mode\n ...\n" }, { "commit": "ffbdd3f7931fb7cb7e36d00d16303ec433be5145", "tree": "503e1ad819bb3f1d682de24de5271935849ba5ff", "parents": [ "24a4742f0be6226eb0106fbb17caf4d711d1ad43" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Tue May 10 10:02:27 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sat May 21 12:17:09 2011 -0700" }, "message": "PCI: Add interfaces to store and load the device saved state\n\nFor KVM device assignment, we\u0027d like to save off the state of a device\nprior to passing it to the guest and restore it later. We also want\nto allow pci_reset_funciton() to be called while the device is owned\nby the guest. This however overwrites and invalidates the struct pci_dev\nbuffers, so we can\u0027t just manually call save and restore. Add generic\ninterfaces for the saved state to be stored and reloaded back into\nstruct pci_dev at a later time.\n\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "24a4742f0be6226eb0106fbb17caf4d711d1ad43", "tree": "43c61634fec10605571321daa38b81de4006eab6", "parents": [ "9f728f53dd70396f3183d2f0861022259471824b" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Tue May 10 10:02:11 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sat May 21 12:17:08 2011 -0700" }, "message": "PCI: Track the size of each saved capability data area\n\nThis will allow us to store and load it later.\n\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "51c2e0a7e5bc7ed1384cc68cfb95e702571500c9", "tree": "839dc5d6eb233b009c8802cb8cafde68f5a2ce6e", "parents": [ "48a92a8179b3e677fac07db7bd109e68f020468c" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 14 08:53:04 2011 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed May 11 15:18:53 2011 -0700" }, "message": "PCI: add latency tolerance reporting enable/disable support\n\nLatency tolerance reporting allows devices to send messages to the root\ncomplex indicating their latency tolerance for snooped \u0026 unsnooped\nmemory transactions. Add support for enabling \u0026 disabling this\nfeature, along with a routine to set the max latencies a device should\nsend upstream.\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "48a92a8179b3e677fac07db7bd109e68f020468c", "tree": "a0d43c7fc33fd5c899ce81103097117c27dd3e60", "parents": [ "b48d4425b602f5f4978299474743dbea130d940d" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 10 12:46:36 2011 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed May 11 15:18:48 2011 -0700" }, "message": "PCI: add OBFF enable/disable support\n\nOBFF (optimized buffer flush/fill), where supported, can help improve\nenergy efficiency by giving devices information about when interrupts\nand other activity will have a reduced power impact. It requires\nsupport from both the device and system (i.e. not only does the device\nneed to respond to OBFF messages, but the platform must be capable of\ngenerating and routing them to the end point).\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b48d4425b602f5f4978299474743dbea130d940d", "tree": "7da23c264cab62bce753e60c4e8d5fbbb0aab0e7", "parents": [ "69643e4829c5cd13bafe44a6b9f3eb2086e0f618" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Oct 19 13:07:57 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed May 11 15:18:40 2011 -0700" }, "message": "PCI: add ID-based ordering enable/disable support\n\nAdd support to allow drivers to enable/disable ID-based ordering. Where\nsupported, ID-based ordering can significantly improve the latency of\nindividual requests by preventing them from queueing up behind unrelated\ntraffic.\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3448a19da479b6bd1e28e2a2be9fa16c6a6feb39", "tree": "b69bfa9e71e46c8c7470cbdf49de8530227d6687", "parents": [ "8116188fdef5946bcbb2d73e41d7412a57ffb034" ], "author": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Tue Jun 01 15:32:24 2010 +1000" }, "committer": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Wed May 04 13:38:46 2011 +1000" }, "message": "vgaarb: use bridges to control VGA routing where possible.\n\nSo in a lot of modern systems, a GPU will always be below a parent bridge that won\u0027t share with any other GPUs. This means VGA arbitration on those GPUs can be controlled by using the bridge routing instead of io/mem decodes.\n\nThe problem is locating which GPUs share which upstream bridges. This patch attempts to identify all the GPUs which can be controlled via bridges, and ones that can\u0027t. This patch endeavours to work out the bridge sharing semantics.\n\nWhen disabling GPUs via a bridge, it doesn\u0027t do irq callbacks or touch the io/mem decodes for the gpu.\n\nSigned-off-by: Dave Airlie \u003cairlied@redhat.com\u003e\n" }, { "commit": "8b8bae901ce23addbdcdb54fa1696fb2d049feb5", "tree": "4b95885dc5ba5b6105231289501e83ef429987c2", "parents": [ "a44f99c7efdb88fa41128065c9a9445c19894e34" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Mar 05 13:21:51 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Mar 21 09:38:02 2011 -0700" }, "message": "PCI/ACPI: Report ASPM support to BIOS if not disabled from command line\n\nWe need to distinguish the situation in which ASPM support is\ndisabled from the command line or through .config from the situation\nin which it is disabled, because the hardware or BIOS can\u0027t handle\nit. In the former case we should not report ASPM support to the BIOS\nthrough ACPI _OSC, but in the latter case we should do that.\n\nIntroduce pcie_aspm_support_enabled() that can be used by\nacpi_pci_root_add() to determine whether or not it should report ASPM\nsupport to the BIOS through _OSC.\n\nCc: stable@kernel.org\nReferences: https://bugzilla.kernel.org/show_bug.cgi?id\u003d29722\nReferences: https://bugzilla.kernel.org/show_bug.cgi?id\u003d20232\nReported-and-tested-by: Ortwin Glück \u003codi@odi.ch\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nTested-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "99759619b27662d1290901228d77a293e6e83200", "tree": "e76841fa3f59ebfc3975ff40bbc14363d0fdc5d3", "parents": [ "b061c59c27e0385e53c961d9fbd18c1c078d9823", "65d8defe2e13fbebd74f96d2b5ca9aad435e6648" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 18 10:56:44 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 18 10:56:44 2011 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n PCI: label: remove #include of ACPI header to avoid warnings\n PCI: label: Fix compilation error when CONFIG_ACPI is unset\n PCI: pre-allocate additional resources to devices only after successful allocation of essential resources.\n PCI: introduce reset_resource()\n PCI: data structure agnostic free list function\n PCI: refactor io size calculation code\n PCI: do not create quirk I/O regions below PCIBIOS_MIN_IO for ICH\n PCI hotplug: acpiphp: set current_state to D0 in register_slot\n PCI: Export ACPI _DSM provided firmware instance number and string name to sysfs\n PCI: add more checking to ICH region quirks\n PCI: aer-inject: Override PCIe AER Mask Registers\n PCI: fix tlan build when CONFIG_PCI is not enabled\n PCI: remove quirk for pre-production systems\n PCI: Avoid potential NULL pointer dereference in pci_scan_bridge\n PCI/lpc: irq and pci_ids patch for Intel DH89xxCC DeviceIDs\n PCI: sysfs: Fix failure path for addition of \"vpd\" attribute\n" }, { "commit": "d4894f3ea7375dd9492b5d3d2ecb0b6e4bdb604e", "tree": "a538179ac50d080a4240f7f9da77655d4b40160c", "parents": [ "01c3a3920f9f78866420b2004602944fca45083a" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Wed Mar 09 16:58:21 2011 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Mar 10 01:56:12 2011 -0800" }, "message": "tg3: Add code to verify RODATA checksum of VPD\n\nThis patch adds code to verify the checksum stored in the \"RV\" info\nkeyword of the RODATA VPD section.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nReviewed-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3449248c8731e8474980856d76bbf9bac9b0682f", "tree": "b849554444b0b0fa923ec46f7cf168590d8d6b81", "parents": [ "b99af4b002e4908d1a5cdaf424529bdf1dc69768" ], "author": { "name": "Randy Dunlap", "email": "randy.dunlap@oracle.com", "time": "Mon Feb 14 12:27:50 2011 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Feb 16 11:46:09 2011 -0800" }, "message": "PCI: fix tlan build when CONFIG_PCI is not enabled\n\nWhen CONFIG_PCI is not enabled, tlan.c has a build error:\ndrivers/net/tlan.c:503: error: implicit declaration of function \u0027pci_wake_from_d3\u0027\n\nso add an inline function stub for this function to pci.h when\nPCI is not enabled, similar to other stubbed PCI functions.\n\nSigned-off-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\nAcked-by: Sakari Ailus \u003csakari.ailus@iki.fi\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ab0724ffee24409a7f81afb539b2ac29090bff3e", "tree": "8d0611d921494af2477d517f4f8a331150bf328d", "parents": [ "9a1fe2f27f71dd275caf2be5be2fa59bd2a3f8d4" ], "author": { "name": "Markus Trippelsdorf", "email": "markus@trippelsdorf.de", "time": "Sat Jan 15 00:07:22 2011 +0100" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jan 14 15:23:25 2011 -0800" }, "message": "PCI / ACPI: Fix build issue in pci_root.c for !CONFIG_PCIEPORTBUS\n\nThe compilation of drivers/acpi/pci_root.c fails if\nCONFIG_PCIEPORTBUS is unset. Fix the problem.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "b6e335aeeb114dccb07eaa09e8b62ff9510cf745", "tree": "f4292a579e594b6c0312e9c34467649cb978aea5", "parents": [ "ff29530e651a3449aea6b0ef4c7048db9e22ef27" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Dec 29 13:21:23 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 14 08:55:43 2011 -0800" }, "message": "PCI/PM: Use pm_wakeup_event() directly for reporting wakeup events\n\nAfter recent changes related to wakeup events pm_wakeup_event()\nautomatically checks if the given device is configured to signal wakeup,\nso pci_wakeup_event() may be a static inline function calling\npm_wakeup_event() directly.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "415e12b2379239973feab91850b0dce985c6058a", "tree": "aa79c7a87fd30ac13ae3fd146aad5a44e854c4bc", "parents": [ "6e8af08dfa40b747002207d3ce8e8b43a050d99f" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Fri Jan 07 00:55:09 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 14 08:55:41 2011 -0800" }, "message": "PCI/ACPI: Request _OSC control once for each root bridge (v3)\n\nMove the evaluation of acpi_pci_osc_control_set() (to request control of\nPCI Express native features) into acpi_pci_root_add() to avoid calling\nit many times for the same root complex with the same arguments.\nAdditionally, check if all of the requisite _OSC support bits are set\nbefore calling acpi_pci_osc_control_set() for a given root complex.\n\nReferences: https://bugzilla.kernel.org/show_bug.cgi?id\u003d20232\nReported-by: Ozan Caglayan \u003cozan@pardus.org.tr\u003e\nTested-by: Ozan Caglayan \u003cozan@pardus.org.tr\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1d3c16a818e992c199844954d95c17fd7ce6cbba", "tree": "6f54b4153b8f7e54bdb5a8abc3ceffa7b4eec0e2", "parents": [ "2f671e2dbff6eb5ef4e2600adbec550c13b8fe72" ], "author": { "name": "Jon Mason", "email": "jon.mason@exar.com", "time": "Tue Nov 30 17:43:26 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Dec 23 12:53:09 2010 -0800" }, "message": "PCI: make pci_restore_state return void\n\npci_restore_state only ever returns 0, thus there is no benefit in\nhaving it return any value. Also, a large majority of the callers do\nnot check the return code of pci_restore_state. Make the\npci_restore_state a void return and avoid the overhead.\n\nAcked-by: Mauro Carvalho Chehab \u003cmchehab@redhat.com\u003e\nSigned-off-by: Jon Mason \u003cjon.mason@exar.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bf4d29086972ceaeaf72544d8f64933c2cfdc992", "tree": "301ee83217bc9a19cef5c7569801095b4d6f89b4", "parents": [ "1bcd495be9ed3194f618e8af0446459dc52a1423" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Mon Oct 04 14:22:26 2010 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sun Oct 17 20:03:06 2010 -0700" }, "message": "PCI: Export some PCI PM functionality\n\nIt\u0027s helpful to have some extra PCI power management functions available to\nplatform code, so move the declarations to an exported header.\n\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "42b219322a97ccef347388b233aceaafe3fa517d", "tree": "eb810f27080a9eab5cee2e52413fcc46788d7a15", "parents": [ "5a37f1381f1d8625fa458360c9b5d17f0c5f1dea" ], "author": { "name": "Stephen Hemminger", "email": "shemminger@vyatta.com", "time": "Thu Sep 02 14:28:51 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Oct 15 13:09:49 2010 -0700" }, "message": "PCI: pci_driver make name const\n\nThe name field in pci_driver should be const, it is not\nmodified by PCI subsystem.\n\nSigned-off-by: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "92298e668372f2f6c8a79fb272f13d65161a4876", "tree": "0e7a20da42b5fba01873cba65141f0c947f953ff", "parents": [ "2be1f3a73dd02e38e181cf5abacb3d45a6a2d6b8" ], "author": { "name": "Dave Airlie", "email": "airlied@gmail.com", "time": "Fri Aug 13 10:22:17 2010 +1000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Aug 13 16:19:59 2010 -0700" }, "message": "PCI: provide stub pci_domain_nr function for !CONFIG_PCI configs\n\nAllows the new PCI domain aware DRM code to compile on m68k.\n\nReported-by: Geert Uytterhoeven \u003cgeert@linux-m68k.org\u003e\nSigned-off-by: Dave Airlie \u003cairlied@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "253d2e549818f5a4a52e2db0aba3dacee21e5b38", "tree": "535ff224cb89860809fa5d948e19e1f3342cf7b3", "parents": [ "fcd097f31a6ee207cc0c3da9cccd2a86d4334785" ], "author": { "name": "Jacob Pan", "email": "jacob.jun.pan@linux.intel.com", "time": "Fri Jul 16 10:19:22 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 30 09:29:35 2010 -0700" }, "message": "PCI: disable mmio during bar sizing\n\nIt is a known issue that mmio decoding shall be disabled while doing PCI\nbar sizing. Host bridge and other devices (PCI PIC) shall be excluded for\ncertain platforms. This patch mainly comes from Mathew Willcox\u0027s\npatch in http://kerneltrap.org/mailarchive/linux-kernel/2007/9/13/258969.\n\nA new flag bit \"mmio_alway_on\" is added to pci_dev with the intention that\ndevices with their mmio decoding cannot be disabled during BAR sizing shall\nhave this bit set, preferrablly in their quirks.\n\nWithout this patch, Intel Moorestown platform graphics unit will be\ncorrupted during bar sizing activities.\n\nSigned-off-by: Jacob Pan \u003cjacob.jun.pan@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "58c84eda07560a6b75b03e8d3b26d6eddfc14011", "tree": "0104345d24d5fb79842ffd563ea69fdf2906931d", "parents": [ "2f7989efd4398d92b8adffce2e07dd043a0895fe" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Thu Jul 15 09:41:42 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 16 11:39:48 2010 -0700" }, "message": "PCI: fall back to original BIOS BAR addresses\n\nIf we fail to assign resources to a PCI BAR, this patch makes us try the\noriginal address from BIOS rather than leaving it disabled.\n\nLinux tries to make sure all PCI device BARs are inside the upstream\nPCI host bridge or P2P bridge apertures, reassigning BARs if necessary.\nWindows does similar reassignment.\n\nBefore this patch, if we could not move a BAR into an aperture, we left\nthe resource unassigned, i.e., at address zero. Windows leaves such BARs\nat the original BIOS addresses, and this patch makes Linux do the same.\n\nThis is a bit ugly because we disable the resource long before we try to\nreassign it, so we have to keep track of the BIOS BAR address somewhere.\nFor lack of a better place, I put it in the struct pci_dev.\n\nI think it would be cleaner to attempt the assignment immediately when the\nclaim fails, so we could easily remember the original address. But we\ncurrently claim motherboard resources in the middle, after attempting to\nclaim PCI resources and before assigning new PCI resources, and changing\nthat is a fairly big job.\n\nAddresses https://bugzilla.kernel.org/show_bug.cgi?id\u003d16263\n\nReported-by: Andrew \u003cnitr0@seti.kr.ua\u003e\nTested-by: Andrew \u003cnitr0@seti.kr.ua\u003e\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9a9620db07b27700a4de9e86985735fffb78e2f8", "tree": "14cf3a384ea0d7afeb759cdaf96de7fec7abc9a7", "parents": [ "e620d1e39aa33b43bed96aa7f2ebbc88914aed58", "52707f918cca231f8461d45e78a60014795f20d9" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jun 04 15:39:54 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jun 04 15:39:54 2010 -0700" }, "message": "Merge branch \u0027linux_next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/i7core\n\n* \u0027linux_next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/i7core: (83 commits)\n i7core_edac: Better describe the supported devices\n Add support for Westmere to i7core_edac driver\n i7core_edac: don\u0027t free on success\n i7core_edac: Add support for X5670\n Always call i7core_[ur]dimm_check_mc_ecc_err\n i7core_edac: fix memory leak of i7core_dev\n EDAC: add __init to i7core_xeon_pci_fixup\n i7core_edac: Fix wrong device id for channel 1 devices\n i7core: add support for Lynnfield alternate address\n i7core_edac: Add initial support for Lynnfield\n i7core_edac: do not export static functions\n edac: fix i7core build\n edac: i7core_edac produces undefined behaviour on 32bit\n i7core_edac: Use a more generic approach for probing PCI devices\n i7core_edac: PCI device is called NONCORE, instead of NOCORE\n i7core_edac: Fix ringbuffer maxsize\n i7core_edac: First store, then increment\n i7core_edac: Better parse \"any\" addrmask\n i7core_edac: Use a lockless ringbuffer\n edac: Create an unique instance for each kobj\n ...\n" }, { "commit": "9a90e09854a3c7cc603ab8fc9163f77bb1f66cfa", "tree": "c8c5f767dd2351c9db440f003cc14401583bafd3", "parents": [ "d372e7fe4698bde3a00b718f7901a0025dda47ef", "d3b383338f105f50724c10a7d81b04a3930e886b" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 28 14:42:18 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 28 14:42:18 2010 -0700" }, "message": "Merge branch \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6\n\n* \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: (27 commits)\n ACPI: Don\u0027t let acpi_pad needlessly mark TSC unstable\n drivers/acpi/sleep.h: Checkpatch cleanup\n ACPI: Minor cleanup eliminating redundant PMTIMER_TICKS to NS conversion\n ACPI: delete unused c-state promotion/demotion data strucutures\n ACPI: video: fix acpi_backlight\u003dvideo\n ACPI: EC: Use kmemdup\n drivers/acpi: use kasprintf\n ACPI, APEI, EINJ injection parameters support\n Add x64 support to debugfs\n ACPI, APEI, Use ERST for persistent storage of MCE\n ACPI, APEI, Error Record Serialization Table (ERST) support\n ACPI, APEI, Generic Hardware Error Source memory error support\n ACPI, APEI, UEFI Common Platform Error Record (CPER) header\n Unified UUID/GUID definition\n ACPI Hardware Error Device (PNP0C33) support\n ACPI, APEI, PCIE AER, use general HEST table parsing in AER firmware_first setup\n ACPI, APEI, Document for APEI\n ACPI, APEI, EINJ support\n ACPI, APEI, HEST table parsing\n ACPI, APEI, APEI supporting infrastructure\n ...\n" }, { "commit": "affb72c3a8984ba55e055b0a0228c3ea1a056758", "tree": "a6d4c9051110c03f9222bde9c3dcea7822f8570c", "parents": [ "ea8c071cad789b1919355fc7a67182a5c9994e6b" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Tue May 18 14:35:16 2010 +0800" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed May 19 22:40:14 2010 -0400" }, "message": "ACPI, APEI, PCIE AER, use general HEST table parsing in AER firmware_first setup\n\nNow, a dedicated HEST tabling parsing code is used for PCIE AER\nfirmware_first setup. It is rebased on general HEST tabling parsing\ncode of APEI. The firmware_first setup code is moved from PCI core to\nAER driver too, because it is only AER related.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andi Kleen \u003cak@linux.intel.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "d1fd4fb69eeeb7db0693df58b9116db498d5bfe1", "tree": "e3870ec2d0c20804c2865a67c606acf8a736c01c", "parents": [ "5707b24a50b40582226618c56692af932db9fe02" ], "author": { "name": "Mauro Carvalho Chehab", "email": "mchehab@redhat.com", "time": "Fri Jul 10 18:39:53 2009 -0300" }, "committer": { "name": "Mauro Carvalho Chehab", "email": "mchehab@redhat.com", "time": "Mon May 10 11:44:51 2010 -0300" }, "message": "i7core_edac: Add a code to probe Xeon 55xx bus\n\nThis code changes the detection procedure of i7core_edac. Instead of\ndirectly probing for MC registers, it probes for another register found\non Nehalem. If found, it tries to pick the first MC PCI BUS. This should\nwork fine with Xeon 35xx, but, on Xeon 55xx, this is at bus 254 and 255\nthat are not properly detected by the non-legacy PCI methods.\n\nThe new detection code scans specifically at buses 254 and 255 for the\nXeon 55xx devices.\n\nThis code has not tested yet. After working, a change at the code will\nbe needed, since the i7core is not yet ready for working with 2 sets of\nMC.\n\nSigned-off-by: Mauro Carvalho Chehab \u003cmchehab@redhat.com\u003e\n" }, { "commit": "dda565492776b7dff5f8507298d868745e734aab", "tree": "0e93c6d3cad304b860fa8b8715a3dbd03832b2ae", "parents": [ "680a7524622356f5476e8fad2fe32b2b68b432c0" ], "author": { "name": "Yinghai", "email": "yinghai.lu@oracle.com", "time": "Fri Apr 09 01:07:55 2010 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Apr 09 17:00:00 2010 +0100" }, "message": "intel-iommu: use physfn to search drhd for VF\n\nWhen virtfn is used, we should use physfn to find correct drhd\n\n-v2: add pci_physfn() Suggested by Roland Dreier \u003crdreier@cisco.com\u003e\n do can remove ifdef in dmar.c\n-v3: Chris pointed out we need that for dma_find_matched_atsr_unit too\n also change dmar_pci_device_match() static\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nAcked-by: Roland Dreier \u003crdreier@cisco.com\u003e\nAcked-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "5f3cd1e0bb452c31a306a3e764514ea2eaf7d2e0", "tree": "2fe245e004491e195127fe2327d48775b45ed4e1", "parents": [ "6fee48cd330c68332f9712bc968d934a1a84a32a" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Wed Mar 10 15:23:41 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:42 2010 -0800" }, "message": "dma-mapping: pci: move pci_set_dma_mask and pci_set_consistent_dma_mask to pci-dma-compat.h\n\nWe can use pci-dma-compat.h to implement pci_set_dma_mask and\npci_set_consistent_dma_mask as we do with the other PCI DMA API.\n\nWe can remove HAVE_ARCH_PCI_SET_DMA_MASK too.\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nCc: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "f41b177157718abe9a93868bb76e47d4a6f3681d", "tree": "555d8608a2fe320483c8761dcb2e80cc37b5e822", "parents": [ "c7e67ac1f329fa28b6a411335787c786de618cba" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Wed Mar 10 15:23:30 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:42 2010 -0800" }, "message": "pci-dma: add linux/pci-dma.h to linux/pci.h\n\nAll the architectures properly set NEED_DMA_MAP_STATE now so we can safely\nadd linux/pci-dma.h to linux/pci.h and remove the linux/pci-dma.h\ninclusion in arch\u0027s asm/pci.h\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "322aafa6645a48c3b7837ca7385f126ab78127fd", "tree": "50f6665aedcf051cecd571183df81ba7f248014b", "parents": [ "dd04265b028c00c365a78f9ff78a05e217f98656", "c7bbf52aa4fa332b84c4f2bb33e69561ee6870b4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Mar 07 15:59:39 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Mar 07 15:59:39 2010 -0800" }, "message": "Merge branch \u0027x86-mrst-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-mrst-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (30 commits)\n x86, mrst: Fix whitespace breakage in apb_timer.c\n x86, mrst: Fix APB timer per cpu clockevent\n x86, mrst: Remove X86_MRST dependency on PCI_IOAPIC\n x86, olpc: Use pci subarch init for OLPC\n x86, pci: Add arch_init to x86_init abstraction\n x86, mrst: Add Kconfig dependencies for Moorestown\n x86, pci: Exclude Moorestown PCI code if CONFIG_X86_MRST\u003dn\n x86, numaq: Make CONFIG_X86_NUMAQ depend on CONFIG_PCI\n x86, pci: Add sanity check for PCI fixed bar probing\n x86, legacy_irq: Remove duplicate vector assigment\n x86, legacy_irq: Remove left over nr_legacy_irqs\n x86, mrst: Platform clock setup code\n x86, apbt: Moorestown APB system timer driver\n x86, mrst: Add vrtc platform data setup code\n x86, mrst: Add platform timer info parsing code\n x86, mrst: Fill in PCI functions in x86_init layer\n x86, mrst: Add dummy legacy pic to platform setup\n x86/PCI: Moorestown PCI support\n x86, ioapic: Add dummy ioapic functions\n x86, ioapic: Early enable ioapic for timer irq\n ...\n\nFixed up semantic conflict of new clocksources due to commit\n17622339af25 (\"clocksource: add argument to resume callback\").\n" }, { "commit": "47871889c601d8199c51a4086f77eebd77c29b0b", "tree": "40cdcac3bff0ee40cc33dcca61d0577cdf965f77", "parents": [ "c16cc0b464b8876cfd57ce1c1dbcb6f9a6a0bce3", "30ff056c42c665b9ea535d8515890857ae382540" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 19:23:06 2010 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 19:23:06 2010 -0800" }, "message": "Merge branch \u0027master\u0027 of /home/davem/src/GIT/linux-2.6/\n\nConflicts:\n\tdrivers/firmware/iscsi_ibft.c\n" }, { "commit": "c7e15899d07c9813c1aa96b21699d2d9c8314c4b", "tree": "16e9b4dceddf1b4d1dad05588d700c70cf8fcb88", "parents": [ "f6a0b5cd34d6e922cc7258c5429fb0f17508ceb6", "78c06176466cbd1b3f0f67709d3023c40dbebcbd" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Feb 28 10:59:18 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Feb 28 10:59:18 2010 -0800" }, "message": "Merge branch \u0027x86-pci-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-pci-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n x86: Enable NMI on all cpus on UV\n vgaarb: Add user selectability of the number of GPUS in a system\n vgaarb: Fix VGA arbiter to accept PCI domains other than 0\n x86, uv: Update UV arch to target Legacy VGA I/O correctly.\n pci: Update pci_set_vga_state() to call arch functions\n" }, { "commit": "4067a8541d397e9d6b443dd2ce0ecb78bfd991db", "tree": "49690419b218020b8a0e9381db2f9cc90b658cd0", "parents": [ "e1d5bdabb94da89bdb3c3f2ee105cf61fca88ec8" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Feb 26 14:04:43 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 00:43:33 2010 -0800" }, "message": "pci: Add helper to search for VPD keywords\n\nThis patch adds the pci_vpd_find_info_keyword() helper function to\nfind information field keywords within read-only and read-write large\nresource data type sections.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "e1d5bdabb94da89bdb3c3f2ee105cf61fca88ec8", "tree": "bc5b86b19bc49ace2df10ed9e7ba7d1ca2b74d33", "parents": [ "b55ac1b22690d2e5b02a61cf6d69c2d66969c79d" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Feb 26 14:04:42 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 00:43:32 2010 -0800" }, "message": "pci: Add VPD information field helper functions\n\nThis patch adds a preprocessor constant to describe the PCI VPD\ninformation field header size and an inline function to extract the\nsize of the information field itself.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b55ac1b22690d2e5b02a61cf6d69c2d66969c79d", "tree": "d336b38719dba482e2734f2091f5a60dfcb134b4", "parents": [ "7ad506fa1adc2da3d394c562f09b8e1b3026c402" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Feb 26 14:04:41 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 00:43:32 2010 -0800" }, "message": "pci: Add helper to find a VPD resource data type\n\nThis patch adds the pci_vpd_find_tag() helper function to find VPD\nresource data types in a buffer.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7ad506fa1adc2da3d394c562f09b8e1b3026c402", "tree": "a4ace2d9918a000d7983eb0770f2346ed7e323aa", "parents": [ "a2ce766238f72ff7337606c0bc96803c30c9e05c" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Feb 26 14:04:40 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 00:43:31 2010 -0800" }, "message": "pci: Add large and small resource data type code\n\nThis patch introduces more VPD preprocessor definitions to identify some\nsmall and large resource data type item names. The patch then continues\nto correct how the tg3 and bnx2 drivers search for the \"read-only data\"\nlarge resource data type.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a2ce766238f72ff7337606c0bc96803c30c9e05c", "tree": "5968e585402263556481075a49599dc697aeab49", "parents": [ "2ea186ae533c7b4f4c56811b69d3e40a6209a9c0" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Feb 26 14:04:39 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 00:43:30 2010 -0800" }, "message": "pci: Add PCI LRDT tag size and section size\n\nThis patch adds a preprocessor constant to describe the PCI VPD large\nresource data type tag size and an inline function to extract the large\nresource section size from the large resource data type tag.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "2fe2abf896c1e7a0ee65faaf3ef0ce654848abbd", "tree": "f066d5c94bbed5ca3556b4d2f0c4b3a9795b6eff", "parents": [ "89a74ecccd1f78e51faf6287e5c0e93a92ac096e" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Feb 23 10:24:36 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 23 09:43:37 2010 -0800" }, "message": "PCI: augment bus resource table with a list\n\nPreviously we used a table of size PCI_BUS_NUM_RESOURCES (16) for resources\nforwarded to a bus by its upstream bridge. We\u0027ve increased this size\nseveral times when the table overflowed.\n\nBut there\u0027s no good limit on the number of resources because host bridges\nand subtractive decode bridges can forward any number of ranges to their\nsecondary buses.\n\nThis patch reduces the table to only PCI_BRIDGE_RESOURCE_NUM (4) entries,\nwhich corresponds to the number of windows a PCI-to-PCI (3) or CardBus (4)\nbridge can positively decode. Any additional resources, e.g., PCI host\nbridge windows or subtractively-decoded regions, are kept in a list.\n\nI\u0027d prefer a single list rather than this split table/list approach, but\nthat requires simultaneous changes to every architecture. This approach\nonly requires immediate changes where we set up (a) host bridges with more\nthan four windows and (b) subtractive-decode P2P bridges, and we can\nincrementally change other architectures to use the list.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "89a74ecccd1f78e51faf6287e5c0e93a92ac096e", "tree": "6d167d73fb2cf5bb457b0b19145fcbf81cf441ef", "parents": [ "2adf75160b10bf3f09ed7d3d04e937f923fc557e" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Feb 23 10:24:31 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 23 09:43:31 2010 -0800" }, "message": "PCI: add pci_bus_for_each_resource(), remove direct bus-\u003eresource[] refs\n\nNo functional change; this converts loops that iterate from 0 to\nPCI_BUS_NUM_RESOURCES through pci_bus resource[] table to use the\npci_bus_for_each_resource() iterator instead.\n\nThis doesn\u0027t change the way resources are stored; it merely removes\ndependencies on the fact that they\u0027re in a table.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6cbf82148ff286ec22a55be6836c3a5bffc489c1", "tree": "77b1b0097f9c2389d56734ec4c022611aa1bd9db", "parents": [ "552be54cc4232dc5acc49ccb372129d6f1b6923f" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:44:58 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:21:19 2010 -0800" }, "message": "PCI PM: Run-time callbacks for PCI bus type\n\nIntroduce run-time PM callbacks for the PCI bus type. Make the new\ncallbacks work in analogy with the existing system sleep PM\ncallbacks, so that the drivers already converted to struct dev_pm_ops\ncan use their suspend and resume routines for run-time PM without\nmodifications.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b67ea76172d4b1922c4b3c46c8ea8e9fec1ff38c", "tree": "c2f51811376060b3b59ac43243a182b94a48be9b", "parents": [ "3f0be67188c60ebf1b5d00354b44b4b24f5af313" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:44:09 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:21:02 2010 -0800" }, "message": "PCI / ACPI / PM: Platform support for PCI PME wake-up\n\nAlthough the majority of PCI devices can generate PMEs that in\nprinciple may be used to wake up devices suspended at run time,\nplatform support is generally necessary to convert PMEs into wake-up\nevents that can be delivered to the kernel. If ACPI is used for this\npurpose, PME signals generated by a PCI device will trigger the ACPI\nGPE associated with the device to generate an ACPI wake-up event that\nwe can set up a handler for, provided that everything is configured\ncorrectly.\n\nUnfortunately, the subset of PCI devices that have GPEs associated\nwith them is quite limited. The devices without dedicated GPEs have\nto rely on the GPEs associated with other devices (in the majority of\ncases their upstream bridges and, possibly, the root bridge) to\ngenerate ACPI wake-up events in response to PME signals from them.\n\nAdd ACPI platform support for PCI PME wake-up:\no Add a framework making is possible to use ACPI system notify\n handlers for run-time PM.\no Add new PCI platform callback -\u003erun_wake() to struct\n pci_platform_pm_ops allowing us to enable/disable the platform to\n generate wake-up events for given device. Implemet this callback\n for the ACPI platform.\no Define ACPI wake-up handlers for PCI devices and PCI root buses and\n make the PCI-ACPI binding code register wake-up notifiers for all\n PCI devices present in the ACPI tables.\no Add function pci_dev_run_wake() which can be used by PCI drivers to\n check if given device is capable of generating wake-up events at\n run time.\n\nDeveloped in cooperation with Matthew Garrett \u003cmjg@redhat.com\u003e.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c7f486567c1d0acd2e4166c47069835b9f75e77b", "tree": "5552890ac80fc53f61dd9c53a6211610375efa1f", "parents": [ "58ff463396ad00828e922d50998787e97fd32512" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:39:08 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:20:31 2010 -0800" }, "message": "PCI PM: PCIe PME root port service driver\n\nPCIe native PME detection mechanism is based on interrupts generated\nby root ports or event collectors every time a PCIe device sends a\nPME message upstream.\n\nOnce a PME message has been sent by an endpoint device and received\nby its root port (or event collector in the case of root complex\nintegrated endpoints), the Requester ID from the message header is\nregistered in the root port\u0027s Root Status register. At the same\ntime, the PME Status bit of the Root Status register is set to\nindicate that there\u0027s a PME to handle. If PCIe PME interrupt is\nenabled for the root port, it generates an interrupt once the PME\nStatus has been set. After receiving the interrupt, the kernel can\nidentify the PCIe device that generated the PME using the Requester\nID from the root port\u0027s Root Status register. [For details, see PCI\nExpress Base Specification, Rev. 2.0.]\n\nImplement a driver for the PCIe PME root port service working in\naccordance with the above description.\n\nBased on a patch from Shaohua Li \u003cshaohua.li@intel.com\u003e.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6d3be84aab461815978d970aa45f5bc9e52dd772", "tree": "b81755ad2a384c225c2b707591ef3df049b0653e", "parents": [ "9958610552c0bd7558b41cb8addbd865587f142a" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Feb 09 12:21:27 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:17:26 2010 -0800" }, "message": "PCI: mark is_pcie obsolete\n\nThe \"is_pcie\" field in struct pci_dev is no longer needed because\nstruct pci_dev has PCIe capability offset in \"pcie_cap\" field and\n(pcie_cap !\u003d 0) means the device is PCIe capable. This patch marks\n\"is_pcie\" fields obsolete.\n\nCurrent users of \"is_pcie\" field are:\n\n- drivers/ssb/scan.c\n- drivers/net/wireless/ath/ath9k/pci.c\n- drivers/net/wireless/ath/ath5k/attach.c\n- drivers/net/wireless/ath/ath5k/reset.c\n- drivers/acpi/hest.c\n- drivers/pci/pcie/pme/pcie_pme.c\n\nWill post patches for each to use pci_is_pcie() as a follow-up.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6841ec681a88b66651e4563040b9c7a7ad25d7b5", "tree": "412ddf4db54257d64136930ccd921e674fffd1f9", "parents": [ "977d17bb1749517b353874ccdc9b85abc7a58c2a" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Fri Jan 22 01:02:25 2010 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:17:23 2010 -0800" }, "message": "PCI: introduce pci_assign_unassigned_bridge_resources\n\nFor use by pciehp.\n\npci_setup_bridge() will not check enabled for the slot bridge, otherwise\nupdate res is not updated to bridge BAR. That is, bridge is already\nenabled for port service.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "41a68a748bbc61f5bcea999e33ba72926dfbe6f7", "tree": "d6b100c49d847270c235a9788b0bebb9372bcec9", "parents": [ "7c9342b8dd1a32386fc32bffb9eedebbfe264763" ], "author": { "name": "Tilman Schmidt", "email": "tilman@imap.cc", "time": "Mon Jan 18 17:24:10 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:17:01 2010 -0800" }, "message": "PCI: push deprecated pci_find_device() function to last user\n\nThe ISDN4Linux HiSax driver family contains the last remaining users\nof the deprecated pci_find_device() function. This patch creates a\nprivate copy of that function in HiSax, and removes the now unused\nglobal function together with its controlling configuration option,\nCONFIG_PCI_LEGACY.\n\nSigned-off-by: Tilman Schmidt \u003ctilman@imap.cc\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3b7a17fcdae532d29dffab9d564a28be08960988", "tree": "64ac96e997751e34fcd237485fac9b868d1e0614", "parents": [ "b26b2d494b659f988b4d75eb394dfa0ddac415c9" ], "author": { "name": "Dominik Brodowski", "email": "linux@dominikbrodowski.net", "time": "Fri Jan 01 17:40:50 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:16:57 2010 -0800" }, "message": "resource/PCI: mark struct resource as const\n\nNow that we return the new resource start position, there is no\nneed to update \"struct resource\" inside the align function.\nTherefore, mark the struct resource as const.\n\nCc: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nCc: Yinghai Lu \u003cyhlu.kernel@gmail.com\u003e\nSigned-off-by: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b26b2d494b659f988b4d75eb394dfa0ddac415c9", "tree": "d262f333e529a21017dc072e604a626b38520515", "parents": [ "93da6202264ce1256b04db8008a43882ae62d060" ], "author": { "name": "Dominik Brodowski", "email": "linux@dominikbrodowski.net", "time": "Fri Jan 01 17:40:49 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:16:56 2010 -0800" }, "message": "resource/PCI: align functions now return start of resource\n\nAs suggested by Linus, align functions should return the start\nof a resource, not void. An update of \"res-\u003estart\" is no longer\nnecessary.\n\nCc: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nCc: Yinghai Lu \u003cyhlu.kernel@gmail.com\u003e\nSigned-off-by: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "93177a748ba0d4f3d3e51c8e6c785773bf6a70df", "tree": "1207e03e87d1b68a54ff159c9a8a2f279ea0b6a1", "parents": [ "3804259475314a50e4d7a8a974a22fddb6ac7dd7" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Jan 02 22:57:24 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:21 2010 -0800" }, "message": "PCI: Clean up build for CONFIG_PCI_QUIRKS unset\n\nCurrently, drivers/pci/quirks.c is built unconditionally, but if\nCONFIG_PCI_QUIRKS is unset, the only things actually built in this\nfile are definitions of global variables and empty functions (due to\nthe #ifdef CONFIG_PCI_QUIRKS embracing all of the code inside the\nfile). This is not particularly nice and if someone overlooks\nthe #ifdef CONFIG_PCI_QUIRKS, build errors are introduced.\n\nTo clean that up, move the definitions of the global variables in\nquirks.c that are always built to pci.c, move the definitions of\nthe empty functions (compiled when CONFIG_PCI_QUIRKS is unset) to\nheaders (additionally make these functions static inline) and modify\ndrivers/pci/Makefile so that quirks.c is only built if\nCONFIG_PCI_QUIRKS is set.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9dfd97fe12f79ec8b68feb63912a4ef2f31f571a", "tree": "845515c430a3cc48b1d88496d3b8f4d13bd7efb2", "parents": [ "45b4cdd57ef0e57555b2ab61b584784819b39365" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:35 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:19 2010 -0800" }, "message": "PCI: Add support for reporting PCIe 3.0 speeds\n\nAdd the 8.0 GT/s speed.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "45b4cdd57ef0e57555b2ab61b584784819b39365", "tree": "1e08008e0cdc57252022b5ad1a0e3029c7e96f99", "parents": [ "9be60ca0497a2563662fde4c9007841c3b79a742" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:34 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:19 2010 -0800" }, "message": "PCI: Add support for AGP in cur/max bus speed\n\nTake advantage of some gaps in the table to fit in support for AGP speeds.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3749c51ac6c1560aa1cb1520066bed84c6f8152a", "tree": "3cbfb6a6d2df821e3e80ccce29ede8011b94246e", "parents": [ "536c8cb49eccd4f753b4782e7e975ef87359cb44" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:32 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:17 2010 -0800" }, "message": "PCI: Make current and maximum bus speeds part of the PCI core\n\nMove the max_bus_speed and cur_bus_speed into the pci_bus. Expose the\nvalues through the PCI slot driver instead of the hotplug slot driver.\nUpdate all the hotplug drivers to use the pci_bus instead of their own\ndata structures.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "536c8cb49eccd4f753b4782e7e975ef87359cb44", "tree": "1cc2a32b17e4eb1fc4c9b64dc4895892a2fd3d41", "parents": [ "f07852d6442c46c50b59c7e2acc8a1b291f9ab6d" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:31 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:17 2010 -0800" }, "message": "PCI: Unify pcie_link_speed and pci_bus_speed\n\nThese enums must not overlap anyway, since we only have a single\npci_bus_speed_strings array. Use a single enum, and move it to\npci.h. Add \u0027SPEED\u0027 to the pcie names to make it clear what they are.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "cf4c43dd439b90a1a876b3f836ebe745abb9a269", "tree": "59d7a278d9d5cb6c9927819fa75231e284b29556", "parents": [ "724e6d3fe8003c3f60bf404bf22e4e331327c596" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jul 15 13:13:00 2009 -0700" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@zytor.com", "time": "Fri Feb 19 16:12:26 2010 -0800" }, "message": "PCI: Add pci_bus_find_ext_capability\n\nFor use by code that needs to walk extended capability lists before\npci_dev structures are set up.\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nLKML-Reference: \u003c43F901BD926A4E43B106BF17856F07559FB80CFD@orsmsx508.amr.corp.intel.com\u003e\nSigned-off-by: Jacob Pan \u003cjacob.jun.pan@intel.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@zytor.com\u003e\n" }, { "commit": "2bb4646fce8d09916b351d1a62f98db7cec6fc41", "tree": "c1f0d002e69868606eca9d1b919835f422892063", "parents": [ "6836b9bdd98e3b500cd49512484df68f46e14659", "b0483e78e5c4c9871fc5541875b3bc006846d46b" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Feb 16 22:09:29 2010 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Feb 16 22:09:29 2010 -0800" }, "message": "Merge branch \u0027master\u0027 of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6\n" }, { "commit": "fb8a0d9d1bfd1e4355f307e86a6da7209eefd5f3", "tree": "99f23a4bc7c51343619f63970e5d017d75b5a66f", "parents": [ "81d54ec8479a2c695760da81f05b5a9fb2dbe40a" ], "author": { "name": "Williams, Mitch A", "email": "mitch.a.williams@intel.com", "time": "Wed Feb 10 01:43:04 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Feb 12 16:56:07 2010 -0800" }, "message": "pci: Add SR-IOV convenience functions and macros\n\nAdd and export pci_num_vf to allow other subsystems to determine how many\nvirtual function devices are associated with an SR-IOV physical function\ndevice.\nAdd macros dev_is_pci, dev_is_ps, and dev_num_vf to make it easier for\nnon-PCI specific code to determine SR-IOV capabilities.\n\nSigned-off-by: Mitch Williams \u003cmitch.a.williams@intel.com\u003e\nSigned-off-by: Jeff Kirsher \u003cjeffrey.t.kirsher@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "95a8b6efc5d07103583f706c8a5889437d537939", "tree": "a8e9161eea03b0eb21e838826c547771158ecdce", "parents": [ "499a2673713c85734a54c37dd90b4b729de399c4" ], "author": { "name": "Mike Travis", "email": "travis@sgi.com", "time": "Tue Feb 02 14:38:13 2010 -0800" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@zytor.com", "time": "Fri Feb 05 14:05:41 2010 -0800" }, "message": "pci: Update pci_set_vga_state() to call arch functions\n\nUpdate pci_set_vga_state to call arch dependent functions to enable Legacy\nVGA I/O transactions to be redirected to correct target.\n\n[akpm@linux-foundation.org: make pci_register_set_vga_state() __init]\nSigned-off-by: Mike Travis \u003ctravis@sgi.com\u003e\nLKML-Reference: \u003c201002022238.o12McE1J018723@imap1.linux-foundation.org\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Robin Holt \u003cholt@sgi.com\u003e\nCc: Jack Steiner \u003csteiner@sgi.com\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCc: David Airlie \u003cairlied@linux.ie\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@zytor.com\u003e\n" }, { "commit": "bb209c8287d2d55ec4a67e3933346e0a3ee0da76", "tree": "2e444f273e631fa4dded4ee13ac779565e5efb43", "parents": [ "b04da8bfdfbbd79544cab2fadfdc12e87eb01600" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Tue Jan 26 17:10:03 2010 +0000" }, "committer": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Fri Jan 29 16:51:10 2010 +1100" }, "message": "powerpc/pci: Add calls to set_pcie_port_type() and set_pcie_hotplug_bridge()\n\nWe are missing these when building the pci_dev from scratch off\nthe Open Firmware device-tree\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1ae861e652b5457e7fa98ccbc55abea1e207916e", "tree": "d0326aab2746a779f3ab140ec9fdea2508f2e99b", "parents": [ "6be954d1f91b81ca85c74792b13654069278c577" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Thu Dec 31 12:15:54 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 15:41:47 2010 -0800" }, "message": "PCI/PM: Use per-device D3 delays\n\nIt turns out that some PCI devices require extra delays when changing\npower state from D3 to D0 (and the other way around). Although this\nis against the PCI specification, we can handle it quite easily by\nallowing drivers to define arbitrary D3 delays for devices known to\nrequire extra time for switching power states.\n\nIntroduce additional field d3_delay in struct pci_dev and use it to\nstore the value of the device\u0027s D0-\u003eD3 delay, in miliseconds. Make\nthe PCI PM core code use the per-device d3_delay unless\npci_pm_d3_delay is greater (in which case the latter is used).\n[This also allows the driver to specify d3_delay shorter than the\n 10 ms required by the PCI standard if the device is known to be able\n to handle that.]\n\nMake the sky2 driver set d3_delay to 150 for devices handled by it.\n\nFixes http://bugzilla.kernel.org/show_bug.cgi?id\u003d14730 which is a\nlisted regression from 2.6.30.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2d1c861871d767153538a77c498752b36d4bb4b8", "tree": "2ed80140487cd68e539c55876ba361199a4b92c1", "parents": [ "7e8af37a9a71b479f58d2fd5f0ddaa6780c51f11" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Wed Dec 09 17:52:13 2009 +1100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 18:55:51 2009 -0800" }, "message": "PCI/cardbus: Add a fixup hook and fix powerpc\n\nThe cardbus code creates PCI devices without ever going through the\nnecessary fixup bits and pieces that normal PCI devices go through.\n\nThere\u0027s in fact a commented out call to pcibios_fixup_bus() in there,\nit\u0027s commented because ... it doesn\u0027t work.\n\nI could make pcibios_fixup_bus() do the right thing on powerpc easily\nbut I felt it cleaner instead to provide a specific hook pci_fixup_cardbus\nfor which a weak empty implementation is provided by the PCI core.\n\nThis fixes cardbus on powerbooks and probably all other PowerPC\nplatforms which was broken completely for ever on some platforms and\nsince 2.6.31 on others such as PowerBooks when we made the DMA ops\nmandatory (since those are setup by the fixups).\n\nAcked-by: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "491424c0f46c282a854b88830212bdb0763e93dc", "tree": "54e3272da9bdc638c6efcb43fa94f96454106d0a", "parents": [ "5185fb069972b653dd7177292e7510ff99d9e8aa" ], "author": { "name": "David Howells", "email": "dhowells@redhat.com", "time": "Mon Dec 14 14:13:44 2009 +0000" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Dec 14 10:11:34 2009 -0800" }, "message": "PCI: Global variable decls must match the defs in section attributes\n\nGlobal variable declarations must match the definitions in section attributes\nas the compiler is at liberty to vary the method it uses to access a variable,\ndepending on the section it is in.\n\nWhen building the FRV arch, I now see:\n\n drivers/built-in.o: In function `pci_apply_final_quirks\u0027:\n drivers/pci/quirks.c:2606: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size\u0027 defined in .devinit.data section in drivers/built-in.o\n drivers/pci/quirks.c:2623: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size\u0027 defined in .devinit.data section in drivers/built-in.o\n drivers/pci/quirks.c:2630: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size\u0027 defined in .devinit.data section in drivers/built-in.o\n\nbecause the declaration of pci_dfl_cache_line_size in linux/pci.h does not\nmatch the definition in drivers/pci/pci.c.\n\nSigned-off-by: David Howells \u003cdhowells@redhat.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "5d990b627537e59a3a2f039ff588a4750e9c1a6a", "tree": "8c0e723c3f9146da52b30c087a80fc417df2b41b", "parents": [ "b26a34aa4792b3db2500b8a98cb7702765c1a92e" ], "author": { "name": "Chris Wright", "email": "chrisw@sous-sol.org", "time": "Fri Dec 04 12:15:21 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:19:24 2009 -0800" }, "message": "PCI: add pci_request_acs\n\nCommit ae21ee65e8bc228416bbcc8a1da01c56a847a60c \"PCI: acs p2p upsteram\nforwarding enabling\" doesn\u0027t actually enable ACS.\n\nAdd a function to pci core to allow an IOMMU to request that ACS\nbe enabled. The existing mechanism of using iommu_found() in the pci\ncore to know when ACS should be enabled doesn\u0027t actually work due to\ninitialization order; iommu has only been detected not initialized.\n\nHave Intel and AMD IOMMUs request ACS, and Xen does as well during early\ninit of dom0.\n\nCc: Allen Kay \u003callen.m.kay@intel.com\u003e\nCc: David Woodhouse \u003cdwmw2@infradead.org\u003e\nCc: Jeremy Fitzhardinge \u003cjeremy@goop.org\u003e\nCc: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7eb776c42e75d17bd8107a1359068d8c742639d1", "tree": "eddee4ecffebc2ac54c1eee548802367c5f17c68", "parents": [ "1518c17ab736303098843bd306a0fc4f8f5faa42" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:35:22 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:16 2009 -0800" }, "message": "PCI: introduce pci_is_pcie()\n\nIntroduce pci_is_pcie() which returns true if the specified PCI device\nis PCI Express capable, false otherwise.\n\nThe purpose of pci_is_pcie() is removing \u0027is_pcie\u0027 flag in the struct\npci_dev, which is not needed because we can check it using \u0027pcie_cap\u0027\nfield. To remove \u0027is_pcie\u0027, we need to update user of \u0027is_pcie\u0027 to use\npci_is_pcie() instead first.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d7b7e60526d54da4c94afe5f137714cee7d05c41", "tree": "e8cdf8d2e60c274848e860501234ebb958ab0ae9", "parents": [ "8c8def26bfaa704db67d515da3eb92cf26067548" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:29:54 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:11 2009 -0800" }, "message": "PCI: introduce pci_pcie_cap()\n\nIntroduce pci_pcie_cap() API that returns saved PCIe capability offset\n(currently it is saved in \u0027pcie_cap\u0027 field in the struct PCI dev).\nUsing pci_pcie_cap() instead of pci_find_capability() avoids\nunnecessary search in PCI configuration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0efea0006335a2425b1a12a2ad35efad626fe353", "tree": "d139b06a32665ec1227c06f1c0a14b21e3c0d654", "parents": [ "1e5ad9679016275d422e36b12a98b0927d76f556" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Thu Nov 05 12:05:11 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 06 13:59:02 2009 -0800" }, "message": "PCI: cache PCIe capability offset\n\nThere are a lot of codes that searches PCI express capability offset\nin the PCI configuration space using pci_find_capability(). Caching it\nin the struct pci_dev will reduce unncecessary search. This patch adds\nan additional \u0027pcie_cap\u0027 fields into struct pci_dev, which is\ninitialized at pci device scan time (in set_pcie_port_type()).\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3c299dc22635e500214707aa28be119ff2b3901c", "tree": "6d9cb3710c674639041ead3247e179fa82dcaf35", "parents": [ "bc577d2bb98cc44371287fce3e892d26ad4050a8" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Oct 12 13:14:00 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:36 2009 -0800" }, "message": "PCI: add pci_get_domain_bus_and_slot function\n\nAdded the pci_get_domain_and_slot_function which is analogous to\npci_get_bus_and_slot. It returns a pci_dev given a domain (segment) number,\nbus number, and devnr. Like pci_get_bus_and_slot,\npci_get_domain_bus_and_slot holds a reference to the returned pci_dev.\n\nConverted pci_get_bus_and_slot to a wrapper that calls\npci_get_domain_bus_and_slot with the domain hard-coded to 0.\n\nThis routine was patterned off code suggested by Bjorn Helgaas.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0584396157ad2d008e2cc76b4ed6254151183a25", "tree": "8860a033938b1a01cccf9a203208f741758724ac", "parents": [ "8792e11f1c54bcba34412f03959e70ee217f2231" ], "author": { "name": "Matt Domsch", "email": "Matt_Domsch@dell.com", "time": "Mon Nov 02 11:51:24 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:25 2009 -0800" }, "message": "PCI: PCIe AER: honor ACPI HEST FIRMWARE FIRST mode\n\nFeedback from Hidetoshi Seto and Kenji Kaneshige incorporated. This\ncorrectly handles PCI-X bridges, PCIe root ports and endpoints, and\nprints debug messages when invalid/reserved types are found in the\nHEST. PCI devices not in domain/segment 0 are not represented in\nHEST, thus will be ignored.\n\nToday, the PCIe Advanced Error Reporting (AER) driver attaches itself\nto every PCIe root port for which BIOS reports it should, via ACPI\n_OSC.\n\nHowever, _OSC alone is insufficient for newer BIOSes. Part of ACPI\n4.0 is the new APEI (ACPI Platform Error Interfaces) which is a way\nfor OS and BIOS to handshake over which errors for which components\neach will handle. One table in ACPI 4.0 is the Hardware Error Source\nTable (HEST), where BIOS can define that errors for certain PCIe\ndevices (or all devices), should be handled by BIOS (\"Firmware First\nmode\"), rather than be handled by the OS.\n\nDell PowerEdge 11G server BIOS defines Firmware First mode in HEST, so\nthat it may manage such errors, log them to the System Event Log, and\npossibly take other actions. The aer driver should honor this, and\nnot attach itself to devices noted as such.\n\nFurthermore, Kenji Kaneshige reminded us to disallow changing the AER\nregisters when respecting Firmware First mode. Platform firmware is\nexpected to manage these, and if changes to them are allowed, it could\nbreak that firmware\u0027s behavior.\n\nThe HEST parsing code may be replaced in the future by a more\nfeature-rich implementation. This patch provides the minimum needed\nto prevent breakage until that implementation is available.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Matt Domsch \u003cMatt_Domsch@dell.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "15ea76d407d560f985224b65fe59c9db01692a0d", "tree": "dd9dd1cd4cab4bff26c34853a1c67898e8500243", "parents": [ "4c0eec7a86303ce6e3edf7825d0ef1d414e76767" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Sep 22 17:34:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:47:11 2009 -0800" }, "message": "pccard: configure CLS on attach\n\nFor non hotplug PCI devices, the system firmware usually configures\nCLS correctly. For pccard devices system firmware can\u0027t do it and\nLinux PCI layer doesn\u0027t do it either. Unfortunately this leads to\npoor performance for certain devices (sata_sil). Unless MWI, which\nrequires separate configuration, is to be used, CLS doesn\u0027t affect\ncorrectness, so the configuration should be harmless.\n\nThis patch makes pci_set_cacheline_size() always built and export it\nand make pccard call it during attach.\n\nPlease note that some other PCI hotplug drivers (shpchp and pciehp)\nalso configure CLS on hotplug.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nCc: Daniel Ritz \u003cdaniel.ritz@gmx.ch\u003e\nCc: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nCc: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nCc: Axel Birndt \u003ctowerlexa@gmx.de\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ac1aa47b131416a6ff37eb1005a0a1d2541aad6c", "tree": "1d7efa15a16f61664a240520970e729b1a47e4a5", "parents": [ "99935a7a59eaca0292c1a5880e10bae03f4a5e3d" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Oct 26 13:20:44 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:47:10 2009 -0800" }, "message": "PCI: determine CLS more intelligently\n\nTill now, CLS has been determined either by arch code or as\nL1_CACHE_BYTES. Only x86 and ia64 set CLS explicitly and x86 doesn\u0027t\nalways get it right. On most configurations, the chance is that\nfirmware configures the correct value during boot.\n\nThis patch makes pci_init() determine CLS by looking at what firmware\nhas configured. It scans all devices and if all non-zero values\nagree, the value is used. If none is configured or there is a\ndisagreement, pci_dfl_cache_line_size is used. arch can set the dfl\nvalue (via PCI_CACHE_LINE_BYTES or pci_dfl_cache_line_size) or\noverride the actual one.\n\nia64, x86 and sparc64 updated to set the default cls instead of the\nactual one.\n\nWhile at it, declare pci_cache_line_size and pci_dfl_cache_line_size\nin pci.h and drop private declarations from arch code.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nAcked-by: David Miller \u003cdavem@davemloft.net\u003e\nAcked-by: Greg KH \u003cgregkh@suse.de\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Tony Luck \u003ctony.luck@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e80bb09d2c73d76a2a4cd79e4a83802dd901c642", "tree": "fff892db62dd092ab8e3d70d19d813d4979a2503", "parents": [ "df8db91fc3b543d373afa61beef35b072eea1368" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Tue Sep 08 23:14:49 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:19:11 2009 -0700" }, "message": "PCI PM: Introduce device flag wakeup_prepared\n\nIntroduce a new PCI device flag, wakeup_prepared, to prevent PCI\nwake-up preparation code from being executed twice in a row for the\nsame device and for the same purpose.\n\nReviewed-by: Matthew Garrett \u003cmjg59@srcf.ucam.org\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "28760489a3f1e136c5ae8581c0fa8f63511f2f4c", "tree": "a3c890e9c8d9e98385691d56f5c007d280514fe5", "parents": [ "0ba379ec0fb182a87b8891c5754abbcd9c035b4f" ], "author": { "name": "Eric W. Biederman", "email": "ebiederm@aristanetworks.com", "time": "Wed Sep 09 14:09:24 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:10:24 2009 -0700" }, "message": "PCI: pcie: Ensure hotplug ports have a minimum number of resources\n\nIn general a BIOS may goof or we may hotplug in a hotplug controller.\nIn either case the kernel needs to reserve resources for plugging\nin more devices in the future instead of creating a minimal resource\nassignment.\n\nWe already do this for cardbus bridges I am just adding a variant\nfor pcie bridges.\n\nv2: Make testing for pcie hotplug bridges based on a flag.\n\n So far we only set the flag for pcie but a header_quirk\n could easily be added for the non-standard pci hotplug\n bridges.\n\nSigned-off-by: Eric W. Biederman \u003cebiederm@aristanetworks.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9dba910e9de2c4aa15ec1286f10052c107ef48ca", "tree": "4870eccc95e406ae8d490136f5d65953203418c8", "parents": [ "825c423a35a80a8fd66398a3f9bde7f0b0187a76" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Thu Sep 03 15:26:36 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:43:58 2009 -0700" }, "message": "PCI: separate out pci_add_dynid()\n\nSeparate out pci_add_dynid() from store_new_id() and export it so that\nin-kernel code can add PCI IDs dynamically. As the function will be\navailable regardless of HOTPLUG, put it and pull pci_free_dynids()\noutside of CONFIG_HOTPLUG.\n\nThis will be used by pci-stub to initialize initial IDs via module\nparam.\n\nWhile at it, remove bogus get_driver() failure check.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nReviewed-by: Grant Grundler \u003cgrundler@parisc-linux.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" } ], "next": "260d703adc5f275e3ba7ddff6e2e0217bc613b35" }