)]}' { "log": [ { "commit": "9bb676966aa85e56af00b353387d3c274a26e480", "tree": "cafc9a409aa05cc9060eb53f03c35881f41b6cec", "parents": [ "0f2cc4ecd81dc1917a041dc93db0ada28f8356fa", "dd58ffcf5a5352fc10820c8ffbcd5fed416a2c3a" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Mar 04 08:20:14 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Mar 04 08:20:14 2010 -0800" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (28 commits)\n ioat: cleanup -\u003etimer_fn() and -\u003ecleanup_fn() prototypes\n ioat3: interrupt coalescing\n ioat: close potential BUG_ON race in the descriptor cleanup path\n ioat2: kill pending flag\n ioat3: use ioat2_quiesce()\n ioat3: cleanup, don\u0027t enable DCA completion writes\n DMAENGINE: COH 901 318 lli sg offset fix\n DMAENGINE: COH 901 318 configure channel direction\n DMAENGINE: COH 901 318 remove irq counting\n DMAENGINE: COH 901 318 descriptor pool refactoring\n DMAENGINE: COH 901 318 cleanups\n dma: Add MPC512x DMA driver\n Debugging options for the DMA engine subsystem\n iop-adma: redundant/wrong tests in iop_*_count()?\n dmatest: fix handling of an even number of xor_sources\n dmatest: correct raid6 PQ test\n fsldma: Fix cookie issues\n fsldma: Fix cookie issues\n dma: cases IPU_PIX_FMT_BGRA32, BGR32 and ABGR32 are the same in ipu_ch_param_set_size()\n dma: make Open Firmware device id constant\n ...\n" }, { "commit": "76bd061f5c7b7550cdaed68ad6219ea7cee288fc", "tree": "5ae663b8bab6bd77cab2b8bc095c0743cc2da138", "parents": [ "6ca3a7a96e91b1aa8c704153c992b191d35b5747" ], "author": { "name": "Steven J. Magnani", "email": "steve@digidescorp.com", "time": "Sun Feb 28 22:18:16 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Feb 28 22:18:16 2010 -0700" }, "message": "fsldma: Fix cookie issues\n\nfsl_dma_update_completed_cookie() appears to calculate the last completed\ncookie incorrectly in the corner case where DMA on cookie 1 is in progress\njust following a cookie wrap.\n\nSigned-off-by: Steven J. Magnani \u003csteve@digidescorp.com\u003e\nAcked-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\n[dan.j.williams@intel.com: fix an integer overflow warning with INT_MAX]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a29d8b8e2d811a24bbe49215a0f0c536b72ebc18", "tree": "5a714679aeebd5f7af5d1fc521f0db8639324f6c", "parents": [ "003cb608a2533d0927a83bc4e07e46d7a622eda9" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Feb 02 14:39:15 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Feb 17 11:17:38 2010 +0900" }, "message": "percpu: add __percpu sparse annotations to what\u0027s left\n\nAdd __percpu sparse annotations to places which didn\u0027t make it in one\nof the previous patches. All converions are trivial.\n\nThese annotations are to make sparse consider percpu variables to be\nin a different address space and warn if accessed without going\nthrough percpu accessors. This patch doesn\u0027t affect normal builds.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nAcked-by: Borislav Petkov \u003cborislav.petkov@amd.com\u003e\nCc: Dan Williams \u003cdan.j.williams@intel.com\u003e\nCc: Huang Ying \u003cying.huang@intel.com\u003e\nCc: Len Brown \u003clenb@kernel.org\u003e\nCc: Neil Brown \u003cneilb@suse.de\u003e\n" }, { "commit": "a88f6667078412e5eff37ead68a043ee0ec9f1da", "tree": "81f51a6a14670a8902d454e84eec1de444c2a09a", "parents": [ "86d61b33e48f1da5a6b310d3de93187db62ab72a" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Dec 10 18:35:15 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 10 23:43:19 2009 -0700" }, "message": "dmaengine: clarify the meaning of the DMA_CTRL_ACK flag\n\nDMA_CTRL_ACK\u0027s description applies to its clear state, not to its set state.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bbb20089a3275a19e475dbc21320c3742e3ca423", "tree": "216fdc1cbef450ca688135c5b8969169482d9a48", "parents": [ "3e48e656903e9fd8bc805c6a2c4264d7808d315b", "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "message": "Merge branch \u0027dmaengine\u0027 into async-tx-next\n\nConflicts:\n\tcrypto/async_tx/async_xor.c\n\tdrivers/dma/ioat/dma_v2.h\n\tdrivers/dma/ioat/pci.c\n\tdrivers/md/raid5.c\n" }, { "commit": "0803172778901e24a75ab074798d98c2b7411559", "tree": "a3e1d0cf4228d65dc1fac2ad56f3beb6b6f3474b", "parents": [ "1979b186b80449ac6574d97c254b694c8a99b703" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "dmaengine: kill tx_list\n\nThe tx_list attribute of struct dma_async_tx_descriptor is common to\nmost, but not all dma driver implementations. None of the upper level\ncode (dmaengine/async_tx) uses it, so allow drivers to implement it\nlocally if they need it. This saves sizeof(struct list_head) bytes for\ndrivers that do not manage descriptors with a linked list (e.g.: ioatdma\nv2,3).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7", "tree": "bc4b28c2e5bdae01a2c8a250176fcdac6ae7a8ce", "parents": [ "9308add6ea4fedeba37b0d7c4630a542bd34f214" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "message": "dmaengine, async_tx: support alignment checks\n\nSome engines have transfer size and address alignment restrictions. Add\na per-operation alignment property to struct dma_device that the async\nroutines and dmatest can use to check alignment capabilities.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9308add6ea4fedeba37b0d7c4630a542bd34f214", "tree": "5b94b9c8eebc7a7ef6879a7fdfc553c6758312dc", "parents": [ "138f4c359d23d2ec38d18bd70dd9613ae515fe93" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:52 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:52 2009 -0700" }, "message": "dmaengine: cleanup unused transaction types\n\nNo drivers currently implement these operation types, so they can be\ndeleted.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "138f4c359d23d2ec38d18bd70dd9613ae515fe93", "tree": "ad7fafba6eac74d9d92ade839a65171466d67a70", "parents": [ "0403e3827788d878163f9ef0541b748b0f88ca5d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "message": "dmaengine, async_tx: add a \"no channel switch\" allocator\n\nChannel switching is problematic for some dmaengine drivers as the\narchitecture precludes separating the -\u003eprep from -\u003esubmit. In these\ncases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify\nthe async_tx allocator to only return channels that support all of the\nrequired asynchronous operations.\n\nFor example MD_RAID456\u003dy selects support for asynchronous xor, xor\nvalidate, pq, pq validate, and memcpy. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dy any channel with all these\ncapabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to\nquickly locate compatible channels with the guarantee that dependency\nchains will remain on one channel. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dn async_tx_find_channel() may select\nchannels that lead to operation chains that need to cross channel\nboundaries using the async_tx channel switch capability.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0403e3827788d878163f9ef0541b748b0f88ca5d", "tree": "2dc73744bd92c268a1310f24668167f130877278", "parents": [ "f9dd2134374c8de6b911e2b8652c6c9622eaa658" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:50 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:50 2009 -0700" }, "message": "dmaengine: add fence support\n\nSome engines optimize operation by reading ahead in the descriptor chain\nsuch that descriptor2 may start execution before descriptor1 completes.\nIf descriptor2 depends on the result from descriptor1 then a fence is\nrequired (on descriptor2) to disable this optimization. The async_tx\napi could implicitly identify dependencies via the \u0027depend_tx\u0027\nparameter, but that would constrain cases where the dependency chain\nonly specifies a completion order rather than a data dependency. So,\nprovide an ASYNC_TX_FENCE to explicitly identify data dependencies.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f9dd2134374c8de6b911e2b8652c6c9622eaa658", "tree": "c1b8f8d622941606b9e7247ab31d811ba4295011", "parents": [ "4b652f0db3be891c7b76b109c3b55003b920fc96", "07a3b417dc3d00802bd7b4874c3e811f0b015a7d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:29 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:29 2009 -0700" }, "message": "Merge branch \u0027md-raid6-accel\u0027 into ioat3.2\n\nConflicts:\n\tinclude/linux/dmaengine.h\n" }, { "commit": "b2f46fd8ef3dff2ab30f31126833f78b7480283a", "tree": "9f111e3e313b4d142c12d2d8156a2704a36904f8", "parents": [ "95475e57113c66aac7583925736ed2e2d58c990d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:20:36 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "async_tx: add support for asynchronous GF multiplication\n\n[ Based on an original patch by Yuri Tikhonov ]\n\nThis adds support for doing asynchronous GF multiplication by adding\ntwo additional functions to the async_tx API:\n\n async_gen_syndrome() does simultaneous XOR and Galois field\n multiplication of sources.\n\n async_syndrome_val() validates the given source buffers against known P\n and Q values.\n\nWhen a request is made to run async_pq against more than the hardware\nmaximum number of supported sources we need to reuse the previous\ngenerated P and Q values as sources into the next operation. Care must\nbe taken to remove Q from P\u0027 and P from Q\u0027. For example to perform a 5\nsource pq op with hardware that only supports 4 sources at a time the\nfollowing approach is taken:\n\np, q \u003d PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))\np\u0027, q\u0027 \u003d PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))\n\np\u0027 \u003d p + q + q + src4 \u003d p + src4\nq\u0027 \u003d {00}*p + {01}*q + {00}*q + {10}*src4 \u003d q + {10}*src4\n\nNote: 4 is the minimum acceptable maxpq otherwise we punt to\nsynchronous-software path.\n\nThe DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as\nsources (in the above manner) and fill the remaining slots up to maxpq\nwith the new sources/coefficients.\n\nNote1: Some devices have native support for P+Q continuation and can skip\nthis extra work. Devices with this capability can advertise it with\ndma_set_maxpq. It is up to each driver how to handle the\nDMA_PREP_CONTINUE flag.\n\nNote2: The api supports disabling the generation of P when generating Q,\nthis is ignored by the synchronous path but is implemented by some dma\ndevices to save unnecessary writes. In this case the continuation\nalgorithm is simplified to only reuse Q as a source.\n\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "ad283ea4a3ce82cda2efe33163748a397b31b1eb", "tree": "11cd739195f336895abe9e4a62d824e49a41c24f", "parents": [ "d6f38f31f3ad4b0dd33fe970988f14e7c65ef702" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "message": "async_tx: add sum check flags\n\nReplace the flat zero_sum_result with a collection of flags to contain\nthe P (xor) zero-sum result, and the soon to be utilized Q (raid6 reed\nsolomon syndrome) zero-sum result. Use the SUM_CHECK_ namespace instead\nof DMA_ since these flags will be used on non-dma-zero-sum enabled\nplatforms.\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "4f005dbe5584fe54c9f6d6d4f0acd3fb29be84da", "tree": "d9a4add9553af6c50fae59a79e9ab217945a7090", "parents": [ "ca50a51e890b0a62b44b5642c1ba5049909e5a8b" ], "author": { "name": "Maciej Sosnowski", "email": "maciej.sosnowski@intel.com", "time": "Thu Apr 23 12:31:51 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue May 12 14:41:47 2009 -0700" }, "message": "ioatdma: fix \"ioatdma frees DMA memory with wrong function\"\n\nas reported by Alexander Beregalov \u003ca.beregalov@gmail.com\u003e\n\nioatdma 0000:00:08.0: DMA-API: device driver frees DMA memory with\nwrong function [device address\u003d0x000000007f76f800] [size\u003d2000 bytes]\n[map\nped as single] [unmapped as page]\n\nThe ioatdma driver was unmapping all regions\n(either allocated as page or single) using unmap_page.\nThis patch lets dma driver recognize if unmap_single or unmap_page should be used.\nIt introduces two new dma control flags:\nDMA_COMPL_SRC_UNMAP_SINGLE and DMA_COMPL_DEST_UNMAP_SINGLE.\nThey should be set to indicate dma driver to do dma-unmapping as single\n(first one for the source, tha latter for the destination).\nIf respective flag is not set, the driver assumes dma-unmapping as page.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nReported-by: Alexander Beregalov \u003ca.beregalov@gmail.com\u003e\nTested-by: Alexander Beregalov \u003ca.beregalov@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "099f53cb50e45ef617a9f1d63ceec799e489418b", "tree": "fd57f259f58bcf615fe2b17734ed0cbec612782d", "parents": [ "fd74ea65883c7e6903e9b652795f72b723a2be69" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Apr 08 14:28:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Apr 08 14:28:37 2009 -0700" }, "message": "async_tx: rename zero_sum to val\n\n\u0027zero_sum\u0027 does not properly describe the operation of generating parity\nand checking that it validates against an existing buffer. Change the\nname of the operation to \u0027val\u0027 (for \u0027validate\u0027). This is in\nanticipation of the p+q case where it is a requirement to identify the\ntarget parity buffers separately from the source buffers, because the\ntarget parity buffers will not have corresponding pq coefficients.\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0f571515c332e00b3515dbe0859ceaa30ab66e00", "tree": "6d67c555714264dda749e387cee6738f770abc5d", "parents": [ "e44e0aa3cfa97cddff01704751a4b25151830c72" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Fri Mar 06 20:07:14 2009 +0900" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Mar 26 09:48:09 2009 -0700" }, "message": "dmaengine: Add privatecnt to revert DMA_PRIVATE property\n\nCurrently dma_request_channel() set DMA_PRIVATE capability but never\nclear it. So if a public channel was once grabbed by\ndma_request_channel(), the device stay PRIVATE forever. Add\nprivatecnt member to dma_device to correctly revert it.\n\n[lg@denx.de: fix bad usage of \u0027chan\u0027 in dma_async_device_register]\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "729b5d1b8ec72c28e99840b3f300ba67726e3ab9", "tree": "8eac6444ea80bf05f461eb77243f56b008ee5083", "parents": [ "06164f3194e01ea4c76941ac60f541d656c8975f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:25 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:25 2009 -0700" }, "message": "dmaengine: allow dma support for async_tx to be toggled\n\nProvide a config option for blocking the allocation of dma channels to\nthe async_tx api.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "54aee6a5f560d0e1bf3f39987c6ebe06daeb0ce1", "tree": "b1cab9a10387f12305f5e92ce5e91eabdfc78367", "parents": [ "ccccce229c633a92c42cd1a40c0738d7b0d12644" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "message": "dmaengine: kill some unused headers\n\nThe dmaengine redux left some unneeded headers in\ninclude/linux/dmaengine.h, clean them up.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "5dc18f51a2c06ddab708184e30b7967fb71c1784", "tree": "b080f2a651f694f523491487bf92d28c3c63d981", "parents": [ "fd6ec5f3acfe7e94469d83374b83ff183953fa45", "7cbd4877e5b167b56a3d6033b926a9f925186e12" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Mar 08 10:23:05 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Mar 08 10:23:05 2009 -0700" }, "message": "Merge branch \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n dmatest: fix use after free in dmatest_exit\n ipu_idmac: fix spinlock type\n iop-adma, mv_xor: fix mem leak on self-test setup failure\n fsldma: fix off by one in dma_halt\n I/OAT: fail self-test if callback test reaches timeout\n I/OAT: update driver version and copyright dates\n I/OAT: list usage cleanup\n I/OAT: set tcp_dma_copybreak to 256k for I/OAT ver.3\n I/OAT: cancel watchdog before dma remove\n I/OAT: fail initialization on zero channels detection\n I/OAT: do not set DCACTRL_CMPL_WRITE_ENABLE for I/OAT ver.3\n I/OAT: add verification for proper APICID_TAG_MAP setting by BIOS\n dmaengine: update kerneldoc\n" }, { "commit": "287d859222e0adbc67666a6154aaf42d7d5bbb54", "tree": "a3e00f7b42f91c0d00f9d5a8d79414939b3c566f", "parents": [ "9ccf3b5e8409927835c4d38cb2f380c9e4349e76" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 18 14:48:26 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Feb 18 15:37:55 2009 -0800" }, "message": "atmel-mci: fix initialization of dma slave data\n\nThe conversion of atmel-mci to dma_request_channel missed the\ninitialization of the channel dma_slave information. The filter_fn passed\nto dma_request_channel is responsible for initializing the channel\u0027s\nprivate data. This implementation has the additional benefit of enabling\na generic client-channel data passing mechanism.\n\nReviewed-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "1d93e52eb48df986a3c4d5ad8a520bf1f6837367", "tree": "cb173060e2aa73d2a77058a40a35cae5942b5184", "parents": [ "6c6f1f0f4db31a192916eaa31ec2f114fda7d5e5" ], "author": { "name": "Johannes Weiner", "email": "jw@emlix.com", "time": "Wed Feb 11 08:47:19 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 11 17:12:27 2009 -0700" }, "message": "dmaengine: update kerneldoc\n\nSome of the kerneldoc comments in the dmaengine header describe\nalready removed structure members. Remove them.\n\nAlso add a short description for dma_device-\u003edevice_is_tx_complete.\n\nSigned-off-by: Johannes Weiner \u003cjw@emlix.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b4bd07c20ba0c1fa7ad09ba257e0a5cfc2bf6bb3", "tree": "41fb5a2fe732a0e4f3da00e31b55418ff988932f", "parents": [ "152abd139cca049c9b559a7cca762fa7fd9fd264" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Feb 06 22:06:43 2009 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Feb 06 22:06:43 2009 -0800" }, "message": "net_dma: call dmaengine_get only if NET_DMA enabled\n\nBased upon a patch from Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\n\n--------------------\nThe commit 649274d993212e7c23c0cb734572c2311c200872 (\"net_dma:\nacquire/release dma channels on ifup/ifdown\") added unconditional call\nof dmaengine_get() to net_dma. The API should be called only if\nNET_DMA was enabled.\n--------------------\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7954d5cf39ee1ce9bb0a4b19fcf1924885a9cad1", "tree": "3515ebb6ed3f15ead563ac3e30e30fd4b37992fb", "parents": [ "37f5fed55559a030c430550bcacec75e6a833f1b", "86528da229a448577a8401a17c295883640d336c" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jan 26 10:13:08 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jan 26 10:13:08 2009 -0800" }, "message": "Merge branch \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n i.MX31: framebuffer driver\n i.MX31: Image Processing Unit DMA and IRQ drivers\n dmaengine: add async_tx_clear_ack() macro\n dmaengine: dma_issue_pending_all \u003d\u003d nop when CONFIG_DMA_ENGINE\u003dn\n dmaengine: kill some dubious WARN_ONCEs\n fsldma: print correct IRQ on mpc83xx\n fsldma: check for NO_IRQ in fsl_dma_chan_remove()\n dmatest: Use custom map/unmap for destination buffer\n fsldma: use a valid \u0027device\u0027 for dma_pool_create\n dmaengine: fix dependency chaining\n" }, { "commit": "ef560682a97491f62ef538931a4861b57d66c52c", "tree": "3dc1fe733675eb99bd92e680946c1deeaf64b2ef", "parents": [ "c50331e8be32eaba5e1949f98c70d50b891262db" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Mon Jan 19 15:36:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 19 15:36:21 2009 -0700" }, "message": "dmaengine: add async_tx_clear_ack() macro\n\nTo complete the DMA_CTRL_ACK handling API add a async_tx_clear_ack() macro.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "c50331e8be32eaba5e1949f98c70d50b891262db", "tree": "b748c607329fd03868226ab4fba234a5702368d9", "parents": [ "83436a0560e9ef8af2f0796264dde4bed1415359" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 19 15:33:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 19 15:35:54 2009 -0700" }, "message": "dmaengine: dma_issue_pending_all \u003d\u003d nop when CONFIG_DMA_ENGINE\u003dn\n\nThe device list will always be empty in this configuration, so no need\nto walk the list.\n\nReported-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "649274d993212e7c23c0cb734572c2311c200872", "tree": "84ff8e44e5b44bbe3c388eded5c3e28bf0bd2375", "parents": [ "47fd23fe8efeea3af4593a8424419df48724eb25" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Jan 11 00:20:39 2009 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Jan 11 00:20:39 2009 -0800" }, "message": "net_dma: acquire/release dma channels on ifup/ifdown\n\nThe recent dmaengine rework removed the capability to remove dma device\ndriver modules while net_dma is active. Rather than notify\ndmaengine-clients that channels are trying to be removed, we now rely on\nclients to notify dmaengine when they no longer have a need for\nchannels. Teach net_dma to release channels by taking dmaengine\nreferences at netdevice open and dropping references at netdevice close.\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "864498aaa9fef69ee166da023d12413a7776342d", "tree": "023d6bfc15ba192c1a92caab3ff7525a84e409fc", "parents": [ "41d5e59c1299f27983977bcfe3b360600996051c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:21 2009 -0700" }, "message": "dmaengine: use idr for registering dma device numbers\n\nThis brings some predictability to dma device numbers, i.e. an rmmod/insmod\ncycle may now result in /sys/class/dma/dma0chan0 being restored rather than\n/sys/class/dma/dma1chan0 appearing.\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n" }, { "commit": "41d5e59c1299f27983977bcfe3b360600996051c", "tree": "f0e80b6fea3af04f266843af97f433198ad535c7", "parents": [ "4fac7fa57cf8001be259688468c825f836daf739" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:21 2009 -0700" }, "message": "dmaengine: add a release for dma class devices and dependent infrastructure\n\nResolves:\nWARNING: at drivers/base/core.c:122 device_release+0x4d/0x52()\nDevice \u0027dma0chan0\u0027 does not have a release() function, it is broken and must be fixed.\n\nThe dma_chan_dev object is introduced to gear-match sysfs kobject and\ndmaengine channel lifetimes. When a channel is removed access to the\nsysfs entries return -ENODEV until the kobject can be released.\n\nThe bulk of the change is updates to existing code to handle the extra\nlayer of indirection between a dma_chan and its struct device.\n\nReported-by: Alexander Beregalov \u003ca.beregalov@gmail.com\u003e\nAcked-by: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n" }, { "commit": "7dd602510128d7a64b11ff3b7d4f30ac8e3946ce", "tree": "6a87f942c72b0b02d24db7144cad435211178fcc", "parents": [ "f27c580c3628d79b17f38976d842a6d7f3616e2e" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:19 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:19 2009 -0700" }, "message": "dmaengine: kill enum dma_state_client\n\nDMA_NAK is now useless. We can just use a bool instead.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "f27c580c3628d79b17f38976d842a6d7f3616e2e", "tree": "f1a1a96c1130e7e1c88f75cb5f5aab4c53fe0297", "parents": [ "aa1e6f1a385eb2b04171ec841f3b760091e4a8ee" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:18 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:18 2009 -0700" }, "message": "dmaengine: remove \u0027bigref\u0027 infrastructure\n\nReference counting is done at the module level so clients need not worry\nthat a channel will leave while they are actively using dmaengine.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "aa1e6f1a385eb2b04171ec841f3b760091e4a8ee", "tree": "1401e7f1e867e5d4a769b648605e0317d25d5ccb", "parents": [ "209b84a88fe81341b4d8d465acc4a67cb7c3feb3" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:17 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:17 2009 -0700" }, "message": "dmaengine: kill struct dma_client and supporting infrastructure\n\nAll users have been converted to either the general-purpose allocator,\ndma_find_channel, or dma_request_channel.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n" }, { "commit": "209b84a88fe81341b4d8d465acc4a67cb7c3feb3", "tree": "134632ed8c914f0ee497e7a22bc616d84e068119", "parents": [ "74465b4ff9ac1da503025c0a0042e023bfa6505c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:17 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:17 2009 -0700" }, "message": "dmaengine: replace dma_async_client_register with dmaengine_get\n\nNow that clients no longer need to be notified of channel arrival\ndma_async_client_register can simply increment the dmaengine_ref_count.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "74465b4ff9ac1da503025c0a0042e023bfa6505c", "tree": "ce63f4a4b055b65cae1edaddd334931bf512c76e", "parents": [ "33df8ca068123457db56c316946a3c0e4ef787d6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:16 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:16 2009 -0700" }, "message": "atmel-mci: convert to dma_request_channel and down-level dma_slave\n\ndma_request_channel provides an exclusive channel, so we no longer need to\npass slave data through dmaengine.\n\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "33df8ca068123457db56c316946a3c0e4ef787d6", "tree": "e594340e903ea3eb8af83906c649eeaf85cbc0b2", "parents": [ "59b5ec21446b9239d706ab237fb261d525b75e81" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:15 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:15 2009 -0700" }, "message": "dmatest: convert to dma_request_channel\n\nReplace the client registration infrastructure with a custom loop to\npoll for channels. Once dma_request_channel returns NULL stop asking\nfor channels. A userspace side effect of this change if that loading\nthe dmatest module before loading a dma driver will result in no\nchannels being found, previously dmatest would get a callback. To\nfacilitate testing in the built-in case dmatest_init is marked as a\nlate_initcall. Another side effect is that channels under test can not\nbe used for any other purpose.\n\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "59b5ec21446b9239d706ab237fb261d525b75e81", "tree": "a437a354e84d311104829ca0e8b00b0ec8cb05c4", "parents": [ "f67b45999205164958de4ec0658d51fa4bee066d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:15 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:15 2009 -0700" }, "message": "dmaengine: introduce dma_request_channel and private channels\n\nThis interface is primarily for device-to-memory clients which need to\nsearch for dma channels with platform-specific characteristics. The\nprototype is:\n\nstruct dma_chan *dma_request_channel(dma_cap_mask_t mask,\n dma_filter_fn filter_fn,\n void *filter_param);\n\nWhen the optional \u0027filter_fn\u0027 parameter is set to NULL\ndma_request_channel simply returns the first channel that satisfies the\ncapability mask. Otherwise, when the mask parameter is insufficient for\nspecifying the necessary channel, the filter_fn routine can be used to\ndisposition the available channels in the system. The filter_fn routine\nis called once for each free channel in the system. Upon seeing a\nsuitable channel filter_fn returns DMA_ACK which flags that channel to\nbe the return value from dma_request_channel. A channel allocated via\nthis interface is exclusive to the caller, until dma_release_channel()\nis called.\n\nTo ensure that all channels are not consumed by the general-purpose\nallocator the DMA_PRIVATE capability is provided to exclude a dma_device\nfrom general-purpose (memory-to-memory) consideration.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n" }, { "commit": "2ba05622b8b143b0c95968ba59bddfbd6d2f2559", "tree": "b7b72d02a993ff2ba731d6608f4ab8ce87482bcb", "parents": [ "bec085134e446577a983f17f57d642a88d1af53b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "message": "dmaengine: provide a common \u0027issue_pending_all\u0027 implementation\n\nasync_tx and net_dma each have open-coded versions of issue_pending_all,\nso provide a common routine in dmaengine.\n\nThe implementation needs to walk the global device list, so implement\nrcu to allow dma_issue_pending_all to run lockless. Clients protect\nthemselves from channel removal events by holding a dmaengine reference.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "bec085134e446577a983f17f57d642a88d1af53b", "tree": "7d29afc53fedc72349ee78112fb71f68ff48ce24", "parents": [ "6f49a57aa5a0c6d4e4e27c85f7af6c83325a12d1" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "message": "dmaengine: centralize channel allocation, introduce dma_find_channel\n\nAllowing multiple clients to each define their own channel allocation\nscheme quickly leads to a pathological situation. For memory-to-memory\noffload all clients can share a central allocator.\n\nThis simply moves the existing async_tx allocator to dmaengine with\nminimal fixups:\n* async_tx.c:get_chan_ref_by_cap --\u003e dmaengine.c:nth_chan\n* async_tx.c:async_tx_rebalance --\u003e dmaengine.c:dma_channel_rebalance\n* split out common code from async_tx.c:__async_tx_find_channel --\u003e\n dma_find_channel\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "6f49a57aa5a0c6d4e4e27c85f7af6c83325a12d1", "tree": "afba24357d1f4ff69ccb2b39a19542546590a50b", "parents": [ "07f2211e4fbce6990722d78c4f04225da9c0e9cf" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "message": "dmaengine: up-level reference counting to the module level\n\nSimply, if a client wants any dmaengine channel then prevent all dmaengine\nmodules from being removed. Once the clients are done re-enable module\nremoval.\n\nWhy?, beyond reducing complication:\n1/ Tracking reference counts per-transaction in an efficient manner, as\n is currently done, requires a complicated scheme to avoid cache-line\n bouncing effects.\n2/ Per-transaction ref-counting gives the false impression that a\n dma-driver can be gracefully removed ahead of its user (net, md, or\n dma-slave)\n3/ None of the in-tree dma-drivers talk to hot pluggable hardware, but\n if such an engine were built one day we still would not need to notify\n clients of remove events. The driver can simply return NULL to a\n -\u003eprep() request, something that is much easier for a client to handle.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "07f2211e4fbce6990722d78c4f04225da9c0e9cf", "tree": "51934e20a334e93c8c399d2e6375f264551e9bc3", "parents": [ "28405d8d9ce05f5bd869ef8b48da5086f9527d73" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 05 17:14:31 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 05 18:10:19 2009 -0700" }, "message": "dmaengine: remove dependency on async_tx\n\nasync_tx.ko is a consumer of dma channels. A circular dependency arises\nif modules in drivers/dma rely on common code in async_tx.ko. It\nprevents either module from being unloaded.\n\nMove dma_wait_for_async_tx and async_tx_run_dependencies to dmaeninge.o\nwhere they should have been from the beginning.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "0839875e0c197ded56bbae820e699f26d6fa2697", "tree": "87e8a41e6332db67d9a765af875aae59e6f048ba", "parents": [ "3dce01713723bbcc92562bd4488e8b840a4f786c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 17 17:59:56 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 17 17:59:56 2008 -0700" }, "message": "async_tx: make async_tx_test_ack a boolean routine\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "dc0ee6435cb92ccc81b14ff28d163fecc5a7f120", "tree": "0a494946593f36516a997f64cb299d898cdf463f", "parents": [ "e1d181efb14a93cf263d6c588a5395518edf3294" ], "author": { "name": "Haavard Skinnemoen", "email": "haavard.skinnemoen@atmel.com", "time": "Tue Jul 08 11:59:35 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:59:35 2008 -0700" }, "message": "dmaengine: Add slave DMA interface\n\nThis patch adds the necessary interfaces to the DMA Engine framework\nto use functionality found on most embedded DMA controllers: DMA from\nand to I/O registers with hardware handshaking.\n\nIn this context, hardware hanshaking means that the peripheral that\nowns the I/O registers in question is able to tell the DMA controller\nwhen more data is available for reading, or when there is room for\nmore data to be written. This usually happens internally on the chip,\nbut these signals may also be exported outside the chip for things\nlike IDE DMA, etc.\n\nA new struct dma_slave is introduced. This contains information that\nthe DMA engine driver needs to set up slave transfers to and from a\nslave device. Most engines supporting DMA slave transfers will want to\nextend this structure with controller-specific parameters. This\nadditional information is usually passed from the platform/board code\nthrough the client driver.\n\nA \"slave\" pointer is added to the dma_client struct. This must point\nto a valid dma_slave structure iff the DMA_SLAVE capability is\nrequested. The DMA engine driver may use this information in its\ndevice_alloc_chan_resources hook to configure the DMA controller for\nslave transfers from and to the given slave device.\n\nA new operation for preparing slave DMA transfers is added to struct\ndma_device. This takes a scatterlist and returns a single descriptor\nrepresenting the whole transfer.\n\nAnother new operation for terminating all pending transfers is added as\nwell. The latter is needed because there may be errors outside the scope\nof the DMA Engine framework that may require DMA operations to be\nterminated prematurely.\n\nDMA Engine drivers may extend the dma_device, dma_chan and/or\ndma_slave_descriptor structures to allow controller-specific\noperations. The client driver can detect such extensions by looking at\nthe DMA Engine\u0027s struct device, or it can request a specific DMA\nEngine device by setting the dma_dev field in struct dma_slave.\n\ndmaslave interface changes since v4:\n * Fix checkpatch errors\n * Fix changelog (there are no slave descriptors anymore)\n\ndmaslave interface changes since v3:\n * Use dma_data_direction instead of a new enum\n * Submit slave transfers as scatterlists\n * Remove the DMA slave descriptor struct\n\ndmaslave interface changes since v2:\n * Add a dma_dev field to struct dma_slave. If set, the client can\n only be bound to the DMA controller that corresponds to this\n device. This allows controller-specific extensions of the\n dma_slave structure; if the device matches, the controller may\n safely assume its extensions are present.\n * Move reg_width into struct dma_slave as there are currently no\n users that need to be able to set the width on a per-transfer\n basis.\n\ndmaslave interface changes since v1:\n * Drop the set_direction and set_width descriptor hooks. Pass the\n direction and width to the prep function instead.\n * Declare a dma_slave struct with fixed information about a slave,\n i.e. register addresses, handshake interfaces and such.\n * Add pointer to a dma_slave struct to dma_client. Can be NULL if\n the DMA_SLAVE capability isn\u0027t requested.\n * Drop the set_slave device hook since the alloc_chan_resources hook\n now has enough information to set up the channel for slave\n transfers.\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e1d181efb14a93cf263d6c588a5395518edf3294", "tree": "1792d1faa7e344401789bbcfad8102d0d93036e2", "parents": [ "848c536a37b8db4e461f14ca15fe29850151c822" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 04 00:13:40 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:59:12 2008 -0700" }, "message": "dmaengine: add DMA_COMPL_SKIP_{SRC,DEST}_UNMAP flags to control dma unmap\n\nIn some cases client code may need the dma-driver to skip the unmap of source\nand/or destination buffers. Setting these flags indicates to the driver to\nskip the unmap step. In this regard async_xor is currently broken in that it\nallows the destination buffer to be unmapped while an operation is still in\nprogress, i.e. when the number of sources exceeds the hardware channel\u0027s\nmaximum (fixed in a subsequent patch).\n\nAcked-by: Saeed Bishara \u003csaeed@marvell.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "848c536a37b8db4e461f14ca15fe29850151c822", "tree": "f4a88e92e31de28511e3a3de99200a77d2613dae", "parents": [ "4a776f0aa922a552460192c07b56f4fe9cd82632" ], "author": { "name": "Haavard Skinnemoen", "email": "haavard.skinnemoen@atmel.com", "time": "Tue Jul 08 11:58:58 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:58:58 2008 -0700" }, "message": "dmaengine: Add dma_client parameter to device_alloc_chan_resources\n\nA DMA controller capable of doing slave transfers may need to know a\nfew things about the slave when preparing the channel. We don\u0027t want\nto add this information to struct dma_channel since the channel hasn\u0027t\nyet been bound to a client at this point.\n\nInstead, pass a reference to the client requesting the channel to the\ndriver\u0027s device_alloc_chan_resources hook so that it can pick the\nnecessary information from the dma_client struct by itself.\n\n[dan.j.williams@intel.com: fixed up fsldma and mv_xor]\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7cc5bf9a3a84e5a02e23e5739fb894790b37c101", "tree": "b526b348ed1b64884bf672924540bb5dc29cb211", "parents": [ "9c402f4e196290692d998b188f9094deb1619e57" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:58:21 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:58:21 2008 -0700" }, "message": "dmaengine: track the number of clients using a channel\n\nHaavard\u0027s dma-slave interface would like to test for exclusive access to a\nchannel. The standard channel refcounting is not sufficient in that it\ntracks more than just client references, it is also inaccurate as reference\ncounts are percpu until the channel is removed.\n\nThis change also enables a future fix to deallocate resources when a client\ndeclines to use a capable channel.\n\nAcked-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "8a5703f846e2363fc466aff3f53608340a1ae33f", "tree": "b229bba81473078275ff811254bf23f640f85e09", "parents": [ "218ff137bc67252694420563d23d051ab9227f17" ], "author": { "name": "Sebastian Siewior", "email": "bigeasy@tglx.de", "time": "Mon Apr 21 22:38:45 2008 +0000" }, "committer": { "name": "Jesper Juhl", "email": "juhl@hera.kernel.org", "time": "Mon Apr 21 22:38:45 2008 +0000" }, "message": "DMA engine: typo fixes\n\nSpelling fixes for dmaengine.[ch]\n\nSigned-off-by: Sebastian Siewior \u003cbigeasy@linutronix.de\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Jesper Juhl \u003cjesper.juhl@gmail.com\u003e\n" }, { "commit": "636bdeaa1243327501edfd2a597ed7443eb4239a", "tree": "59b894f124e3664ea4a537d7c07c527abdb9c8da", "parents": [ "c4fe15541d0ef5cc8cc1ce43057663851f8fc387" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 20:17:26 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 13:25:54 2008 -0700" }, "message": "dmaengine: ack to flags: make use of the unused bits in the \u0027ack\u0027 field\n\n\u0027ack\u0027 is currently a simple integer that flags whether or not a client is done\ntouching fields in the given descriptor. It is effectively just a single bit\nof information. Converting this to a flags parameter allows the other bits to\nbe put to use to control completion actions, like dma-unmap, and capture\nresults, like xor-zero-sum \u003d\u003d 0.\n\nChanges are one of:\n1/ convert all open-coded -\u003eack manipulations to use async_tx_ack\n and async_tx_test_ack.\n2/ set the ack bit at prep time where possible\n3/ make drivers store the flags at prep time\n4/ add flags to the device_prep_dma_interrupt prototype\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ce4d65a5db77e1568c82d5151a746f627c4f6ed5", "tree": "1f3936d2984fc03125bde025796465f9cada9075", "parents": [ "19242d7233df7d658405d4b7ee1758d21414cfaa" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 20:17:26 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 13:25:54 2008 -0700" }, "message": "async_tx: kill -\u003edevice_dependency_added\n\nDMA drivers no longer need to be notified of dependency submission\nevents as async_tx_run_dependencies and async_tx_channel_switch will\nhandle the scheduling and execution of dependent operations.\n\n[sfr@canb.auug.org.au: extend this for fsldma]\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "19242d7233df7d658405d4b7ee1758d21414cfaa", "tree": "4bffa2700c30fdb454dfa150115a0607c6cf3d2a", "parents": [ "1c62979ed29a8e2bf9fbe1db101c81a0089676f8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 20:17:25 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 13:25:05 2008 -0700" }, "message": "async_tx: fix multiple dependency submission\n\nShrink struct dma_async_tx_descriptor and introduce\nasync_tx_channel_switch to properly inject a channel switch interrupt in\nthe descriptor stream. This simplifies the locking model as drivers no\nlonger need to handle dma_async_tx_descriptor.lock.\n\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b2ddb9019ea13fb7b62d8e45adcc468376af0de7", "tree": "c01b69aeaf16eb84989a9011ec85e03f3fdec83e", "parents": [ "2b210adcb08c7966feeb8574cd90514f1e797ae9" ], "author": { "name": "Al Viro", "email": "viro@ftp.linux.org.uk", "time": "Sat Mar 29 03:09:38 2008 +0000" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Mar 30 14:20:23 2008 -0700" }, "message": "dma_page_list -\u003ebase_address is a userland pointer\n\nSigned-off-by: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "ec8670f1f795badedaa056a3a3245b9b82201747", "tree": "dbca9b272bcf13d7d4a4b86cfabdc396f685f488", "parents": [ "222ccf9ab838a1ca7163969fabd2cddc10403fb5" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Mar 01 07:51:29 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Mar 04 10:16:46 2008 -0700" }, "message": "dmaengine: fix sparse warning\n\ninclude/linux/dmaengine.h:364:2: warning: returning void-valued expression\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d4c56f97ff21df405d0cebe11f49e3c3c79662b5", "tree": "e6b0de433d7c985982ac12815998242a786d87b2", "parents": [ "0036731c88fdb5bf4f04a796a30b5e445fc57f54" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Feb 02 19:49:58 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 06 10:12:18 2008 -0700" }, "message": "async_tx: replace \u0027int_en\u0027 with operation preparation flags\n\nPass a full set of flags to drivers\u0027 per-operation \u0027prep\u0027 routines.\nCurrently the only flag passed is DMA_PREP_INTERRUPT. The expectation is\nthat arch-specific async_tx_find_channel() implementations can exploit this\ncapability to find the best channel for an operation.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nReviewed-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n" }, { "commit": "0036731c88fdb5bf4f04a796a30b5e445fc57f54", "tree": "66982e4a9fdb92fedadca35c0ccaa0b9a75e9d2e", "parents": [ "d909b347591a23c5a2c324fbccd4c9c966f31c67" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Feb 02 19:49:57 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 06 10:12:17 2008 -0700" }, "message": "async_tx: kill tx_set_src and tx_set_dest methods\n\nThe tx_set_src and tx_set_dest methods were originally implemented to allow\nan array of addresses to be passed down from async_xor to the dmaengine\ndriver while minimizing stack overhead. Removing these methods allows\ndrivers to have all transaction parameters available at \u0027prep\u0027 time, saves\ntwo function pointers in struct dma_async_tx_descriptor, and reduces the\nnumber of indirect branches..\n\nA consequence of moving this data to the \u0027prep\u0027 routine is that\nmulti-source routines like async_xor need temporary storage to convert an\narray of linear addresses into an array of dma addresses. In order to keep\nthe same stack footprint of the previous implementation the input array is\nreused as storage for the dma addresses. This requires that\nsizeof(dma_addr_t) be less than or equal to sizeof(void *). As a\nconsequence CONFIG_DMADEVICES now depends on !CONFIG_HIGHMEM64G. It also\nrequires that drivers be able to make descriptor resources available when\nthe \u0027prep\u0027 routine is polled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\n" }, { "commit": "fd3f8984f6fa1ad1a6c2283eef48ba6e5242bcc5", "tree": "12f69b5301ece00daff4a73aa9ed92e9e88d07a0", "parents": [ "ab690d9fedf5103bc3057bcd20555159f613b5f2" ], "author": { "name": "Joe Perches", "email": "joe@perches.com", "time": "Sun Feb 03 17:45:46 2008 +0200" }, "committer": { "name": "Adrian Bunk", "email": "bunk@kernel.org", "time": "Sun Feb 03 17:45:46 2008 +0200" }, "message": "include/linux/: Spelling fixes\n\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nSigned-off-by: Adrian Bunk \u003cbunk@kernel.org\u003e\n" }, { "commit": "891f78ea833edd4a1e524e15bfe297a7a84d81a0", "tree": "533f12df743c4adc6d2b40d048ffb7d16c93e591", "parents": [ "62ca8792560e5bd7dc09f54ed3523a7864f416c7" ], "author": { "name": "Tony Jones", "email": "tonyj@suse.de", "time": "Tue Sep 25 02:03:03 2007 +0200" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Thu Jan 24 20:40:05 2008 -0800" }, "message": "DMA: Convert from class_device to device for DMA engine\n\nSigned-off-by: Tony Jones \u003ctonyj@suse.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nCc: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nCc: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "d379b01e9087a582d58f4b678208a4f8d8376fe7", "tree": "155920bca93c18afba66b9d5acfecd359d5bec65", "parents": [ "7405f74badf46b5d023c5d2b670b4471525f6c91" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jul 09 11:56:42 2007 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 13 08:06:13 2007 -0700" }, "message": "dmaengine: make clients responsible for managing channels\n\nThe current implementation assumes that a channel will only be used by one\nclient at a time. In order to enable channel sharing the dmaengine core is\nchanged to a model where clients subscribe to channel-available-events.\nInstead of tracking how many channels a client wants and how many it has\nreceived the core just broadcasts the available channels and lets the\nclients optionally take a reference. The core learns about the clients\u0027\nneeds at dma_event_callback time.\n\nIn support of multiple operation types, clients can specify a capability\nmask to only be notified of channels that satisfy a certain set of\ncapabilities.\n\nChangelog:\n* removed DMA_TX_ARRAY_INIT, no longer needed\n* dma_client_chan_free -\u003e dma_chan_release: switch to global reference\n counting only at device unregistration time, before it was also happening\n at client unregistration time\n* clients now return dma_state_client to dmaengine (ack, dup, nak)\n* checkpatch.pl fixes\n* fixup merge with git-ioat\n\nCc: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7405f74badf46b5d023c5d2b670b4471525f6c91", "tree": "20dd20571637dba1c2b04c7b13ac208c33b5706b", "parents": [ "428ed6024fa74a271142f3257966e9b5e1cb37a1" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 02 11:10:43 2007 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 13 08:06:11 2007 -0700" }, "message": "dmaengine: refactor dmaengine around dma_async_tx_descriptor\n\nThe current dmaengine interface defines mutliple routines per operation,\ni.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding\nmore operation types (xor, crc, etc) to this model would result in an\nunmanageable number of method permutations.\n\n\tAre we really going to add a set of hooks for each DMA engine\n\twhizbang feature?\n\t\t- Jeff Garzik\n\nThe descriptor creation process is refactored using the new common\ndma_async_tx_descriptor structure. Instead of per driver\ndo_\u003coperation\u003e_\u003cdest\u003e_to_\u003csrc\u003e methods, drivers integrate\ndma_async_tx_descriptor into their private software descriptor and then\ndefine a \u0027prep\u0027 routine per operation. The prep routine allocates a\ndescriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines\nare valid. Descriptor creation and submission becomes:\n\nstruct dma_device *dev;\nstruct dma_chan *chan;\nstruct dma_async_tx_descriptor *tx;\n\ntx \u003d dev-\u003edevice_prep_dma_\u003coperation\u003e(chan, len, int_flag)\ntx-\u003etx_set_src(dma_addr_t, tx, index /* for multi-source ops */)\ntx-\u003etx_set_dest(dma_addr_t, tx, index)\ntx-\u003etx_submit(tx)\n\nIn addition to the refactoring, dma_async_tx_descriptor also lays the\ngroundwork for definining cross-channel-operation dependencies, and a\ncallback facility for asynchronous notification of operation completion.\n\nChangelog:\n* drop dma mapping methods, suggested by Chris Leech\n* fix ioat_dma_dependency_added, also caught by Andrew Morton\n* fix dma_sync_wait, change from Andrew Morton\n* uninline large functions, change from Andrew Morton\n* add tx-\u003ecallback \u003d NULL to dmaengine calls to interoperate with async_tx\n calls\n* hookup ioat_tx_submit\n* convert channel capabilities to a \u0027cpumask_t like\u0027 bitmap\n* removed DMA_TX_ARRAY_INIT, no longer needed\n* checkpatch.pl fixes\n* make set_src, set_dest, and tx_submit descriptor specific methods\n* fixup git-ioat merge\n* move group_list and phys to dma_async_tx_descriptor\n\nCc: Jeff Garzik \u003cjeff@garzik.org\u003e\nCc: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "fe4ada2d6f0b746246e9b5bf0f4f2e4d3a07d26e", "tree": "4087d9e0d655cc6b6e1b31f61edf40ee3549a650", "parents": [ "b0026624f1aa3e38a887cb483de61f104d600b97" ], "author": { "name": "Randy Dunlap", "email": "rdunlap@xenotime.net", "time": "Mon Jul 03 19:44:51 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Jul 03 19:44:51 2006 -0700" }, "message": "[IOAT]: fix header file kernel-doc\n\nFix kernel-doc problems in include/linux/dmaengine.h:\n- add some fields/parameters\n- expand some descriptions\n- fix typos\n\nSigned-off-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1c0f16e5cdff59f3b132a1b0c0d44a941f8813d2", "tree": "b2693f9e481381ae3e703afa3b68ad3531ea6645", "parents": [ "34af946a22724c4e2b204957f2b24b22a0fb121c" ], "author": { "name": "David Woodhouse", "email": "dwmw2@infradead.org", "time": "Tue Jun 27 02:53:56 2006 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Tue Jun 27 17:32:39 2006 -0700" }, "message": "[PATCH] Remove gratuitous inclusion of \u003clinux/config.h\u003e from \u003clinux/dmaengine.h\u003e\n\nWe include config.h on the compiler command line. There\u0027s no need for it\nto be included again.\n\nSigned-off-by: David Woodhouse \u003cdwmw2@infradead.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "de5506e155276d385712c2aa1c2d9a27cd4ed947", "tree": "219c30dab27b9aef2597d8735dfc19db8454849e", "parents": [ "db21733488f84a596faaad0d05430b3f51804692" ], "author": { "name": "Chris Leech", "email": "christopher.leech@intel.com", "time": "Tue May 23 17:50:37 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Jun 17 21:25:46 2006 -0700" }, "message": "[I/OAT]: Utility functions for offloading sk_buff to iovec copies\n\nProvides for pinning user space pages in memory, copying to iovecs,\nand copying from sk_buffs including fragmented and chained sk_buffs.\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c13c8260da3155f2cefb63b0d1b7dcdcb405c644", "tree": "ecfe02fa44a423a948f5fb5ad76497da2bb7a402", "parents": [ "427abfa28afedffadfca9dd8b067eb6d36bac53f" ], "author": { "name": "Chris Leech", "email": "christopher.leech@intel.com", "time": "Tue May 23 17:18:44 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Jun 17 21:18:43 2006 -0700" }, "message": "[I/OAT]: DMA memcpy subsystem\n\nProvides an API for offloading memory copies to DMA devices\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" } ] }