)]}' { "log": [ { "commit": "12679a2d7e3bfbdc7586e3e86d1ca90c46659363", "tree": "d9c00f2e599d1c3e04a349229a6a19906d01f99e", "parents": [ "1c036588772d01655d851f75dffc27c971e072e2", "b0df89868006517417251e02cc4ce5d4b0165885" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Mar 29 16:53:48 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Mar 29 16:53:48 2012 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.linaro.org/people/rmk/linux-arm\n\nPull more ARM updates from Russell King.\n\nThis got a fair number of conflicts with the \u003casm/system.h\u003e split, but\nalso with some other sparse-irq and header file include cleanups. They\nall looked pretty trivial, though.\n\n* \u0027for-linus\u0027 of git://git.linaro.org/people/rmk/linux-arm: (59 commits)\n ARM: fix Kconfig warning for HAVE_BPF_JIT\n ARM: 7361/1: provide XIP_VIRT_ADDR for no-MMU builds\n ARM: 7349/1: integrator: convert to sparse irqs\n ARM: 7259/3: net: JIT compiler for packet filters\n ARM: 7334/1: add jump label support\n ARM: 7333/2: jump label: detect %c support for ARM\n ARM: 7338/1: add support for early console output via semihosting\n ARM: use set_current_blocked() and block_sigmask()\n ARM: exec: remove redundant set_fs(USER_DS)\n ARM: 7332/1: extract out code patch function from kprobes\n ARM: 7331/1: extract out insn generation code from ftrace\n ARM: 7330/1: ftrace: use canonical Thumb-2 wide instruction format\n ARM: 7351/1: ftrace: remove useless memory checks\n ARM: 7316/1: kexec: EOI active and mask all interrupts in kexec crash path\n ARM: Versatile Express: add NO_IOPORT\n ARM: get rid of asm/irq.h in asm/prom.h\n ARM: 7319/1: Print debug info for SIGBUS in user faults\n ARM: 7318/1: gic: refactor irq_start assignment\n ARM: 7317/1: irq: avoid NULL check in for_each_irq_desc loop\n ARM: 7315/1: perf: add support for the Cortex-A7 PMU\n ...\n" }, { "commit": "7bf97e1d5a94b6a71815771bb9452fc2c022c966", "tree": "f89082dbd33a51a79c9a9c0dddb29e2b11b8207e", "parents": [ "30304e5a79d424eb2c8707b3ff0e9b8bf6ab3e8f", "c77c8a6fd3d57b586ff5ecb5ab5b32ca4f54fe75" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 28 14:08:46 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 28 14:08:46 2012 -0700" }, "message": "Merge tag \u0027gpio-for-linus\u0027 of git://git.secretlab.ca/git/linux-2.6\n\nPull GPIO changes for v3.4 from Grant Likely:\n \"Primarily gpio device driver changes with some minor side effects\n under arch/arm and arch/x86. Also includes a few core changes such as\n explicitly supporting (electrical) open source and open drain outputs\n and some help for parsing gpio devicetree properties.\"\n\nFix up context conflict due to Laxman Dewangan adding sleep control for\nthe tps65910 driver separately for gpio\u0027s and regulators.\n\n* tag \u0027gpio-for-linus\u0027 of git://git.secretlab.ca/git/linux-2.6: (34 commits)\n gpio/ep93xx: Remove unused inline function and useless pr_err message\n gpio/sodaville: Mark broken due to core irqdomain migration\n gpio/omap: fix redundant decoding of gpio offset\n gpio/omap: fix incorrect update to context.irqenable1\n gpio/omap: fix incorrect context restore logic in omap_gpio_runtime_*\n gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg\n gpio/omap: fix _set_gpio_irqenable implementation\n gpio/omap: fix trigger type to unsigned\n gpio/omap: fix wakeup_en register update in _set_gpio_wakeup()\n gpio: tegra: tegra_gpio_config shouldn\u0027t be __init\n gpio/davinci: fix enabling unbanked GPIO IRQs\n gpio/davinci: fix oops on unbanked gpio irq request\n gpio/omap: Fix section warning for omap_mpuio_alloc_gc()\n ARM: tegra: export tegra_gpio_{en,dis}able\n gpio/gpio-stmpe: Fix the value returned by _get_value routine\n Documentation/gpio.txt: Explain expected pinctrl interaction\n GPIO: LPC32xx: Add output reading to GPO P3\n GPIO: LPC32xx: Fix missing bit selection mask\n gpio/omap: fix wakeups on level-triggered GPIOs\n gpio/omap: Fix IRQ handling for SPARSE_IRQ\n ...\n" }, { "commit": "30304e5a79d424eb2c8707b3ff0e9b8bf6ab3e8f", "tree": "63968fb97b86861e31922515395feef8a110f884", "parents": [ "750f77064a290beb162352077b52c61b04bcae0e", "b8589e2a8065b8e7773742b60ae96b63b757bb69" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 28 13:56:35 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 28 13:56:35 2012 -0700" }, "message": "Merge tag \u0027mfd_3.4-1\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6\n\nPull MFD changes from Samuel Ortiz:\n - 4 new drivers: Freescale i.MX on-chip Anatop, Ricoh\u0027s RC5T583 and\n TI\u0027s TPS65090 and TPS65217.\n - New variants support (8420, 8520 ab9540), cleanups and bug fixes for\n the abx500 and db8500 ST-E chipsets.\n - Some minor fixes and update for the wm8994 from Mark.\n - The beginning of a long term TWL cleanup effort coming from the TI\n folks.\n - Various fixes and cleanups for the s5m, TPS659xx, pm860x, and MAX8997\n drivers.\n\nFix up trivial conflicts due to duplicate patches and header file\ncleanups (\u003clinux/device.h\u003e removal etc).\n\n* tag \u0027mfd_3.4-1\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (97 commits)\n gpio/twl: Add DT support to gpio-twl4030 driver\n gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ support\n mfd: Detach twl6040 from the pmic mfd driver\n mfd: Replace twl-* pr_ macros by the dev_ equivalent and do various cleanups\n mfd: Micro-optimization on twl4030 IRQ handler\n mfd: Make twl4030 SIH SPARSE_IRQ capable\n mfd: Move twl-core IRQ allocation into twl[4030|6030]-irq files\n mfd: Remove references already defineid in header file from twl-core\n mfd: Remove unneeded header from twl-core\n mfd: Make twl-core not depend on pdata-\u003eirq_base/end\n ARM: OMAP2+: board-omap4-*: Do not use anymore TWL6030_IRQ_BASE in board files\n mfd: Return twl6030_mmc_card_detect IRQ for board setup\n Revert \"mfd: Add platform data for MAX8997 haptic driver\"\n mfd: Add support for TPS65090\n mfd: Add some da9052-i2c section annotations\n mfd: Build rtc5t583 only if I2C config is selected to y.\n mfd: Add anatop mfd driver\n mfd: Fix compilation error in tps65910.h\n mfd: Add 8420 variant to db8500-prcmu\n mfd: Add 8520 PRCMU variant to db8500-prcmu\n ...\n" }, { "commit": "ff877c498eb2f9c4ea386270642e383bc867f63c", "tree": "ae37e2f57ac6e6d19d01b7380f77db2a1c6c5b14", "parents": [ "529b73fc0a9764050dcc597f4851728e8ff59165", "1f5b7dcfdad3840d4bce27ab0b3cc8f376b81544" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 28 12:17:06 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 28 12:17:06 2012 -0700" }, "message": "Merge tag \u0027drivers2\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc\n\nPull \"ARM: More SoC driver updates\" from Olof Johansson:\n \"This branch contains a handful of driver updates, mostly to the\n LPC32xx platform but also for Samsung EXYNOS and Davinci.\n\n It had a few context conflicts against patches already merged through\n fixes-non-critical. We should have resolved this early during the\n development cycle by pulling them in as a dependency, instead I did it\n after the fact this time.\"\n\n* tag \u0027drivers2\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:\n gpio/samsung: use ioremap() for EXYNOS4 GPIOlib\n gpio/samsung: add support GPIOlib for EXYNOS5250\n ARM: EXYNOS: add support GPIO for EXYNOS5250\n ARM: LPC32xx: Ethernet support\n ARM: LPC32xx: USB Support\n ARM: davinci: dm644x evm: add support for VPBE display\n ARM: davinci: dm644x: add support for v4l2 video display\n ARM: EXYNOS: Hook up JPEG PD to generic PD infrastructure\n ARM: EXYNOS: Hook up G2D PD to generic PD infrastructure\n arm: lpc32xx: phy3250: add rtc \u0026 touch device\n ARM: LPC32xx: clock.c: Clock registration fixes\n ARM: LPC32xx: clock.c: jiffies wrapping\n ARM: LPC32xx: clock.c: Missing header file\n ARM: LPC32XX: Remove broken non-static declaration\n ARM: LPC32xx: clock.c: Fix mutex lock issues\n ARM: LPC32xx: clock.c: warning fix\n ARM: LPC32xx: Added lpc32xx_defconfig\n" }, { "commit": "9e4db1c3eed55c22328d8022c2c80adb3093833f", "tree": "9643545e6bd182f1d3e19942f590a6a1e3198320", "parents": [ "de8856d2c11f562c60ed9340a83db4a4f829a6e6", "aae528d9a8ad79d4b21b1b723abc9447fdb0d200" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Mar 27 18:17:02 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Mar 27 18:17:02 2012 -0700" }, "message": "Merge branch \u0027platforms\u0027 of git://git.linaro.org/people/rmk/linux-arm\n\nPull ARM platform updates from Russell King:\n \"This covers platform stuff for platforms I have a direct interest in\n (iow, I have the hardware). Essentially:\n - as we no longer support any other Acorn platforms other than RiscPC\n anymore, we can collect all that code into mach-rpc.\n - convert Acorn expansion card stuff to use IRQ allocation functions,\n and get rid of NO_IRQ from there.\n - cleanups to the ebsa110 platform to move some private stuff out of\n its header files.\n - large amount of SA11x0 updates:\n - conversion of private DMA implementation to DMA engine support\n (this actually gives us greater flexibility in drivers over the old\n API.)\n - re-worked ucb1x00 updates - convert to genirq, remove sa11x0\n dependencies, fix various minor issues\n - move platform specific sa11x0 framebuffer data into platform files\n in arch/arm instead of keeping this in the driver itself\n - update sa11x0 IrDA driver for DMA engine, and allow it to use DMA\n for SIR transmissions as well as FIR\n - rework sa1111 support for genirq, and irq allocation\n - fix sa1111 IRQ support so it works again\n - use sparse IRQ support\n\n After this, I have one more pull request remaining from my current\n set, which I think is going to be the most problematical as it\n generates 8 conflicts.\"\n\nFixed up the trivial conflict in arch/arm/mach-rpc/Makefile as per\nRussell.\n\n* \u0027platforms\u0027 of git://git.linaro.org/people/rmk/linux-arm: (125 commits)\n ARM: 7343/1: sa11x0: convert to sparse IRQ\n ARM: 7342/2: sa1100: prepare for sparse irq conversion\n ARM: 7341/1: input: prepare jornada720 keyboard and ts for sa11x0 sparse irq\n ARM: 7340/1: rtc: sa1100: include mach/irqs.h instead of asm/irq.h\n ARM: sa11x0: remove unused DMA controller definitions\n ARM: sa11x0: remove old SoC private DMA driver\n USB: sa1111: add hcd .reset method\n USB: sa1111: add OHCI shutdown methods\n USB: sa1111: reorganize ohci-sa1111.c\n USB: sa1111: get rid of nasty printk(KERN_DEBUG \"%s: ...\", __FILE__)\n USB: sa1111: sparse and checkpatch cleanups\n ARM: sa11x0: don\u0027t static map sa1111\n ARM: sa1111: use dev_err() rather than printk()\n ARM: sa1111: cleanup sub-device registration and unregistration\n ARM: sa1111: only setup DMA for DMA capable devices\n ARM: sa1111: register sa1111 devices with dmabounce in bus notifier\n ARM: sa1111: move USB interface register definitions to ohci-sa1111.c\n ARM: sa1111: move PCMCIA interface register definitions to sa1111_generic.c\n ARM: sa1111: move PS/2 interface register definitions to sa1111p2.c\n ARM: sa1111: delete unused physical GPIO register definitions\n ...\n" }, { "commit": "34800598b2eebe061445216473b1e4c2ff5cba99", "tree": "a6d0eb6fe45d9480888d7ddb34840e172ed80e56", "parents": [ "46b407ca4a6149c8d27fcec1881d4f184bec7c77", "511f1cb6d426938fabf9c6d69ce4861b66ffd919" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Mar 27 16:41:24 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Mar 27 16:41:24 2012 -0700" }, "message": "Merge tag \u0027drivers\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc\n\nPull \"ARM: driver specific updates\" from Arnd Bergmann:\n \"These are all specific to some driver. They are typically the\n platform side of a change in the drivers directory, such as adding a\n new driver or extending the interface to the platform. In cases where\n there is no maintainer for the driver, or the maintainer prefers to\n have the platform changes in the same branch as the driver changes,\n the patches to the drivers are included as well.\n\n A much smaller set of driver updates that depend on other branches\n getting merged first will be sent later.\n\n The new export of tegra_chip_uid conflicts with other changes in\n fuse.c. In rtc-sa1100.c, the global removal of IRQF_DISABLED\n conflicts with the cleanup of the interrupt handling of that driver.\n\n Signed-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\"\n\nFixed up aforementioned trivial conflicts.\n\n* tag \u0027drivers\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (94 commits)\n ARM: SAMSUNG: change the name from s3c-sdhci to exynos4-sdhci\n mmc: sdhci-s3c: add platform data for the second capability\n ARM: SAMSUNG: support the second capability for samsung-soc\n ARM: EXYNOS: add support DMA for EXYNOS4X12 SoC\n ARM: EXYNOS: Add apb_pclk clkdev entry for mdma1\n ARM: EXYNOS: Enable MDMA driver\n regulator: Remove bq24022 regulator driver\n rtc: sa1100: add OF support\n pxa: magician/hx4700: Convert to gpio-regulator from bq24022\n ARM: OMAP3+: SmartReflex: fix error handling\n ARM: OMAP3+: SmartReflex: fix the use of debugfs_create_* API\n ARM: OMAP3+: SmartReflex: micro-optimization for sanity check\n ARM: OMAP3+: SmartReflex: misc cleanups\n ARM: OMAP3+: SmartReflex: move late_initcall() closer to its argument\n ARM: OMAP3+: SmartReflex: add missing platform_set_drvdata()\n ARM: OMAP3+: hwmod: add SmartReflex IRQs\n ARM: OMAP3+: SmartReflex: clear ERRCONFIG_VPBOUNDINTST only on a need\n ARM: OMAP3+: SmartReflex: Fix status masking in ERRCONFIG register\n ARM: OMAP3+: SmartReflex: Add a shutdown hook\n ARM: OMAP3+: SmartReflex Class3: disable errorgen before disable VP\n ...\n\nConflicts:\n\tarch/arm/mach-tegra/Makefile\n\tarch/arm/mach-tegra/fuse.c\n\tdrivers/rtc/rtc-sa1100.c\n" }, { "commit": "d61b7a572b292e2be409e13b4b3adf475f18fb29", "tree": "e9d30390860147136c05e66abf1edda1bc5b0562", "parents": [ "18d9946bc7e2252fe3c0f2f609ac383c627edefd", "f4e2467bad53023589cbff18dd1ab6e0aa3f004c" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Mar 27 16:03:32 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Mar 27 16:03:32 2012 -0700" }, "message": "Merge tag \u0027cleanup\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc\n\nPull \"ARM: global cleanups\" from Arnd Bergmann:\n \"Quite a bit of code gets removed, and some stuff moved around, mostly\n the old samsung s3c24xx stuff. There should be no functional changes\n in this series otherwise. Some cleanups have dependencies on other\n arm-soc branches and will be sent in the second round.\n\n Signed-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\"\n\nFixed up trivial conflicts mainly due to #include\u0027s being changes on\nboth sides.\n\n* tag \u0027cleanup\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (121 commits)\n ep93xx: Remove unnecessary includes of ep93xx-regs.h\n ep93xx: Move EP93XX_SYSCON defines to SoC private header\n ep93xx: Move crunch code to mach-ep93xx directory\n ep93xx: Make syscon access functions private to SoC\n ep93xx: Configure GPIO ports in core code\n ep93xx: Move peripheral defines to local SoC header\n ep93xx: Convert the watchdog driver into a platform device.\n ep93xx: Use ioremap for backlight driver\n ep93xx: Move GPIO defines to gpio-ep93xx.h\n ep93xx: Don\u0027t use system controller defines in audio drivers\n ep93xx: Move PHYS_BASE defines to local SoC header file\n ARM: EXYNOS: Add clock register addresses for EXYNOS4X12 bus devfreq driver\n ARM: EXYNOS: add clock registers for exynos4x12-cpufreq\n PM / devfreq: update the name of EXYNOS clock registers that were omitted\n PM / devfreq: update the name of EXYNOS clock register\n ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock\n ARM: EXYNOS: use static declaration on regarding clock\n ARM: EXYNOS: replace clock.c for other new EXYNOS SoCs\n ARM: OMAP2+: Fix build error after merge\n ARM: S3C24XX: remove call to s3c24xx_setup_clocks\n ...\n" }, { "commit": "c77c8a6fd3d57b586ff5ecb5ab5b32ca4f54fe75", "tree": "b679d557b1047c6333c5fe0f5a87aedd7f654514", "parents": [ "8194c7c4d5ea14d819bb2eab6a23b07331b734d8" ], "author": { "name": "H Hartley Sweeten", "email": "hartleys@visionengravers.com", "time": "Wed Mar 21 11:13:27 2012 -0700" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Sun Mar 25 21:25:56 2012 -0700" }, "message": "gpio/ep93xx: Remove unused inline function and useless pr_err message\n\nMinor removal of an unused inline function and a useless pr_err message.\n\nSigned-off-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "f314f33be77d6a48ae19748e3dc4a6657042b525", "tree": "6943191f7d9052c51dd66c4cdb99e5a265d2d0de", "parents": [ "3638dd2b45ceac2e9526f0ee83b0923db3546979" ], "author": { "name": "Rob Herring", "email": "rob.herring@calxeda.com", "time": "Fri Feb 24 00:06:51 2012 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Mar 25 23:57:20 2012 +0100" }, "message": "ARM: 7342/2: sa1100: prepare for sparse irq conversion\n\nIn preparation to convert SA1100 to sparse irq, set .nr_irqs for each machine\nand explicitly include mach/irqs.h as needed.\n\nSigned-off-by: Rob Herring \u003crob.herring@calxeda.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "8194c7c4d5ea14d819bb2eab6a23b07331b734d8", "tree": "e7fbfeba06812b54036e67e39abb15dc18b96320", "parents": [ "5430528b8bfa2c4d10df3bd59b73ab5faf6fa6cb" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Fri Mar 23 08:56:10 2012 +0000" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Fri Mar 23 08:56:10 2012 +0000" }, "message": "gpio/sodaville: Mark broken due to core irqdomain migration\n\nThe sodaville driver doesn\u0027t build anymore due to the transition to\ncommon irq_domain in the core code. It needs to be reworked, but\nthe rework isn\u0027t trivial. Since this is a new driver anyway for\nv3.4, mark it as broken now and a fixup patch can re-enable it when\nthe rework change has been tested.\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "5430528b8bfa2c4d10df3bd59b73ab5faf6fa6cb", "tree": "660dbb75b3f91b07b1c21ec3d44d70d606bb648f", "parents": [ "b0092f2665be3dd04f923d09a6a0deeddb4e96ec", "7fcca715de3438b8fc3c8a144702f3a95c8ff63c" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Fri Mar 23 08:48:06 2012 +0000" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Fri Mar 23 08:48:06 2012 +0000" }, "message": "Merge branch \u0027for_3.4/fixes/gpio-2\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into gpio/next\n" }, { "commit": "b8589e2a8065b8e7773742b60ae96b63b757bb69", "tree": "ad20ba6cc9205cbaf0e99c444cfca22e1e44db17", "parents": [ "2d9dd99b4470a2ef05509435465e055f50456330" ], "author": { "name": "Benoit Cousson", "email": "b-cousson@ti.com", "time": "Wed Feb 29 22:51:32 2012 +0100" }, "committer": { "name": "Samuel Ortiz", "email": "sameo@linux.intel.com", "time": "Thu Mar 22 13:05:55 2012 +0100" }, "message": "gpio/twl: Add DT support to gpio-twl4030 driver\n\nAdd the DT support for the I2C GPIO expander inside the twl4030.\n\nNote: The pdata parameters still have to be properly adapted using\ndedicated bindings.\n\nSigned-off-by: Benoit Cousson \u003cb-cousson@ti.com\u003e\nAcked-by: Felipe Balbi \u003cbalbi@ti.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nSigned-off-by: Samuel Ortiz \u003csameo@linux.intel.com\u003e\n" }, { "commit": "2d9dd99b4470a2ef05509435465e055f50456330", "tree": "a0a3ff0ef75ac90324131e9785cb389861272b4e", "parents": [ "364cedb2f97063d649b2950c099883b89b60c000" ], "author": { "name": "Benoit Cousson", "email": "b-cousson@ti.com", "time": "Wed Feb 29 22:48:32 2012 +0100" }, "committer": { "name": "Samuel Ortiz", "email": "sameo@linux.intel.com", "time": "Thu Mar 22 13:05:53 2012 +0100" }, "message": "gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ support\n\nDo not use the board pdata for irq_base, but allocate them dynamically\nto allow a proper support of SPARSE_IRQ.\n\nFix an unneeded line wrap.\n\nSigned-off-by: Benoit Cousson \u003cb-cousson@ti.com\u003e\nAcked-by: Felipe Balbi \u003cbalbi@ti.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nSigned-off-by: Samuel Ortiz \u003csameo@linux.intel.com\u003e\n" }, { "commit": "f01b1f90bf46ddaf2a68215a9489364c974e5689", "tree": "3beb31a6777b16926d81eb10d1ec0c901a175503", "parents": [ "78518ffa08fceee42d61359303c58bdd0a82033f" ], "author": { "name": "Benoit Cousson", "email": "b-cousson@ti.com", "time": "Wed Feb 29 22:38:06 2012 +0100" }, "committer": { "name": "Samuel Ortiz", "email": "sameo@linux.intel.com", "time": "Thu Mar 22 13:04:54 2012 +0100" }, "message": "mfd: Make twl4030 SIH SPARSE_IRQ capable\n\ntwl4030 is using a two level irq controllers infrastruture.\nSo far, only the first level was using dynamic irq_desc allocation\nto be able to have irq_domain support for device tree.\nThere is a need to allocate separate irq_descs for the SIH too to\navoid hacking the first level with interrupts from the second level.\n\nAdd an irq_base parameter to allow the caller to provide the base from\npdata or from dynamic allocation.\n\nAffect TWL4030_NR_IRQS to the twl-core IRQs only.\n\nMoreover that will allow the extraction of the of_node pointer for further\nDevice Tree conversion.\n\nSigned-off-by: Felipe Balbi \u003cbalbi@ti.com\u003e\nSigned-off-by: Benoit Cousson \u003cb-cousson@ti.com\u003e\nSigned-off-by: Samuel Ortiz \u003csameo@linux.intel.com\u003e\n" }, { "commit": "5375871d432ae9fc581014ac117b96aaee3cd0c7", "tree": "be98e8255b0f927fb920fb532a598b93fa140dbe", "parents": [ "b57cb7231b2ce52d3dda14a7b417ae125fb2eb97", "dfbc2d75c1bd47c3186fa91f1655ea2f3825b0ec" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 21 18:55:10 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 21 18:55:10 2012 -0700" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc\n\nPull powerpc merge from Benjamin Herrenschmidt:\n \"Here\u0027s the powerpc batch for this merge window. It is going to be a\n bit more nasty than usual as in touching things outside of\n arch/powerpc mostly due to the big iSeriesectomy :-) We finally got\n rid of the bugger (legacy iSeries support) which was a PITA to\n maintain and that nobody really used anymore.\n\n Here are some of the highlights:\n\n - Legacy iSeries is gone. Thanks Stephen ! There\u0027s still some bits\n and pieces remaining if you do a grep -ir series arch/powerpc but\n they are harmless and will be removed in the next few weeks\n hopefully.\n\n - The \u0027fadump\u0027 functionality (Firmware Assisted Dump) replaces the\n previous (equivalent) \"pHyp assisted dump\"... it\u0027s a rewrite of a\n mechanism to get the hypervisor to do crash dumps on pSeries, the\n new implementation hopefully being much more reliable. Thanks\n Mahesh Salgaonkar.\n\n - The \"EEH\" code (pSeries PCI error handling \u0026 recovery) got a big\n spring cleaning, motivated by the need to be able to implement a\n new backend for it on top of some new different type of firwmare.\n\n The work isn\u0027t complete yet, but a good chunk of the cleanups is\n there. Note that this adds a field to struct device_node which is\n not very nice and which Grant objects to. I will have a patch soon\n that moves that to a powerpc private data structure (hopefully\n before rc1) and we\u0027ll improve things further later on (hopefully\n getting rid of the need for that pointer completely). Thanks Gavin\n Shan.\n\n - I dug into our exception \u0026 interrupt handling code to improve the\n way we do lazy interrupt handling (and make it work properly with\n \"edge\" triggered interrupt sources), and while at it found \u0026 fixed\n a wagon of issues in those areas, including adding support for page\n fault retry \u0026 fatal signals on page faults.\n\n - Your usual random batch of small fixes \u0026 updates, including a bunch\n of new embedded boards, both Freescale and APM based ones, etc...\"\n\nI fixed up some conflicts with the generalized irq-domain changes from\nGrant Likely, hopefully correctly.\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (141 commits)\n powerpc/ps3: Do not adjust the wrapper load address\n powerpc: Remove the rest of the legacy iSeries include files\n powerpc: Remove the remaining CONFIG_PPC_ISERIES pieces\n init: Remove CONFIG_PPC_ISERIES\n powerpc: Remove FW_FEATURE ISERIES from arch code\n tty/hvc_vio: FW_FEATURE_ISERIES is no longer selectable\n powerpc/spufs: Fix double unlocks\n powerpc/5200: convert mpc5200 to use of_platform_populate()\n powerpc/mpc5200: add options to mpc5200_defconfig\n powerpc/mpc52xx: add a4m072 board support\n powerpc/mpc5200: update mpc5200_defconfig to fit for charon board\n Documentation/powerpc/mpc52xx.txt: Checkpatch cleanup\n powerpc/44x: Add additional device support for APM821xx SoC and Bluestone board\n powerpc/44x: Add support PCI-E for APM821xx SoC and Bluestone board\n MAINTAINERS: Update PowerPC 4xx tree\n powerpc/44x: The bug fixed support for APM821xx SoC and Bluestone board\n powerpc: document the FSL MPIC message register binding\n powerpc: add support for MPIC message register API\n powerpc/fsl: Added aliased MSIIR register address to MSI node in dts\n powerpc/85xx: mpc8548cds - add 36-bit dts\n ...\n" }, { "commit": "7fcca715de3438b8fc3c8a144702f3a95c8ff63c", "tree": "aef934198309bad7f0fca3a392e8360185d40e7d", "parents": [ "2a900eb74c123a21054836ab2c63d6ff46f854c6" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 27 11:46:09 2012 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Wed Mar 21 10:21:24 2012 +0530" }, "message": "gpio/omap: fix redundant decoding of gpio offset\n\nIn gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of\nun-necessary operation to compute gpio mask. The gpio offset passed\nto gpio_get() is sufficient to do that.\n\nHere is Russell\u0027s original comment:\nCan someone explain to me this:\n\nstatic int _get_gpio_datain(struct gpio_bank *bank, int gpio)\n{\n void __iomem *reg \u003d bank-\u003ebase + bank-\u003eregs-\u003edatain;\n\n return (__raw_readl(reg) \u0026 GPIO_BIT(bank, gpio)) !\u003d 0;\n}\n\nstatic int gpio_get(struct gpio_chip *chip, unsigned offset)\n{\n struct gpio_bank *bank \u003d container_of(chip, struct gpio_bank, chip);\n void __iomem *reg \u003d bank-\u003ebase;\n int gpio \u003d chip-\u003ebase + offset;\n u32 mask \u003d GPIO_BIT(bank, gpio);\n\n if (gpio_is_input(bank, mask))\n return _get_gpio_datain(bank, gpio);\n else\n return _get_gpio_dataout(bank, gpio);\n}\n\nGiven that bank-\u003ewidth on OMAP is either 32 or 16, and GPIO numbers for\nany GPIO chip are always aligned to 32 or 16, why does this code bother\nadding the chips base gpio number and then modulo the width?\n\nSurely this means if - for argument sake - you registered a GPIO chip\nwith 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0\nbit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be\nchip 1 bit 0..7.\n\nHowever, if you registered a GPIO chip with 16 lines first, it would\nmean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be\nchip 1 bit 0..15.\n\nSurely this kind of behaviour is not intended?\n\nIs there a reason why the bitmask can\u0027t just be (1 \u003c\u003c offset) where\noffset is passed into these functions as GPIO number - chip-\u003ebase ?\n\nReported-by: Russell King - ARM Linux \u003clinux@arm.linux.org.uk\u003e\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "2a900eb74c123a21054836ab2c63d6ff46f854c6", "tree": "1607c091f750be0704c00d7e6f0446087f8659cf", "parents": [ "960edffe29dfd845ee532ee51398592cba96d701" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Mar 06 12:08:16 2012 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Wed Mar 21 10:18:54 2012 +0530" }, "message": "gpio/omap: fix incorrect update to context.irqenable1\n\nIn _enable_gpio_irqbank() when bank-\u003eregs-\u003eset_irqenable is TRUE,\ngpio_mask can be directly set by writing to set_irqenable register\nwithout overwriting current value. In order to ensure the same is\nstored in context.irqenable1, we must avoid overwriting it with\ngpio_mask at the end of the function. Instead, update irqenable1\nappropriately by OR\u0027ing with gpio_mask.\nFor the case where bank-\u003eregs-\u003eset_irqenable is FALSE, irqenable1\ncan be directly overwritten with \u0027l\u0027 which holds correct computed\nvalue.\n if (bank-\u003eregs-\u003eset_irqenable) {\n reg +\u003d bank-\u003eregs-\u003eset_irqenable;\n l \u003d gpio_mask;\n } else {\n reg +\u003d bank-\u003eregs-\u003eirqenable;\n l \u003d __raw_readl(reg);\n if (bank-\u003eregs-\u003eirqenable_inv)\n l \u0026\u003d ~gpio_mask;\n else\n l |\u003d gpio_mask;\n }\n\nMake similar change for _disable_gpio_irqbank().\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "960edffe29dfd845ee532ee51398592cba96d701", "tree": "6763cad852af2d069335a2398e7978144ac4c812", "parents": [ "2c836f7ea5e7b5eec2a798e02b1d76ea791fa094" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Mar 05 16:00:54 2012 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Mar 20 15:32:46 2012 +0530" }, "message": "gpio/omap: fix incorrect context restore logic in omap_gpio_runtime_*\n\nIn omap_gpio_runtime_suspend/resume() the context save/restore should\nbe independent of bank-\u003eenabled_non_wakeup_gpios. This was preventing\ncontext restore of GPIO lines which are not wakeup enabled.\n\nReported-by: Govindraj Raja \u003cgovindraj.raja@ti.com\u003e\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "2c836f7ea5e7b5eec2a798e02b1d76ea791fa094", "tree": "27c9f53b677bcea98198a0eb196b13af1d32dd9d", "parents": [ "8276536cec38bc6bde30d0aa67716f22b9b9705a" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Fri Mar 02 12:52:52 2012 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Mar 20 15:29:52 2012 +0530" }, "message": "gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg\n\nThere are two functions, _set_gpio_dataout_reg() and _set_gpio_dataout_mask()\nwhich writes to dataout register and the dataout context must be saved.\nIt is missing in the first function, _set_gpio_dataout_reg(). Fix this.\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "8276536cec38bc6bde30d0aa67716f22b9b9705a", "tree": "d403517a6f691daa13cb6245930b3219b893094a", "parents": [ "00ece7e4826e631565eae089d3c813120c6535ef" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Fri Nov 25 15:27:37 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Mar 20 15:29:09 2012 +0530" }, "message": "gpio/omap: fix _set_gpio_irqenable implementation\n\nThis function should be capable of both enabling and disabling interrupts\nbased upon the *enable* parameter. Right now the function only enables\nthe interrupt and *enable* is not used at all. So add the interrupt\ndisable capability also using the parameter.\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Felipe Balbi \u003cbalbi@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "00ece7e4826e631565eae089d3c813120c6535ef", "tree": "16bbc4ff0a13bb03fde0a4c7d17e4e6c5d74d147", "parents": [ "381a752f291763bd6971521fa44c76ad9e937f7b" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Fri Nov 25 15:41:06 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Mar 20 15:29:04 2012 +0530" }, "message": "gpio/omap: fix trigger type to unsigned\n\nThe GPIO trigger parameter is of type unsigned.\nenum {\n IRQ_TYPE_NONE \u003d 0x00000000,\n IRQ_TYPE_EDGE_RISING \u003d 0x00000001,\n IRQ_TYPE_EDGE_FALLING \u003d 0x00000002,\n IRQ_TYPE_EDGE_BOTH \u003d (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),\n IRQ_TYPE_LEVEL_HIGH \u003d 0x00000004,\n IRQ_TYPE_LEVEL_LOW \u003d 0x00000008,\n IRQ_TYPE_LEVEL_MASK \u003d (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),\n IRQ_TYPE_SENSE_MASK \u003d 0x0000000f,\n\n IRQ_TYPE_PROBE \u003d 0x00000010,\n...\n};\nEven though gpio_irq_type(struct irq_data *d, unsigned type) has the right type\nof parameter, the subsequent called functions set_gpio_triggering() and\nset_gpio_trigger() wrongly makes it signed integer. Fix this.\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Felipe Balbi \u003cbalbi@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "381a752f291763bd6971521fa44c76ad9e937f7b", "tree": "b8d934798fbc29b0bac9c81642eb24feec31f5af", "parents": [ "81b279d80a63628e580c71a31d30a8c3b3047ad4" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Wed Feb 29 21:49:21 2012 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Mar 20 15:28:58 2012 +0530" }, "message": "gpio/omap: fix wakeup_en register update in _set_gpio_wakeup()\n\nThere are two ways through which wakeup_en register can be programmed\nusing gpiolib APIs as shown below. It is seen that in the second case\nin _set_gpio_wakeup(), even though bank-\u003esuspend_wakeup is updated\ncorrectly, its value is not programmed in wakeup_en register. Fix this.\n\nirq_set_type()-\u003egpio_irq_type()-\u003e_set_gpio_triggering()-\u003eset_gpio_trigger()\nirq_set_wake()-\u003egpio_wake_enable()-\u003e_set_gpio_wakeup()\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "b0092f2665be3dd04f923d09a6a0deeddb4e96ec", "tree": "e741e9d997aaf673b5955fa469b7d8bd61b38895", "parents": [ "81b279d80a63628e580c71a31d30a8c3b3047ad4" ], "author": { "name": "Stephen Warren", "email": "swarren@wwwdotorg.org", "time": "Mon Mar 19 11:36:00 2012 -0600" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 19 21:49:41 2012 +0000" }, "message": "gpio: tegra: tegra_gpio_config shouldn\u0027t be __init\n\nThis function is called from non-__init context, just like\ntegra_gpio_enable()/disable(). Remove the __init annotation to avoid\nsection mismatch warnings during compile.\n\nSigned-off-by: Stephen Warren \u003cswarren@wwwdotorg.org\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "e041013ac0df7fc7dea73c9ca73a33ab5b48d155", "tree": "223d3cc0558010519456af6caffa0df1fd4cf03f", "parents": [ "44b24b74abc37e3c0f28c8288178056f10074863" ], "author": { "name": "Martyn Welch", "email": "martyn.welch@ge.com", "time": "Mon Mar 12 17:13:00 2012 +0000" }, "committer": { "name": "Kumar Gala", "email": "galak@kernel.crashing.org", "time": "Fri Mar 16 11:15:48 2012 -0500" }, "message": "powerpc/85xx: Board support for GE IMP3A\n\nInitial board support for the GE IMP3A, a 3U compactPCI card with a p2020\nprocessor.\n\nSigned-off-by: Martyn Welch \u003cmartyn.welch@ge.com\u003e\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n" }, { "commit": "6518bb69f463446a1552f52093cc699497f18fe0", "tree": "0630ca895b251cf06eb88321fb9502b78bd7aa58", "parents": [ "330bbf485447c0cf127750eb7d68d43a73f59356" ], "author": { "name": "Martyn Welch", "email": "martyn.welch@ge.com", "time": "Mon Mar 12 17:12:58 2012 +0000" }, "committer": { "name": "Kumar Gala", "email": "galak@kernel.crashing.org", "time": "Fri Mar 16 11:08:08 2012 -0500" }, "message": "gpio: Move GE GPIO driver to reside within GPIO subsystem\n\nThe GE GPIO driver provides basic support (set direction, read/write state)\nfor the GPIO provided on some GE single board computers. This patch moves\nthe driver from the 86xx specific platform directrory to the GPIO subsystem\nso that it can be used on non-86xx boards.\n\nSigned-off-by: Martyn Welch \u003cmartyn.welch@ge.com\u003e\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n" }, { "commit": "4788d72ce6c0d71220c06a242f935a056eccf424", "tree": "851ba5c54b4889b78b2a217c285e87c9e73536d3", "parents": [ "e594a97c8c74533ec105b2ac9194217e918f172f", "d39c815278bef7ce896100d8b385c81ed5cac015" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Thu Mar 15 20:50:16 2012 +0000" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Thu Mar 15 20:50:16 2012 +0000" }, "message": "Merge branch \u0027next/soc-exynos5250-gpio\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers\n\n* \u0027next/soc-exynos5250-gpio\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (201 commits)\n gpio/samsung: use ioremap() for EXYNOS4 GPIOlib\n gpio/samsung: add support GPIOlib for EXYNOS5250\n ARM: EXYNOS: add support GPIO for EXYNOS5250\n(update to v3.3-rc7)\n\nConflicts:\n\tarch/arm/mach-pxa/pxa25x.c\n\tarch/arm/mach-pxa/pxa27x.c\n\nThe dummy clock for the pxa rtc in those files keeps getting added and\nremoved in various trees. Apparently removing is the correct solution.\n\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "f4e2467bad53023589cbff18dd1ab6e0aa3f004c", "tree": "8d7abbf418eabd25bbcdc9b6de2f8216d2eaa616", "parents": [ "e3643b77de143c5548ec93abd8aa68f4123295ea", "a6de3df4f172e124280d88e617ee7d29f7af970b" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Thu Mar 15 15:19:05 2012 +0000" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Thu Mar 15 15:20:07 2012 +0000" }, "message": "Merge branch \u0027ep93xx-for-arm-soc\u0027 of git://github.com/RyanMallon/linux-2.6 into next/cleanup\n\n* \u0027ep93xx-for-arm-soc\u0027 of git://github.com/RyanMallon/linux-2.6:\n ep93xx: Remove unnecessary includes of ep93xx-regs.h\n ep93xx: Move EP93XX_SYSCON defines to SoC private header\n ep93xx: Move crunch code to mach-ep93xx directory\n ep93xx: Make syscon access functions private to SoC\n ep93xx: Configure GPIO ports in core code\n ep93xx: Move peripheral defines to local SoC header\n ep93xx: Convert the watchdog driver into a platform device.\n ep93xx: Use ioremap for backlight driver\n ep93xx: Move GPIO defines to gpio-ep93xx.h\n ep93xx: Don\u0027t use system controller defines in audio drivers\n ep93xx: Move PHYS_BASE defines to local SoC header file\n\n(update to v3.3-rc7)\n\nConflicts:\n\tarch/arm/mach-s3c2440/common.h\n" }, { "commit": "d39c815278bef7ce896100d8b385c81ed5cac015", "tree": "997fb400741a1a42828e0d57a2db67d7fb40d1db", "parents": [ "a9696d840ed503da6458335bdcd4defbeb480ea7" ], "author": { "name": "Sangsu Park", "email": "sangsu4u.park@samsung.com", "time": "Mon Mar 12 16:23:33 2012 -0700" }, "committer": { "name": "Kukjin Kim", "email": "kgene.kim@samsung.com", "time": "Wed Mar 14 06:51:35 2012 -0700" }, "message": "gpio/samsung: use ioremap() for EXYNOS4 GPIOlib\n\nThis patch changes to use ioremap() for EXYNOS4210\nso that we can drop the static mapping for EXYNOS\nSoCs.\n\nNote: Will be updated for all of Samsung GPIOlibs\nto use ioremap() next time.\n\nSigned-off-by: Sangsu Park \u003csangsu4u.park@samsung.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nSigned-off-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\n" }, { "commit": "a9696d840ed503da6458335bdcd4defbeb480ea7", "tree": "b0141eb5d50008261689fbb16b611c658db9fc8e", "parents": [ "bcdc87b594e779b6aa753c912fa4a14942edb01e" ], "author": { "name": "Sangsu Park", "email": "sangsu4u.park@samsung.com", "time": "Mon Mar 12 16:23:33 2012 -0700" }, "committer": { "name": "Kukjin Kim", "email": "kgene.kim@samsung.com", "time": "Wed Mar 14 06:51:29 2012 -0700" }, "message": "gpio/samsung: add support GPIOlib for EXYNOS5250\n\nThis patch adds gpio_chips for EXYNOS5250 and replaces\nexynos4_xxx() with exynos_xxx() and variables to support\nexynos4 and exynos5 together.\nIn addition, use ioreamp() for base address of gpios.\n\nSigned-off-by: Sangsu Park \u003csangsu4u.park@samsung.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nSigned-off-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\n" }, { "commit": "08932d81961b1c57870949d069ce2dad235da443", "tree": "cd1a70688920cd83632c116019dd6e7d9152f00a", "parents": [ "a05baf335b8bc25e0fab0fd1821e796174f98ea1" ], "author": { "name": "Ryan Mallon", "email": "rmallon@gmail.com", "time": "Wed Jan 11 09:58:30 2012 +1100" }, "committer": { "name": "Ryan Mallon", "email": "rmallon@gmail.com", "time": "Wed Mar 14 11:42:30 2012 +1100" }, "message": "ep93xx: Configure GPIO ports in core code\n\nMove the pinmux setting of the EP93xx GPIOs to the core code. This\nremoves the need for the GPIO driver to have access to the system\ncontroller registers.\n\nSigned-off-by: Ryan Mallon \u003crmallon@gmail.com\u003e\nCc: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nReviewed-by: Mika Westerberg \u003cmika.westerberg@iki.fi\u003e\nAcked-by: Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\n" }, { "commit": "81b279d80a63628e580c71a31d30a8c3b3047ad4", "tree": "d0695169d5445ce6f7bcd50e558b196dd47f2a1e", "parents": [ "ab2dde9924dd1ddb791fa8b14aa52e1df681e20c" ], "author": { "name": "Sekhar Nori", "email": "nsekhar@ti.com", "time": "Sun Mar 11 18:16:12 2012 +0530" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 12 11:53:33 2012 -0600" }, "message": "gpio/davinci: fix enabling unbanked GPIO IRQs\n\nUnbanked GPIO IRQ handling code made a copy of just\nthe irq_chip structure for GPIO IRQ lines which caused\nproblems after the generic IRQ chip conversion because\nthere was no valid irq_chip_type structure with the\nright \"regs\" populated. irq_gc_mask_set_bit() was\ntherefore accessing random addresses.\n\nFix it by making a copy of irq_chip_type structure\ninstead. This will ensure sane register offsets.\n\nCc: \u003cstable@vger.kernel.org\u003e # v3.0.x+\nReported-by: Jon Povey \u003cJon.Povey@racelogic.co.uk\u003e\nTested-by: Jon Povey \u003cJon.Povey@racelogic.co.uk\u003e\nSigned-off-by: Sekhar Nori \u003cnsekhar@ti.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "ab2dde9924dd1ddb791fa8b14aa52e1df681e20c", "tree": "56310874792ccd9208bae177cbd63d62630f9313", "parents": [ "8805f410e4fb88a56552c1af42d61b38837a38fd" ], "author": { "name": "Sekhar Nori", "email": "nsekhar@ti.com", "time": "Sun Mar 11 18:16:11 2012 +0530" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 12 11:49:33 2012 -0600" }, "message": "gpio/davinci: fix oops on unbanked gpio irq request\n\nUnbanked GPIO irq setup code was overwriting chip_data leading\nto the following oops on request_irq()\n\nUnable to handle kernel paging request at virtual address febfffff\npgd \u003d c22dc000\n[febfffff] *pgd\u003d00000000\nInternal error: Oops: 801 [#1] PREEMPT\nModules linked in: mcu(+) edmak irqk cmemk\nCPU: 0 Not tainted (3.0.0-rc7+ #93)\nPC is at irq_gc_mask_set_bit+0x68/0x7c\nLR is at vprintk+0x22c/0x484\npc : [\u003cc0080c0c\u003e] lr : [\u003cc00457e0\u003e] psr: 60000093\nsp : c33e3ba0 ip : c33e3af0 fp : c33e3bc4\nr10: c04555bc r9 : c33d4340 r8 : 60000013\nr7 : 0000002d r6 : c04555bc r5 : fec67010 r4 : 00000000\nr3 : c04734c8 r2 : fec00000 r1 : ffffffff r0 : 00000026\nFlags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user\nControl: 0005317f Table: 822dc000 DAC: 00000015\nProcess modprobe (pid: 526, stack limit \u003d 0xc33e2270)\nStack: (0xc33e3ba0 to 0xc33e4000)\n3ba0: 00000000 c007d3d4 c33e3bcc c04555bc c04555bc c33d4340 c33e3bdc c33e3bc8\n3bc0: c007f5f8 c0080bb4 00000000 c04555bc c33e3bf4 c33e3be0 c007f654 c007f5c0\n3be0: 00000000 c04555bc c33e3c24 c33e3bf8 c007e6e8 c007f618 c01f2284 c0350af8\n3c00: c0405214 bf016c98 00000001 00000000 c33dc008 0000002d c33e3c54 c33e3c28\n3c20: c007e888 c007e408 00000001 c23ef880 c33dc000 00000000 c33dc080 c25caa00\n3c40: c0487498 bf017078 c33e3c94 c33e3c58 bf016b44 c007e7d4 bf017078 c33dc008\n3c60: c25caa08 c33dc008 c33e3c84 bf017484 c25caa00 c25caa00 c01f5f48 c25caa08\n3c80: c0496d60 bf017484 c33e3ca4 c33e3c98 c022a698 bf01692c c33e3cd4 c33e3ca8\n3ca0: c01f5d88 c022a688 00000000 bf017484 c25caa00 c25caa00 c01f5f48 c25caa08\n3cc0: c0496d60 00000000 c33e3cec c33e3cd8 c01f5f8c c01f5d10 00000000 c33e3cf0\n3ce0: c33e3d14 c33e3cf0 c01f5210 c01f5f58 c303cb48 c25ecf94 c25caa00 c25caa00\n3d00: c25caa34 c33e3dd8 c33e3d34 c33e3d18 c01f6044 c01f51b8 c0496d3c c25caa00\n3d20: c044e918 c33e3dd8 c33e3d44 c33e3d38 c01f4ff4 c01f5fcc c33e3d94 c33e3d48\n3d40: c01f3d10 c01f4fd8 00000000 c044e918 00000000 00000000 c01f52c0 c034d570\n3d60: c33e3d84 c33e3d70 c022bf84 c25caa00 00000000 c044e918 c33e3dd8 c25c2e00\n3d80: c0496d60 bf01763c c33e3db4 c33e3d98 c022b1a0 c01f384c c25caa00 c33e3dd8\n3da0: 00000000 c33e3dd8 c33e3dd4 c33e3db8 c022b27c c022b0e8 00000000 bf01763c\n3dc0: c0451c80 c33e3dd8 c33e3e34 c33e3dd8 bf016f60 c022b210 5f75636d 746e6f63\n3de0: 006c6f72 00000000 00000000 00000000 00000000 00000000 00000000 bf0174bc\n3e00: 00000000 00989680 00000000 00000020 c0451c80 c0451c80 bf0174dc c01f5eb0\n3e20: c33f0f00 bf0174dc c33e3e44 c33e3e38 c01f72f4 bf016e2c c33e3e74 c33e3e48\n3e40: c01f5d88 c01f72e4 00000000 c0451c80 c0451cb4 bf0174dc c01f5eb0 c33f0f00\n3e60: c0473100 00000000 c33e3e94 c33e3e78 c01f5f44 c01f5d10 00000000 c33e3e98\n3e80: bf0174dc c01f5eb0 c33e3ebc c33e3e98 c01f5534 c01f5ec0 c303c038 c3061c30\n3ea0: 00003cd8 00098258 bf0174dc c0462ac8 c33e3ecc c33e3ec0 c01f5bec c01f54dc\n3ec0: c33e3efc c33e3ed0 c01f4d30 c01f5bdc bf0173a0 c33e2000 00003cd8 00098258\n3ee0: bf0174dc c33e2000 c00301a4 bf019000 c33e3f1c c33e3f00 c01f6588 c01f4c8c\n3f00: 00003cd8 00098258 00000000 c33e2000 c33e3f2c c33e3f20 c01f777c c01f6524\n3f20: c33e3f3c c33e3f30 bf019014 c01f7740 c33e3f7c c33e3f40 c002f3ec bf019010\n3f40: 00000000 00003cd8 00098258 bf017518 00000000 00003cd8 00098258 bf017518\n3f60: 00000000 c00301a4 c33e2000 00000000 c33e3fa4 c33e3f80 c007b934 c002f3c4\n3f80: c00b307c c00b2f48 00003cd8 00000000 00000003 00000080 00000000 c33e3fa8\n3fa0: c0030020 c007b8b8 00003cd8 00000000 00098288 00003cd8 00098258 00098240\n3fc0: 00003cd8 00000000 00000003 00000080 00098008 00098028 00098288 00000001\n3fe0: be892998 be892988 00013d7c 40178740 60000010 00098288 09089041 00200845\nBacktrace:\n[\u003cc0080ba4\u003e] (irq_gc_mask_set_bit+0x0/0x7c) from [\u003cc007f5f8\u003e] (irq_enable+0x48/0x58)\n r6:c33d4340 r5:c04555bc r4:c04555bc\n[\u003cc007f5b0\u003e] (irq_enable+0x0/0x58) from [\u003cc007f654\u003e] (irq_startup+0x4c/0x54)\n r5:c04555bc r4:00000000\n[\u003cc007f608\u003e] (irq_startup+0x0/0x54) from [\u003cc007e6e8\u003e] (__setup_irq+0x2f0/0x3cc)\n r5:c04555bc r4:00000000\n[\u003cc007e3f8\u003e] (__setup_irq+0x0/0x3cc) from [\u003cc007e888\u003e] (request_threaded_irq+0xc4/0x110)\n r8:0000002d r7:c33dc008 r6:00000000 r5:00000001 r4:bf016c98\n[\u003cc007e7c4\u003e] (request_threaded_irq+0x0/0x110) from [\u003cbf016b44\u003e] (mcu_spi_probe+0x228/0x37c [mcu])\n[\u003cbf01691c\u003e] (mcu_spi_probe+0x0/0x37c [mcu]) from [\u003cc022a698\u003e] (spi_drv_probe+0x20/0x24)\n[\u003cc022a678\u003e] (spi_drv_probe+0x0/0x24) from [\u003cc01f5d88\u003e] (driver_probe_device+0x88/0x1b0)\n[\u003cc01f5d00\u003e] (driver_probe_device+0x0/0x1b0) from [\u003cc01f5f8c\u003e] (__device_attach+0x44/0x48)\n[\u003cc01f5f48\u003e] (__device_attach+0x0/0x48) from [\u003cc01f5210\u003e] (bus_for_each_drv+0x68/0x94)\n r5:c33e3cf0 r4:00000000\n[\u003cc01f51a8\u003e] (bus_for_each_drv+0x0/0x94) from [\u003cc01f6044\u003e] (device_attach+0x88/0xa0)\n r7:c33e3dd8 r6:c25caa34 r5:c25caa00 r4:c25caa00\n[\u003cc01f5fbc\u003e] (device_attach+0x0/0xa0) from [\u003cc01f4ff4\u003e] (bus_probe_device+0x2c/0x4c)\n r7:c33e3dd8 r6:c044e918 r5:c25caa00 r4:c0496d3c\n[\u003cc01f4fc8\u003e] (bus_probe_device+0x0/0x4c) from [\u003cc01f3d10\u003e] (device_add+0x4d4/0x648)\n[\u003cc01f383c\u003e] (device_add+0x0/0x648) from [\u003cc022b1a0\u003e] (spi_add_device+0xc8/0x128)\n[\u003cc022b0d8\u003e] (spi_add_device+0x0/0x128) from [\u003cc022b27c\u003e] (spi_new_device+0x7c/0xb4)\n r7:c33e3dd8 r6:00000000 r5:c33e3dd8 r4:c25caa00\n[\u003cc022b200\u003e] (spi_new_device+0x0/0xb4) from [\u003cbf016f60\u003e] (mcu_probe+0x144/0x224 [mcu])\n r7:c33e3dd8 r6:c0451c80 r5:bf01763c r4:00000000\n[\u003cbf016e1c\u003e] (mcu_probe+0x0/0x224 [mcu]) from [\u003cc01f72f4\u003e] (platform_drv_probe+0x20/0x24)\n[\u003cc01f72d4\u003e] (platform_drv_probe+0x0/0x24) from [\u003cc01f5d88\u003e] (driver_probe_device+0x88/0x1b0)\n[\u003cc01f5d00\u003e] (driver_probe_device+0x0/0x1b0) from [\u003cc01f5f44\u003e] (__driver_attach+0x94/0x98)\n[\u003cc01f5eb0\u003e] (__driver_attach+0x0/0x98) from [\u003cc01f5534\u003e] (bus_for_each_dev+0x68/0x94)\n r7:c01f5eb0 r6:bf0174dc r5:c33e3e98 r4:00000000\n[\u003cc01f54cc\u003e] (bus_for_each_dev+0x0/0x94) from [\u003cc01f5bec\u003e] (driver_attach+0x20/0x28)\n r7:c0462ac8 r6:bf0174dc r5:00098258 r4:00003cd8\n[\u003cc01f5bcc\u003e] (driver_attach+0x0/0x28) from [\u003cc01f4d30\u003e] (bus_add_driver+0xb4/0x258)\n[\u003cc01f4c7c\u003e] (bus_add_driver+0x0/0x258) from [\u003cc01f6588\u003e] (driver_register+0x74/0x158)\n[\u003cc01f6514\u003e] (driver_register+0x0/0x158) from [\u003cc01f777c\u003e] (platform_driver_register+0x4c/0x60)\n r7:c33e2000 r6:00000000 r5:00098258 r4:00003cd8\n[\u003cc01f7730\u003e] (platform_driver_register+0x0/0x60) from [\u003cbf019014\u003e] (mcu_init+0x14/0x20 [mcu])\n[\u003cbf019000\u003e] (mcu_init+0x0/0x20 [mcu]) from [\u003cc002f3ec\u003e] (do_one_initcall+0x38/0x170)\n[\u003cc002f3b4\u003e] (do_one_initcall+0x0/0x170) from [\u003cc007b934\u003e] (sys_init_module+0x8c/0x1a4)\n[\u003cc007b8a8\u003e] (sys_init_module+0x0/0x1a4) from [\u003cc0030020\u003e] (ret_fast_syscall+0x0/0x2c)\n r7:00000080 r6:00000003 r5:00000000 r4:00003cd8\nCode: e1844003 e585400c e596300c e5932064 (e7814002)\n\nFix the issue.\n\nCc: \u003cstable@vger.kernel.org\u003e # v3.0.x+\nReported-by: Jon Povey \u003cJon.Povey@racelogic.co.uk\u003e\nSigned-off-by: Sekhar Nori \u003cnsekhar@ti.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "8805f410e4fb88a56552c1af42d61b38837a38fd", "tree": "3deb89add9b380d08abc9ae46a3045b791dd6474", "parents": [ "691e06c0ff2cd0cfe79db5c52baac4fe18ca55af" ], "author": { "name": "Tony Lindgren", "email": "tony@atomide.com", "time": "Mon Mar 05 15:32:38 2012 -0800" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 12 11:44:46 2012 -0600" }, "message": "gpio/omap: Fix section warning for omap_mpuio_alloc_gc()\n\nMake omap_mpuio_alloc_gc() __devinit as omap_gpio_chip_init()\nis __devinit. Otherwise we get:\n\nWARNING: vmlinux.o(.devinit.text+0xa10): Section mismatch in reference\nfrom the function omap_gpio_chip_init() to the function .init.text:omap_mpuio_alloc_gc()\nThe function __devinit omap_gpio_chip_init() references\na function __init omap_mpuio_alloc_gc().\nIf omap_mpuio_alloc_gc is only used by omap_gpio_chip_init then\nannotate omap_mpuio_alloc_gc with a matching annotation.\n\nSigned-off-by: Tony Lindgren \u003ctony@atomide.com\u003e\nAcked-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "691e06c0ff2cd0cfe79db5c52baac4fe18ca55af", "tree": "f1024d1dfd932ccaaffaa9a9a12f5dd77dde70e4", "parents": [ "7535b8bef067b71070ed5bdcf3606402f1e99618" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Fri Mar 02 17:32:24 2012 -0500" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 12 11:42:49 2012 -0600" }, "message": "ARM: tegra: export tegra_gpio_{en,dis}able\n\nThese two functions are used in drivers that can be\nmodules, so they need to be exported.\n\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nSigned-off-by: Alan Ott \u003calan@signal11.us\u003e\nAcked-by: Olof Johansson \u003colof@lixom.net\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "7535b8bef067b71070ed5bdcf3606402f1e99618", "tree": "bb4c57bbbe2c143a98d9d1f9690df8dc2ed97356", "parents": [ "0dc665d426691fd75fe9b6b16295ad0c02677d21" ], "author": { "name": "Bhupesh Sharma", "email": "bhupesh.sharma@st.com", "time": "Mon Feb 27 11:19:43 2012 +0530" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 12 11:36:38 2012 -0600" }, "message": "gpio/gpio-stmpe: Fix the value returned by _get_value routine\n\nThe present _get_value routine returns the contents of the GPIO Monitor Pin\nStatus Register(GPMR) starting from the bit whose value is requested to BIT 0\n(irrelevant bits are replace by 0).\n\nFor e.g. if we request the value of GPIO 6 in the earlier implementation the\nvalue returned is:\n\n\tBIT6 followed by 6 0\u0027s\n\nwhereas it should just return BIT6.\n\nThis patch addresses the same.\n\nSigned-off-by: Bhupesh Sharma \u003cbhupesh.sharma@st.com\u003e\nReviewed-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "46158aad96b0a90b52fd345f89951a50b3d1a81f", "tree": "b6ce41ea7ece7c0833fd42120a14e96455b1fd5f", "parents": [ "8e5fb37b9873eacb2381f2931d252b6db6e2cb16" ], "author": { "name": "Roland Stigge", "email": "stigge@antcom.de", "time": "Mon Mar 05 23:01:11 2012 +0100" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 12 11:25:30 2012 -0600" }, "message": "GPIO: LPC32xx: Add output reading to GPO P3\n\nThe chip offers the function to detect the current state of output of the GPO\nP3 pins. Useful for reading GPIO output state in Linux\u0027 GPIO API, e.g. via\nsysfs.\n\nPlease note that this only reads back the currently programmed output state,\nnot the actual electrical level in terms of a GPI function. Finally, GPO3 is\nstill just an output.\n\nSigned-off-by: Roland Stigge \u003cstigge@antcom.de\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "8e5fb37b9873eacb2381f2931d252b6db6e2cb16", "tree": "7232857eab0a85f5e938584d38d782d93de40918", "parents": [ "68942edb09f69b6e09522d1d346665eb3aadde49" ], "author": { "name": "Roland Stigge", "email": "stigge@antcom.de", "time": "Mon Mar 05 23:01:10 2012 +0100" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 12 11:25:30 2012 -0600" }, "message": "GPIO: LPC32xx: Fix missing bit selection mask\n\nAdd missing mask to pin bit selection in gpio-lpc32xx.c\n(#define GPIO3_PIN_IN_SEL)\n\nSigned-off-by: Roland Stigge \u003cstigge@antcom.de\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "68942edb09f69b6e09522d1d346665eb3aadde49", "tree": "d274bac19fdd5c0c46a67e8410960a16bf0c205a", "parents": [ "e2aa4177264c1a459779d6e35fae22adf17a9232" ], "author": { "name": "Kevin Hilman", "email": "khilman@ti.com", "time": "Mon Mar 05 15:10:04 2012 -0800" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 12 10:16:11 2012 -0600" }, "message": "gpio/omap: fix wakeups on level-triggered GPIOs\n\nWhile both level- and edge-triggered GPIOs are capable of generating\ninterrupts, only edge-triggered GPIOs are capable of generating a\nmodule-level wakeup to the PRCM (c.f. 34xx NDA TRM section 25.5.3.2.)\n\nIn order to ensure that devices using level-triggered GPIOs as\ninterrupts can also cause wakeups (e.g. from idle), this patch enables\nedge-triggering for wakeup-enabled, level-triggered GPIOs when a GPIO\nbank is runtime-suspended (which also happens during idle.)\n\nThis fixes a problem found in GPMC-connected network cards with GPIO\ninterrupts (e.g. smsc911x on Zoom3, Overo, ...) where network booting\nwith NFSroot was very slow since the GPIO IRQs used by the NIC were\nnot generating PRCM wakeups, and thus not waking the system from idle.\nNOTE: until v3.3, this boot-time problem was somewhat masked because\nthe UART init prevented WFI during boot until the full serial driver\nwas available. Preventing WFI allowed regular GPIO interrupts to fire\nand this problem was not seen. After the UART runtime PM cleanups, we\nno longer avoid WFI during boot, so GPIO IRQs that were not causing\nwakeups resulted in very slow IRQ response times.\n\nTested on platforms using level-triggered GPIOs for network IRQs using\nthe SMSC911x NIC: 3530/Overo and 3630/Zoom3.\n\nReported-by: Tony Lindgren \u003ctony@atomide.com\u003e\nTested-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nTested-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "38040c858cbd4c06080e7d1e79e9ff4c74c33d2c", "tree": "12d6a0ca7cf6cfbd2781c11d685e9aeb152c1d83", "parents": [ "e31f9b826486c48f20e4f1066aa3e23e111c3a4e" ], "author": { "name": "Chris Blair", "email": "chris.blair@stericsson.com", "time": "Thu Jan 26 22:17:15 2012 +0100" }, "committer": { "name": "Samuel Ortiz", "email": "sameo@linux.intel.com", "time": "Tue Mar 06 18:46:38 2012 +0100" }, "message": "gpio: Support no-irq stmpe mode\n\nAdds support for boards which have an STMPE GPIO device without the\ninterrupt pin connected. This means that no interrupt can be received\nbut the GPIO pins can still be driven and read.\n\nCc: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nAcked-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nTested-by: Michel Jaouen \u003cmichel.jaouen@stericsson.com\u003e\nSigned-off-by: Chris Blair \u003cchris.blair@stericsson.com\u003e\nAcked-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nSigned-off-by: Samuel Ortiz \u003csameo@linux.intel.com\u003e\n" }, { "commit": "25db711df3258d125dc1209800317e5c0ef3c870", "tree": "7445b68d6f50f65cb1f316dcf135494e3737910a", "parents": [ "384ebe1c2849160d040df3e68634ec506f13d9ff" ], "author": { "name": "Benoit Cousson", "email": "b-cousson@ti.com", "time": "Thu Feb 23 21:50:10 2012 +0100" }, "committer": { "name": "Benoit Cousson", "email": "b-cousson@ti.com", "time": "Mon Mar 05 23:02:53 2012 +0100" }, "message": "gpio/omap: Fix IRQ handling for SPARSE_IRQ\n\nThe driver is still relying on internal OMAP IRQ defines that\nare not relevant anymore if OMAP is built with SPARSE_IRQ.\n\nReplace the defines with the proper IRQ base number.\nClean some comment style issue.\nRemove some hidden and ugly cpu_class_is_omap1() inside the\ngpio header.\n\nSigned-off-by: Benoit Cousson \u003cb-cousson@ti.com\u003e\nTested-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\n" }, { "commit": "384ebe1c2849160d040df3e68634ec506f13d9ff", "tree": "75fa1a39e94203c5a85a61300578aaac4edfc9b1", "parents": [ "96751fcbe5438e95514b025e9cee7a6d38038f40" ], "author": { "name": "Benoit Cousson", "email": "b-cousson@ti.com", "time": "Tue Aug 16 11:53:02 2011 +0200" }, "committer": { "name": "Benoit Cousson", "email": "b-cousson@ti.com", "time": "Mon Mar 05 23:02:53 2012 +0100" }, "message": "gpio/omap: Add DT support to GPIO driver\n\nAdapt the GPIO driver to retrieve information from a DT file.\n\nAllocate the irq_base dynamically and rename bank-\u003evirtual_irq_start\nto bank-\u003eirq_base.\nChange irq_base type to int instead of u16 to match irq_alloc_descs\noutput.\n\nAdd documentation for GPIO properties specific to OMAP.\n\nSigned-off-by: Benoit Cousson \u003cb-cousson@ti.com\u003e\nCc: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nAcked-by: Rob Herring \u003crob.herring@calxeda.com\u003e\n" }, { "commit": "96751fcbe5438e95514b025e9cee7a6d38038f40", "tree": "b9193d0fcccbac8738cf934e37da1934ab3ebfff", "parents": [ "862ff64011e606582cec80cc3fa4fcd3e585d76f" ], "author": { "name": "Benoit Cousson", "email": "b-cousson@ti.com", "time": "Wed Feb 01 16:01:39 2012 +0100" }, "committer": { "name": "Benoit Cousson", "email": "b-cousson@ti.com", "time": "Mon Mar 05 23:02:52 2012 +0100" }, "message": "gpio/omap: Use devm_ API and add request_mem_region\n\nReplace the regular kzalloc and ioremap with the devm_ equivalent\nto simplify error handling.\n\nAdd the missing devm_request_mem_region to reserve the region used\nby the driver.\n\nSigned-off-by: Benoit Cousson \u003cb-cousson@ti.com\u003e\nCc: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\n" }, { "commit": "862ff64011e606582cec80cc3fa4fcd3e585d76f", "tree": "960417c31113f992bec6e3817b97a21628e38bdb", "parents": [ "e4e449e82871c53ef3b22bd3a50fceabc0638926" ], "author": { "name": "Benoit Cousson", "email": "b-cousson@ti.com", "time": "Wed Feb 01 15:58:56 2012 +0100" }, "committer": { "name": "Benoit Cousson", "email": "b-cousson@ti.com", "time": "Mon Mar 05 23:02:51 2012 +0100" }, "message": "gpio/omap: Remove bank-\u003eid information and misc cleanup\n\nThe driver does not need anymore any id to identify the GPIO instance.\nRemove every occurence of the bank-\u003eid inside the driver.\n\nRemove two trailing spaces.\nAdd a dev variable for better readability in probe.\nRemove unused variable bank-\u003epbase.\n\nSigned-off-by: Benoit Cousson \u003cb-cousson@ti.com\u003e\nAcked-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\n" }, { "commit": "3a70b7e05f62d4e1bfd5744368ea1fd855b6e03c", "tree": "0a74b982ab63dd20433bfe6abefdc8dd1b7336b4", "parents": [ "7cb7f82611dddb4b471d42d0fad645dd0dc3f360", "280ad7fda5f95211857fda38960f2b6fdf6edd3e" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Mon Mar 05 16:57:58 2012 +0000" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Mon Mar 05 16:58:11 2012 +0000" }, "message": "Merge branch \u0027depends/irqdomain\u0027 into next/drivers\n\nThis is needed in order for the tegra/soc-drivers branch\nto work.\n\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "e4e449e82871c53ef3b22bd3a50fceabc0638926", "tree": "87e14ac729928d7e1c54e7a975b365714c50bf85", "parents": [ "25553ff0756c59b617af6bdd280c94e943164184" ], "author": { "name": "Mark Brown", "email": "broonie@opensource.wolfsonmicro.com", "time": "Fri Feb 17 10:46:00 2012 -0800" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 05 08:05:08 2012 -0700" }, "message": "gpiolib: Add comments explaining the _cansleep() WARN_ON()s\n\nI\u0027ve seen users getting very confused by the WARN_ON()s for can_sleep\nGPIOs in the atomic-safe paths, the discoverability of the non-atomic\nversion of the API seems to be hampered by the fact that it\u0027s defined\nin a header file not the .c file where the warnings are.\n\nAdd a couple of comments next to the warnings to help people on their\nway.\n\nSigned-off-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nReviwed-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "25553ff0756c59b617af6bdd280c94e943164184", "tree": "6ca9ec045b5d2e10523fdf46facac59aa683f4ce", "parents": [ "aca5ce14eb773a75e5d935968b2e390dc5bd29c3" ], "author": { "name": "Laxman Dewangan", "email": "ldewangan@nvidia.com", "time": "Fri Feb 17 20:26:22 2012 +0530" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 05 07:49:44 2012 -0700" }, "message": "gpio: gpiolib: Support for open source/emitter gpios\n\nAdding support for the open source gpio on which client\ncan specify the open source property through GPIO flag\nGPIOF_OPEN_SOURCE at the time of gpio request.\nThe open source pins are normally pulled low and it\ncannot be driven to output with value of 0 and so\nwhen client request for setting the pin to LOW, the\ngpio will be set to input direction to make pin in tristate\nand hence PULL-DOWN on pins will make the state to LOW.\nThe open source pin can be driven to HIGH by setting output\nwith value of 1.\n\nSigned-off-by: Laxman Dewangan \u003cldewangan@nvidia.com\u003e\nReviwed-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "aca5ce14eb773a75e5d935968b2e390dc5bd29c3", "tree": "7da20e783f03b076d41163aad82dfb6878964ff9", "parents": [ "3d2ddfdcf05f5f816f829f81858c54827d7be5b4" ], "author": { "name": "Laxman Dewangan", "email": "ldewangan@nvidia.com", "time": "Fri Feb 17 20:26:21 2012 +0530" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Mar 05 07:49:44 2012 -0700" }, "message": "gpio: gpiolib: Support for open drain/collector gpios\n\nAdding support for the open drain gpio on which client\ncan specify the open drain property through GPIO flag\nGPIOF_OPEN_DRAIN at the time of gpio request.\nThe open drain pins are normally pulled high and it\ncannot be driven to output with value of 1 and so\nwhen client request for setting the pin to HIGH, the\ngpio will be set to input direction to make pin in tristate\nand hence PULL-UP on pins will make the state to HIGH.\nThe open drain pin can be driven to LOW by setting output\nwith value of 0.\n\nSigned-off-by: Laxman Dewangan \u003cldewangan@nvidia.com\u003e\nReviwed-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "7cb7f82611dddb4b471d42d0fad645dd0dc3f360", "tree": "61cb56ea1a885c96e6cb78fcd12e6abddd77e27c", "parents": [ "7169ff4a0942adf524f25713eaed30599d438926", "e77a6b313fdfe4faa8f9a8edf919c7eb8d095fb5" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Sun Mar 04 21:00:27 2012 +0000" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Sun Mar 04 21:03:30 2012 +0000" }, "message": "Merge tag \u0027tegra-soc-drivers\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra into tegra/soc-drivers\n\nTegra SoC driver support.\n\nSome device tree conversions, some new drivers. and a fix for an issue\nintroduced in Grant Likely\u0027s irq_domain conversion in his tree. Because\nof that, this branch depends on his branch to build (but not to merge):\n\ngit://git.secretlab.ca/git/linux-2.6.git irqdomain/next\n\n* tag \u0027tegra-soc-drivers\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra: (34 commits)\n ARM: tegra: uncompress.h: Don\u0027t depend on kernel headers\n gpio: tegra: Fix build issue due to irq_domain rework.\n ARM: tegra: Remove duplicate PMU interrupt inversion code\n ARM: tegra: Add a simple PMC driver\n ARM: tegra: dma: not required to move requestor when stopping.\n ARM: tegra: Fix EMC pdata initialization from registers\n gpio: tegra: Parameterize the number of banks\n gpio: tegra: Dynamically allocate IRQ base, and support DT\n ARM: tegra: Remove use of TEGRA_GPIO_TO_IRQ\n ARM: tegra: Pass uncompress.h UART selection to DEBUG_LL\n ARM: tegra: uncompress.h: Choose a UART at runtime\n ARM: tegra: uncompress.h: Store UART address in a variable\n ARM: tegra: Introduce define DEBUG_UART_SHIFT\n ARM: tegra: Support Tegra30 in decompressor UART setup\n ARM: tegra: Pause DMA when reading transfer count\n ARM: tegra: emc: device tree support\n ARM: tegra: emc: convert tegra2_emc to a platform driver\n ARM: tegra: fuse: add bct strapping reading\n ARM: tegra: fuse: add functions to access chip revision\n ARM: tegra: fuse: use apbio dma for register access\n ...\n\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "6e2cf6514066cdd5a0844b34760029a5a4870318", "tree": "620b38b5117a8b5a225714647e8f7a4d6d3f196d", "parents": [ "b3950d50cfc343b3e7dc5c69c96a61b182fd1e37" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Fri Mar 02 15:56:03 2012 -0700" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Fri Mar 02 15:56:03 2012 -0700" }, "message": "gpio: constify the data parameter to gpiochip_find()\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n\n" }, { "commit": "1220547bfd7f7dd97f770a04b533323e5404b8e9", "tree": "a4231b9570f3302f032a2d757fb3af24a4238d46", "parents": [ "a26d3c4fcd4bb875ae5adc32f27fab7a478bb00d", "f86bcc302a8c570dd0f5a50097a6af96a0e717c2" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Fri Mar 02 13:05:00 2012 +0000" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Fri Mar 02 13:05:00 2012 +0000" }, "message": "Merge branch \u0027depends/omap/gpio/runtime-pm-cleanup\u0027 into next/cleanup\n\nConflicts:\n\tarch/arm/mach-omap1/gpio16xx.c\n\tdrivers/gpio/gpio-omap.c\n\nMerge in the runtime-pm-cleanup branch from the gpio tree into\nnext/cleanup, this resolves a nonobvious merge conflict between\nthe two branches. Both branches move parts of the gpio-omap\ndriver into platform code, this takes the superset of both\nchanges.\n\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "b3950d50cfc343b3e7dc5c69c96a61b182fd1e37", "tree": "d54affae2b1e25464493b48aa88cd8d6b4770812", "parents": [ "daefd89efc279b142bbb054577c2d706da211723", "280ad7fda5f95211857fda38960f2b6fdf6edd3e" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Tue Feb 28 13:48:58 2012 -0600" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Tue Feb 28 13:48:58 2012 -0600" }, "message": "Merge branch \u0027irqdomain/next\u0027 into gpio/next\n" }, { "commit": "bdc93a77da75ee421125896ce4bbd91afff63809", "tree": "8b55ee08e35ae6acb341e97bd62eff00192f2dbb", "parents": [ "129cee1020d8031df1e3986673c64ca9eb7a2617" ], "author": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Mon Feb 13 16:21:15 2012 -0700" }, "committer": { "name": "Olof Johansson", "email": "olof@lixom.net", "time": "Sun Feb 26 13:21:18 2012 -0800" }, "message": "gpio: tegra: Fix build issue due to irq_domain rework.\n\nCommit 7da5a66 \"irq_domain: Remove \u0027new\u0027 irq_domain in favour of the\nppc one\" changed the set of available irq domain APIs. Update the Tegra\nGPIO driver to account for those changes, to solve a build break.\n\nSigned-off-by: Stephen Warren \u003cswarren@nvidia.com\u003e\nSigned-off-by: Olof Johansson \u003colof@lixom.net\u003e\n" }, { "commit": "63325ff235deeed5a5fc25705e292239115c76cd", "tree": "115ac82cd6f5c5abaaf7b1e622a9b522914ca05a", "parents": [ "a4f34197120be8edfe099bb6cde35740d299b6d1" ], "author": { "name": "Tony Lindgren", "email": "tony@atomide.com", "time": "Fri Feb 24 10:34:33 2012 -0800" }, "committer": { "name": "Tony Lindgren", "email": "tony@atomide.com", "time": "Fri Feb 24 10:34:33 2012 -0800" }, "message": "ARM: OMAP1: Move 16xx GPIO system clock to platform init code\n\nThis way we can remove omap_read/write call from the GPIO driver\nand remove include to linux/io.h.\n\nCc: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nSigned-off-by: Tony Lindgren \u003ctony@atomide.com\u003e\n" }, { "commit": "daefd89efc279b142bbb054577c2d706da211723", "tree": "2298056232548f6f22d7bbff2662a2bbf64520de", "parents": [ "6e33aceda2d82126e9d08a39e21a15be0dd00a6c", "f86bcc302a8c570dd0f5a50097a6af96a0e717c2" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Wed Feb 22 18:36:17 2012 -0700" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Wed Feb 22 18:36:17 2012 -0700" }, "message": "Merge branch \u0027for_3.4/gpio/runtime-pm-cleanup\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into gpio/next\n" }, { "commit": "6e33aceda2d82126e9d08a39e21a15be0dd00a6c", "tree": "4ee9e2c3af2307ea4541aaedb794e5b195a6fd03", "parents": [ "864533ceb6db336dead389577c102a8b792a121a" ], "author": { "name": "Viresh Kumar", "email": "viresh.kumar@st.com", "time": "Wed Jan 11 15:25:20 2012 +0530" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Thu Feb 16 06:37:51 2012 -0700" }, "message": "gpio/gpio-pl061: No need of thaw and poweroff routines for hibernate\n\npl061 uses same routines for suspend/freeze/poweroff and resume/thaw/restore.\nWe are only saving and restoring register values on these routines.\n\nDuring hibernation, in freeze() we take a snapshot of gpio registers. In thaw()\nwe don\u0027t actually need to restore these registers, as power was never shut down\ntill now. Similarly, in poweroff() we don\u0027t need to take snapshot of these\nregisters again, as it was done during freeze() and by now the image is already\nsaved on disk.\n\nThis patch passes poweroff() and thaw() routines as NULL to avoid this extra\nwork done.\n\nSigned-off-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "ff8c3ab8161d0df52858966e0347e05791da40df", "tree": "f0c17341977c555165d332033c03067d768ed0db", "parents": [ "9f70b8eb3cd37c6ef3371f972db799250e3eb86e" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Tue Jan 24 17:09:13 2012 -0700" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Thu Feb 16 06:11:24 2012 -0700" }, "message": "irq_domain/powerpc: Replace custom xlate functions with library functions\n\nThis patch converts a number of the powerpc drivers to use the common library\nof irq_domain xlate functions, dropping a bunch of lines in the process.\n\nv5: - Remove tsi108 changes from patch\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nCc: Rob Herring \u003crob.herring@calxeda.com\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Milton Miller \u003cmiltonm@bga.com\u003e\nTested-by: Olof Johansson \u003colof@lixom.net\u003e\n" }, { "commit": "a8db8cf0d894df5f1dcfd4bce9894e0dbcc01c96", "tree": "f9f2c53c57eeb04e5df60671951bcf4f2ca4966e", "parents": [ "68700650e71b6bb6636673f4f9c8ec807353d8d6" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Tue Feb 14 14:06:54 2012 -0700" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Thu Feb 16 06:11:22 2012 -0700" }, "message": "irq_domain: Replace irq_alloc_host() with revmap-specific initializers\n\nEach revmap type has different arguments for setting up the revmap.\nThis patch splits up the generator functions so that each revmap type\ncan do its own setup and the user doesn\u0027t need to keep track of how\neach revmap type handles the arguments.\n\nThis patch also adds a host_data argument to the generators. There are\ncases where the host_data pointer will be needed before the function returns.\nie. the legacy map calls the .map callback for each irq before returning.\n\nv2: - Add void *host_data argument to irq_domain_add_*() functions\n - fixed failure to compile\n - Moved IRQ_DOMAIN_MAP_* defines into irqdomain.c\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nCc: Rob Herring \u003crob.herring@calxeda.com\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Milton Miller \u003cmiltonm@bga.com\u003e\nTested-by: Olof Johansson \u003colof@lixom.net\u003e\n" }, { "commit": "864533ceb6db336dead389577c102a8b792a121a", "tree": "a9535b1d26af60737f136f0e9c717300f303f6f2", "parents": [ "ff64abefb6680dfc2aca7ecaa5e695949e7335c9" ], "author": { "name": "Ming Lei", "email": "tom.leiming@gmail.com", "time": "Mon Feb 13 22:53:20 2012 +0800" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Wed Feb 15 13:06:07 2012 -0700" }, "message": "Fix circular locking dependency (3.3-rc2)\n\nHi,\n\nOn Wed, Feb 8, 2012 at 8:41 PM, Felipe Balbi \u003cbalbi@ti.com\u003e wrote:\n\u003e Hi guys,\n\u003e\n\u003e I have just triggered the folllowing:\n\u003e\n\u003e [   84.860321] \u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\u003e [   84.860321] [ INFO: possible circular locking dependency detected ]\n\u003e [   84.860321] 3.3.0-rc2-00026-ge4e8a39 #474 Not tainted\n\u003e [   84.860321] -------------------------------------------------------\n\u003e [   84.860321] bash/949 is trying to acquire lock:\n\u003e [   84.860321]  (sysfs_lock){+.+.+.}, at: [\u003cc0275358\u003e] gpio_value_store+0x24/0xcc\n\u003e [   84.860321]\n\u003e [   84.860321] but task is already holding lock:\n\u003e [   84.860321]  (s_active#22){++++.+}, at: [\u003cc016996c\u003e] sysfs_write_file+0xdc/0x184\n\u003e [   84.911468]\n\u003e [   84.911468] which lock already depends on the new lock.\n\u003e [   84.911468]\n\u003e [   84.920043]\n\u003e [   84.920043] the existing dependency chain (in reverse order) is:\n\u003e [   84.920043]\n\u003e [   84.927886] -\u003e #1 (s_active#22){++++.+}:\n\u003e [   84.927886]        [\u003cc008f640\u003e] check_prevs_add+0xdc/0x150\n\u003e [   84.927886]        [\u003cc008fc18\u003e] validate_chain.clone.24+0x564/0x694\n\u003e [   84.927886]        [\u003cc0090cdc\u003e] __lock_acquire+0x49c/0x980\n\u003e [   84.951660]        [\u003cc0091838\u003e] lock_acquire+0x98/0x100\n\u003e [   84.951660]        [\u003cc016a8e8\u003e] sysfs_deactivate+0xb0/0x100\n\u003e [   84.962982]        [\u003cc016b1b4\u003e] sysfs_addrm_finish+0x2c/0x6c\n\u003e [   84.962982]        [\u003cc016b8bc\u003e] sysfs_remove_dir+0x84/0x98\n\u003e [   84.962982]        [\u003cc02590d8\u003e] kobject_del+0x10/0x78\n\u003e [   84.974670]        [\u003cc02c29e8\u003e] device_del+0x140/0x170\n\u003e [   84.974670]        [\u003cc02c2a24\u003e] device_unregister+0xc/0x18\n\u003e [   84.985382]        [\u003cc0276894\u003e] gpio_unexport+0xbc/0xdc\n\u003e [   84.985382]        [\u003cc02768c8\u003e] gpio_free+0x14/0xfc\n\u003e [   85.001708]        [\u003cc0276a28\u003e] unexport_store+0x78/0x8c\n\u003e [   85.001708]        [\u003cc02c5af8\u003e] class_attr_store+0x18/0x24\n\u003e [   85.007293]        [\u003cc0169990\u003e] sysfs_write_file+0x100/0x184\n\u003e [   85.018981]        [\u003cc0109d48\u003e] vfs_write+0xb4/0x148\n\u003e [   85.018981]        [\u003cc0109fd0\u003e] sys_write+0x40/0x70\n\u003e [   85.018981]        [\u003cc0013cc0\u003e] ret_fast_syscall+0x0/0x3c\n\u003e [   85.035003]\n\u003e [   85.035003] -\u003e #0 (sysfs_lock){+.+.+.}:\n\u003e [   85.035003]        [\u003cc008f54c\u003e] check_prev_add+0x680/0x698\n\u003e [   85.035003]        [\u003cc008f640\u003e] check_prevs_add+0xdc/0x150\n\u003e [   85.052093]        [\u003cc008fc18\u003e] validate_chain.clone.24+0x564/0x694\n\u003e [   85.052093]        [\u003cc0090cdc\u003e] __lock_acquire+0x49c/0x980\n\u003e [   85.052093]        [\u003cc0091838\u003e] lock_acquire+0x98/0x100\n\u003e [   85.069885]        [\u003cc047e280\u003e] mutex_lock_nested+0x3c/0x2f4\n\u003e [   85.069885]        [\u003cc0275358\u003e] gpio_value_store+0x24/0xcc\n\u003e [   85.069885]        [\u003cc02c18dc\u003e] dev_attr_store+0x18/0x24\n\u003e [   85.087158]        [\u003cc0169990\u003e] sysfs_write_file+0x100/0x184\n\u003e [   85.087158]        [\u003cc0109d48\u003e] vfs_write+0xb4/0x148\n\u003e [   85.098297]        [\u003cc0109fd0\u003e] sys_write+0x40/0x70\n\u003e [   85.098297]        [\u003cc0013cc0\u003e] ret_fast_syscall+0x0/0x3c\n\u003e [   85.109069]\n\u003e [   85.109069] other info that might help us debug this:\n\u003e [   85.109069]\n\u003e [   85.117462]  Possible unsafe locking scenario:\n\u003e [   85.117462]\n\u003e [   85.117462]        CPU0                    CPU1\n\u003e [   85.128417]        ----                    ----\n\u003e [   85.128417]   lock(s_active#22);\n\u003e [   85.128417]                                lock(sysfs_lock);\n\u003e [   85.128417]                                lock(s_active#22);\n\u003e [   85.142486]   lock(sysfs_lock);\n\u003e [   85.151794]\n\u003e [   85.151794]  *** DEADLOCK ***\n\u003e [   85.151794]\n\u003e [   85.151794] 2 locks held by bash/949:\n\u003e [   85.158020]  #0:  (\u0026buffer-\u003emutex){+.+.+.}, at: [\u003cc01698b8\u003e] sysfs_write_file+0x28/0x184\n\u003e [   85.170349]  #1:  (s_active#22){++++.+}, at: [\u003cc016996c\u003e] sysfs_write_file+0xdc/0x184\n\u003e [   85.170349]\n\u003e [   85.178588] stack backtrace:\n\u003e [   85.178588] [\u003cc001b824\u003e] (unwind_backtrace+0x0/0xf0) from [\u003cc008de64\u003e] (print_circular_bug+0x100/0x114)\n\u003e [   85.193023] [\u003cc008de64\u003e] (print_circular_bug+0x100/0x114) from [\u003cc008f54c\u003e] (check_prev_add+0x680/0x698)\n\u003e [   85.193023] [\u003cc008f54c\u003e] (check_prev_add+0x680/0x698) from [\u003cc008f640\u003e] (check_prevs_add+0xdc/0x150)\n\u003e [   85.212524] [\u003cc008f640\u003e] (check_prevs_add+0xdc/0x150) from [\u003cc008fc18\u003e] (validate_chain.clone.24+0x564/0x694)\n\u003e [   85.212524] [\u003cc008fc18\u003e] (validate_chain.clone.24+0x564/0x694) from [\u003cc0090cdc\u003e] (__lock_acquire+0x49c/0x980)\n\u003e [   85.233306] [\u003cc0090cdc\u003e] (__lock_acquire+0x49c/0x980) from [\u003cc0091838\u003e] (lock_acquire+0x98/0x100)\n\u003e [   85.233306] [\u003cc0091838\u003e] (lock_acquire+0x98/0x100) from [\u003cc047e280\u003e] (mutex_lock_nested+0x3c/0x2f4)\n\u003e [   85.242614] [\u003cc047e280\u003e] (mutex_lock_nested+0x3c/0x2f4) from [\u003cc0275358\u003e] (gpio_value_store+0x24/0xcc)\n\u003e [   85.261840] [\u003cc0275358\u003e] (gpio_value_store+0x24/0xcc) from [\u003cc02c18dc\u003e] (dev_attr_store+0x18/0x24)\n\u003e [   85.261840] [\u003cc02c18dc\u003e] (dev_attr_store+0x18/0x24) from [\u003cc0169990\u003e] (sysfs_write_file+0x100/0x184)\n\u003e [   85.271240] [\u003cc0169990\u003e] (sysfs_write_file+0x100/0x184) from [\u003cc0109d48\u003e] (vfs_write+0xb4/0x148)\n\u003e [   85.290008] [\u003cc0109d48\u003e] (vfs_write+0xb4/0x148) from [\u003cc0109fd0\u003e] (sys_write+0x40/0x70)\n\u003e [   85.298400] [\u003cc0109fd0\u003e] (sys_write+0x40/0x70) from [\u003cc0013cc0\u003e] (ret_fast_syscall+0x0/0x3c)\n\u003e -bash: echo: write error: Operation not permitted\n\u003e\n\u003e the way to trigger is:\n\u003e\n\u003e root@legolas:~# cd /sys/class/gpio/\n\u003e root@legolas:/sys/class/gpio# echo 2 \u003e export\n\u003e root@legolas:/sys/class/gpio# echo 2 \u003e unexport\n\u003e root@legolas:/sys/class/gpio# echo 2 \u003e export\n\u003e root@legolas:/sys/class/gpio# cd gpio2/\n\u003e root@legolas:/sys/class/gpio/gpio2# echo 1 \u003e value\n\nLooks \u0027sysfs_lock\u0027 needn\u0027t to be held for unregister, so the patch below may\nfix the problem.\n\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "bae1d8f19983fbfa25559aa3cb6a81a84aa82a18", "tree": "387012cc698159bfb5851c5022d5b55db2dafadc", "parents": [ "644bd954313254b54e08b69077e16831b6e04dfa" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Tue Feb 14 14:06:50 2012 -0700" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Tue Feb 14 14:06:50 2012 -0700" }, "message": "irq_domain/powerpc: Use common irq_domain structure instead of irq_host\n\nThis patch drops the powerpc-specific irq_host structures and uses the common\nirq_domain strucutres defined in linux/irqdomain.h. It also fixes all\nthe users to use the new structure names.\n\nRenaming irq_host to irq_domain has been discussed for a long time, and this\npatch is a step in the process of generalizing the powerpc virq code to be\nusable by all architecture.\n\nAn astute reader will notice that this patch actually removes the irq_host\nstructure instead of renaming it. This is because the irq_domain structure\nalready exists in include/linux/irqdomain.h and has the needed data members.\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Milton Miller \u003cmiltonm@bga.com\u003e\nTested-by: Olof Johansson \u003colof@lixom.net\u003e\n" }, { "commit": "3391811c4294da42e412ec5f83a251caf05869a4", "tree": "ee56741b55aa4f24824e5c75c3aced6254e234fd", "parents": [ "6f74dc9bc8de41f3de474a7269a70921e773c40f" ], "author": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Thu Jan 19 08:16:35 2012 +0000" }, "committer": { "name": "Olof Johansson", "email": "olof@lixom.net", "time": "Mon Feb 06 18:25:00 2012 -0800" }, "message": "gpio: tegra: Parameterize the number of banks\n\nTegra20\u0027s GPIO controller has 7 banks, and Tegra30\u0027s controller has 8\nbanks. Allow the number of banks to be configured at run-time by the\ndevice tree.\n\nSigned-off-by: Stephen Warren \u003cswarren@nvidia.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nSigned-off-by: Olof Johansson \u003colof@lixom.net\u003e\n" }, { "commit": "6f74dc9bc8de41f3de474a7269a70921e773c40f", "tree": "2804776d56077c3732db396e0cf42719ee9a83a5", "parents": [ "2123552d12168e744271aaf206e5826760fbd857" ], "author": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Wed Jan 04 08:39:37 2012 +0000" }, "committer": { "name": "Olof Johansson", "email": "olof@lixom.net", "time": "Mon Feb 06 18:25:00 2012 -0800" }, "message": "gpio: tegra: Dynamically allocate IRQ base, and support DT\n\nEnhance the driver to dynamically allocate the base IRQ number, and\ncreate an IRQ domain for itself. The use of an IRQ domain ensures that\nany device tree node interrupts properties are correctly parsed.\n\nDescribe interrupt-related properties in the device tree binding docs,\nand the contents of \"child\" node interrupts property.\n\nUpdate tegra*.dtsi to specify the required interrupt-related properties.\n\nFinally, remove the definition of TEGRA_GPIO_TO_IRQ; this macro no longer\ngives correct results since the IRQ numbers for GPIOs are dynamically\nallocated.\n\nSigned-off-by: Stephen Warren \u003cswarren@nvidia.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nSigned-off-by: Olof Johansson \u003colof@lixom.net\u003e\n" }, { "commit": "f86bcc302a8c570dd0f5a50097a6af96a0e717c2", "tree": "9cd40d3445205a6a7ce4959ac6be905cc5c68750", "parents": [ "6d13eaaf33436e20d1a41122f28434bcc37999dc" ], "author": { "name": "Nishanth Menon", "email": "nm@ti.com", "time": "Fri Sep 09 19:14:08 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 16:58:45 2012 +0530" }, "message": "gpio/omap: handle set_dataout reg capable IP on restore\n\nGPIO IP revisions such as those used in OMAP4 have a set_dataout\nwhile the previous revisions used a single dataout register.\nDepending on what is available restore the dataout settings\nto the right register.\n\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "6d13eaaf33436e20d1a41122f28434bcc37999dc", "tree": "32c190d212f1456a38e977a6c7325c124d223e5c", "parents": [ "ba805be53cb9112917631d368f859af5e20d695f" ], "author": { "name": "Nishanth Menon", "email": "nm@ti.com", "time": "Mon Aug 29 18:54:50 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 16:57:29 2012 +0530" }, "message": "gpio/omap: restore OE only after setting the output level\n\nSetup the dataout register before restoring OE. This is to make\nsure that we have valid data in dataout register which would be\nmade available in output pins as soon as OE is enabled. Else,\nthere is risk of unknown data getting out into gpio pins.\n\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "ba805be53cb9112917631d368f859af5e20d695f", "tree": "cfcb6050d18f108b1c8cfad673ebf5ea70918f1c", "parents": [ "ae547354a8ed59f19b57f7e1de9c7816edfc3537" ], "author": { "name": "Nishanth Menon", "email": "nm@ti.com", "time": "Mon Aug 29 18:41:08 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 16:56:14 2012 +0530" }, "message": "gpio/omap: enable irq at the end of all configuration in restore\n\nSetup the interrupt enable registers only after we have configured the\nrequired edge and required configurations, not before, to prevent\nspurious events as part of restore routine.\n\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "ae547354a8ed59f19b57f7e1de9c7816edfc3537", "tree": "a8069213450d93f22611804628251d7c785a6266", "parents": [ "41d87cbd660fd5793a6c70f9c93d9dcc8964179d" ], "author": { "name": "Nishanth Menon", "email": "nm@ti.com", "time": "Fri Sep 09 19:08:58 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 16:54:37 2012 +0530" }, "message": "gpio/omap: save and restore debounce registers\n\nGPIO debounce registers need to be saved and restored for proper functioning\nof driver.\n\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\ntarun.kanti@ti.com: Debounce context save is moved to _set_gpio_debounce()\nas part of dynamic context save to remove overhead.\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "41d87cbd660fd5793a6c70f9c93d9dcc8964179d", "tree": "6c9242bc406e263e050766e43c1c96c91bd56ea0", "parents": [ "6fd9c421649961a9d6d30b149e0128dde1b806b4" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Nov 15 12:52:38 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 16:45:01 2012 +0530" }, "message": "gpio/omap: remove omap_gpio_save_context overhead\n\nContext is now saved dynamically in respective functions whenever and\nwhichever registers are modified. This avoid overhead of saving all\nregisters context in the runtime suspend callback.\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "6fd9c421649961a9d6d30b149e0128dde1b806b4", "tree": "52f347eb9d42eb1445a506443a6f1f25ee9ec0db", "parents": [ "72f83af99838bb663f85b65386db5b875748f379" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Thu Nov 24 03:58:54 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 16:41:45 2012 +0530" }, "message": "gpio/omap: fix incorrect access of debounce module\n\nEnable debounce clock before writing/reading debounce registers.\nDisable the clock at the end so that it is synchronized with the\npm_runtime_get/put_sync calls.\n\nEnable debounce clock per module. This call is mandatory because\nin omap_gpio_request() when *_runtime_get_sync() is called,\n_gpio_dbck_enable() within runtime callbck fails to turn on dbck\n because dbck_enable_mask used within _gpio_dbck_enable() is still\nnot initialized at that point. Therefore we have to enable dbck here.\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "72f83af99838bb663f85b65386db5b875748f379", "tree": "612ddc67b783a82a40650acbf8a5a2e40f712307", "parents": [ "2dc983c565e03f6f6f96c5fe7449b65d86af4dee" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Thu Nov 24 03:03:28 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 16:41:35 2012 +0530" }, "message": "gpio/omap: fix debounce clock handling\n\nThe dbck_enable_mask indicates which all GPIOs within a bank have debounce\nenabled and dbck is enabled/disabled based upon this. But there is no\nmechanism to track the dbck state. In order to manage the dbck state we need\nadditional flag and logic so that turning off/on dbck is synchronized with\npm_runtime_put/get_sync calls.\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "2dc983c565e03f6f6f96c5fe7449b65d86af4dee", "tree": "10603d101152685569c0dca7107ba733c9b6d133", "parents": [ "065cd795d2721f8d2d1f2967ee6ed0aec07a4202" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Thu Nov 24 02:44:29 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 16:40:48 2012 +0530" }, "message": "gpio/omap: cleanup prepare_for_idle and resume_after_idle\n\nSince *_prepare_for_idle() and *_resume_after_idle() are called\nwith interrupts disabled they should be kept as simple as possible.\nSo, moving most of the stuff to *_runtime_suspend/resume() callbacks.\n\nTo avoid invalid context restore happening in *_runtime_resume()\ncallback as a result of *_get_sync() call in *_gpio_probe(), update\nbank-\u003econtext_loss_count. This would make context restore condition\ncheck false in the callback and skip restore until further\ninitialization take place. The workaround_enabled static variable\nis now a member of struct gpio_bank.\n\nUnlike most GPIO registers the OE has 0xffffffff as the default value.\nTo make sure invalid context is not restored, updating the OE context\nwith default value.\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "065cd795d2721f8d2d1f2967ee6ed0aec07a4202", "tree": "086a4d5bb9302394f7360646ee1ae2676ec3876d", "parents": [ "55b93c32520dc7ff0097db81db9b1e6b735951a9" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Thu Nov 24 01:48:52 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:44 2012 +0530" }, "message": "gpio/omap: optimize suspend and resume functions\n\nThere is no need to operate on all the banks every time the function is called.\nJust operate on the current bank passed by the framework.\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "55b93c32520dc7ff0097db81db9b1e6b735951a9", "tree": "49b2c64c5a0d32382e1980245b601d47ff500c30", "parents": [ "ec9af5d9f9399ceb340ee26afcc7d23e9d2a94c2" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Thu Sep 29 07:23:22 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:44 2012 +0530" }, "message": "gpio/omap: use pm-runtime framework\n\nCall runtime pm APIs pm_runtime_get_sync() and pm_runtime_put()\nfor enabling/disabling clocks appropriately. Remove syscore_ops and\ninstead use SET_RUNTIME_PM_OPS macro.\n\nThere is no more need to call omap_device_disable_idle_on_suspend\nsince driver is PM runtime adapted now.\n\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "d0d665a896c5b9a0aa60e8bac15c270cb59aa9e7", "tree": "de66912f404bbf0987427e4b0bfc772ebb963e3e", "parents": [ "d3901eaf1fc289e8175faa8c7c460d542b6eb7dd" ], "author": { "name": "Charulatha V", "email": "charu@ti.com", "time": "Wed Aug 31 00:02:21 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:43 2012 +0530" }, "message": "gpio/omap: remove bank-\u003emethod \u0026 METHOD_* macros\n\nThe only bank-\u003etype (method) used in the OMAP GPIO driver is MPUIO type as they\nneed to be handled separately. Identify the same using a flag and remove all\nMETHOD_* macros.\n\nmpuio_init() function is defined under #ifdefs. It is required only in case\nof MPUIO bank type and only when PM operations are supported by it.\nThis is applicable only in case of OMAP16xx SoC\u0027s MPUIO GPIO bank type.\nFor all the other cases it is a dummy function. Hence clean up the same\nand remove all the OMAP SoC specific #ifdefs.\n\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "d3901eaf1fc289e8175faa8c7c460d542b6eb7dd", "tree": "0d75db4627421ae9e076840a06c57dbd0be1cd51", "parents": [ "fad96ea825e7a8ee0c5b77292b470e4978157ee7" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Sep 27 05:38:09 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:43 2012 +0530" }, "message": "gpio/omap: remove unnecessary bit-masking for read access\n\nRemove un-necessary bit masking. Since the register are 4 byte aligned\nand readl would work as is. The \u0027enabled\u0027 mask is already taking care\nto mask for bank width.\n\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "fad96ea825e7a8ee0c5b77292b470e4978157ee7", "tree": "1e013b7a881a3abaa6a6e6b1812bfdd38537cae1", "parents": [ "ab985f0f7c2c0ef90b7c832f0c04f470dda0593d" ], "author": { "name": "Charulatha V", "email": "charu@ti.com", "time": "Wed May 25 11:23:50 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:43 2012 +0530" }, "message": "gpio/omap: use pinctrl offset instead of macro\n\nUse regs-\u003epinctrl field instead of using the macro OMAP1510_GPIO_PIN_CONTROL\n\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "ab985f0f7c2c0ef90b7c832f0c04f470dda0593d", "tree": "6a65b11d802d12787147d6cfab49758101f5389f", "parents": [ "5e571f38f6a44ef541fac0821631509d787ef0cd" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Sep 13 15:12:05 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:42 2012 +0530" }, "message": "gpio/omap: cleanup omap_gpio_mod_init function\n\nWith register offsets now defined for respective OMAP versions we can get rid\nof cpu_class_* checks. This function now has common initialization code for\nall OMAP versions. Initialization specific to OMAP16xx has been moved within\nomap16xx_gpio_init().\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "5e571f38f6a44ef541fac0821631509d787ef0cd", "tree": "eb19a3db74cae81d503ec8689fcc03bde8c27dfb", "parents": [ "ae10f2336b9c0c8da73da2878eba684ab876eb8f" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Sep 13 15:02:14 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:42 2012 +0530" }, "message": "gpio/omap: cleanup set_gpio_triggering function\n\nGetting rid of ifdefs within the function by adding register offset intctrl\nand associating OMAPXXXX_GPIO_INT_CONTROL in respective SoC specific files.\nAlso, use wkup_status register consistently instead of referring to wakeup\nclear and wakeup set register offsets. Get rid of cpu_is_xxxx checks in\nset_gpio_trigger() using irqctrl.\n\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "ae10f2336b9c0c8da73da2878eba684ab876eb8f", "tree": "442d2f48b9544153a63b7690a8eef27939f04419", "parents": [ "9ea14d8cbbf1c8fc941e8e8a12aa0a3edc5c336e" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Aug 30 15:24:27 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:42 2012 +0530" }, "message": "gpio/omap: remove hardcoded offsets in context save/restore\n\nIt is not required to use hard-coded offsets any more in context save and\nrestore functions and instead use the generic offsets which have been correctly\ninitialized during device registration.\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "9ea14d8cbbf1c8fc941e8e8a12aa0a3edc5c336e", "tree": "e31c48539315249da6ee68b16452d1f5abf2e6cb", "parents": [ "6ed87c5b66ca81996fae2dae6d1e702d66b9832b" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Aug 30 15:05:44 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:41 2012 +0530" }, "message": "gpio/omap: use level/edge detect reg offsets\n\nBy adding level and edge detection register offsets and then initializing them\ncorrectly according to OMAP versions during device registrations we can now remove\nlot of revision checks in these functions.\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "6ed87c5b66ca81996fae2dae6d1e702d66b9832b", "tree": "af6b3cfb3ec6627ebc7fec876abf470dd8482bec", "parents": [ "c8eef65a2fc311f8edca47f2e4ac2cccb70eb192" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Tue Sep 13 14:41:44 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:41 2012 +0530" }, "message": "gpio/omap: further cleanup using wkup_en register\n\nWakeup enable register offset initialized according to OMAP versions\nduring device registration. Use this to avoid version checks.\nStarting with OMAP4, legacy registers should not be used in combination\nwith the updated regsiters. Use wkup_en register consistently for\nall SoCs wherever applicable.\n\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "c8eef65a2fc311f8edca47f2e4ac2cccb70eb192", "tree": "d3be0559d9f02b16131dc9b46958e994fd3704f1", "parents": [ "803a24343f94c3eaeed35e69efa12a576258ca70" ], "author": { "name": "Charulatha V", "email": "charu@ti.com", "time": "Mon May 02 15:21:42 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:41 2012 +0530" }, "message": "gpio/omap: avoid cpu checks during module ena/disable\n\nRemove cpu-is checks while enabling/disabling OMAP GPIO module during a gpio\nrequest/free.\n\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "803a24343f94c3eaeed35e69efa12a576258ca70", "tree": "fbaf81ee15aa0e8e701e7231e8cff9bcfe26c1a9", "parents": [ "60a3437dc9a61c7f4b199c2bac3dcc7b611b1178" ], "author": { "name": "Charulatha V", "email": "charu@ti.com", "time": "Thu May 05 17:04:12 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:41 2012 +0530" }, "message": "gpio/omap: make non-wakeup GPIO part of pdata\n\nNon-wakeup GPIOs are available only in OMAP2. Avoid cpu_is checks by making\nnon_wakeup_gpios as part of pdata.\n\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "60a3437dc9a61c7f4b199c2bac3dcc7b611b1178", "tree": "c115df789b5da33b843ee7dddf34ddf58e2ae49d", "parents": [ "6d62e216b2ccbb8176dca73b6899b12a417bb22d" ], "author": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Thu Sep 29 04:47:25 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:40 2012 +0530" }, "message": "gpio/omap: handle save/restore context in GPIO driver\n\nModify omap_gpio_prepare_for_idle() \u0026 omap_gpio_resume_after_idle() functions\nto handle save context \u0026 restore context respectively in the OMAP GPIO driver\nitself instead of calling these functions from pm specific files.\nFor this, in gpio_prepare_for_idle(), call *_get_context_loss_count() and in\ngpio_resume_after_idle() call it again. If the count is different, do restore\ncontext.\n\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nSigned-off-by: Tarun Kanti DebBarma \u003ctarun.kanti@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "6d62e216b2ccbb8176dca73b6899b12a417bb22d", "tree": "f52895f475b0be9684056fb8bee75bd273f847ac", "parents": [ "0cde8d03dd297fa8e7e88cedeb498d0ed5b7776d" ], "author": { "name": "Charulatha V", "email": "charu@ti.com", "time": "Mon Apr 18 15:06:51 2011 +0000" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:40 2012 +0530" }, "message": "gpio/omap: make gpio_context part of gpio_bank structure\n\nCurrently gpio_context array used to save gpio bank\u0027s context, is used only for\nOMAP3 architecture. Move gpio_context as part of gpio_bank structure so that it\ncan be specific to each gpio bank and can be used for any OMAP architecture\n\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "0cde8d03dd297fa8e7e88cedeb498d0ed5b7776d", "tree": "542a4f06bc659180898d9e9d6bc3e540ddd088f1", "parents": [ "03e128ca35e5da22e9e65ec8ab158ec0e905fdea" ], "author": { "name": "Charulatha V", "email": "charu@ti.com", "time": "Thu May 05 20:15:16 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:40 2012 +0530" }, "message": "gpio/omap: use flag to identify wakeup domain\n\nIn omap3, save/restore context is implemented for GPIO banks 2-6 as GPIO bank1\nis in wakeup domain. Instead of identifying bank\u0027s power domain by bank id,\nuse \u0027loses_context\u0027 flag which is filled by pwrdm_can_ever_lose_context()\nduring dev_init.\n\nFor getting the powerdomain pointer, omap_hwmod_get_pwrdm() is used.\nomap_device_get_pwrdm() could not be used as the pwrdm information needs to be\nfilled in pdata, whereas omap_device_get_pwrdm() could be used only after\nomap_device_build() call.\n\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "03e128ca35e5da22e9e65ec8ab158ec0e905fdea", "tree": "2c1a95e5a8dd50429291f27a537e6b8cfadf22e5", "parents": [ "62aa2b537c6f5957afd98e29f96897419ed5ebab" ], "author": { "name": "Charulatha V", "email": "charu@ti.com", "time": "Thu May 05 19:58:01 2011 +0530" }, "committer": { "name": "Tarun Kanti DebBarma", "email": "tarun.kanti@ti.com", "time": "Mon Feb 06 14:13:40 2012 +0530" }, "message": "gpio/omap: remove dependency on gpio_bank_count\n\nThe gpio_bank_count is the count of number of GPIO devices in a SoC. Remove this\ndependency from the driver by using list. Also remove the dependency on array of\npointers to gpio_bank struct of all GPIO devices.\n\nSigned-off-by: Charulatha V \u003ccharu@ti.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "9467d298e92455e6fd411d7ef1f367ced940587c", "tree": "b739a190c7aba72531e9592cbc9937b1a159db6c", "parents": [ "b43ab901d671e3e3cad425ea5e9a3c74e266dcdd" ], "author": { "name": "Laxman Dewangan", "email": "ldewangan@nvidia.com", "time": "Wed Feb 01 12:09:04 2012 +0530" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Sun Feb 05 23:08:29 2012 -0700" }, "message": "gpio: tps65910: Add sleep control support\n\nThe device tps65910/tps65911 supports the sleep\nfunctionality in some of gpios. If gpio is configured\nin output mode and sleep is enabled then during device\nsleep state, the output of gpio becomes LOW regardless\nof non-sleep output value.\nSuch gpio can be used to control regulator switch such\nthat output of regulator is off in device sleep state.\n\nSigned-off-by: Laxman Dewangan \u003cldewangan@nvidia.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\n" }, { "commit": "b43ab901d671e3e3cad425ea5e9a3c74e266dcdd", "tree": "9527497057e939c478ff8ac5760f71cafff3b996", "parents": [ "608589b15f02e59e8c40df7ef861064f1b6fa504" ], "author": { "name": "Sebastian Andrzej Siewior", "email": "bigeasy@linutronix.de", "time": "Mon Jun 27 09:26:23 2011 +0200" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Fri Feb 03 16:13:25 2012 -0700" }, "message": "gpio: Add a driver for Sodaville GPIO controller\n\nSodaville has GPIO controller behind the PCI bus. To my suprissed it is\nnot the same as on PXA.\n\nThe interrupt \u0026 gpio chip can be referenced from the device tree like\nfrom any other driver. Unfortunately the driver which uses the gpio\ninterrupt has to use irq_of_parse_and_map() instead of\nplatform_get_irq(). The problem is that the platform device (which is\ncreated from the device tree) is most likely created before the\ninterrupt chip is registered and therefore irq_of_parse_and_map() fails.\n\nIn theory the driver works as module. In reality most of the irq\nfunctions are not exported to modules and it is possible that _this_\nmodule is unloaded while the provided irqs are still in use.\n\nSigned-off-by: Hans J. Koch \u003chjk@linutronix.de\u003e\n[torbenh@linutronix.de: make it work after the irq namespace cleanup,\n\t add some device tree entries.]\nSigned-off-by: Torben Hohn \u003ctorbenh@linutronix.de\u003e\n[bigeasy@linutronix.de: convert to generic irq \u0026 gpio chip]\nSigned-off-by: Sebastian Andrzej Siewior \u003cbigeasy@linutronix.de\u003e\n[grant.likely@secretlab.ca: depend on x86 to avoid irq_domain breakage]\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "7e3a70fb7bccada029c188c89bfbf3c0a63c1500", "tree": "b333d3233560bfa5b32bf2fea659ecdadd92d2b4", "parents": [ "d166370ad86b33b1111af3a0cdd7de94e03789a6" ], "author": { "name": "Axel Lin", "email": "axel.lin@gmail.com", "time": "Wed Feb 01 10:50:05 2012 +0800" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Wed Feb 01 21:59:37 2012 -0700" }, "message": "gpio: Add missing spin_lock_init in gpio-ml-ioh driver\n\nThis bug was introduced by commit 54be5663\n\"gpio-ml-ioh: Support interrupt function\" which adds a spinlock to struct\nioh_gpio but never init the spinlock.\n\nSigned-off-by: Axel Lin \u003caxel.lin@gmail.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "d166370ad86b33b1111af3a0cdd7de94e03789a6", "tree": "5f7ec948fd7fbade13192aa11311bad91cde2b7a", "parents": [ "876cf5e7b9e4bae014b0fa2cc18b21bce6d99073" ], "author": { "name": "Axel Lin", "email": "axel.lin@gmail.com", "time": "Wed Feb 01 10:51:53 2012 +0800" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Wed Feb 01 21:59:15 2012 -0700" }, "message": "gpio: Add missing spin_lock_init in gpio-pch driver\n\nThis bug was introduced by commit d568a681\n\"gpio-pch: add spinlock in suspend/resume processing\"\nwhich adds a spinlock to struct pch_gpio but never init the spinlock.\n\nReported-by: Tomoya MORINAGA \u003ctomoya.rohm@gmail.com\u003e\nSigned-off-by: Axel Lin \u003caxel.lin@gmail.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "876cf5e7b9e4bae014b0fa2cc18b21bce6d99073", "tree": "3a466167c9028aeb30e506ce09c6b8ab85012e4b", "parents": [ "95120d5d1bc17bdec29085186b6ab3d90e92d6f3" ], "author": { "name": "Thomas Abraham", "email": "thomas.abraham@linaro.org", "time": "Wed Feb 01 18:32:32 2012 +0530" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Wed Feb 01 17:05:28 2012 -0700" }, "message": "gpio: samsung: adapt to changes in gpio specifier translator function declaration\n\nCommit 15c9a0acc3f7 (of: create of_phandle_args to simplify return of phandle\nparsing data) modifies the parameter list of of_xlate function pointer declaration\nin gpio_chip. Adapt the gpio specifier translate function for this change.\n\nReported-by: Tushar Behera \u003ctushar.behera@linaro.org\u003e\nSigned-off-by: Thomas Abraham \u003cthomas.abraham@linaro.org\u003e\nTested-by: Karol Lewandowski \u003ck.lewandowsk@samsung.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "608589b15f02e59e8c40df7ef861064f1b6fa504", "tree": "55c7119187542ee660cc7aaafa8662caf2cc894e", "parents": [ "dcd6c92267155e70a94b3927bce681ce74b80d1f" ], "author": { "name": "wu guoxing", "email": "b39297@freescale.com", "time": "Mon Jan 30 14:31:20 2012 +0800" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Jan 30 07:49:08 2012 -0700" }, "message": "ARM/mx35/3ds: gpio: add mc9s08dz60 gpio function\n\nwe only use the gpio function of mc9s08dz60 mcu chip, so just\nadd the gpio driver, as this mcu will never be used in other board.\n\nSigned-off-by: Wu Guoxing \u003cb39297@freescale.com\u003e\nReviewed-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nAcked-by: Marc Kleine-Budde \u003cmkl@pengutronix.de\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "feefe73fcbb4dfc952d4185d80435fb8e053e2a7", "tree": "f0555d596a893656ab2b5f33a5b55007c9dbc776", "parents": [ "9482ee7175d1c312c96ffc85c7c413b283cf847b" ], "author": { "name": "Rob Herring", "email": "rob.herring@calxeda.com", "time": "Tue Jan 03 15:52:42 2012 -0600" }, "committer": { "name": "Rob Herring", "email": "rob.herring@calxeda.com", "time": "Wed Jan 25 20:37:43 2012 -0600" }, "message": "gpio: pxa: explicitly include mach/irqs.h\n\nIn preparation to make mach/irqs.h optional and remove from asm/irq.h,\ndirectly include mach/irq.h to get MMP_GPIO_TO_IRQ and PXA_GPIO_TO_IRQ.\n\nSigned-off-by: Rob Herring \u003crob.herring@calxeda.com\u003e\n" }, { "commit": "95120d5d1bc17bdec29085186b6ab3d90e92d6f3", "tree": "48d9b0cfd64033ec7177f43b09ac7b3ea0723711", "parents": [ "dcd6c92267155e70a94b3927bce681ce74b80d1f" ], "author": { "name": "Roland Stigge", "email": "stigge@antcom.de", "time": "Sun Jan 22 18:57:57 2012 +0100" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Sun Jan 22 12:31:04 2012 -0700" }, "message": "Correct bad gpio naming\n\nOne of the GPIO names in drivers/gpio/gpio-lpc32xx.c\nwas bad. Renaming gpi000 -\u003e gpio00\n\nSigned-off-by: Roland Stigge \u003cstigge@antcom.de\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "94bd2442d25454a874e070d871f50f4ce9d57101", "tree": "ff71c15e4aa0c0f89efc01adc63ef49c4446d1e5", "parents": [ "265fe02b6fade1704f01c4e96f99ac051b7fab9d" ], "author": { "name": "Laxman Dewangan", "email": "ldewangan@nvidia.com", "time": "Wed Jan 18 20:07:35 2012 +0530" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Wed Jan 18 13:48:43 2012 -0700" }, "message": "gpio: tps65910: Use correct offset for gpio initialization\n\nUsing the correct gpio offset for setting the initial value\nof gpio when setting output direction.\n\nSigned-off-by: Laxman Dewangan \u003cldewangan@nvidia.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "265fe02b6fade1704f01c4e96f99ac051b7fab9d", "tree": "37da7860b4e7c6fe5982ff55d6e705c25d556862", "parents": [ "dd9328a6b026060699d4136d8f926e39281c8a18" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Wed Jan 11 11:03:41 2012 -0700" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Tue Jan 17 17:43:09 2012 -0700" }, "message": "gpio/it8761e: Restrict it8761e gpio driver to x86.\n\nThis driver does an unconditional read of io space during module init which\ncauses a bad dereference on ARM. It looks to me like this is an x86 only\ndrivers, so restrict it to only compile on x86.\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nCc: Denis Turischev \u003cdenis@compulab.co.il\u003e\n" }, { "commit": "dd9328a6b026060699d4136d8f926e39281c8a18", "tree": "2804e3e33c18f3fb942c34b63a322bdc77c9c2e0", "parents": [ "2bd1c85e855c94da564e151cb54553e6cfc2f04b" ], "author": { "name": "Márton Németh", "email": "nm127@freemail.hu", "time": "Sun Jan 15 10:57:34 2012 +0100" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Jan 16 09:12:24 2012 -0700" }, "message": "gpio-ml-ioh: cleanup __iomem annotation usage\n\nThe __iomem annotation is to be used together with pointers used\nin iowrite32() but not for pointers returned by kzalloc().\nFor more details see [1] and [2].\n\nThis patch will remove the following sparse warning (i.e. when\ncopiling with \"make C\u003d1\"):\n * warning: incorrect type in assignment (different address spaces)\n\nReferences:\n[1] A new I/O memory access mechanism (Sep 15, 2004)\n http://lwn.net/Articles/102232/\n\n[2] Being more anal about iospace accesses (Sep 15, 2004)\n http://lwn.net/Articles/102240/\n\nSigned-off-by: Márton Németh \u003cnm127@freemail.hu\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "2bd1c85e855c94da564e151cb54553e6cfc2f04b", "tree": "4bc8f753fdbedac92b14be7bff97705045537517", "parents": [ "cd7bf8a554fdfaadcee6d66900c7710651dc58f2" ], "author": { "name": "Márton Németh", "email": "nm127@freemail.hu", "time": "Sun Jan 15 10:57:43 2012 +0100" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Jan 16 09:12:24 2012 -0700" }, "message": "gpio-ml-ioh: cleanup NULL pointer checking\n\nThis patch will remove the following sparse warning (\"make C\u003d1\"):\n * warning: Using plain integer as NULL pointer\n\nSigned-off-by: Márton Németh \u003cnm127@freemail.hu\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "cd7bf8a554fdfaadcee6d66900c7710651dc58f2", "tree": "d06059e07ae37ad8503227724b19f85410671a8e", "parents": [ "c4addcb55417a246b4419cbb075a2e4f412a8645" ], "author": { "name": "Márton Németh", "email": "nm127@freemail.hu", "time": "Sun Jan 15 11:32:24 2012 +0100" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Jan 16 09:12:24 2012 -0700" }, "message": "gpio-pch: cleanup __iomem annotation usage\n\nThe __iomem annotation is to be used together with pointers used\nas iowrite32() parameter. For more details see [1] and [2].\n\nThis patch will remove the following sparse warnings (\"make C\u003d1\"):\n * warning: incorrect type in assignment (different address spaces)\n * warning: incorrect type in argument 1 (different address spaces)\n * warning: incorrect type in argument 2 (different address spaces)\n\nReferences:\n[1] A new I/O memory access mechanism (Sep 15, 2004)\n http://lwn.net/Articles/102232/\n\n[2] Being more anal about iospace accesses (Sep 15, 2004)\n http://lwn.net/Articles/102240/\n\nSigned-off-by: Márton Németh \u003cnm127@freemail.hu\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "c4addcb55417a246b4419cbb075a2e4f412a8645", "tree": "492f689bca2db1865927f66ae43c0b906ac3be8a", "parents": [ "53999bf34d55981328f8ba9def558d3e104d6e36" ], "author": { "name": "Márton Németh", "email": "nm127@freemail.hu", "time": "Sun Jan 15 11:32:30 2012 +0100" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Mon Jan 16 09:12:24 2012 -0700" }, "message": "gpio-pch: cleanup NULL pointer checking\n\nThis patch will remove the following sparse warning (\"make C\u003d1\"):\n * warning: Using plain integer as NULL pointer\n\nSigned-off-by: Márton Németh \u003cnm127@freemail.hu\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "f5e4e20faa1eee3feaa0394897bbd1aca544e809", "tree": "047a93ff025c46ed97d3192a79f55b38fa071ca1", "parents": [ "4964e0664c80680fa6b28ef91381c076a5b25c2c", "f408c985cefc9b1d99bc099e1208dd7df3445aa5" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Jan 14 13:25:23 2012 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Jan 14 13:25:23 2012 -0800" }, "message": "Merge tag \u0027gpio-for-linus\u0027 of git://git.secretlab.ca/git/linux-2.6\n\n2nd round of GPIO changes for v3.3 merge window\n\n* tag \u0027gpio-for-linus\u0027 of git://git.secretlab.ca/git/linux-2.6:\n GPIO: sa1100: implement proper gpiolib gpio_to_irq conversion\n gpio: pl061: remove combined interrupt\n gpio: pl061: convert to use generic irq chip\n GPIO: add bindings for managed devices\n ARM: realview: convert pl061 no irq to 0 instead of -1\n gpio: pl061: convert to use 0 for no irq\n gpio: pl061: use chained_irq_* functions in irq handler\n GPIO/pl061: Add suspend resume capability\n drivers/gpio/gpio-tegra.c: use devm_request_and_ioremap\n" } ], "next": "f408c985cefc9b1d99bc099e1208dd7df3445aa5" }