)]}' { "log": [ { "commit": "06c10884486a63a1e4ff657aaa51e848e64b9dc3", "tree": "3913f3d19b60a9e6a62484e2f4e352d9dcf995a8", "parents": [ "841f48a849e0dc14fe6f3d2bd31e831ac6a76546" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 13 00:15:25 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Oct 13 00:19:03 2010 +0100" }, "message": "ARM: relax ioremap prohibition (309caa9) for -final and -stable\n\n... but produce a big warning about the problem as encouragement\nfor people to fix their drivers.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "c0bb5862a9076992e2cbeb5fa0d08c2ac3d4fbb0", "tree": "1309a6b52c09b010d6fcbeca95a9f657977afe3e", "parents": [ "5c189208b606a85b4e97109af70d59f10a42fdfd" ], "author": { "name": "Tony Lindgren", "email": "tony@atomide.com", "time": "Thu Oct 07 19:34:04 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Oct 08 10:01:23 2010 +0100" }, "message": "ARM: 6435/1: Fix HWCAP_TLS flag for ARM11MPCore/Cortex-A9\n\nCommit 14eff1812679c76564b775aa95cdd378965f6cfb added proper\ndetection for ARM11MPCore/Cortex-A9 instead of detecting them\nas ARMv7. However, it was missing the HWCAP_TLS flags.\n\nHWCAP_TLS is needed if support for earlier ARMv6 is compiled\ninto the same kernel. Without HWCAP_TLS flags the userspace\nwon\u0027t work unless nosmp is specified:\n\nKernel panic - not syncing: Attempted to kill init!\nCPU0: stopping\n\u003cc005d5e4\u003e] (unwind_backtrace+0x0/0xec) from [\u003cc004c2f8\u003e] (do_IPI+0xfc/0x184)\n\u003cc004c2f8\u003e] (do_IPI+0xfc/0x184) from [\u003cc03f25bc\u003e] (__irq_svc+0x9c/0x160)\nException stack(0xc0565f80 to 0xc0565fc8)\n5f80: 00000001 c05772a0 00000000 00003a61 c0564000 c05cf500 c003603c c0578600\n5fa0: 80033ef0 410fc091 0000001f 00000000 00000000 c0565fc8 c00b91f8 c0057cb4\n5fc0: 20000013 ffffffff\n[\u003cc03f25bc\u003e] (__irq_svc+0x9c/0x160) from [\u003cc0057cb4\u003e] (default_idle+0x30/0x38)\n[\u003cc0057cb4\u003e] (default_idle+0x30/0x38) from [\u003cc005829c\u003e] (cpu_idle+0x9c/0xf8)\n[\u003cc005829c\u003e] (cpu_idle+0x9c/0xf8) from [\u003cc0008d48\u003e] (start_kernel+0x2a4/0x300)\n[\u003cc0008d48\u003e] (start_kernel+0x2a4/0x300) from [\u003c80008084\u003e] (0x80008084)\n\nSigned-off-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7f58217bb6d39edac68ae0988cdb96a520ad916f", "tree": "9d1b9eb06abb657e2943f1db5759ca1a0cf3617c", "parents": [ "475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2d" ], "author": { "name": "Santosh Shilimkar", "email": "santosh.shilimkar@ti.com", "time": "Thu Sep 30 09:02:17 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 04 19:20:18 2010 +0100" }, "message": "ARM: 6419/1: mmu: Fix MT_MEMORY and MT_MEMORY_NONCACHED pte flags\n\nThe commit f1a2481c0 sets up the default flags for MT_MEMORY and\nMT_MEMORY_NONCACHED memory types. L_PTE_USER flag is wrongly\nset as default for these entries so remove it. Also adding\nthe \u0027L_PTE_WRITE\u0027 flag so that these pages become read-write\ninstead of just being read-only\n\n[this stops them being exposed to userspace, which is the main\nconcern here --rmk]\n\nReported-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2d", "tree": "c2c3e98575957a0eab1492da35921c982c5d2e1e", "parents": [ "c6ea21e35bf3691cad59647c771e6606067f627d" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Sep 28 14:02:02 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 04 19:20:14 2010 +0100" }, "message": "ARM: 6416/1: errata: faulty hazard checking in the Store Buffer may lead to data corruption\n\nOn the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption\ncan occur under very rare conditions due to a store buffer optimisation.\n\nThis workaround sets a bit in the diagnostic register of the Cortex-A9,\ndisabling the optimisation and preventing the problem from occurring.\n\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f1a2481c0ad3aebd94d11b317c488deaadc25002", "tree": "34835ebb681604635db2f8b44c2fa7d2d0f75933", "parents": [ "f933b87e6f06fcce5988fd5e8ebf3a97858a7155" ], "author": { "name": "Santosh Shilimkar", "email": "santosh.shilimkar@ti.com", "time": "Fri Sep 24 07:18:22 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Sep 25 15:58:39 2010 +0100" }, "message": "ARM: 6407/1: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries\n\nThis patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED\ntypes so that at boot-up, we can map memories outside system memory\nat page level granularity\n\nPreviously the mapping was limiting to section level, which creates\nunnecessary additional mapping for which physical memory may not\npresent. On the newer ARM with speculation, this is dangerous and can\nresult in untraceable aborts.\n\nSigned-off-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "2f27bf834e1d0a06e83d7458b535891c552271aa", "tree": "6d0ed3804614f146a8001245d52579c4ee0cb311", "parents": [ "1d5b4c0fa9ff79a4f01e5efc1caefd16b190a3dc" ], "author": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Mon Sep 20 04:10:43 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Sep 23 15:17:04 2010 +0100" }, "message": "ARM: 6401/1: plug a race in the alignment trap handler\n\nWhen the policy for user space is to ignore misaligned accesses from user\nspace, the processor then performs a documented rotation on the accessed\ndata. This is the result of the access being trapped, and the kernel\ndisabling the alignment trap before returning to user space again.\n\nIn kernel space we always want misaligned accesses to be fixed up. This\nis enforced by always re-enabling the alignment trap on every entry into\nkernel space from user space. No such re-enabling is performed when an\nexception occurs while already in kernel space as the alignment trap is\nalways supposed to be enabled in that case.\n\nThere is however a small race window when a misaligned access in user\nspace is trapped and the alignment trap disabled, but the CPU didn\u0027t\nreturn to user space just yet. Any exception would be entered from kernel\nspace at that point and the kernel would then execute with the alignment\ntrap disabled.\n\nThanks to Maxime Bizon \u003cmbizon@freebox.fr\u003e for providing a test module\nthat made this issue reproducible.\n\nSigned-off-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d907387c42e9e39261629890e45a08ef4c3ed3fe", "tree": "c25c1c7bde121ccb9ac56a434113c16d24203647", "parents": [ "79e27dc0677b969e2d53b76fa0fa58467cce946a" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Mon Sep 13 16:01:24 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Sep 19 12:19:18 2010 +0100" }, "message": "ARM: 6383/1: Implement phys_mem_access_prot() to avoid attributes aliasing\n\nARMv7 onwards requires that there are no aliases to the same physical\nlocation using different memory types (i.e. Normal vs Strongly Ordered).\nAccess to SO mappings when the unaligned accesses are handled in\nhardware is also Unpredictable (pgprot_noncached() mappings in user\nspace).\n\nThe /dev/mem driver requires uncached mappings with O_SYNC. The patch\nimplements the phys_mem_access_prot() function which generates Strongly\nOrdered memory attributes if !pfn_valid() (independent of O_SYNC) and\nNormal Noncacheable (writecombine) if O_SYNC.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "14eff1812679c76564b775aa95cdd378965f6cfb", "tree": "af574c59bddc14386830a7e93d63a8a7c29a4904", "parents": [ "b2b163bb82b12bae2504a5b31399c37d099ad3cc" ], "author": { "name": "Daniel Walker", "email": "dwalker@fifo99.com", "time": "Fri Sep 17 16:42:10 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Sep 17 16:44:24 2010 +0100" }, "message": "ARM: 6398/1: add proc info for ARM11MPCore/Cortex-A9 from ARM\n\nSetting of these bits can cause issues on other SMP SoC\u0027s not produced\nby ARM.\n\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Daniel Walker \u003cdwalker@codeaurora.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a672e99b129e286df2e2697a1b603d82321117f3", "tree": "3307cdb68df62a67d78309ecdf6c35cab7321892", "parents": [ "9f05027c7cb3cfe56a31892bd83391138d41a667" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Sep 14 09:53:02 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Sep 17 10:16:52 2010 +0100" }, "message": "ARM: 6389/1: errata: incorrect hazard handling in the SCU may lead to data corruption\n\nOn the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption\ncan occur if a shared cache line is replaced on one CPU as another CPU\nis accessing it.\n\nThis workaround sets two bits in the diagnostic register of the Cortex-A9,\nreducing the linefill issuing capabilities of the processor and\navoiding the erroneous behaviour.\n\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9f05027c7cb3cfe56a31892bd83391138d41a667", "tree": "efe9361be8e1b8d78ff44ef13a1e46e1a4b9b23a", "parents": [ "6491848d1ab246f6d243ddef25085fc1d836ff2c" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Sep 14 09:51:43 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Sep 17 10:16:51 2010 +0100" }, "message": "ARM: 6388/1: errata: DMB operation may be faulty\n\nOn versions of the Cortex-A9 up to and including r2p2, under rare\ncircumstances, a DMB instruction between 2 write operations may not\nensure the correct visibility ordering of the 2 writes.\n\nThis workaround sets a bit in the diagnostic register of the Cortex-A9,\ncausing the DMB instruction to behave like a DSB, which functions\ncorrectly on the affected cores.\n\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "6491848d1ab246f6d243ddef25085fc1d836ff2c", "tree": "c818251255daf1edc51f4fe04b2a34c0e8580c2c", "parents": [ "63f469324f999a28e67b90eb27a5fe0e379b7064" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Sep 14 09:50:03 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Sep 17 10:16:50 2010 +0100" }, "message": "ARM: 6387/1: errata: check primary part ID in proc-v7.S\n\nKconfig doesn\u0027t have any knowledge of specific v7 cores, so it is possible\nto select errata workarounds that may cause inadvertent behaviour when\nexecuted on a core other than those targetted by the fix.\n\nThis patch improves the variant and revision checking in proc-v7.S so\nthat the primary part number is also considered when applying errata\nworkarounds.\n\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "2be23c475af8ae4e25f8bab08d815b17593bd547", "tree": "864cf9dca5faaa51c9346a8835c8f101bd5c8fa2", "parents": [ "a387f0f5409276c5cf75eecb61ef6e6896f851b4" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Sep 08 16:27:56 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Sep 08 16:27:56 2010 +0100" }, "message": "ARM: Ensure PTE modifications via dma_alloc_coherent are visible\n\nDave Hylands reports:\n| We\u0027ve observed a problem with dma_alloc_writecombine when the system\n| is under heavy load (heavy bus traffic). We\u0027ve managed to reduce the\n| problem to the following snippet, which is run from a kthread in a\n| continuous loop:\n|\n| void *virtAddr;\n| dma_addr_t physAddr;\n| unsigned int numBytes \u003d 256;\n|\n| for (;;) {\n| virtAddr \u003d dma_alloc_writecombine(NULL,\n| numBytes, \u0026physAddr, GFP_KERNEL);\n| if (virtAddr \u003d\u003d NULL) {\n| printk(KERN_ERR \"Running out of memory\\n\");\n| break;\n| }\n|\n| /* access DMA memory allocated */\n| tmp \u003d virtAddr;\n| *tmp \u003d 0x77;\n|\n| /* free DMA memory */\n| dma_free_writecombine(NULL,\n| numBytes, virtAddr, physAddr);\n|\n| ...sleep here...\n| }\n|\n| By itself, the code will run forever with no issues. However, as we\n| increase our bus traffic (typically using DMA) then the *tmp \u003d 0x77\n| line will eventually cause a page fault. If we add a small delay (a\n| few microseconds) before the *tmp \u003d 0x77, then we don\u0027t see a page\n| fault, even under heavy load.\n\nA dsb() is required after modifying the PTE entries to ensure that they\nwill always be visible. Add this dsb().\n\nReported-by: Dave Hylands \u003cdhylands@gmail.com\u003e\nTested-by: Dave Hylands \u003cdhylands@gmail.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "026b5ca3b65f878019a8eb0c7a702cd5c20a4104", "tree": "fbab114954b4134635af3b93f5fcddd6e32ce025", "parents": [ "b6d17c1a8e64e8b7f58dde3d353de664a492908a" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Wed Sep 01 14:33:29 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Sep 02 15:32:13 2010 +0100" }, "message": "ARM: 6344/1: Mark CPU_32v6K as depended on CPU_V7\n\nCPU_32v6K is selected by CPU_V7 but it only depends on CPU_V6.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nAcked-by: Uwe Kleine-König \u003cu.kleine-koenig@pengutronix.de\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "0b019a41553a919965bb02d07d54e3e6c57a796d", "tree": "6e329b4159b440d2aac5200a5c07103fe261c096", "parents": [ "5f6878b0d22f9b93f9698f88c335007e2a3c3bbc", "054d5c9238f3c577ad51195c3ee7803613f322cc" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Aug 10 23:17:52 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Aug 10 23:17:52 2010 +0100" }, "message": "Merge branches \u0027master\u0027 and \u0027devel\u0027 into for-linus\n\nConflicts:\n\tarch/arm/Kconfig\n\tarch/arm/mm/Kconfig\n" }, { "commit": "597781f3e51f48ef8e67be772196d9e9673752c4", "tree": "6e1974bc899889da40f2fde47b04a5ece0bd3399", "parents": [ "3edd4fc9537d95e460d502987c63a90d6b9a7a82" ], "author": { "name": "Cesar Eduardo Barros", "email": "cesarb@cesarb.net", "time": "Mon Aug 09 17:18:32 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Aug 09 20:44:54 2010 -0700" }, "message": "kmap_atomic: make kunmap_atomic() harder to misuse\n\nkunmap_atomic() is currently at level -4 on Rusty\u0027s \"Hard To Misuse\"\nlist[1] (\"Follow common convention and you\u0027ll get it wrong\"), except in\nsome architectures when CONFIG_DEBUG_HIGHMEM is set[2][3].\n\nkunmap() takes a pointer to a struct page; kunmap_atomic(), however, takes\ntakes a pointer to within the page itself. This seems to once in a while\ntrip people up (the convention they are following is the one from\nkunmap()).\n\nMake it much harder to misuse, by moving it to level 9 on Rusty\u0027s list[4]\n(\"The compiler/linker won\u0027t let you get it wrong\"). This is done by\nrefusing to build if the type of its first argument is a pointer to a\nstruct page.\n\nThe real kunmap_atomic() is renamed to kunmap_atomic_notypecheck()\n(which is what you would call in case for some strange reason calling it\nwith a pointer to a struct page is not incorrect in your code).\n\nThe previous version of this patch was compile tested on x86-64.\n\n[1] http://ozlabs.org/~rusty/index.cgi/tech/2008-04-01.html\n[2] In these cases, it is at level 5, \"Do it right or it will always\n break at runtime.\"\n[3] At least mips and powerpc look very similar, and sparc also seems to\n share a common ancestor with both; there seems to be quite some\n degree of copy-and-paste coding here. The include/asm/highmem.h file\n for these three archs mention x86 CPUs at its top.\n[4] http://ozlabs.org/~rusty/index.cgi/tech/2008-03-30.html\n[5] As an aside, could someone tell me why mn10300 uses unsigned long as\n the first parameter of kunmap_atomic() instead of void *?\n\nSigned-off-by: Cesar Eduardo Barros \u003ccesarb@cesarb.net\u003e\nCc: Russell King \u003clinux@arm.linux.org.uk\u003e (arch/arm)\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e (arch/mips)\nCc: David Howells \u003cdhowells@redhat.com\u003e (arch/frv, arch/mn10300)\nCc: Koichi Yasutake \u003cyasutake.koichi@jp.panasonic.com\u003e (arch/mn10300)\nCc: Kyle McMartin \u003ckyle@mcmartin.ca\u003e (arch/parisc)\nCc: Helge Deller \u003cdeller@gmx.de\u003e (arch/parisc)\nCc: \"James E.J. Bottomley\" \u003cjejb@parisc-linux.org\u003e (arch/parisc)\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e (arch/powerpc)\nCc: Paul Mackerras \u003cpaulus@samba.org\u003e (arch/powerpc)\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e (arch/sparc)\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e (arch/x86)\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e (arch/x86)\nCc: \"H. Peter Anvin\" \u003chpa@zytor.com\u003e (arch/x86)\nCc: Arnd Bergmann \u003carnd@arndb.de\u003e (include/asm-generic)\nCc: Rusty Russell \u003crusty@rustcorp.com.au\u003e (\"Hard To Misuse\" list)\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "2192482ee5ce5d5d4a6cec0c351b2d3a744606eb", "tree": "15ab3c23d05e98829741b03922b51b81fd102b64", "parents": [ "500b9fc922cbec572f4fd1436533bfaed5011262", "a68fefe0d2f364ac3d8497ef37dcad713c261103" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Aug 09 14:07:19 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Aug 09 14:07:19 2010 +0100" }, "message": "Merge branch \u0027for-rmk\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into devel-stable\n\nConflicts:\n\tarch/arm/Kconfig\n" }, { "commit": "c5f800656bc985b448b1d848d309648826536543", "tree": "efac337e79b73bf24ce639840e41f77bcd46d707", "parents": [ "cdd854bc42b5e6c79bbbc40c6600d995ffe6e747" ], "author": { "name": "Erik Gilling", "email": "konkers@android.com", "time": "Thu Jan 21 16:53:02 2010 -0800" }, "committer": { "name": "Erik Gilling", "email": "konkers@android.com", "time": "Thu Aug 05 14:51:42 2010 -0700" }, "message": "[ARM] tegra: initial tegra support\n\nv2: Fixes from Mike Rapoport\n\t- remove unused header files (mach/dma.h and mach/nand.h)\n\t- remove tegra 1 references from Makefile.boot\n\nv2: fixes from Russell King\n\t- remove mach/io.h include from mach/iomap.h\n\t- fix whitespace in Kconfig\n\nv2: from Colin Cross\n\t- fix invalid immediate in debug-macro.S\n\nv3:\n\t- allow selection of multiple boards\n\nSigned-off-by: Colin Cross \u003cccross@android.com\u003e\nSigned-off-by: Erik Gilling \u003ckonkers@android.com\u003e\n" }, { "commit": "cc0e72b87a4afb520fab09b67e1c16e4ec4aaadb", "tree": "e105572441c714d86c84d611f375dd1c32f372c6", "parents": [ "cfca3a619baeaba3a0037fef5da48108e9c0bb1c" ], "author": { "name": "Changhwan Youn", "email": "chaos.youn@samsung.com", "time": "Fri Jul 16 12:15:38 2010 +0900" }, "committer": { "name": "Kukjin Kim", "email": "kgene.kim@samsung.com", "time": "Thu Aug 05 18:32:42 2010 +0900" }, "message": "ARM: S5PV310: Add new Kconfig and Makefiles\n\nThis patch adds the Kconfig and Makefile for the new S5PV310 SoC.\nIt also updates arch/arm Kconfig, Makefile and arch/arm/mm/Kconfig\nto include support for the new S5PV310.\n\nSigned-off-by: Changhwan Youn \u003cchaos.youn@samsung.com\u003e\nSigned-off-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\n" }, { "commit": "be82ae0238b0453afcf4a76f0512b7dde34ba500", "tree": "aaa3f5f11fd51fd73365ee1a2164aad9a03de060", "parents": [ "4b4fd27c0b5ec638a1f06ced9226fd95229dbbf0", "7b70c4275f28702b76b273c8534c38f8313812e9" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Aug 03 14:31:24 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Aug 03 14:31:24 2010 -0700" }, "message": "Merge branch \u0027devel\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027devel\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm: (291 commits)\n ARM: AMBA: Add pclk support to AMBA bus infrastructure\n ARM: 6278/2: fix regression in RealView after the introduction of pclk\n ARM: 6277/1: mach-shmobile: Allow users to select HZ, default to 128\n ARM: 6276/1: mach-shmobile: remove duplicate NR_IRQS_LEGACY\n ARM: 6246/1: mmci: support larger MMCIDATALENGTH register\n ARM: 6245/1: mmci: enable hardware flow control on Ux500 variants\n ARM: 6244/1: mmci: add variant data and default MCICLOCK support\n ARM: 6243/1: mmci: pass power_mode to the translate_vdd callback\n ARM: 6274/1: add global control registers definition header file for nuc900\n mx2_camera: fix type of dma buffer virtual address pointer\n mx2_camera: Add soc_camera support for i.MX25/i.MX27\n arm/imx/gpio: add spinlock protection\n ARM: Add support for the LPC32XX arch\n ARM: LPC32XX: Arch config menu supoport and makefiles\n ARM: LPC32XX: Phytec 3250 platform support\n ARM: LPC32XX: Misc support functions\n ARM: LPC32XX: Serial support code\n ARM: LPC32XX: System suspend support\n ARM: LPC32XX: GPIO, timer, and IRQ drivers\n ARM: LPC32XX: Clock driver\n ...\n" }, { "commit": "7b70c4275f28702b76b273c8534c38f8313812e9", "tree": "1df2229ca02466bd1adda814ac5c37aa0a597db1", "parents": [ "ceb0885d3b01bb2e2f18765770e212914f2864be", "a20df564d15bd28e3df24e1c65b885bd74d23f17" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Jul 31 14:20:16 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Jul 31 14:20:16 2010 +0100" }, "message": "Merge branch \u0027devel-stable\u0027 into devel\n\nConflicts:\n\tarch/arm/kernel/entry-armv.S\n\tarch/arm/kernel/setup.c\n\tarch/arm/mm/init.c\n" }, { "commit": "ceb0885d3b01bb2e2f18765770e212914f2864be", "tree": "0952c90cd49704a9172e985ca491d79b60c40bc8", "parents": [ "b31fc7af78e17b0203e1cd5a195c590e8adeae0d", "08458ef6eede6cf7d5a33c3a7c8bcdc3943012c2" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Jul 31 14:20:02 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Jul 31 14:20:02 2010 +0100" }, "message": "Merge branch \u0027misc\u0027 into devel\n\nConflicts:\n\tarch/arm/mm/init.c\n" }, { "commit": "b31fc7af78e17b0203e1cd5a195c590e8adeae0d", "tree": "4032893d60c28e28a39bace2c48483352f626ba9", "parents": [ "f13b1035ce8bbc27d4ce7c281cddd2718f2cf5b0", "4037242c4f5ff77afe61bf07ca1e8a99490219e5", "a0fb007bf0c7de9ae361a9ad3821df4c69d4d2d9", "cea0bb1bc59b94625e60b69aaa9ad6749d5b57dd", "7d63397574c874a05e071987248c44fcf13eccf1", "a9deb137e4eb94d0a4fa0c3535b2c056d9363bef", "39ae702cd3b8b9d30693b73ad1a3d74c799b5b1a", "f4f5e28d2ee02e3b68da4a8b6156f3b4872d03be", "7cfe249475fdd82ad3c2767a9b906cc775dab868", "4bd48940190a34fe5a78a1595ec7756edf36b18a", "a3e5bb42898d10cff1d054d4b115d4dd608c0566" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Jul 31 14:19:35 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Jul 31 14:19:35 2010 +0100" }, "message": "Merge branches \u0027at91\u0027, \u0027ep93xx\u0027, \u0027kexec\u0027, \u0027iop\u0027, \u0027lmb\u0027, \u0027nomadik\u0027, \u0027nuc\u0027, \u0027pl\u0027, \u0027spear\u0027 and \u0027versatile\u0027 into devel\n" }, { "commit": "831e8047eb2af310184a9d4d9e749f3de119ae39", "tree": "f9fd2e3982796a50e2d2b9374c80ba0c1c4204bb", "parents": [ "b92b3612134faff171981fad4f0adb33f485e02e" ], "author": { "name": "Gary King", "email": "gking@nvidia.com", "time": "Thu Jul 29 17:37:20 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jul 30 23:16:07 2010 +0100" }, "message": "ARM: 6279/1: highmem: fix SMP preemption bug in kmap_high_l1_vipt\n\nsmp_processor_id() must not be called from a preemptible context (this\nis checked by CONFIG_DEBUG_PREEMPT). kmap_high_l1_vipt() was doing so.\nThis lead to a problem where the wrong per_cpu kmap_high_l1_vipt_depth\ncould be incremented, causing a BUG_ON(*depth \u003c\u003d 0); in\nkunmap_high_l1_vipt().\n\nThe solution is to move the call to smp_processor_id() after the call\nto preempt_disable().\n\nOriginally by: Andrew Howe \u003cahowe@nvidia.com\u003e\n\nSigned-off-by: Gary King \u003cgking@nvidia.com\u003e\nAcked-by: Nicolas Pitre \u003cnico.as.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "6775a558fece413376e1dacd435adb5fbe225f40", "tree": "e4428d3915151d3718a9687f843ecec115aeb546", "parents": [ "e936771a76a7b61ca55a5142a3de835c2e196871" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Wed Jul 28 22:01:25 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 29 14:04:36 2010 +0100" }, "message": "ARM: 6272/1: Convert L2x0 to use the IO relaxed operations\n\nThis patch is in preparation for a subsequent patch which adds barriers\nto the I/O accessors. Since the mandatory barriers may do an L2 cache\nsync, this patch avoids a recursive call into l2x0_cache_sync() via the\nwrite*() accessors and wmb() and a call into l2x0_cache_sync() with the\nl2x0_lock held.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "9ca03a21e320a6bf44559323527aba704bcc8772", "tree": "c3422c49decfdca220c0088938546c49ee71ba64", "parents": [ "b8ab5397bcbd92e3fd4a9770e0bf59315fa38dab" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jul 26 12:22:12 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 10:48:42 2010 +0100" }, "message": "ARM: Factor out common code from cpu_proc_fin()\n\nAll implementations of cpu_proc_fin() start by disabling interrupts\nand then flush caches. Rather than have every processors proc_fin()\nimplementation do this, move it out into generic code - and move the\ncache flush past setup_mm_for_reboot() (so it can benefit from having\ncaches still enabled.)\n\nThis allows cpu_proc_fin() to become independent of the L1/L2 cache\ntypes, and eventually move the L2 cache flushing into the L2 support\ncode.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b8ab5397bcbd92e3fd4a9770e0bf59315fa38dab", "tree": "4def9ea84d54ce112c91e906e10fb8756151327c", "parents": [ "993bf4ec8c2a2b7979389ab196bf2fe217117158" ], "author": { "name": "Kirill A. Shutemov", "email": "kirill@shutemov.name", "time": "Mon Jul 26 11:20:41 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 10:48:41 2010 +0100" }, "message": "ARM: 6268/1: ARMv6K and ARMv7 use fault statuses 3 and 6 as Access Flag fault\n\nStatuses 3 (0b00011) and 6 (0x00110) of DFSR are Access Flags faults on\nARMv6K and ARMv7. Let\u0027s patch fsr_info[] at runtime if we are on ARMv7\nor later.\n\nUnfortunately, we don\u0027t have runtime check for \u0027K\u0027 extension, so we\ncan\u0027t check for it.\n\nSigned-off-by: Kirill A. Shutemov \u003ckirill@shutemov.name\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "993bf4ec8c2a2b7979389ab196bf2fe217117158", "tree": "a7363405e866c1ae7a6259fb7fc85adf2208adaa", "parents": [ "33a9c41bf5d8adae9d882513e617c4c645195e71" ], "author": { "name": "Kirill A. Shutemov", "email": "kirill@shutemov.name", "time": "Thu Jul 22 13:23:25 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 10:48:41 2010 +0100" }, "message": "ARM: 6256/1: Check arch version and modify fsr_info[] depends on it at runtime\n\nSigned-off-by: Kirill A. Shutemov \u003ckirill@shutemov.name\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "33a9c41bf5d8adae9d882513e617c4c645195e71", "tree": "adcb4a60ff55f9b3f88eaeeca628f7398300121e", "parents": [ "6338a6aa7c082f11d55712251e14178c68bf5869" ], "author": { "name": "Kirill A. Shutemov", "email": "kirill@shutemov.name", "time": "Thu Jul 22 13:20:22 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 10:48:41 2010 +0100" }, "message": "ARM: 6255/1: Workaround infinity loop in handling of translation faults\n\nOn ARM one Linux PGD entry contains two hardware entries (see page\ntables layout in pgtable.h). We normally guarantee that we always\nfill both L1 entries. But create_mapping() doesn\u0027t follow the rule.\nIt can create inidividual L1 entries, so here we have to call\npmd_none() check in do_translation_fault() for the entry really\ncorresponded to address, not for the first of pair.\n\nSigned-off-by: Kirill A. Shutemov \u003ckirill@shutemov.name\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "6338a6aa7c082f11d55712251e14178c68bf5869", "tree": "4d85f1401efd41757741388e4b6a3801fa8d4d8b", "parents": [ "3dc91aff9c3ef54b15cdaf32f61f973489fe69eb" ], "author": { "name": "Kirill A. Shutemov", "email": "kirill@shutemov.name", "time": "Thu Jul 22 13:18:19 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 10:48:34 2010 +0100" }, "message": "ARM: 6269/1: Add \u0027code\u0027 parameter for hook_fault_code()\n\nAdd one more parameter to hook_fault_code() to be able to set \u0027code\u0027\nfield of struct fsr_info.\n\nSigned-off-by: Kirill A. Shutemov \u003ckirill@shutemov.name\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "3dc91aff9c3ef54b15cdaf32f61f973489fe69eb", "tree": "6ce52b2b5ea6cb1b0317142ecf06b04d52bc1d34", "parents": [ "c1ba6ba3dd4c127dd1b14125ac7feed43d974436" ], "author": { "name": "Kirill A. Shutemov", "email": "kirill@shutemov.name", "time": "Thu Jul 22 13:16:49 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 10:43:49 2010 +0100" }, "message": "ARM: 6252/1: Use SIGBUS for unaligned access instead of SIGILL\n\nPOSIX specify to use signal SIGBUS with code BUS_ADRALN for invalid\naddress alignment.\n\nSigned-off-by: Kirill A. Shutemov \u003ckirill@shutemov.name\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "5bc23d32d86a132b5636a48dca0fa2528ef69ff9", "tree": "b23c8c9ad3693e39e42b2fb389aab037b14ed9a0", "parents": [ "d746196361c9c635128249bb6cf13e709ae6abe1" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Jul 25 08:57:02 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 10:43:48 2010 +0100" }, "message": "ARM: DMA coherent allocator: align remapped addresses\n\nThe DMA coherent remap area is used to provide an uncached mapping\nof memory for coherency with DMA engines. Currently, we look for\nany free hole which our allocation will fit in with page alignment.\n\nHowever, this can lead to fragmentation of the area, and allows small\nallocations to cross L1 entry boundaries. This is undesirable as we\nwant to move towards allocating sections of memory.\n\nAlign allocations according to the size, limiting the alignment between\nthe page and section sizes.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d746196361c9c635128249bb6cf13e709ae6abe1", "tree": "112d387c207d06849c7ced234df9d9bcdc9bf7f5", "parents": [ "ac3e3fb424d44109dda3b1a3459e1b30fa60ac4a" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jul 26 10:29:13 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 10:43:47 2010 +0100" }, "message": "ARM: use generic ioremap_page_range()\n\nWe don\u0027t need our own implementation of this, use the generic\nlibrary implementation instead.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "4708ac49305bbcd511600d4af71a4c6dca15af65", "tree": "77ba5c83a7d4f4a119e3fd524d82adc297df1e35", "parents": [ "1dbd30e9890fd69e50b17edd70ca583546b0fe4e", "2f7989efd4398d92b8adffce2e07dd043a0895fe" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 10:42:48 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 10:42:52 2010 +0100" }, "message": "Merge branch \u0027origin\u0027 into misc\n" }, { "commit": "1dbd30e9890fd69e50b17edd70ca583546b0fe4e", "tree": "5b5ab74c1792a81340478f7bbccd053e60a23a5e", "parents": [ "07d2a5c721c6aa2bd69812a74c8b3b116abf3e56" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Mon Jul 12 21:53:28 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 10:42:38 2010 +0100" }, "message": "ARM: 6225/1: make TCM allocation static and common for all archs\n\nThis changes the TCM handling so that a fixed area is reserved at\n0xfffe0000-0xfffeffff for TCM. This areas is used by XScale but\nXScale does not have TCM so the mechanisms are mutually exclusive.\n\nThis change is needed to make TCM detection more dynamic while\nstill being able to compile code into it, and is a must for the\nunified ARM goals: the current TCM allocation at different places\nin memory for each machine would be a nightmare if you want to\ncompile a single image for more than one machine with TCM so it\nhas to be nailed down in one place.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a9deb137e4eb94d0a4fa0c3535b2c056d9363bef", "tree": "27d76af7e2cf402d48df0d0a1a68c8afefbe8928", "parents": [ "e07b9e08601b400aee7e076e7b31799d3dd48c1e" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 01 18:35:07 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 08:48:25 2010 +0100" }, "message": "ARM: Remove unnecessary call to find_limits()\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "e07b9e08601b400aee7e076e7b31799d3dd48c1e", "tree": "28a030ef024bb5677546c8a6dad2769176bb0545", "parents": [ "eda2e5dcc914b4d70f665443efc9780e89a5e5c1" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 01 12:03:29 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 08:48:24 2010 +0100" }, "message": "ARM: LMB: convert pfn_valid to use LMB\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "eda2e5dcc914b4d70f665443efc9780e89a5e5c1", "tree": "7ae6f96890ca4a5b7e9c14bf0723f9f275ddfe87", "parents": [ "98864ff58dd2b8ef9e72b0d2c70f34e7ff24a2ee" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 01 12:00:57 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 08:48:23 2010 +0100" }, "message": "ARM: LMB: Convert arm_memory_present() to use LMB memory information\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "8d717a52d1b0959128be5134dd12608e8e4f2115", "tree": "6bc2aca8c9b14a9b0d2f86609e63c2436b03c2d6", "parents": [ "2778f62056ada442414392d7ccd41188bb631619" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 22 19:47:18 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 08:48:23 2010 +0100" }, "message": "ARM: Convert platform reservations to use LMB rather than bootmem\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "2778f62056ada442414392d7ccd41188bb631619", "tree": "a7c15cc7ca077e5e4c2161f5062c44e408c03a08", "parents": [ "4bb2e27db10abc555dfabd73661485fb75e4e97d" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jul 09 16:27:52 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 08:48:22 2010 +0100" }, "message": "ARM: initial LMB trial\n\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "4bb2e27db10abc555dfabd73661485fb75e4e97d", "tree": "4d2bf627268e82162583ed35c20ff047ca4d5e2f", "parents": [ "3abe9d33b382cb9eee7bfee8d90b10078f4baa4d" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 01 18:33:29 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jul 27 08:47:59 2010 +0100" }, "message": "ARM: early_pte_alloc()\n\nProvide a common function for allocating early PTE tables.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "14764b01a5576ce23a9d0c95a027049206a19cef", "tree": "fa7f4e3b9b62598076baf7d312dd37d6c91b0d56", "parents": [ "fc4978b796e5e52ab3a709495a968199afe0a108", "5ccd4302a20bfe56eb72a5e27ad0be046fc820a5" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jul 21 09:22:45 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jul 21 09:22:45 2010 +0100" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stable\n" }, { "commit": "07d2a5c721c6aa2bd69812a74c8b3b116abf3e56", "tree": "40ab4a702ab18547aa0be9b84e63da222ff50597", "parents": [ "598509779e5b8037d371df764d7438744a24b61f" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Mon Jul 12 21:52:34 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Jul 18 20:29:48 2010 +0100" }, "message": "ARM: 6224/1: print TCM whereabouts in init message\n\nIf TCM is in use, we should display it in the virtual memory\nlayout along with everything else.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "cb9d7707cd9be57830f31616233f6a872ca8416d", "tree": "6b380a5fc3c0f8efcc97455ee85a08da1d6ce4f9", "parents": [ "f159f4ed55bb0fa5470800641e03a13a7e0eae6e" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Mon Jul 12 21:50:59 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Jul 18 20:29:47 2010 +0100" }, "message": "ARM: 6222/1: add memory types for the TCMs\n\nThe earlier TCM memory regions were mapped as MT_MEMORY_UNCACHED\nwhich doesn\u0027t really work on platforms supporting the new v6\nfeatures like the NX bit. Add unique MT_MEMORY_[I|D]TCM types\ninstead.\n\nCc: Nicolas Pitre \u003cnico@fluxnic.net\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "3abe9d33b382cb9eee7bfee8d90b10078f4baa4d", "tree": "80c3307c1297405c64f1ab4efbba5195bba48b6d", "parents": [ "71ee7dad9b69917079f24d42aff796bad7932914" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 25 17:02:59 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jul 16 11:06:42 2010 +0100" }, "message": "ARM: early_alloc()\n\nAdd a common early allocator function, in preparation for switching\nover to LMB. When we do, this function will need to do a little more\nthan just allocating memory; we need it zero initialized too.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "98c672cf1fa2a56f6f43e3f48b1208b83845582c", "tree": "39ac68eb0d260f090cebabff9a2f2cf8c6bcebd2", "parents": [ "b65b4781fbd5846a82cdac0c32818af1a7452d1f" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 22 18:18:57 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jul 16 11:06:40 2010 +0100" }, "message": "ARM: Move platform memory reservations out of generic code\n\nMove the platform specific bootmem memory reservations out of\narch/arm/mm/mmu.c into their respective platform files.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b65b4781fbd5846a82cdac0c32818af1a7452d1f", "tree": "532f95a901c0d7dcd1d628e68d7984f09750bb4d", "parents": [ "be370302742ff9948f2a42b15cb2ba174d97b930" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 22 20:58:51 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jul 16 10:57:36 2010 +0100" }, "message": "ARM: Remove \u0027node\u0027 argument form arch_adjust_zones()\n\nSince we no longer support discontigmem, node is always zero, so\nremove this argument.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "be370302742ff9948f2a42b15cb2ba174d97b930", "tree": "977bfa71c1e1483c22a40d85dfd3b233e5ac5d06", "parents": [ "7961239599de71130c852ecfa9a4140f3f60547b" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri May 07 17:40:33 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jul 16 10:57:35 2010 +0100" }, "message": "ARM: Remove DISCONTIGMEM support\n\nEverything should now be using sparsemem rather than discontigmem, so\nremove the code supporting discontigmem from ARM.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7961239599de71130c852ecfa9a4140f3f60547b", "tree": "99f08f76ad8dfd8c671f713a3ec87769dc315632", "parents": [ "2f7989efd4398d92b8adffce2e07dd043a0895fe" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 22 16:20:14 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jul 16 10:57:35 2010 +0100" }, "message": "ARM: Precalculate vmalloc_min\n\nRather than storing the minimum size of the vmalloc area, store the\nmaximum permitted address of the vmalloc area instead.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f159f4ed55bb0fa5470800641e03a13a7e0eae6e", "tree": "c2ed54b103c2a1c58fa4b50740fec462ccfeec74", "parents": [ "c1b2d9704c77ddaec46d5d681e1360ac40268743" ], "author": { "name": "Tony Lindgren", "email": "tony@atomide.com", "time": "Mon Jul 05 14:53:10 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jul 09 14:41:35 2010 +0100" }, "message": "ARM: 6207/1: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6\n\nThe TLS register is only available on ARM1136 r1p0 and later.\nSet HWCAP_TLS flags if hardware TLS is available and test for\nit if CONFIG_CPU_32v6K is not set for V6.\n\nNote that we set the TLS instruction in __kuser_get_tls\ndynamically as suggested by Jamie Lokier \u003cjamie@shareable.org\u003e.\n\nAlso the __switch_to code is optimized out in most cases as\nsuggested by Nicolas Pitre \u003cnico@fluxnic.net\u003e.\n\nReviewed-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "4082cfa77680a70e407efdfb207c743107bd8fe4", "tree": "50220be137306502a61dfcc866c5482b14317783", "parents": [ "e467e104bb7482170b79f516d2025e7cfcaaa733" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Thu Jul 08 08:36:21 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jul 09 11:28:53 2010 +0100" }, "message": "ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRL\n\nOn i.MX35 the L2X0_AUX_CTRL register does not have sensible reset\ndefault values. Allow them to be overwritten with the aux_val/aux_mask\narguments passed to l2x0_init().\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "42c4dafe803dcad82980fd8b0831a89032156f93", "tree": "4ee6615d25d034420925215ee798924f54b4a0c3", "parents": [ "2503a5ecd86c002506001eba432c524ea009fe7f" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu Jul 01 13:22:48 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Jul 02 10:10:20 2010 +0100" }, "message": "ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220\n\nRealView boards with certain revisions of the L210/L220 cache controller\nmay have issues (hardware deadlock) with the mandatory barriers (DSB\nfollowed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled.\nThe patch disables ARM_DMA_MEM_BUFFERABLE for these boards.\n\nTested-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ad642d9f58f1af6e96efccb5f84e52c6d01db5c4", "tree": "4319ed1e81f50c7035457cc0fa1cf4bcdf760abb", "parents": [ "ca57926d53580f7c950496cb7ef6d7930610e1dd" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Mon Jun 21 15:10:07 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 01 10:12:31 2010 +0100" }, "message": "ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance workaround\n\nCommit f4d6477f introduced a workaround for the lack of hardware\nbroadcasting of the cache maintenance operations on ARM11MPCore.\nHowever, the workaround is only valid on CPUs that do not do speculative\nloads into the D-cache.\n\nThis patch adds a Kconfig option with the corresponding help to make the\nabove clear. When the DMA_CACHE_RWFO option is disabled, the kernel\nbehaviour is that prior to the f4d6477f commit. This also allows ARMv6\nUP processors with speculative loads to work correctly.\n\nFor other processors, a different workaround may be needed.\n\nCc: Ronen Shitrit \u003crshitrit@marvell.com\u003e\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ca57926d53580f7c950496cb7ef6d7930610e1dd", "tree": "93a559372fcc905726c6e253e463d101a5916837", "parents": [ "a5e9d38b226686c89fd78413456535d5b66e8b1f" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Mon Jun 21 15:09:36 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 01 10:12:14 2010 +0100" }, "message": "ARM: 6187/1: The v6_dma_inv_range() function must preserve data on SMP\n\nA recent patch for DMA cache maintenance on ARM11MPCore added a write\nfor ownership trick to the v6_dma_inv_range() function. Such operation\ndestroys data already present in the buffer. However, this function is\nused with with dma_sync_single_for_device() which is supposed to\npreserve the existing data transfered into the buffer. This patch adds a\ncombination of read/write for ownership to preserve the original data.\n\nReported-by: Ronen Shitrit \u003crshitrit@marvell.com\u003e\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a5e9d38b226686c89fd78413456535d5b66e8b1f", "tree": "48a58b3a8630a8a436f3f4b57580ced6685ceaec", "parents": [ "980019d74e4b2428362b36a0506519d6d9460800" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Mon Jun 21 15:09:06 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 01 10:12:07 2010 +0100" }, "message": "ARM: 6186/1: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds\n\nThis macro is not defined when !CONFIG_MMU so this patch moves the\nCONSISTENT_* definitions to the CONFIG_MMU section.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "fc4978b796e5e52ab3a709495a968199afe0a108", "tree": "102c74707940214f3c9810dadaf62d0d378a7a8c", "parents": [ "3260e5293727f16ffdce9a6a6203fd9a6b149e58", "df0698be14c6683606d5df2d83e3ae40f85ed0d9" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jun 30 11:00:01 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jun 30 11:00:01 2010 +0100" }, "message": "Merge git://git.linaro.org/nico/arm_security into devel-stable\n" }, { "commit": "309caa9cc6ff39d261264ec4ff10e29489afc8f8", "tree": "7ade7d69461250a39fabcd8a79d885253c6fd299", "parents": [ "7e27d6e778cd87b6f2415515d7127eba53fe5d02" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jun 21 21:03:18 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Jun 21 21:03:18 2010 +0100" }, "message": "ARM: Prohibit ioremap() on kernel managed RAM\n\nARMv6 and above have a restriction whereby aliasing virtual:physical\nmappings must not have differing memory type and sharability\nattributes. Strictly, this covers the memory type (strongly ordered,\ndevice, memory), cache attributes (uncached, write combine, write\nthrough, write back read alloc, write back write alloc) and the\nshared bit.\n\nHowever, using ioremap() and its variants on system RAM results in\nmappings which differ in these attributes from the main system RAM\nmapping. Other architectures which similar restrictions approch this\nproblem in the same way - they do not permit ioremap on main system\nRAM.\n\nMake ARM behave in the same way, with a WARN_ON() such that users can\nbe traced and an alternative approach found.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "3260e5293727f16ffdce9a6a6203fd9a6b149e58", "tree": "5be7569566f262f3c953e8ac9bbec6f656c03354", "parents": [ "923a081c72fa2dccb7ea7070bd8e0f4dc99ceff8" ], "author": { "name": "Michael Bohan", "email": "mbohan@codeaurora.org", "time": "Mon Jun 14 13:06:56 2010 -0700" }, "committer": { "name": "Daniel Walker", "email": "dwalker@codeaurora.org", "time": "Tue Jun 15 13:19:55 2010 -0700" }, "message": "arm: mm: Don\u0027t free prohibited memmap entries\n\nThe VM subsystem assumes that there are valid memmap entries to\nthe bank end aligned to MAX_ORDER_NR_PAGES. It will try and read\nthese page structs, and so we cannot free any memmap entries that\nit may inspect.\n\nSigned-off-by: Michael Bohan \u003cmbohan@codeaurora.org\u003e\nSigned-off-by: Daniel Walker \u003cdwalker@codeaurora.org\u003e\n" }, { "commit": "cc92c28b2db5b406657ecc05235d4ca4e222ae34", "tree": "202734aa4fc2e5b9953deb3fa8a5d249e21a7fe2", "parents": [ "990cb8acf23cab19a2930f1ed5e7dc108f89079b" ], "author": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Mon Jun 14 21:16:19 2010 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Mon Jun 14 21:22:11 2010 -0400" }, "message": "[ARM] add address randomization to mmap()\n\nSigned-off-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "9a40ac86152c9cffd3dca482a15ddf9a8c5716b3", "tree": "52a74a0826d771141b78b1a04928e75df5726ebf", "parents": [ "76962be8491b18ae7ff4fd6a4accd398bdb402a2" ], "author": { "name": "Khem Raj", "email": "raj.khem@gmail.com", "time": "Fri Jun 04 04:05:15 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jun 08 19:42:18 2010 +0100" }, "message": "ARM: 6164/1: Add kto and kfrom to input operands list.\n\nWhen functions incoming parameters are not in input operands list gcc\n4.5 does not load the parameters into registers before calling this\nfunction but the inline assembly assumes valid addresses inside this\nfunction. This breaks the code because r0 and r1 are invalid when\nexecution enters v4wb_copy_user_page ()\n\nAlso the constant needs to be used as third input operand so account\nfor that as well.\n\nTested on qemu arm.\n\nCC: \u003cstable@kernel.org\u003e\nSigned-off-by: Khem Raj \u003craj.khem@gmail.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "5e27fb78df95e027723af2c90ecc9b4527ae59e9", "tree": "4f91874c2d4b2beef198e9116a500a76e5751cff", "parents": [ "17ebba1fe4da4b5d62782be8743e0e8231812af9" ], "author": { "name": "Anfei", "email": "anfei.zhou@gmail.com", "time": "Tue Jun 08 15:16:49 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jun 08 19:39:57 2010 +0100" }, "message": "ARM: 6166/1: Proper prefetch abort handling on pre-ARMv6\n\nInstruction faults on pre-ARMv6 CPUs are interpreted as\na \u0027translation fault\u0027, but do_translation_fault doesn\u0027t\nhandle well if user mode trying to run instruction above\nTASK_SIZE, and result in the infinite retry of that\ninstruction.\n\nCC: \u003cstable@kernel.org\u003e\nSigned-off-by: Anfei Zhou \u003canfei.zhou@gmail.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "17ebba1fe4da4b5d62782be8743e0e8231812af9", "tree": "aef818d66f5dbe04817b88b8d0351035740118ba", "parents": [ "b394eebdd3d436f1796e53b97799554c5aa77431" ], "author": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Mon Jun 07 21:28:55 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Jun 08 19:25:50 2010 +0100" }, "message": "ARM: 6165/1: trap overflows on highmem pages from kmap_atomic when debugging\n\nWhen CONFIG_DEBUG_HIGHMEM is used, the fixmap entry used for a highmem page\nby kmap_atomic() is always cleared by kunmap_atomic(). This helps find\nbad usages such as dereferences after the unmap, or overflow into the\nadjacent fixmap areas.\n\nBut this debugging aid is completely bypassed when a kmap for the same\npage already exists as the kmap is reused instead. ON VIVT systems we\nhave no choice but to reuse that kmap due to cache coherency issues,\nbut on non VIVT systems we should always force the fixmap usage when\ndebugging is active.\n\nSigned-off-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ea208f646c8fb91c39c852e952fc911e1ad045ab", "tree": "bf4cd875b052996eb13dd30a66647334082b28a2", "parents": [ "138de1c44a8e0606501cd8593407e9248e84f1b7" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Wed May 26 07:37:57 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu May 27 10:36:07 2010 +0100" }, "message": "ARM: 6144/1: TCM memory bug freeing bug\n\nThis fixes a bug in mm/init.c when freeing the TCM compile memory,\nthis was being referred to as a char * which is incorrect: this\nwill dereference the pointer and feed in the value at the location\ninstead of the address to it. Change it to a plain char and use\n\u0026(char) to reference it.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a901ff715d53c109821cbbd9d7ea1f2a311646a9", "tree": "0d2eaa7e5ffa29aa15d966545028a7fc47d76474", "parents": [ "e1695307e6b85477afd2421d3b4891ca5bea8300" ], "author": { "name": "Santosh Shilimkar", "email": "santosh.shilimkar@ti.com", "time": "Thu May 20 08:33:38 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu May 20 23:52:38 2010 +0100" }, "message": "ARM: 6139/1: ARMv7: Use the Inner Shareable I-cache on MP\n\nThis patch fixes the flush_cache_all for ARMv7 SMP.It was\nmissing from commit b8349b569aae661dea9d59d7d2ee587ccea3336c\n\nSigned-off-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "349e1fba7e63b1067b5915337986060c13d9edd0", "tree": "7450f8355fb7f050066aab3fb94c1073e2080f7a", "parents": [ "fa9dc265ace9774e62f0e31108e5f47911124bda", "504d36e91ac12ccdb0e1193cee7bef9831a1c99e" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed May 19 11:49:33 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed May 19 11:49:33 2010 -0700" }, "message": "Merge branch \u0027for-linus/samsung4\u0027 of git://git.fluff.org/bjdooks/linux\n\n* \u0027for-linus/samsung4\u0027 of git://git.fluff.org/bjdooks/linux: (98 commits)\n Input: s3c24xx_ts - depend on SAMSUNG_DEV_TS and update menu entry\n Input: s3c24xx_ts - Add FEAT for Samsung touchscreen support\n Input: s3c24xx_ts - Implement generic GPIO configuration callback\n ARM: SAMSUNG: Move s3c64xx dev-ts.c to plat-samsung and rename configuration\n ARM: SAMSUNG: Implements cfg_gpio function for Samsung touchscreen\n ARM: S3C64XX: Add touchscreen platform device definition\n ARM: SAMSUNG: Move mach/ts.h to plat/ts.h\n ARM: S5PC100: Move i2c helpers from plat-s5pc1xx to mach-s5pc100\n ARM: S5PC100: Move frame buffer helpers from plat-s5pc1xx to mach-s5pc100\n ARM: S5PC100: gpio.h cleanup\n ARM: S5PC100: Move gpio support from plat-s5pc1xx to mach-s5pc100\n ARM: S5PC100: Use common functions for gpiolib implementation\n drivers: serial: S5PC100 serial driver cleanup\n ARM: S5PC100: Pre-requisite clock patch for plat-s5pc1xx to plat-s5p move\n ARM: SAMSUNG: Copy common I2C0 device helpers to machine directories\n ARM: SAMSUNG: move driver strength gpio configuration helper to common dir\n ARM: S5PV210: Add GPIOlib support\n ARM: SAMSUNGy: fix broken timer irq base\n ARM: SMDK6440: Add audio devices on board\n ARM: S5P6440: Add audio platform devices\n ...\n" }, { "commit": "1d3c6ff44ad4b5f113602e153026a338f0f9b3ff", "tree": "1e1f2932634fc6d0e4acfe68496c1c727b83a13e", "parents": [ "7c7cbaf5b82c418cd3b1dcf718f71d0e6057e639", "717e7c2672e37253a4d3aa70e4716b5b0a658761" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed May 19 11:37:22 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed May 19 11:37:22 2010 -0700" }, "message": "Merge branch \u0027devel\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027devel\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm: (224 commits)\n ARM: remove \u0027select GENERIC_TIME\u0027\n ARM: 6136/1: ARCH_REQUIRE_GPIOLIB selects GENERIC_GPIO\n ARM: 6074/1: oprofile: convert from sysdev to platform device\n ARM: 6073/1: oprofile: remove old files and update KConfig\n ARM: 6072/1: oprofile: use perf-events framework as backend\n ARM: 6071/1: perf-events: allow modules to query the number of hardware counters\n ARM: 6070/1: perf-events: add support for xscale PMUs\n ARM: 6069/1: perf-events: use numeric ID to identify PMU\n ARM: 6064/1: pmu: register IRQs at runtime\n ARM: Optionally allow ARMv6 to use \u0027normal, bufferable\u0027 memory for DMA\n ARM: 6134/1: Handle instruction cache maintenance fault properly\n ARM: nwfpe: allow debugging output to be configured at runtime\n ARM: rename mach_cpu_disable() to platform_cpu_disable()\n ARM: 6132/1: PL330: Add common core driver\n ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310\n ARM: Move memory mapping into mmu.c\n ARM: Ensure meminfo is sorted prior to sanity_check_meminfo\n ARM: Remove useless linux/bootmem.h includes\n ARM: convert /proc/cpu/aligment to seq_file\n arm: use asm-generic/scatterlist.h\n ...\n" }, { "commit": "ac1d426e825ab5778995f2f6f053ca2e6b45c622", "tree": "75b91356ca39463e0112931aa6790802fb1e07a2", "parents": [ "fda0e18c8a7a3e02747c2b045b4fcd2c920410b9", "a3685f00652af83f12b63e3b4ef48f29581ba48b" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon May 17 17:24:04 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon May 17 17:24:04 2010 +0100" }, "message": "Merge branch \u0027devel-stable\u0027 into devel\n\nConflicts:\n\tarch/arm/Kconfig\n\tarch/arm/include/asm/system.h\n\tarch/arm/mm/Kconfig\n" }, { "commit": "c39e52a793f5599582dbacf4d8f62634a492f79e", "tree": "7379649b5a722ceb45cc66f049a7571c66054dcd", "parents": [ "762253741942d8ddbaca1c1ee62d7ed57544332b", "8716011315a5b2fa932fa1e7570c34975ed2cb14", "4fec9978822a66b25f5645eb20c115034a18cfd1", "de4338f40e48da3b604219909a1d4aa7aa60870f", "47ab0dee661dbd5aca67abe44a333e471134fbf9", "2a847513cdecd517f7efc06296c539c3a936cf98", "883413341e479d4e9f9c69def4884b4c6e1cef4e", "3e9cc70590287f7cb7e38793bbf968b3362b7612", "4c18e77f718cdda33363132127db4df795eadbd9", "f417cbad7394fdccec850d13d7d5621516d693ce" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon May 17 11:52:31 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon May 17 11:53:39 2010 +0100" }, "message": "Merge branches \u0027at91\u0027, \u0027bcmring\u0027, \u0027ep93xx\u0027, \u0027iop\u0027, \u0027misc\u0027, \u0027nomadik\u0027, \u0027omap\u0027, \u0027pxa\u0027, \u0027spear\u0027 and \u0027versatile\u0027 into devel\n\nConflicts:\n\tarch/arm/Makefile\n\tarch/arm/common/Makefile\n\tarch/arm/mm/Kconfig\n" }, { "commit": "47ab0dee661dbd5aca67abe44a333e471134fbf9", "tree": "6464acf6eb3cd42102fa70e160335626354edfc1", "parents": [ "8c0b742ca7a7d21de0ddc87eda6ef0b282e4de18" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 15 11:02:43 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon May 17 11:52:11 2010 +0100" }, "message": "ARM: Optionally allow ARMv6 to use \u0027normal, bufferable\u0027 memory for DMA\n\nProvide a configuration option to allow the ARMv6 to use normal\nbufferable memory for coherent DMA. This option is forced to \u0027y\u0027\nfor ARMv7, and offered as a configuration option on ARMv6.\n\nEnabling this option requires drivers to have the necessary barriers\nto ensure that data in DMA coherent memory is visible prior to the\nDMA operation commencing.\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "8c0b742ca7a7d21de0ddc87eda6ef0b282e4de18", "tree": "282fc26ab73adf3a611ae50ff67d7abf799589d0", "parents": [ "49aea0fd95495538230e19f58e217fb06ffdbfeb" ], "author": { "name": "Kirill A. Shutemov", "email": "kirill@shutemov.name", "time": "Sat May 15 09:57:06 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 15 15:03:52 2010 +0100" }, "message": "ARM: 6134/1: Handle instruction cache maintenance fault properly\n\nBetween \"clean D line...\" and \"invalidate I line\" operations in\nv7_coherent_user_range(), the memory page may get swapped out.\nAnd the fault on \"invalidate I line\" could not be properly handled\ncausing the oops.\n\nIn ARMv6 \"external abort on linefetch\" replaced by \"instruction cache\nmaintenance fault\". Let\u0027s handle it as translation fault. It fixes the\nissue.\n\nI\u0027m not sure if it\u0027s reasonable to check arch version in run-time.\nLet\u0027s do it in compile time for now.\n\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Siarhei Siamashka \u003csiarhei.siamashka@nokia.com\u003e\nSigned-off-by: Kirill A. Shutemov \u003ckirill@shutemov.name\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "64039be8226b9f6c80c704d94ac9891eee4a274c", "tree": "60a675fdc5e5734a8f73b5c1081f4b966fea59e8", "parents": [ "a2227120eead4ea7d2ea04d8ce0947f1dd23dedf" ], "author": { "name": "Jason McMullan", "email": "jason.mcmullan@gmail.com", "time": "Wed May 05 18:59:37 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 15 15:03:50 2010 +0100" }, "message": "ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310\n\nThe L310 cache controller\u0027s interface is almost identical\nto the L210. One major difference is that the PL310 can\nhave up to 16 ways.\n\nThis change uses the cache\u0027s part ID and the Associativity\nbits in the AUX_CTRL register to determine the number of ways.\n\nAlso, this version prints out the CACHE_ID and AUX_CTRL registers.\n\nAcked-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nAcked-by: Acked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Jason S. McMullan \u003cjason.mcmullan@netronome.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a2227120eead4ea7d2ea04d8ce0947f1dd23dedf", "tree": "42b8ef27585c8f4cac294594659f52833037a577", "parents": [ "ceb683d3bc36f213aeef0c5d79e6fbb1e16bd459" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 25 18:56:05 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 15 15:03:49 2010 +0100" }, "message": "ARM: Move memory mapping into mmu.c\n\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ceb683d3bc36f213aeef0c5d79e6fbb1e16bd459", "tree": "a01d44449f12a866bd292d95a37db638820f0cd8", "parents": [ "6262c92f51ffb074800d5a340ee16bc06758e037" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 25 18:47:20 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 15 15:03:49 2010 +0100" }, "message": "ARM: Ensure meminfo is sorted prior to sanity_check_meminfo\n\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b7072c63c1b0611042ba6ecf0152a33c7b806e67", "tree": "a47d0c9c580a965b6ae8c0d986228e5765e8e0e5", "parents": [ "4d736b5e1cffb716bfbad669ce6aedf454779373" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Sun May 02 12:40:35 2010 +0300" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 15 15:03:48 2010 +0100" }, "message": "ARM: convert /proc/cpu/aligment to seq_file\n\nConvert code away from -\u003eread_proc/-\u003ewrite_proc interfaces. Switch to\nproc_create()/proc_create_data() which makes addition of proc entries\nreliable wrt NULL -\u003eproc_fops, NULL -\u003edata and so on.\n\nProblem with -\u003eread_proc et al is described here commit\n786d7e1612f0b0adb6046f19b906609e4fe8b1ba \"Fix rmmod/read/write races in\n/proc entries\"\n\nThis patch is part of an effort to remove the old simple procfs PAGE_SIZE\nbuffer interface.\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "74b8721099992b76d3faff78cb8a5d13c65c3529", "tree": "2c9971160051cae98237715f791ce2b93a0720b5", "parents": [ "4bddaf66093ce0e0c1fce505f091f4cd52e73e2e", "baffe1699c68da5040de6b274054adc995795782" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu May 13 09:56:24 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu May 13 09:56:24 2010 +0100" }, "message": "Merge branch \u0027devel\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel-stable\n" }, { "commit": "0741b7d2699d1e7b4ceab27522c9e5518b2dbd2c", "tree": "8b5b3dc90af2ce6358f44a18aa80a70ae773569c", "parents": [ "c4761b69f4c3bd2f6e62d9cba6d78b5fd4b24203" ], "author": { "name": "Vasily Khoruzhick", "email": "anarsoul@gmail.com", "time": "Tue May 11 09:55:10 2010 +0300" }, "committer": { "name": "Ben Dooks", "email": "ben-linux@fluff.org", "time": "Wed May 12 09:19:54 2010 +0900" }, "message": "ARM: RX1950: Add suspend/resume support for RX1950\n\nSigned-off-by: Vasily Khoruzhick \u003canarsoul@gmail.com\u003e\nSigned-off-by: Ben Dooks \u003cben-linux@fluff.org\u003e\n" }, { "commit": "66b196475031c748a5861390a4fadb915e14ccdc", "tree": "eaad4bcc929f4a744bc41c6fe739ef5278105031", "parents": [ "e598863690d956ad4e18904bb5b6c63fea1ad255" ], "author": { "name": "Haojian Zhuang", "email": "haojian.zhuang@marvell.com", "time": "Wed Apr 28 10:59:45 2010 -0400" }, "committer": { "name": "Eric Miao", "email": "eric.y.miao@gmail.com", "time": "Tue May 11 17:25:04 2010 +0200" }, "message": "[ARM] mmp: enable L2 in mmp2\n\nEnable Tauros2 L2 in mmp2. Tauros2 L2 is shared in Marvell ARM cores.\n\nSigned-off-by: Haojian Zhuang \u003chaojian.zhuang@marvell.com\u003e\nSigned-off-by: Eric Miao \u003ceric.y.miao@gmail.com\u003e\n" }, { "commit": "b8349b569aae661dea9d59d7d2ee587ccea3336c", "tree": "297ce3147521e0658321d61114a045bef4eca1d0", "parents": [ "f4d6477f7f073b99220386d62f5bf54bec3482cc" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri May 07 18:03:05 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 08 10:44:30 2010 +0100" }, "message": "ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP\n\nThe standard I-cache Invalidate All (ICIALLU) and Branch Predication\nInvalidate All (BPIALL) operations are not automatically broadcast to\nthe other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable\nvariants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f4d6477f7f073b99220386d62f5bf54bec3482cc", "tree": "4c6a13a762f54bfd30550a70226268edcb9d38a7", "parents": [ "b5a07faadeb4e0cfd6dcee359e501d4755cab875" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Fri May 07 16:26:24 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 08 10:44:30 2010 +0100" }, "message": "ARM: 6111/1: Implement read/write for ownership in the ARMv6 DMA cache ops\n\nThe Snoop Control Unit on the ARM11MPCore hardware does not detect the\ncache operations and the dma_cache_maint*() functions may leave stale\ncache entries on other CPUs. The solution implemented in this patch\nperforms a Read or Write For Ownership in the ARMv6 DMA cache\nmaintenance functions. These LDR/STR instructions change the cache line\nstate to shared or exclusive so that the cache maintenance operation has\nthe desired effect.\n\nTested-by: George G. Davis \u003cgdavis@mvista.com\u003e\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b5a07faadeb4e0cfd6dcee359e501d4755cab875", "tree": "5067c51450d33e64316084c0eecac15e0326119c", "parents": [ "b1a9ceb2e003aab7b96e30d990c1092453a0ea44" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu May 06 15:15:28 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 08 10:44:22 2010 +0100" }, "message": "ARM: 6106/1: Implement copy_to_user_page() for noMMU\n\nCommit 7959722 introduced calls to copy_(to|from)_user_page() from\naccess_process_vm() in mm/nommu.c. The copy_to_user_page() was not\nimplemented on noMMU ARM.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b1a9ceb2e003aab7b96e30d990c1092453a0ea44", "tree": "89a9e816273c5e0a835f22e5d864343ac14a1334", "parents": [ "f1c448e0a9e99c76f4ece368714fb35a40a8daba" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Thu May 06 15:14:09 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat May 08 10:44:21 2010 +0100" }, "message": "ARM: 6105/1: Fix the __arm_ioremap_caller() definition in nommu.c\n\nCommit 31aa8fd6 introduced the __arm_ioremap_caller() function but the\nnommu.c version did not have the _caller suffix.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "35c44933ef10ff4e47c9b28a7e61e648edd38845", "tree": "7490f78f5479620ee5cf931f9701a673908e39ce", "parents": [ "941f81c16ec7497ecce6f1f611277d67e89bdfe1", "a3be6327163c223c1715c8307a616941fbf8bf73" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri May 07 21:39:35 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri May 07 21:39:35 2010 +0100" }, "message": "Merge branch \u0027gemini_fix\u0027 of git://git.berlios.de/gemini-board into devel-stable\n" }, { "commit": "ea056df7965fc46cfff28fd3808bf3ada23d5059", "tree": "4bc56774dfc4217db45ad304a0463532d6ff4808", "parents": [ "ab92e74f799a1cbc6b3c9bf90ed05403689ddecc" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Tue May 04 17:27:43 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue May 04 17:31:03 2010 +0100" }, "message": "ARM: 6093/1: Fix kernel memory printing for sparsemem\n\nThe show_mem() and mem_init() function are assuming that the page map is\ncontiguous and calculates the start and end page of a bank using (map +\npfn). This fails with SPARSEMEM where pfn_to_page() must be used.\n\nTested-by: Will Deacon \u003cWill.Deacon@arm.com\u003e\nTested-by: Marek Vasut \u003cmarek.vasut@gmail.com\u003e\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "e220ba60223a9d63e70217e5b112160df8c21cea", "tree": "cdbdcbd9865d10ed0d3b977bc254c1ee0328e460", "parents": [ "ee3c454b8da04815c1884ed85fe89d2d131c0e51" ], "author": { "name": "Dave Estes", "email": "cestes@quicinc.com", "time": "Tue Aug 11 17:58:49 2009 -0400" }, "committer": { "name": "Daniel Walker", "email": "dwalker@codeaurora.org", "time": "Mon May 03 11:15:05 2010 -0700" }, "message": "arm: mm: qsd8x50: Fix incorrect permission faults\n\nHandle incorrectly reported permission faults for qsd8650. On\npermission faults, retry MVA to PA conversion. If retry detects\ntranslation fault. Report as translation fault.\n\nCc: Jamie Lokier \u003cjamie@shareable.org\u003e\nSigned-off-by: Dave Estes \u003ccestes@quicinc.com\u003e\n" }, { "commit": "fef88f10767cfd9f9b4eebb5d5490214c5e13ad5", "tree": "cf4a8cb7d8e3959a0d1692314ec41282eeeff6c3", "parents": [ "ceade897f31b8bb66f378cc35859fcfd0d46aaa2" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Feb 28 17:26:25 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun May 02 09:35:39 2010 +0100" }, "message": "ARM: Add Versatile Express CA9x4 processor support\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a3be6327163c223c1715c8307a616941fbf8bf73", "tree": "0604946ac2cbc93a9c385aac44744faf4d0bebd1", "parents": [ "352d4657b23fbd329efccc396000a549e0150907" ], "author": { "name": "Hans Ulli Kroll", "email": "ulli.kroll@googlemail.com", "time": "Tue Apr 27 12:45:10 2010 +0200" }, "committer": { "name": "Hans Ulli Kroll", "email": "ulli.kroll@googlemail.com", "time": "Tue Apr 27 12:45:10 2010 +0200" }, "message": "ARM: Gemini: fix compiler error in copypage-fa.c\n\nFix compiler error in copypage-fs.c\nmissing struct vm_area_struct *vma in function\nfa_copy_user_highpage\n\nSigned-off-by: Hans Ulli Kroll \u003culli.kroll@googlemail.com\u003e\n" }, { "commit": "4260415f6a3b92c5c986398d96c314df37a4ccbf", "tree": "13db8d997677c70d7b3f880daafab41d0b6711f3", "parents": [ "05ce7bfe547c9fa967d9cab6c37867a9cb6fb3fa" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Apr 19 10:15:03 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Apr 21 08:45:21 2010 +0100" }, "message": "ARM: fix build error in arch/arm/kernel/process.c\n\n/tmp/ccJ3ssZW.s: Assembler messages:\n/tmp/ccJ3ssZW.s:1952: Error: can\u0027t resolve `.text\u0027 {.text section} - `.LFB1077\u0027\n\nThis is caused because:\n\n\t.section .data\n\t.section .text\n\t.section .text\n\t.previous\n\ndoes not return us to the .text section, but the .data section; this\nmakes use of .previous dangerous if the ordering of previous sections\nis not known.\n\nFix up the other users of .previous; .pushsection and .popsection are\na safer pairing to use than .section and .previous.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "8e797a7e4f588fb3b9cfe9860b00dcd3b14f8b60", "tree": "57ac8c456499c5438274a99617e50ea4e46ac8a1", "parents": [ "b102c01faed5e0083a4e6d29a2d61f6b57716e94" ], "author": { "name": "Srinidhi Kasagar", "email": "srinidhi.kasagar@stericsson.com", "time": "Sat Apr 03 19:10:45 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Apr 14 16:08:10 2010 +0100" }, "message": "ARM: 6027/1: ux500: enable l2x0 support\n\nThis enables the l2x0 support and ensures that the secondary\nCPU can see the page table and secondary data at this point.\n\nSigned-off-by: srinidhi kasagar \u003csrinidhi.kasagar@stericsson.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f76348a360fe92063e07a8f54b0c1ea67f91e76c", "tree": "78d9d4de02d0c2d1283f47344f2656c7d751d754", "parents": [ "6e8699f7d68589e0e9ab324f598a3357bceb40bc" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Dec 24 12:57:01 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Apr 14 13:13:25 2010 +0100" }, "message": "ARM: remove unnecessary cache flush\n\nThis cache flush occurs when we first insert a page into the page\ntables, where a page did not exist previously. There can be no\ncache lines associated with this virtual mapping, so this cache\nflush is redundant.\n\nTested-by: Mike Rapoport \u003cmike@compulab.co.il\u003e\nTested-by: Mikael Pettersson \u003cmikpe at it.uu.se\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "3f2d4f561fab4588344cc519fd323382ab950928", "tree": "8998ed2d054db2e446532507d9c742cfbc289502", "parents": [ "82c6f5a5b3e91ef4d2fb8725de4b8cf7affd4d61" ], "author": { "name": "Mika Westerberg", "email": "mika.westerberg@iki.fi", "time": "Tue Apr 13 07:01:46 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Apr 14 11:11:31 2010 +0100" }, "message": "ARM: 6052/1: kdump: make kexec work in interrupt context\n\nWhen crash happens in interrupt context there is no userspace context.\nWe always use current-\u003eactive_mm in those cases.\n\nSigned-off-by: Mika Westerberg \u003cext-mika.1.westerberg@nokia.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7e5a69e83ba7a0d5917ad830f417cba8b8d6aa72", "tree": "d8547f21cc0dd6fbc605d5f72c5662f65bbd18cd", "parents": [ "317aa408d69a5b833a116317c18c7e957989ce44" ], "author": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Mon Mar 29 21:46:02 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Apr 14 11:11:27 2010 +0100" }, "message": "ARM: 6007/1: fix highmem with VIPT cache and DMA\n\nThe VIVT cache of a highmem page is always flushed before the page\nis unmapped. This cache flush is explicit through flush_cache_kmaps()\nin flush_all_zero_pkmaps(), or through __cpuc_flush_dcache_area() in\nkunmap_atomic(). There is also an implicit flush of those highmem pages\nthat were part of a process that just terminated making those pages free\nas the whole VIVT cache has to be flushed on every task switch. Hence\nunmapped highmem pages need no cache maintenance in that case.\n\nHowever unmapped pages may still be cached with a VIPT cache because the\ncache is tagged with physical addresses. There is no need for a whole\ncache flush during task switching for that reason, and despite the\nexplicit cache flushes in flush_all_zero_pkmaps() and kunmap_atomic(),\nsome highmem pages that were mapped in user space end up still cached\neven when they become unmapped.\n\nSo, we do have to perform cache maintenance on those unmapped highmem\npages in the context of DMA when using a VIPT cache. Unfortunately,\nit is not possible to perform that cache maintenance using physical\naddresses as all the L1 cache maintenance coprocessor functions accept\nvirtual addresses only. Therefore we have no choice but to set up a\ntemporary virtual mapping for that purpose.\n\nAnd of course the explicit cache flushing when unmapping a highmem page\non a system with a VIPT cache now can go, which should increase\nperformance.\n\nWhile at it, because the code in __flush_dcache_page() has to be modified\nanyway, let\u0027s also make sure the mapped highmem pages are pinned with\nkmap_high_get() for the duration of the cache maintenance operation.\nBecause kunmap() does unmap highmem pages lazily, it was reported by\nGary King \u003cGKing@nvidia.com\u003e that those pages ended up being unmapped\nduring cache maintenance on SMP causing segmentation faults.\n\nSigned-off-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "85b3cce880a19e78286570d5fd004cc3cac06f57", "tree": "bf251707e89682972089dfec185ca5625db88e34", "parents": [ "9823f1a8463fb631fe965110fe19adeb3df239c4" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Apr 09 15:00:11 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Apr 09 15:00:11 2010 +0100" }, "message": "ARM: Fix ioremap_cached()/ioremap_wc() for SMP platforms\n\nWrite combining/cached device mappings are not setting the shared bit,\nwhich could potentially cause problems on SMP systems since the cache\nlines won\u0027t participate in the cache coherency protocol.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nTested-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\n" }, { "commit": "336f5899d287f06d8329e208fc14ce50f7ec9698", "tree": "9b762d450d5eb248a6ff8317badb7e223d93ed58", "parents": [ "a4ab2773205e8b94c18625455f85e3b6bb9d7ad6", "db217dece3003df0841bacf9556b5c06aa097dae" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Mon Apr 05 11:37:28 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Mon Apr 05 11:37:28 2010 +0900" }, "message": "Merge branch \u0027master\u0027 into export-slabh\n" }, { "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05", "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1", "parents": [ "ed391f4ebf8f701d3566423ce8f17e614cde9806" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Mar 24 17:04:11 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Mar 30 22:02:32 2010 +0900" }, "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files. percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed. Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability. As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n only the necessary includes are there. ie. if only gfp is used,\n gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n blocks and try to put the new include such that its order conforms\n to its surrounding. It\u0027s put in the include block which contains\n core kernel includes, in the same order that the rest are ordered -\n alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n because the file doesn\u0027t have fitting include block), it prints out\n an error message indicating which .h file needs to be added to the\n file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n and ~3000 slab.h inclusions. The script emitted errors for ~400\n files.\n\n2. Each error was manually checked. Some didn\u0027t need the inclusion,\n some needed manual addition while adding it to implementation .h or\n embedding .c file was more appropriate for others. This step added\n inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n editing them as sprinkling gfp.h and slab.h inclusions around .h\n files could easily lead to inclusion dependency hell. Most gfp.h\n inclusion directives were ignored as stuff from gfp.h was usually\n wildly available and often used in preprocessor macros. Each\n slab.h inclusion directive was examined and added manually as\n necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my\n distributed build env didn\u0027t work with gcov compiles) and a few\n more options had to be turned off depending on archs to make things\n build (like ipr on powerpc/64 which failed due to missing writeq).\n\n * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n * powerpc and powerpc64 SMP allmodconfig\n * sparc and sparc64 SMP allmodconfig\n * ia64 SMP allmodconfig\n * s390 SMP allmodconfig\n * alpha SMP allmodconfig\n * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n" }, { "commit": "e7c5650f6067f65f8e961394f376d4862808d0d2", "tree": "ac1a298272cf4b452f3b36fef7878982d7eead9c", "parents": [ "23107c542068b2b94390aa333f6b330af64961e4" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Wed Mar 24 16:49:54 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 25 21:13:50 2010 +0000" }, "message": "ARM: 5996/1: ARM: Change the mandatory barriers implementation (4/4)\n\nThe mandatory barriers (mb, rmb, wmb) are used even on uniprocessor\nsystems for things like ordering Normal Non-cacheable memory accesses\nwith DMA transfer (via Device memory writes). The current implementation\nuses dmb() for mb() and friends but this is not sufficient. The DMB only\nensures the relative ordering of the observability of accesses by other\nprocessors or devices acting as masters. In case of DMA transfers\nstarted by writes to device memory, the relative ordering is not ensured\nbecause accesses to slave ports of a device are not considered\nobservable by the DMB definition.\n\nA DSB is required for the data to reach the main memory (even if mapped\nas Normal Non-cacheable) before the device receives the notification to\nbegin the transfer. Furthermore, some L2 cache controllers (like L2x0 or\nPL310) buffer stores to Normal Non-cacheable memory and this would need\nto be drained with the outer_sync() function call.\n\nThe patch also allows platforms to define their own mandatory barriers\nimplementation by selecting CONFIG_ARCH_HAS_BARRIERS and providing a\nmach/barriers.h file.\n\nNote that the SMP barriers are unchanged (being DMBs as before) since\nthey are only guaranteed to work with Normal Cacheable memory.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "23107c542068b2b94390aa333f6b330af64961e4", "tree": "8730f15e805ec2c02aaf6eac1780dcdbe22c2c04", "parents": [ "319f551a0a167b49b5bbb4a9ff4802046a572bc5" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Wed Mar 24 16:48:53 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 25 21:13:50 2010 +0000" }, "message": "ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)\n\nThe L2x0 cache controllers need to explicitly drain their write buffer\neven for Normal Noncacheable memory accesses.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "319f551a0a167b49b5bbb4a9ff4802046a572bc5", "tree": "b10f922c96e8f0a6ead8557677badeaf27bea630", "parents": [ "33f663ff9186da1bcc88dc7830b3a632bd472da5" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Wed Mar 24 16:47:53 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Mar 25 21:13:49 2010 +0000" }, "message": "ARM: 5994/1: ARM: Add outer_cache_fns.sync function pointer (2/4)\n\nThis patch introduces the outer_cache_fns.sync function pointer together\nwith the OUTER_CACHE_SYNC config option that can be used to drain the\nwrite buffer of the outer cache.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ac0f6f927db539e03e1f3f61bcd4ed57d5cde7a9", "tree": "816e5ac643b15c2050c64a7075f0f7e13d86ea09", "parents": [ "b1bf9368407ae7e89d8a005bb40beb70a41df539", "9f33be2c3a80bdc2cc08342dd77fac87652e0548" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Mar 01 09:15:15 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Mar 01 09:15:15 2010 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027for-linus\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm: (100 commits)\n ARM: Eliminate decompressor -Dstatic\u003d PIC hack\n ARM: 5958/1: ARM: U300: fix inverted clk round rate\n ARM: 5956/1: misplaced parentheses\n ARM: 5955/1: ep93xx: move timer defines into core.c and document\n ARM: 5954/1: ep93xx: move gpio interrupt support to gpio.c\n ARM: 5953/1: ep93xx: fix broken build of clock.c\n ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig\n ARM: 5949/1: NUC900 add gpio virtual memory map\n ARM: 5948/1: Enable timer0 to time4 clock support for nuc910\n ARM: 5940/2: ARM: MMCI: remove custom DBG macro and printk\n ARM: make_coherent(): fix problems with highpte, part 2\n MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself\n ARM: 5945/1: ep93xx: include correct irq.h in core.c\n ARM: 5933/1: amba-pl011: support hardware flow control\n ARM: 5930/1: Add PKMAP area description to memory.txt.\n ARM: 5929/1: Add checks to detect overlap of memory regions.\n ARM: 5928/1: Change type of VMALLOC_END to unsigned long.\n ARM: 5927/1: Make delimiters of DMA area globally visibly.\n ARM: 5926/1: Add \"Virtual kernel memory...\" printout.\n ARM: 5920/1: OMAP4: Enable L2 Cache\n ...\n\nFix up trivial conflict in arch/arm/mach-mx25/clock.c\n" }, { "commit": "9f33be2c3a80bdc2cc08342dd77fac87652e0548", "tree": "7ad6e825427a15c5ec0fc15540abc0429d7f4bce", "parents": [ "2741ecb4ce5c2d430b5c44b0a169038338c21df5", "eed18b5fa4d297c681b00144e8c6942dd35d39a7" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 25 22:10:38 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 25 22:10:38 2010 +0000" }, "message": "Merge branches \u0027clks\u0027 and \u0027pnx\u0027 into devel\n" }, { "commit": "2741ecb4ce5c2d430b5c44b0a169038338c21df5", "tree": "4aa71d7551184ee88f32c7f3660d821133058c32", "parents": [ "bc85e585c6d0fab4bde12d60964b2f25802c3163", "5de813b6cd06460b337f9da9afe316823cf3ef45" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 25 22:09:41 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 25 22:09:41 2010 +0000" }, "message": "Merge branch \u0027misc2\u0027 into devel\n" }, { "commit": "bc85e585c6d0fab4bde12d60964b2f25802c3163", "tree": "80f5fe916e3458d0676e595e3433a0313e7ba72b", "parents": [ "186f93ea1f274f4cde4a356401c1786c818ff881", "796d12959ad374cae8eb77faaf4243455a305433" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 25 22:09:22 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Feb 25 22:09:22 2010 +0000" }, "message": "Merge branch \u0027perf\u0027 into devel\n\nConflicts:\n\tarch/arm/Kconfig\n" } ], "next": "3560adf62075829393743667ff338dd8fd26a5c2" }