)]}'
{
  "log": [
    {
      "commit": "e0cc09e295f346b7921e921f385fe5213472316a",
      "tree": "3705c5bbd44afc235f39697a5b0c00d0d020188c",
      "parents": [
        "40caf5ea5a7d47f8a33e26b63ca81dea4b5109d2",
        "e1b43bd556a611584a65f529e5077c1b54ace4f7"
      ],
      "author": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Mon Apr 30 13:55:43 2007 -0700"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Mon Apr 30 13:55:43 2007 -0700"
      },
      "message": "Pull error-inject into release branch\n"
    },
    {
      "commit": "618b206f0b580d965eb26f704ed23beee2a8c25d",
      "tree": "a286eca054a9d5e8fbd54463647b68158f2a50d2",
      "parents": [
        "908e0a8a265fe8057604a9a30aec3f0be7bb5ebb"
      ],
      "author": {
        "name": "Russ Anderson",
        "email": "rja@sgi.com",
        "time": "Thu Dec 14 16:01:41 2006 -0600"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Thu Mar 08 09:41:46 2007 -0800"
      },
      "message": "[IA64] Proper handling of TLB errors from duplicate itr.d dropins\n\nJack Steiner noticed that duplicate TLB DTC entries do not cause a\nlinux panic.  See discussion:\n\nhttp://www.gelato.unsw.edu.au/archives/linux-ia64/0307/6108.html\n\nThe current TLB recovery code is recovering from the duplicate itr.d\ndropins, masking the underlying problem.  This change modifies\nthe MCA recovery code to look for the TLB check signature of the\nduplicate TLB entry and panic in that case.\n\nSigned-off-by: Russ Anderson (rja@sgi.com)\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "1b3c3714cb4767d00f507cc6854d3339d82c5b9d",
      "tree": "70a24435398cee2939bd71377f2fdf4d58aad8c0",
      "parents": [
        "85d1fe095ccb6318f7a128c96630477a8859cfce"
      ],
      "author": {
        "name": "Uwe Kleine-König",
        "email": "zeisberg@informatik.uni-freiburg.de",
        "time": "Sat Feb 17 19:23:03 2007 +0100"
      },
      "committer": {
        "name": "Adrian Bunk",
        "email": "bunk@stusta.de",
        "time": "Sat Feb 17 19:23:03 2007 +0100"
      },
      "message": "Fix typos concerning hierarchy\n\n        heirarchical, hierachical -\u003e hierarchical\n        heirarchy, hierachy -\u003e hierarchy\n\nSigned-off-by: Uwe Kleine-König \u003czeisberg@informatik.uni-freiburg.de\u003e\nSigned-off-by: Adrian Bunk \u003cbunk@stusta.de\u003e\n"
    },
    {
      "commit": "1138b7e2d40711b024768034beb64885994271e4",
      "tree": "b175b368e75dabbbc540e2cb7add05a749056151",
      "parents": [
        "539d517ad10bbaac2c04e0ee22916a360c5bcc0d"
      ],
      "author": {
        "name": "Fenghua Yu",
        "email": "fenghua.yu@intel.com",
        "time": "Fri Dec 08 16:17:31 2006 -0800"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Mon Jan 29 15:29:56 2007 -0800"
      },
      "message": "[IA64] Itanium MC Error Injection Tool: pal_mc_error_inject() interface\n\nThis patch implements pal_mc_error_inject() interface in kernel. Both physical\nmode and virtual mode are supported.\n\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "17e77b1cc31454908aa286bb1db3c611295ce25c",
      "tree": "8d4cae677dfec84d4f41a93b8758bad5b1b8761f",
      "parents": [
        "6dbfc19b7ea93f94f1efabaae71a921b49d8cae2"
      ],
      "author": {
        "name": "Venkatesh Pallipadi",
        "email": "venkatesh.pallipadi@intel.com",
        "time": "Fri Dec 01 15:28:14 2006 -0800"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Thu Dec 07 11:21:55 2006 -0800"
      },
      "message": "[PATCH] Add support for type argument in PAL_GET_PSTATE\n\nPAL_GET_PSTATE accepts a type argument to return different kinds of\nfrequency information.\nRefer: Intel Itanium®Architecture Software Developer\u0027s Manual -\nVolume 2: System Architecture, Revision 2.2\n(http://developer.intel.com/design/itanium/manuals/245318.htm)\n\nAdd the support for type argument and use Instantaneous frequency\nin the acpi driver.\n\nAlso fix a bug, where in return value of PAL_GET_PSTATE was getting compared\nwith \u0027control\u0027 bits instead of \u0027status\u0027 bits.\n\nSigned-off-by: Venkatesh Pallipadi \u003cvenkatesh.pallipadi@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "5b4d5681ffaa6e1bf3b085beb701d87c7c7404da",
      "tree": "2db8dfeb74989741039242bb734a57e79caaf176",
      "parents": [
        "895309ff6f22a9d107e007521e44aac4400b365d"
      ],
      "author": {
        "name": "Russ Anderson",
        "email": "rja@sgi.com",
        "time": "Mon Nov 06 16:45:18 2006 -0600"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Thu Dec 07 11:10:16 2006 -0800"
      },
      "message": "[IA64] More Itanium PAL spec updates\n\nAdditional updates to conform with Rev 2.2 of Volume 2 of \"Intel\nItanium Architecture Software Developer\u0027s Manual\" (January 2006).\n\nAdd pal_bus_features_s bits 52 \u0026 53 (page 2:347)\nAdd pal_vm_info_2_s field max_purges (page 2:2:451)\nAdd PAL_GET_HW_POLICY call (page 2:381)\nAdd PAL_SET_HW_POLICY call (page 2:439)\n\nSample output before:\n---------------------------------------------------------------------\ncobra:~ # cat /proc/pal/cpu0/vm_info\nPhysical Address Space         : 50 bits\nVirtual Address Space          : 61 bits\nProtection Key Registers(PKR)  : 16\nImplemented bits in PKR.key    : 24\nHash Tag ID                    : 0x2\nSize of RR.rid                 : 24\nSupported memory attributes    : WB, UC, UCE, WC, NaTPage\n---------------------------------------------------------------------\n\nSample output after:\n---------------------------------------------------------------------\ncobra:~ # cat /proc/pal/cpu0/vm_info\nPhysical Address Space         : 50 bits\nVirtual Address Space          : 61 bits\nProtection Key Registers(PKR)  : 16\nImplemented bits in PKR.key    : 24\nHash Tag ID                    : 0x2\nMax Purges                     : 1\nSize of RR.rid                 : 24\nSupported memory attributes    : WB, UC, UCE, WC, NaTPage\n---------------------------------------------------------------------\n\nSigned-off-by: Russ Anderson (rja@sgi.com)\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "6533bdedac9ae2049ae77ebd7c28c65af3619de0",
      "tree": "03ec755db1d5bf0589e9c9382b5dd1fb6ce6ed9a",
      "parents": [
        "323cbb09917024cab522bc7ce5c343659cbe8818"
      ],
      "author": {
        "name": "Russ Anderson",
        "email": "rja@sgi.com",
        "time": "Thu Oct 26 11:53:17 2006 -0500"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Thu Dec 07 11:02:53 2006 -0800"
      },
      "message": "[IA64] Add se bit to Processor State Parameter structure\n\nRev 2.2 of Volume 2 of \"Intel Itanium Architecture Software Developer\u0027s\nManual\" (January 2006) adds a se bit to the Processor State Parameter\nfields (pages 2:299).  This patch gets the structs back in sync\nwith the spec.\n\nSigned-off-by: Russ Anderson (rja@sgi.com)\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "323cbb09917024cab522bc7ce5c343659cbe8818",
      "tree": "f8edcf9abe1236894fa66bf809daddf001a70c4e",
      "parents": [
        "c69577711a8fd232e6b309c3e99f9a8f96f63082"
      ],
      "author": {
        "name": "Russ Anderson",
        "email": "rja@sgi.com",
        "time": "Wed Oct 25 14:18:27 2006 -0500"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Thu Dec 07 11:02:38 2006 -0800"
      },
      "message": "[IA64] Add dp bit to cache and bus check structs\n\nRev 2.2 of Volume 2 of \"Intel Itanium Architecture Software Developer\u0027s\nManual\" (January 2006) adds a dp bit to the cache_check and bus_check\nfields (pages 2:401-2:404).  This patch gets the structs back in sync\nwith the spec.\n\nSigned-off-by: Russ Anderson (rja@sgi.com)\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "c12fb1885787dcc2e20c4b88149e1e607e1293b2",
      "tree": "b607d2cf6e4915b5005a2c98a7efea0742103e28",
      "parents": [
        "accaddb27a2d544e38e10ff2a2782b33bbbad913"
      ],
      "author": {
        "name": "Bjorn Helgaas",
        "email": "bjorn.helgaas@hp.com",
        "time": "Thu Oct 12 16:20:59 2006 -0600"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Tue Oct 17 14:53:52 2006 -0700"
      },
      "message": "[IA64] remove unused PAL_CALL_IC_OFF\n\nLinux maps PAL instructions with an ITR, but uses a DTC for PAL data.\nSection 11.10.2.1.3, \"Making PAL Procedures Calls in Physical or Virtual\nMode,\" of the SDM (rev 2.2), says we must therefore make all PAL calls\nwith PSR.ic \u003d 1 so that Linux can handle any TLB faults.\n\nPAL_CALL_IC_OFF is currently unused, and as long as we use the ITR + DTC\nstrategy, we can\u0027t use it.  So remove it.  I also removed the code in\nia64_pal_call_static() that conditionally cleared PSR.ic.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "b29e7132b5a9f2496beed37beef7ba4d010afb2c",
      "tree": "d274ba31b5f8aa1ab4a3560c3480c5afecca4fe4",
      "parents": [
        "8f9e146732dcba5161dad3747ee73be1f8c13133"
      ],
      "author": {
        "name": "Russ Anderson",
        "email": "rja@sgi.com",
        "time": "Tue Sep 26 14:47:48 2006 -0500"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Tue Sep 26 15:21:11 2006 -0700"
      },
      "message": "[IA64] PAL calls need physical mode, stacked\n\nPAL_CACHE_READ and PAL_CACHE_WRITE need to be called in physical\nmode with stacked registers.\n\nSigned-off-by: Russ Anderson (rja@sgi.com)\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "ae3e0218621db0590163b2d5c424ef1f340e3cc6",
      "tree": "a7e84e4b4a1e32fb64a99d7d5c73420b717f01ae",
      "parents": [
        "e478bec0ba0a83a48a0f6982934b6de079e7e6b3",
        "76d08bb3f09054edc45326ce5c698a3f6c45f5d0"
      ],
      "author": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Tue Sep 26 09:47:04 2006 -0700"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Tue Sep 26 09:47:04 2006 -0700"
      },
      "message": "Pull model-name into release branch\n"
    },
    {
      "commit": "1bf1eba74ec14bc10966a8ddb23bc8deeb91facd",
      "tree": "bf2c62d0625bebb5516aac808f810cc31b146dbd",
      "parents": [
        "b6ff50833ad43a8ebd9b16bf53c334f7aaf33c41"
      ],
      "author": {
        "name": "Matthew Wilcox",
        "email": "matthew@wil.cx",
        "time": "Fri Jun 23 13:15:55 2006 -0600"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Mon Jul 31 11:49:13 2006 -0700"
      },
      "message": "[IA64] Format /proc/pal/*/version_info correctly\n\n/proc/pal/*/version_info is a bit confusing.  HP firmware, at least,\nreports 07.31 instead of 0.7.31.  Also, the comment is out of place;\nit\u0027s an internal detail about the implementation of ia64_pal_version.\nSince the 2.2 revision of the SDM still states that PAL_VERSION can\nbe called in virtual mode, correct the comment to be more accurate.\n\nSigned-off-by: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "76d08bb3f09054edc45326ce5c698a3f6c45f5d0",
      "tree": "5d0197f8ad8e4f778d6f117bcf49f9467fcdc0dd",
      "parents": [
        "672c6108a51bf559d19595d9f8193dfd81f0f752"
      ],
      "author": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Mon Jun 05 13:54:14 2006 -0700"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Mon Jun 05 13:54:14 2006 -0700"
      },
      "message": "[IA64] Add \"model name\" to /proc/cpuinfo\n\nLinux ia64 port tried to decode the processor family number\nto something human-readable, but Intel brandnames don\u0027t change\nsynchronously with updates to the family number.  Adopt a more\ni386-like approach and just print the family number in decimal.\nAdd a new field \"model name\" that uses PAL_BRAND_INFO to find\nthe official name for the cpu, or on older systems, falls back\nto using the well-known codenames (Merced, McKinley, Madison).\n\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "2ab9391dea6e36fed13443c29bf97d3be05f5289",
      "tree": "8bc492fe3df71457caf8009bd081b9be0ec1074a",
      "parents": [
        "f19180056ea09ec6a5d32e741234451a1e6eba4d"
      ],
      "author": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Fri Mar 31 10:28:29 2006 -0800"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Fri Mar 31 10:28:29 2006 -0800"
      },
      "message": "[IA64] Avoid \"u64 foo : 32;\" for gcc3 vs. gcc4 compatibility\n\ngcc3 thinks that a 32-bit field of a u64 type is itself a u64, so\nshould be printed with \"%ld\".  gcc4 thinks it needs just \"%d\".\nMake both versions happy by avoiding this construct.\n\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "f19180056ea09ec6a5d32e741234451a1e6eba4d",
      "tree": "386a178dd80773e3b62e6989f4faaaddb9602aa8",
      "parents": [
        "d1127e40e8d75cd3855e35424937c73d0bcec558"
      ],
      "author": {
        "name": "Zhang, Yanmin",
        "email": "yanmin_zhang@linux.intel.com",
        "time": "Mon Feb 27 11:37:45 2006 +0800"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Thu Mar 30 17:14:12 2006 -0800"
      },
      "message": "[IA64] Export cpu cache info by sysfs\n\nThe patch exports 8 attributes of cpu cache info under\n/sys/devices/system/cpu/cpuX/cache/indexX:\n1) level\n2) type\n3) coherency_line_size\n4) ways_of_associativity\n5) size\n6) shared_cpu_map\n7) attributes\n8) number_of_sets: number_of_sets\u003dsize/ways_of_associativity/coherency_line_size.\n\nSigned-off-by: Zhang Yanmin \u003cyanmin.zhang@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "4129a953ad4db379d8e07b0dd2157998653a1325",
      "tree": "84c6d310953044caa420410165adcd0dfb2ac55f",
      "parents": [
        "4d357acadd7a5e60767c748ed7807e11c4387bdf"
      ],
      "author": {
        "name": "Fenghua Yu",
        "email": "fenghua.yu@intel.com",
        "time": "Mon Feb 27 16:16:22 2006 -0800"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Fri Mar 24 13:15:23 2006 -0800"
      },
      "message": "[IA64] New IA64 core/thread detection patch\n\nIPF SDM 2.2 changes definition of PAL_LOGICAL_TO_PHYSICAL to add\nproc_number\u003d-1 to get core/thread mapping info on the running processer.\n\nBased on this change, we had better to update existing core/thread\ndetection in IA64 kernel correspondingly. The attached patch implements\nthis change. It simplifies detection code and eliminates potential race\ncondition. It also runs a bit faster and has better scalability especially\nwhen cores and threads number grows up in one package.\n\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "f15ac5801fdc1b217c3b8b5dbc63a09371d2ee4d",
      "tree": "b9d4eeb9b5a6ab36fdaebf24263aa4ba5543aec7",
      "parents": [
        "7b9c8ba2d634a0467a8a36018a28624563f34f47"
      ],
      "author": {
        "name": "Xu, Anthony",
        "email": "anthony.xu@intel.com",
        "time": "Mon Jan 09 10:36:35 2006 +0800"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Mon Jan 16 15:44:53 2006 -0800"
      },
      "message": "[IA64] pal cache flush patch\n\nBecause PAL spec has changed since 2002, you can goto\nhttp://developer.intel.com/design/itanium/manuals/iiasdmanual.htm to\ndownload new SDM, all PAL calls should be invoked with psr.ic\u003d1, and\nit\u0027s caller\u0027s responsibility to handle possible tlb miss.\nIa64_pal_cache_flush was written according to old spec, it is obsolete,\nand this patch has ia64_pal_cache_flush conform to new spec.\n\nSigned-off-by Anthony Xu \u003canthony.xu@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "4db8699bcfa8faddb5727b1cb010a4d9b8a42e8c",
      "tree": "eb4cb14927ed9cf4507f875cd69fe35f87b3b3bc",
      "parents": [
        "fd589e0b662c1ea8cfb1e0d20d60a2510979865b"
      ],
      "author": {
        "name": "Venkatesh Pallipadi",
        "email": "venkatesh.pallipadi@intel.com",
        "time": "Fri Jul 29 16:15:00 2005 -0700"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Fri Aug 26 15:09:24 2005 -0700"
      },
      "message": "[IA64] Add ACPI based P-state support\n\nPatch to support P-state transitions on ia64. This driver is based on ACPI,\nand uses the ACPI processor driver interface to find out the P-state support\ninformation for the processor. This driver plugs into generic cpufreq\ninfrastructure.\n\nOnce this driver is loaded successfully, ondemand/userspace governor can be\nused to change the CPU frequency dynamically based on load or on request from\nuserspace process.\n\nRefer :\nACPI specification -\n      http://www.acpi.info\nP-state related PAL calls -\n      http://developer.intel.com/design/itanium/downloads/24869909.pdf\n\nSigned-off-by: Venkatesh Pallipadi \u003cvenkatesh.pallipadi@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "e927ecb05e1ce4bbb1e10f57008c94994e2160f5",
      "tree": "bc8256cc074f02d557088696035982fa7ae0b301",
      "parents": [
        "6118ec847e8e35393efc0f88394c2f5dd48c3313"
      ],
      "author": {
        "name": "Suresh Siddha",
        "email": "suresh.b.siddha@intel.com",
        "time": "Mon Apr 25 13:25:06 2005 -0700"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Mon Apr 25 13:25:06 2005 -0700"
      },
      "message": "[IA64] multi-core/multi-thread identification\n\nVersion 3 - rediffed to apply on top of Ashok\u0027s hotplug cpu\npatch.  /proc/cpuinfo output in step with x86.\n\nThis is an updated MC/MT identification patch based on the \nprevious discussions on list. \n\nAdd the Multi-core and Multi-threading detection for IPF.\n  - Add new core and threading related fields in /proc/cpuinfo.\n\t\tPhysical id\n\t\tCore id\n\t\tThread id\n\t\tSiblings\n  - setup the cpu_core_map and cpu_sibling_map appropriately\n  - Handles Hot plug CPU\n \nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: Gordon Jin \u003cgordon.jin@intel.com\u003e\nSigned-off-by: Rohit Seth \u003crohit.seth@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2",
      "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d",
      "parents": [],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n"
    }
  ]
}