)]}' { "log": [ { "commit": "405d7ca51597645f3be850574d6c10f01be11e8d", "tree": "9461326f1f8e8c51f3d325702f6e0c6946fb0f67", "parents": [ "7c5371c403abb29f01bc6cff6c5096abdf2dc524", "6a43e574c5af7d9bd084992b1c9c3cdbc3b6c0e9" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jul 02 16:51:09 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jul 02 16:51:09 2009 -0700" }, "message": "Merge git://git.infradead.org/iommu-2.6\n\n* git://git.infradead.org/iommu-2.6: (38 commits)\n intel-iommu: Don\u0027t keep freeing page zero in dma_pte_free_pagetable()\n intel-iommu: Introduce first_pte_in_page() to simplify PTE-setting loops\n intel-iommu: Use cmpxchg64_local() for setting PTEs\n intel-iommu: Warn about unmatched unmap requests\n intel-iommu: Kill superfluous mapping_lock\n intel-iommu: Ensure that PTE writes are 64-bit atomic, even on i386\n intel-iommu: Make iommu\u003dpt work on i386 too\n intel-iommu: Performance improvement for dma_pte_free_pagetable()\n intel-iommu: Don\u0027t free too much in dma_pte_free_pagetable()\n intel-iommu: dump mappings but don\u0027t die on pte already set\n intel-iommu: Combine domain_pfn_mapping() and domain_sg_mapping()\n intel-iommu: Introduce domain_sg_mapping() to speed up intel_map_sg()\n intel-iommu: Simplify __intel_alloc_iova()\n intel-iommu: Performance improvement for domain_pfn_mapping()\n intel-iommu: Performance improvement for dma_pte_clear_range()\n intel-iommu: Clean up iommu_domain_identity_map()\n intel-iommu: Remove last use of PHYSICAL_PAGE_MASK, for reserving PCI BARs\n intel-iommu: Make iommu_flush_iotlb_psi() take pfn as argument\n intel-iommu: Change aligned_size() to aligned_nrpages()\n intel-iommu: Clean up intel_map_sg(), remove domain_page_mapping()\n ...\n" }, { "commit": "6a43e574c5af7d9bd084992b1c9c3cdbc3b6c0e9", "tree": "64f32c60749008747d201b7168b33e1181682bf2", "parents": [ "75e6bf9638992dfc0fec9c3ca10444c8e0d6a638" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Jul 02 12:02:34 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Jul 02 12:02:38 2009 +0100" }, "message": "intel-iommu: Don\u0027t keep freeing page zero in dma_pte_free_pagetable()\n\nCheck dma_pte_present() and only free the page if there _is_ one.\nKind of surprising that there was no warning about this.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "75e6bf9638992dfc0fec9c3ca10444c8e0d6a638", "tree": "bdbabd91d77edb3d623292ea97b17d88d053816e", "parents": [ "7766a3fb905f0b078b05f5d6a6be8df4c64b9f51" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Jul 02 11:21:16 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Jul 02 11:27:13 2009 +0100" }, "message": "intel-iommu: Introduce first_pte_in_page() to simplify PTE-setting loops\n\nOn Wed, 2009-07-01 at 16:59 -0700, Linus Torvalds wrote:\n\u003e I also _really_ hate how you do\n\u003e\n\u003e (unsigned long)pte \u003e\u003e VTD_PAGE_SHIFT \u003d\u003d\n\u003e (unsigned long)first_pte \u003e\u003e VTD_PAGE_SHIFT\n\nKill this, in favour of just looking to see if the incremented pte\npointer has \u0027wrapped\u0027 onto the next page. Which means we have to check\nit _after_ incrementing it, not before.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "7766a3fb905f0b078b05f5d6a6be8df4c64b9f51", "tree": "57345b5cf47f50cdc3ba09f4746834e77d22817e", "parents": [ "85b98276f2ffa66b25ae6328b00bfadfd74b74e7" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 20:27:03 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 20:27:03 2009 +0100" }, "message": "intel-iommu: Use cmpxchg64_local() for setting PTEs\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "85b98276f2ffa66b25ae6328b00bfadfd74b74e7", "tree": "17ae570435b8d46e217803b2c536a41f6e8a0c18", "parents": [ "206a73c102fc480ba072a9388bc2142c303113aa" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:27:53 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:54:37 2009 +0100" }, "message": "intel-iommu: Warn about unmatched unmap requests\n\nThis would have found the bug in i386 pci_unmap_addr() a long time ago.\nWe shouldn\u0027t just silently return without doing anything.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "206a73c102fc480ba072a9388bc2142c303113aa", "tree": "0b946089436df51a4444ef23069a9037853d5e61", "parents": [ "c85994e4771025ef2a66533eb1a4c6c2217b9cda" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:30:28 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:43:37 2009 +0100" }, "message": "intel-iommu: Kill superfluous mapping_lock\n\nSince we\u0027re using cmpxchg64() anyway (because that\u0027s the only way to do\nan atomic 64-bit store on i386), we might as well ditch the extra\nlocking and just use cmpxchg64() to ensure that we don\u0027t add the page\ntwice.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "c85994e4771025ef2a66533eb1a4c6c2217b9cda", "tree": "9f827d5587a5cac2c8a412317e2997b8add67b9a", "parents": [ "3238c0c4d68d9a9022b411a11a4b933fbdb53a14" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:21:24 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:21:24 2009 +0100" }, "message": "intel-iommu: Ensure that PTE writes are 64-bit atomic, even on i386\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "a15a519ed6e5e644f5a33c213c00b0c1d3cfe683", "tree": "8b266ba5c56de55adac09a60119a411bd9b4e894", "parents": [ "788d84bba47ea3eb377f7a3ae4fd1ee84b84877b" ], "author": { "name": "David Woodhouse", "email": "dwmw2@infradead.org", "time": "Wed Jul 01 18:49:06 2009 +0100" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Jul 01 11:19:29 2009 -0700" }, "message": "Fix iommu address space allocation\n\nThis fixes kernel.org bug #13584. The IOVA code attempted to optimise\nthe insertion of new ranges into the rbtree, with the unfortunate result\nthat some ranges just didn\u0027t get inserted into the tree at all. Then\nthose ranges would be handed out more than once, and things kind of go\ndownhill from there.\n\nIntroduced after 2.6.25 by ddf02886cbe665d67ca750750196ea5bf524b10b\n(\"PCI: iova RB tree setup tweak\").\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nCc: mark gross \u003cmgross@linux.intel.com\u003e\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: stable@kernel.org\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "f3a0a52fff4dbfdea2dccc908d00c038481d888e", "tree": "956261c5e5a00c115eed6741d1ae10fd71d4a411", "parents": [ "3d7b0e4154b4963d6bd39991ec8eaa09caeb3994" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:40:07 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:58:15 2009 +0100" }, "message": "intel-iommu: Performance improvement for dma_pte_free_pagetable()\n\nAs with other functions, batch the CPU data cache flushes and don\u0027t keep\nrecalculating PTE addresses.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "3d7b0e4154b4963d6bd39991ec8eaa09caeb3994", "tree": "8c92261cda93b9635e7f84f218f47b2f6f68814e", "parents": [ "1bf20f0dc5629032ddd07617139d9fbca66c1642" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:38:09 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:57:38 2009 +0100" }, "message": "intel-iommu: Don\u0027t free too much in dma_pte_free_pagetable()\n\nThe loop condition was wrong -- we should free a PMD only if its\n_entire_ range is within the range we\u0027re intending to clear. The\nearly-termination condition was right, but not the loop.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "1bf20f0dc5629032ddd07617139d9fbca66c1642", "tree": "6911bea8e9333ea7ed36ad4bc7a2c6001000e41d", "parents": [ "9051aa0268dc1c3e42cd79a802b0af1f2bfcadae" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 22:06:43 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:55:21 2009 +0100" }, "message": "intel-iommu: dump mappings but don\u0027t die on pte already set\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "9051aa0268dc1c3e42cd79a802b0af1f2bfcadae", "tree": "2439a585889486158728d3d16587738112b67a36", "parents": [ "e1605495c716ef4eebdb7606bcd1b593f28e2837" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:30:54 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:53:31 2009 +0100" }, "message": "intel-iommu: Combine domain_pfn_mapping() and domain_sg_mapping()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "e1605495c716ef4eebdb7606bcd1b593f28e2837", "tree": "de1144b9697f94dda08b3a9434fa97e0dbaab93f", "parents": [ "875764de6f0ddb23d270c29357d5a339232a0488" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 11:17:38 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:51:30 2009 +0100" }, "message": "intel-iommu: Introduce domain_sg_mapping() to speed up intel_map_sg()\n\nInstead of calling domain_pfn_mapping() repeatedly with single or\nsmall numbers of pages, just pass the sglist in. It can optimise the\nnumber of cache flushes like domain_pfn_mapping() does, and gives a huge\nspeedup for large scatterlists.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "875764de6f0ddb23d270c29357d5a339232a0488", "tree": "d122b470ffbe6c3651a3ba5b0441b46067f69a3b", "parents": [ "6f6a00e40aa3fdd3b29c30e3ef1fc9690506bc03" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 21:20:51 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:39:53 2009 +0100" }, "message": "intel-iommu: Simplify __intel_alloc_iova()\n\nThere\u0027s no need for the separate iommu_alloc_iova() function, and\ncertainly not for it to be global. Remove the underscores while we\u0027re at\nit.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "6f6a00e40aa3fdd3b29c30e3ef1fc9690506bc03", "tree": "ba1f28669888141c99c38cfb8d6b2b6034874e25", "parents": [ "310a5ab93cb4ce29367238f682affd9ac352f4d0" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 20:38:49 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:39:45 2009 +0100" }, "message": "intel-iommu: Performance improvement for domain_pfn_mapping()\n\nAs with dma_pte_clear_range(), don\u0027t keep flushing a single PTE at a\ntime. And also micro-optimise the setting of PTE values rather than\nusing the helper functions to do all the masking.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "310a5ab93cb4ce29367238f682affd9ac352f4d0", "tree": "dc5bb8f208778ebe0aee0054b7af516a36e2b543", "parents": [ "c5395d5c4a82159889cb650de93b591ea51d8c56" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 18:52:20 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:39:17 2009 +0100" }, "message": "intel-iommu: Performance improvement for dma_pte_clear_range()\n\nIt\u0027s a bit silly to repeatedly call domain_flush_cache() for each PTE\nindividually, as we clear it. Instead, batch them up and flush a whole\nrange at a time. We might as well refrain from recalculating the PTE\naddress from scratch each time round the loop too.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "c5395d5c4a82159889cb650de93b591ea51d8c56", "tree": "e53e62d8b5edf352e17c061f876589a49f73e875", "parents": [ "1a4a45516d7a57de0691352d899d7008f2e090d1" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 16:35:56 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:39:12 2009 +0100" }, "message": "intel-iommu: Clean up iommu_domain_identity_map()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "1a4a45516d7a57de0691352d899d7008f2e090d1", "tree": "022ff1b91357207801dc000caab27004324b3c8b", "parents": [ "03d6a2461ab1704c171ce21081c5022378ef7a91" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 16:00:42 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:39:05 2009 +0100" }, "message": "intel-iommu: Remove last use of PHYSICAL_PAGE_MASK, for reserving PCI BARs\n\nThis is fairly broken anyway -- it doesn\u0027t take hotplug into account.\nWe should probably be checking page_is_ram() instead.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "03d6a2461ab1704c171ce21081c5022378ef7a91", "tree": "fdc259ab75aa524a1013c8606e0ba75cb310274c", "parents": [ "88cb6a7424d9465faf6caaaadff5af0766c93991" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 15:33:46 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:38:11 2009 +0100" }, "message": "intel-iommu: Make iommu_flush_iotlb_psi() take pfn as argument\n\nMost of its callers are having to shift for themselves anyway, so we might\nas well do it in iommu_flush_iotlb_psi().\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "88cb6a7424d9465faf6caaaadff5af0766c93991", "tree": "5c50bec9d13911ea295349de24db46ec732c67c7", "parents": [ "b536d24d212c994a7d98469ea3a8891573d45fd4" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 15:03:06 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:38:04 2009 +0100" }, "message": "intel-iommu: Change aligned_size() to aligned_nrpages()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "b536d24d212c994a7d98469ea3a8891573d45fd4", "tree": "137751d6969f757e70548bc5ae5abee55e7c6559", "parents": [ "ad05122162b67f64d5a1c6d35e001f7a88619b88" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 14:49:31 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:35:06 2009 +0100" }, "message": "intel-iommu: Clean up intel_map_sg(), remove domain_page_mapping()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "ad05122162b67f64d5a1c6d35e001f7a88619b88", "tree": "9c406fd2e65fc6f0f0eb931cc951a07177035f4e", "parents": [ "0ab36de274ab094c3992b50c9c48c5c89072ec94" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 14:22:28 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:35:00 2009 +0100" }, "message": "intel-iommu: Use domain_pfn_mapping() in intel_iommu_map_range()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "0ab36de274ab094c3992b50c9c48c5c89072ec94", "tree": "62f7e197958fca2d846bb8821d22fc97e9675231", "parents": [ "61df744314079e8cb8cdec75f517cf0e704e41ef" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 14:01:43 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:34:24 2009 +0100" }, "message": "intel-iommu: Use domain_pfn_mapping() in __intel_map_single()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "61df744314079e8cb8cdec75f517cf0e704e41ef", "tree": "55fd23fd2b1e909e203876d3d3b0d2eec879c675", "parents": [ "1c5a46ed49e37f56f8aa9000bb1c2ac59670c372" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 11:55:58 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:33:59 2009 +0100" }, "message": "intel-iommu: Introduce domain_pfn_mapping()\n\n... and use it in the trivial cases; the other callers want individual\n(and bisectable) attention, since I screwed them up the first time...\n\nMake the BUG_ON() happen on too-large virtual address rather than\nphysical address, too. That\u0027s the one we care about.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "1c5a46ed49e37f56f8aa9000bb1c2ac59670c372", "tree": "70d61d1fdb94824e000a12a7ea086281074823bc", "parents": [ "b026fd28ea23af24a3eea6e5be3f3d0193a8e87d" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 10:53:37 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:33:11 2009 +0100" }, "message": "intel-iommu: Clean up address handling in domain_page_mapping()\n\nNo more masking and alignment; just use pfns.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "b026fd28ea23af24a3eea6e5be3f3d0193a8e87d", "tree": "557ccb29c1213f39951651fef68d7e7910d9893b", "parents": [ "163cc52ccd2cc5c5ae4e1c886f6fde8547feed2a" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 10:37:25 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:32:26 2009 +0100" }, "message": "intel-iommu: Change addr_to_dma_pte() to pfn_to_dma_pte()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "163cc52ccd2cc5c5ae4e1c886f6fde8547feed2a", "tree": "0371640770d8c575779b29cfaea2b27e922ce724", "parents": [ "d794dc9b302c2781c571c10dedb8094e223d31b8" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 00:51:17 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:31:12 2009 +0100" }, "message": "intel-iommu: Clean up intel_iommu_unmap_range()\n\nUse unaligned address for domain-\u003emax_addr. That algorithm isn\u0027t ideal\nanyway -- we should probably just look at the last iova in the tree.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "d794dc9b302c2781c571c10dedb8094e223d31b8", "tree": "60a410f5b37779db3efd946ec6a32aa7bf50e651", "parents": [ "6660c63a79a639b86e3a709e25a8c4fc3ab24770" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 00:27:49 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:30:45 2009 +0100" }, "message": "intel-iommu: Make dma_pte_free_pagetable() take pfns as argument\n\nWith some cleanup of intel_unmap_page(), intel_unmap_sg() and\nvm_domain_exit() to no longer play with 64-bit addresses.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "6660c63a79a639b86e3a709e25a8c4fc3ab24770", "tree": "8e9b0f30973bb33f588f9d80dee91bc798ff4127", "parents": [ "595badf5d65d50300319e6178e6df005ea501f70" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 22:41:00 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:30:35 2009 +0100" }, "message": "intel-iommu: Make dma_pte_free_pagetable() use pfns\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "595badf5d65d50300319e6178e6df005ea501f70", "tree": "00bb65e865ab8aface12c57634a152b1440364ee", "parents": [ "04b18e65dd5a3e544f07f4bcfa8fb52704a1833b" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 22:09:11 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:28:10 2009 +0100" }, "message": "intel-iommu: Make dma_pte_clear_range() take pfns as argument\n\nNoting that this is now an _inclusive_ range.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "04b18e65dd5a3e544f07f4bcfa8fb52704a1833b", "tree": "51b6c12b122a1c186c3f8fea3f723c602a4465d7", "parents": [ "66eae8469e4e4ba6f4ca7ef82103c78f6d645583" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 19:15:01 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:26:36 2009 +0100" }, "message": "intel-iommu: Make dma_pte_clear_range() use pfns\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "66eae8469e4e4ba6f4ca7ef82103c78f6d645583", "tree": "adb12962ecead5e169265aaefdf7c4472609a504", "parents": [ "a75f7cf94f01717c5103138319b96752ee2a2be9" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 19:00:32 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:38:42 2009 +0100" }, "message": "intel-iommu: Don\u0027t just mask out too-big physical addresses; BUG() instead\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "a75f7cf94f01717c5103138319b96752ee2a2be9", "tree": "b268deef1584bbc51a19b550d54339ebb276c1d4", "parents": [ "90dcfb5eb2fd427b16135a14f176a6902750b6b4" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 17:44:39 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:38:40 2009 +0100" }, "message": "intel-iommu: Make dma_pte_clear_one() take pfn not address\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "90dcfb5eb2fd427b16135a14f176a6902750b6b4", "tree": "2951f2a7e9dab02127005937c92dfa8dc0e03e07", "parents": [ "77dfa56c94d2855a25ff552b74980a5538e129f8" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 17:14:59 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:38:38 2009 +0100" }, "message": "intel-iommu: Change dma_addr_level_pte() to dma_pfn_level_pte()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "77dfa56c94d2855a25ff552b74980a5538e129f8", "tree": "be0d357d3b62e7b72ad40dcb66512bc6f29221a7", "parents": [ "dd4e831960e4f0214480fa96a53ca9bb7dd04927" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 16:40:08 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:38:32 2009 +0100" }, "message": "intel-iommu: Change address_level_offset() to pfn_level_offset()\n\nWe\u0027re shifting the inputs for now, but that\u0027ll change...\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "dd4e831960e4f0214480fa96a53ca9bb7dd04927", "tree": "740ef8b4c65d9314d337b618900cf22fdfcbdb17", "parents": [ "c7ab48d2acaf959e4d59c3f55d12fdb7ca9afd7c" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 16:21:20 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:38:11 2009 +0100" }, "message": "intel-iommu: Change dma_set_pte_addr() to dma_set_pte_pfn()\n\nAdd some helpers for converting between VT-d and normal system pfns,\nsince system pages can be larger than VT-d pages.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "c7ab48d2acaf959e4d59c3f55d12fdb7ca9afd7c", "tree": "5474dadf86c95ddf3b347000f5c114f154e7a0ab", "parents": [ "b213203e475212a69ad6fedfb73464087e317148" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Jun 26 19:10:36 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:37:44 2009 +0100" }, "message": "intel-iommu: Clean up identity mapping code, remove CONFIG_DMAR_GFX_WA\n\nThere\u0027s no need for the GFX workaround now we have \u0027iommu\u003dpt\u0027 for the\ncases where people really care about performance. There\u0027s no need to\nhave a special case for just one type of device.\n\nThis also speeds up the iommu\u003dpt path and reduces memory usage by\nsetting up the si_domain _once_ and then using it for all devices,\nrather than giving each device its own private page tables.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "b213203e475212a69ad6fedfb73464087e317148", "tree": "f5969a292e97f50f0bd0d4b7f775641464c3add2", "parents": [ "bf92df30df909710c498d05620e2df1be1ef779b" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Jun 26 18:50:28 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:37:42 2009 +0100" }, "message": "intel-iommu: Create new iommu_domain_identity_map() function\n\nWe\u0027ll want to do this to a _domain_ (the si_domain) rather than a PCI device.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "bf92df30df909710c498d05620e2df1be1ef779b", "tree": "9d1e330524fac88a95b6787e0b754e02e62df039", "parents": [ "a679128d30d0303bbf5cac839c8f6f45793ea775" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Mon Jun 29 11:31:45 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:34:11 2009 +0100" }, "message": "intel-iommu: Only avoid flushing device IOTLB for domain ID 0 in caching mode\n\nIn caching mode, domain ID 0 is reserved for non-present to present\nmapping flush. Device IOTLB doesn\u0027t need to be flushed in this case.\n\nPreviously we were avoiding the flush for domain zero, even if the IOMMU \nwasn\u0027t in caching mode and domain zero wasn\u0027t special.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "7e25a2422987a37729706b18583d177966919d2a", "tree": "dd7ec2e5912b81d73998efa5ab29089ffc50eef1", "parents": [ "28d0325ce6e0a52f53d8af687e6427fee59004d3" ], "author": { "name": "Chris Wright", "email": "chrisw@redhat.com", "time": "Thu Jun 25 18:52:05 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Jun 26 11:26:27 2009 +0100" }, "message": "intel-iommu: fix Identity Mapping to be arch independent\n\nDrop the e820 scanning and use existing function for finding valid\nRAM regions to add to 1:1 mapping.\n\nSigned-off-by: Chris Wright \u003cchrisw@redhat.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "0c26d7cc31cd81a82be3b9d7687217d49fe9c47e", "tree": "1a20b590a5d71e588af7034b21f4779e6a8bd949", "parents": [ "936940a9c7e3d99b25859bf1ff140d8c2480183a", "21ab01e2fcbfcc0d1faba2b7336b3c0f7f3c1ac8" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Jun 24 10:17:07 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Jun 24 10:17:07 2009 -0700" }, "message": "Merge branch \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6\n\n* \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: (72 commits)\n asus-laptop: remove EXPERIMENTAL dependency\n asus-laptop: use pr_fmt and pr_\u003clevel\u003e\n eeepc-laptop: cpufv updates\n eeepc-laptop: sync eeepc-laptop with asus_acpi\n asus_acpi: Deprecate in favor of asus-laptop\n acpi4asus: update MAINTAINER and KConfig links\n asus-laptop: platform dev as parent for led and backlight\n eeepc-laptop: enable camera by default\n ACPI: Rename ACPI processor device bus ID\n acerhdf: Acer Aspire One fan control\n ACPI: video: DMI workaround broken Acer 7720 BIOS enabling display brightness\n ACPI: run ACPI device hot removal in kacpi_hotplug_wq\n ACPI: Add the reference count to avoid unloading ACPI video bus twice\n ACPI: DMI to disable Vista compatibility on some Sony laptops\n ACPI: fix a deadlock in hotplug case\n Show the physical device node of backlight class device.\n ACPI: pdc init related memory leak with physical CPU hotplug\n ACPI: pci_root: remove unused dev/fn information\n ACPI: pci_root: simplify list traversals\n ACPI: pci_root: use driver data rather than list lookup\n ...\n" }, { "commit": "fbe8cddd2d85979d273d7937a2b8a47498694d91", "tree": "2ae3253bfd89337583d36afd783145786ffa531e", "parents": [ "4e8a2372f9255a1464ef488ed925455f53fbdaa1", "e86435eb91b2bff114c5a02e46e16ce21b647ebe", "7fe2a6c275a5bcec52fb3ef643daaf8265b7af0d", "0705495d9010048e293013d9d129cf723363a0a8", "35a7c64fbc77bab4ca8ae477e8ab278ccd679ce2", "152a4e630f7ffdd7ff64427c4ba488dc0bce76af", "86e437f077c68112edcb6854ec036ed7e3f9a7f3", "c8d72a5e76988140bfdfd8722f2228d94e7fa10f", "7a04b8491a077471a34938b8ca060c37220953be", "ee1ca48fae7e575d5e399d4fdcfe0afc1212a64c", "9eccbc2f67efd0d19c47f40182abf2965c287add", "7e275cc4e8e20f82740bf40ae2f5695e9e35ff09", "7b768f07dce463a054c9dd84862d15ccc3d2b712", "8cb24c8fd70ea8431744de1ca0ca34ab45fbbdaa", "113b3a2b901573961509e81a28e9546cf9defef0", "d73772474f6ebbacbe820c31c0fa1cffa7160246", "056c308d3e4859334b519033d62ef050f0e0e261", "871043bc463e7d191e7b5b00436a8852921dd833" ], "author": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed Jun 24 01:19:50 2009 -0400" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed Jun 24 01:19:50 2009 -0400" }, "message": "Merge branches \u0027acerhdf\u0027, \u0027acpi-pci-bind\u0027, \u0027bjorn-pci-root\u0027, \u0027bugzilla-12904\u0027, \u0027bugzilla-13121\u0027, \u0027bugzilla-13396\u0027, \u0027bugzilla-13533\u0027, \u0027bugzilla-13612\u0027, \u0027c3_lock\u0027, \u0027hid-cleanups\u0027, \u0027misc-2.6.31\u0027, \u0027pdc-leak-fix\u0027, \u0027pnpacpi\u0027, \u0027power_nocheck\u0027, \u0027thinkpad_acpi\u0027, \u0027video\u0027 and \u0027wmi\u0027 into release\n" }, { "commit": "f007e99c8e2e322b8331aba72414715119a2920d", "tree": "616bfcdda74341dc8b5d9ea1013bb7506407a961", "parents": [ "c4658b4e777bebf69884f4884a9bfb2f84dd71d9" ], "author": { "name": "Weidong Han", "email": "weidong.han@intel.com", "time": "Sat May 23 00:41:15 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 23 22:09:17 2009 +0100" }, "message": "Intel-IOMMU, intr-remap: source-id checking\n\nTo support domain-isolation usages, the platform hardware must be\ncapable of uniquely identifying the requestor (source-id) for each\ninterrupt message. Without source-id checking for interrupt remapping\n, a rouge guest/VM with assigned devices can launch interrupt attacks\nto bring down anothe guest/VM or the VMM itself.\n\nThis patch adds source-id checking for interrupt remapping, and then\nreally isolates interrupts for guests/VMs with assigned devices.\n\nBecause PCI subsystem is not initialized yet when set up IOAPIC\nentries, use read_pci_config_byte to access PCI config space directly.\n\nSigned-off-by: Weidong Han \u003cweidong.han@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "c4658b4e777bebf69884f4884a9bfb2f84dd71d9", "tree": "c38cf0924b01e42a936b56d9f5c3d254822d3471", "parents": [ "2c2e2c389d03bb16b8cdf9db3ac615385fac100f" ], "author": { "name": "Weidong Han", "email": "weidong.han@intel.com", "time": "Sat May 23 00:41:14 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 23 22:09:15 2009 +0100" }, "message": "Intel-IOMMU, intr-remap: set the whole 128bits of irte when modify/free it\n\nInterrupt remapping table entry is 128bits. Currently, it only sets low\n64bits of irte in modify_irte and free_irte. This ignores high 64bits\nsetting of irte, that means source-id setting will be ignored. This patch\nsets the whole 128bits of irte when modify/free it. Following source-id\nchecking patch depends on this.\n\nSigned-off-by: Weidong Han \u003cweidong.han@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "2c2e2c389d03bb16b8cdf9db3ac615385fac100f", "tree": "19af024e80adbbd1536aae0fa0c23ed4249834fe", "parents": [ "687d680985b1438360a9ba470ece8b57cd205c3b" ], "author": { "name": "Fenghua Yu", "email": "fenghua.yu@intel.com", "time": "Fri Jun 19 13:47:29 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 23 22:07:54 2009 +0100" }, "message": "IOMMU Identity Mapping Support (drivers/pci/intel_iommu.c)\n\nIdentity mapping for IOMMU defines a single domain to 1:1 map all PCI\ndevices to all usable memory.\n\nThis reduces map/unmap overhead in DMA API\u0027s and improve IOMMU\nperformance. On 10Gb network cards, Netperf shows no performance\ndegradation compared to non-IOMMU performance.\n\nThis method may lose some of DMA remapping benefits like isolation.\n\nThe patch sets up identity mapping for all PCI devices to all usable\nmemory. In the DMA API, there is no overhead to maintain page tables,\ninvalidate iotlb, flush cache etc.\n\n32 bit DMA devices don\u0027t use identity mapping domain, in order to access\nmemory beyond 4GiB.\n\nWhen kernel option iommu\u003dpt, pass through is first tried. If pass\nthrough succeeds, IOMMU goes to pass through. If pass through is not\nsupported in hw or fail for whatever reason, IOMMU goes to identity\nmapping.\n\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "687d680985b1438360a9ba470ece8b57cd205c3b", "tree": "ae253608531e5c3e823600974c610e722e7de759", "parents": [ "1053414068bad659479e6efa62a67403b8b1ec0a", "008fe148cb0fb51d266baabe2c09997b21cf90c6" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 21:38:22 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 21:38:22 2009 -0700" }, "message": "Merge git://git.infradead.org/~dwmw2/iommu-2.6.31\n\n* git://git.infradead.org/~dwmw2/iommu-2.6.31:\n intel-iommu: Fix one last ia64 build problem in Pass Through Support\n VT-d: support the device IOTLB\n VT-d: cleanup iommu_flush_iotlb_psi and flush_unmaps\n VT-d: add device IOTLB invalidation support\n VT-d: parse ATSR in DMA Remapping Reporting Structure\n PCI: handle Virtual Function ATS enabling\n PCI: support the ATS capability\n intel-iommu: dmar_set_interrupt return error value\n intel-iommu: Tidy up iommu-\u003egcmd handling\n intel-iommu: Fix tiny theoretical race in write-buffer flush.\n intel-iommu: Clean up handling of \"caching mode\" vs. IOTLB flushing.\n intel-iommu: Clean up handling of \"caching mode\" vs. context flushing.\n VT-d: fix invalid domain id for KVM context flush\n Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support\n Intel IOMMU Pass Through Support\n\nFix up trivial conflicts in drivers/pci/{intel-iommu.c,intr_remapping.c}\n" }, { "commit": "59ef7a83f1127038a433464597df02e2dc9540e7", "tree": "725d262fc2e68eb9c592d76265f878cec73f8f2d", "parents": [ "5165aece0efac6574fc3e32b6f1c2a964820d1c6", "2af5066f664cb011cf17d2e4414491fe24597e07" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 11:59:51 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 11:59:51 2009 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (74 commits)\n PCI: make msi_free_irqs() to use msix_mask_irq() instead of open coded write\n PCI: Fix the NIU MSI-X problem in a better way\n PCI ASPM: remove get_root_port_link\n PCI ASPM: cleanup pcie_aspm_sanity_check\n PCI ASPM: remove has_switch field\n PCI ASPM: cleanup calc_Lx_latency\n PCI ASPM: cleanup pcie_aspm_get_cap_device\n PCI ASPM: cleanup clkpm checks\n PCI ASPM: cleanup __pcie_aspm_check_state_one\n PCI ASPM: cleanup initialization\n PCI ASPM: cleanup change input argument of aspm functions\n PCI ASPM: cleanup misc in struct pcie_link_state\n PCI ASPM: cleanup clkpm state in struct pcie_link_state\n PCI ASPM: cleanup latency field in struct pcie_link_state\n PCI ASPM: cleanup aspm state field in struct pcie_link_state\n PCI ASPM: fix typo in struct pcie_link_state\n PCI: drivers/pci/slot.c should depend on CONFIG_SYSFS\n PCI: remove redundant __msi_set_enable()\n PCI PM: consistently use type bool for wake enable variable\n x86/ACPI: Correct maximum allowed _CRS returned resources and warn if exceeded\n ...\n" }, { "commit": "2af5066f664cb011cf17d2e4414491fe24597e07", "tree": "fe9f787a3eac10cfef1bbc7e18ee7800c281f773", "parents": [ "f598282f5145036312d90875d0ed5c14b49fd8a7" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Jun 18 19:20:26 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jun 19 15:11:45 2009 -0700" }, "message": "PCI: make msi_free_irqs() to use msix_mask_irq() instead of open coded write\n\nUse msix_mask_irq() instead of direct use of writel, so as not to clear\npreserved bits in the Vector Control register [31:1].\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f598282f5145036312d90875d0ed5c14b49fd8a7", "tree": "3cb76a5a2cbd161ce03007370f5e38c133efe21d", "parents": [ "5c92ffb1ecc7f13267cdef5dda8a838937912c93" ], "author": { "name": "Matthew Wilcox", "email": "willy@linux.intel.com", "time": "Thu Jun 18 19:15:59 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jun 19 15:11:39 2009 -0700" }, "message": "PCI: Fix the NIU MSI-X problem in a better way\n\nThe previous MSI-X fix (8d181018532dd709ec1f789e374cda92d7b01ce1) had\nthree bugs. First, it didn\u0027t move the write that disabled the vector.\nThis led to writing garbage to the MSI-X vector (spotted by Michael\nEllerman). It didn\u0027t fix the PCI resume case, and it had a race window\nwhere the device could generate an interrupt before the MSI-X registers\nwere programmed (leading to a DMA to random addresses).\n\nFortunately, the MSI-X capability has a bit to mask all the vectors.\nBy setting this bit instead of clearing the enable bit, we can ensure\nthe device will not generate spurious interrupts. Since the capability\nis now enabled, the NIU device will not have a problem with the reads\nand writes to the MSI-X registers being in the original order in the code.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5c92ffb1ecc7f13267cdef5dda8a838937912c93", "tree": "50a5ffeea038549e1195d80f10b183f55c45e4ef", "parents": [ "3647584d9ef35c9ec4abefdbea29959c26c54f13" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:23:57 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:23 2009 -0700" }, "message": "PCI ASPM: remove get_root_port_link\n\nBy having a pointer to the root port link, we can remove loops in\nget_root_port_link() to search the root port link.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3647584d9ef35c9ec4abefdbea29959c26c54f13", "tree": "107167bb680a15c1581dfb3f05737cfe514c6c29", "parents": [ "efdf8288819df67d608a186f9d17a7d4051f3c1f" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:23:09 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:22 2009 -0700" }, "message": "PCI ASPM: cleanup pcie_aspm_sanity_check\n\nMinor cleanup for pcie_aspm_sanity_check().\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "efdf8288819df67d608a186f9d17a7d4051f3c1f", "tree": "3d781654102cafc726bbc1894070260364eac3af", "parents": [ "5e0eaa7d3679c3ef8618803bc9311270e5816641" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:22:26 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:22 2009 -0700" }, "message": "PCI ASPM: remove has_switch field\n\nWe don\u0027t need the \u0027has_switch\u0027 field in the struct pcie_link_state.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5e0eaa7d3679c3ef8618803bc9311270e5816641", "tree": "895538798c0fd42aa499ac78ed0cb40a8fec27fa", "parents": [ "7ab709910323a8af20722c066267516b3e7680a2" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:21:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:21 2009 -0700" }, "message": "PCI ASPM: cleanup calc_Lx_latency\n\nCleanup for calc_L0S_latency() and calc_L1_latency().\n\n - Separate exit latency and acceptable latency calculation.\n - Some minor cleanups.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7ab709910323a8af20722c066267516b3e7680a2", "tree": "d35af8b1894b3813ef1fc7a6aea13fa9dbda78b9", "parents": [ "430842e29d396928989c0a45e05025e988004d79" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:20:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:20 2009 -0700" }, "message": "PCI ASPM: cleanup pcie_aspm_get_cap_device\n\nMinor cleanup for pcie_aspm_get_cap_device().\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "430842e29d396928989c0a45e05025e988004d79", "tree": "ecdfed05c82324784fabf42f5f008efa1d3c6dc5", "parents": [ "f7ea3d7fc03753b08e267fece19c56383e6b856f" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:20:10 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:19 2009 -0700" }, "message": "PCI ASPM: cleanup clkpm checks\n\nIn the current ASPM implementation, callers of pcie_set_clock_pm() check\nClock PM capability of the link or current Clock PM state of the link.\nThis check should be done in pcie_set_clock_pm() itself.\n\nThis patch moves those checks into pcie_set_clock_pm(). It also\nintroduces pcie_set_clkpm_nocheck() that is equivalent to old\npcie_set_clock_pm(), for the caller who wants to change Clocl PM state\nregardless of the Clock PM capability or current Clock PM state. In\naddition, this patch changes the function name from\npcie_set_clock_pm() to pcie_set_clkpm() for consistency.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f7ea3d7fc03753b08e267fece19c56383e6b856f", "tree": "2ff13c579b8e7dedf3a088b93982e25a3647bdf1", "parents": [ "8d349ace9a5c2a8404bcf4a371fe170480ffbebb" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:19:00 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:18 2009 -0700" }, "message": "PCI ASPM: cleanup __pcie_aspm_check_state_one\n\nClean up and simplify __pcie_aspm_check_state_one().\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8d349ace9a5c2a8404bcf4a371fe170480ffbebb", "tree": "6495378f6b3255752cd04af22e653ece36c7d8b7", "parents": [ "5aa63583cbec27482c6f1d761a0509f59b7969a8" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:18:22 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:15 2009 -0700" }, "message": "PCI ASPM: cleanup initialization\n\nClean up ASPM initialization by refactoring some functionality, renaming\nfunctions, and moving things around.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5aa63583cbec27482c6f1d761a0509f59b7969a8", "tree": "a989edcd7e85199aee66eff2f087dfd6d94176bb", "parents": [ "5cde89d80172a393e49077d2450545b97ac8d972" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:17:44 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:26 2009 -0700" }, "message": "PCI ASPM: cleanup change input argument of aspm functions\n\nIn the current ASPM implementation, there are many functions that\ntake a pointer to struct pci_dev corresponding to the upstream component\nof the link as a parameter. But, since those functions handle PCI\nexpress link state, a pointer to struct pcie_link_state is more\nsuitable than a pointer to struct pci_dev. Changing a parameter to a\npointer to struct pcie_link_state makes ASPM code much simpler and\neasier to read. This patch also contains some minor cleanups. This patch\ndoesn\u0027t have any functional change.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5cde89d80172a393e49077d2450545b97ac8d972", "tree": "86d5810ca54f0be2079c294e90ad3b3c9504bd69", "parents": [ "4d246e458918d469ad645fd5f937ac22982e0466" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:17:04 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:26 2009 -0700" }, "message": "PCI ASPM: cleanup misc in struct pcie_link_state\n\nCleanup for some fields in pcie_link_state.\n\n- Add comments.\n- make \"downstream_has_switch\" field 1-bit.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4d246e458918d469ad645fd5f937ac22982e0466", "tree": "7af516967d8f9ef8824f74f9214bf74fdc93d894", "parents": [ "b6c2e54d3ea27719b920faf15db92dfe0260f0d2" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:15:38 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:25 2009 -0700" }, "message": "PCI ASPM: cleanup clkpm state in struct pcie_link_state\n\nThe \"clk_pm_capable\", \"clk_pm_enable\" and \"bios_clk_state\" fields in\nthe struct pcie_link_state only take 1-bit value. So those fields\ndon\u0027t need to be defined as unsigned int. This patch makes those\nfields 1-bit, and cleans up some related code.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b6c2e54d3ea27719b920faf15db92dfe0260f0d2", "tree": "407745d063fcae2b390515059e17cee5b2d3c13e", "parents": [ "80bfdbe370d56a1448c7078cd6d286b89241a72e" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:14:58 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:25 2009 -0700" }, "message": "PCI ASPM: cleanup latency field in struct pcie_link_state\n\nClean up latency related data structures for ASPM.\n\n- Introduce struct acpi_latency for exit latency and acceptable\n latency management. With this change, struct endpoint_state is no\n longer needed.\n\n- We don\u0027t need to hold both upstream latency and downstream latency\n in the current implementation.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "80bfdbe370d56a1448c7078cd6d286b89241a72e", "tree": "4d3f8c82aa87c1bf498946103b1e816f88121292", "parents": [ "dc64cd1131a3b5762e26bd8b01dc79030dd0c555" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:12:43 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:25 2009 -0700" }, "message": "PCI ASPM: cleanup aspm state field in struct pcie_link_state\n\nThe \"support_state\", \"enabled_state\" and \"bios_aspm_state\" fields in\nthe struct pcie_link_state take 2-bit value. So those fields don\u0027t\nneed to be defined as unsigned int. This patch makes those fields\n2-bit, and cleans up some related code.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dc64cd1131a3b5762e26bd8b01dc79030dd0c555", "tree": "6a994b4e5fc840e071cc2e7510b35a8c7d549200", "parents": [ "268a03a42d3377d5fb41e6e7cbdec4e0b65cab2e" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:11:33 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:25 2009 -0700" }, "message": "PCI ASPM: fix typo in struct pcie_link_state\n\nFix a typo in struct pcie_link_state.\n\nThe \"sibiling\" field in the struct pcie_link_state should be\n\"sibling\".\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "268a03a42d3377d5fb41e6e7cbdec4e0b65cab2e", "tree": "3d94d3a53255fc1acc920f64a85445dbef35f06c", "parents": [ "110828c9cdce6e8ec68479ced4ca0bdc1135bb91" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Wed Jun 17 19:03:57 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:24 2009 -0700" }, "message": "PCI: drivers/pci/slot.c should depend on CONFIG_SYSFS\n\nThere is no way to interact with a physical PCI slot without\nsysfs, so encode the dependency and prevent this build error:\n\n\tdrivers/pci/slot.c: In function \u0027pci_hp_create_module_link\u0027:\n\tdrivers/pci/slot.c:327: error: \u0027module_kset\u0027 undeclared\n\nThis patch _should_ make pci-sysfs.o depend on CONFIG_SYSFS too,\nbut we cannot (yet) because the PCI core merrily assumes the\nexistence of sysfs:\n\n\tdrivers/built-in.o: In function `pci_bus_add_device\u0027:\n\tdrivers/pci/bus.c:89: undefined reference to `pci_create_sysfs_dev_files\u0027\n\tdrivers/built-in.o: In function `pci_stop_dev\u0027:\n\tdrivers/pci/remove.c:24: undefined reference to `pci_remove_sysfs_dev_files\u0027\n\nSo do the minimal bit for now and figure out how to untangle it\nlater.\n\nReported-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nAcked-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nReported-by: Stephen Rothwell \u003csfr@canb.auug.org.au\u003e\nFix-suggested-by: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "110828c9cdce6e8ec68479ced4ca0bdc1135bb91", "tree": "6829824540b2047e275a557609606723a52eb429", "parents": [ "7d9a73f6dcf4390d256bf19330c81e91523a26d5" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Tue Jun 16 06:31:45 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:24 2009 -0700" }, "message": "PCI: remove redundant __msi_set_enable()\n\nWe have the \u0027pos\u0027 of the MSI capability at all locations which call\nmsi_set_enable(), so pass it to msi_set_enable() instead of making it\nfind the capability every time.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d6aa484c1c0cd39ff3a42f4050b55d2a5b285ef5", "tree": "0ed1b14e195fcdf460c2ab64893a8105495cc262", "parents": [ "97719a8726fe8d3ea12a85fbf4f514a915ba30ec" ], "author": { "name": "Alexander Chiang", "email": "achiang@hp.com", "time": "Wed Jun 10 19:55:50 2009 +0000" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed Jun 17 23:32:00 2009 -0400" }, "message": "PCI Hotplug: acpiphp: convert to acpi_get_pci_dev\n\nNow that acpi_get_pci_dev is available, let\u0027s use it instead of\nacpi_get_pci_id.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nAcked-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "275582031f9b3597a1b973f3ff617adfe639faa2", "tree": "7f4e2c43709758108042e5dcf9b89d756e5bf8e5", "parents": [ "ce597bb42aa84bc73db80509b7c37e7fbc0b75c4" ], "author": { "name": "Alexander Chiang", "email": "achiang@hp.com", "time": "Wed Jun 10 19:55:14 2009 +0000" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed Jun 17 23:22:15 2009 -0400" }, "message": "ACPI: Introduce acpi_is_root_bridge()\n\nReturns whether an ACPI CA node is a PCI root bridge or not.\n\nThis API is generically useful, and shouldn\u0027t just be a hotplug function.\n\nThe implementation becomes much simpler as well.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nAcked-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "cebd78a8c5624b5cf04c39c3335a5fc8670a7b69", "tree": "426b2ef97ee950e11e231fff1286ae06cf1f3423", "parents": [ "7cc47662197b3050a974a6c6aed52291bb38ded0" ], "author": { "name": "Matthew Wilcox", "email": "willy@linux.intel.com", "time": "Wed Jun 17 16:33:33 2009 -0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Jun 17 14:04:42 2009 -0700" }, "message": "Fix pci_claim_resource\n\nInstead of starting from the iomem or ioport roots, start from the\nparent bus\u0027 resources. This fixes a bug where child resources would\nappear above their parents resources if they had the same size.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nTested-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "7d9a73f6dcf4390d256bf19330c81e91523a26d5", "tree": "dddaeb3e6a1f5d5dd8d1b96ed6105566b69a3b21", "parents": [ "f9cde5ffed17bf74f6bef042d99edb0622f58576" ], "author": { "name": "Frans Pop", "email": "elendil@planet.nl", "time": "Wed Jun 17 00:16:15 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 15:19:02 2009 -0700" }, "message": "PCI PM: consistently use type bool for wake enable variable\n\nOther functions use type bool, so use that for pci_enable_wake as well.\n\nSigned-off-by: Frans Pop \u003celendil@planet.nl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ab7de999a2c771482698efa6fe7c7b7fcb1d482a", "tree": "64c3df6ccc31c2ca8ec912fec4699bf13aeab979", "parents": [ "d2abdf62882d982c58e7a6b09ecdcfcc28075e2e" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Jun 16 16:25:40 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:18 2009 -0700" }, "message": "PCI: remove invalid comment of msi_mask_irq()\n\nRemove invalid comment of msi_mask_irq().\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d2abdf62882d982c58e7a6b09ecdcfcc28075e2e", "tree": "d43dd7e66f4de4e044ed632a9eb6d61c61019b78", "parents": [ "c12ff1df5f114484e3d8abd028769a624cc3399f" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sun Jun 14 21:25:02 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:17 2009 -0700" }, "message": "PCI PM: Fix handling of devices without PM support by pci_target_state()\n\nIf a PCI device is not power-manageable either by the platform, or\nwith the help of the native PCI PM interface, pci_target_state() will\nreturn either PCI_D3hot, or PCI_POWER_ERROR for it, depending on\nwhether or not the device is configured to wake up the system. Alas,\nnone of these return values is correct, because each of them causes\npci_prepare_to_sleep() to return error code, although it should\ncomplete successfully in such a case.\n\nFix this problem by making pci_target_state() always return PCI_D0\nfor devices that cannot be power managed.\n\nCc: stable@kernel.org\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c12ff1df5f114484e3d8abd028769a624cc3399f", "tree": "410cb0adf85a52772d5acf6621b421c33b44820a", "parents": [ "f85876ba82281f15bc4da11e41b94243a8b2b5b4" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Jun 13 15:52:15 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:16 2009 -0700" }, "message": "PCI: support Secondary Bus Reset\n\nPCI-to-PCI Bridge 1.2 specifies that the Secondary Bus Reset bit can\nforce the assertion of RST# on the secondary interface, which can be\nused to reset all devices including subordinates under this bus. This\ncan be used to reset a function if this function is the only device\nunder this bus.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f85876ba82281f15bc4da11e41b94243a8b2b5b4", "tree": "8a2b9143123a8aa319bbe2e3078d8ea65aeb77da", "parents": [ "8c1c699fec9e9021bf6ff0285dee086bb27aec90" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Jun 13 15:52:14 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:16 2009 -0700" }, "message": "PCI: support PM D0hot-\u003eD3 transition reset\n\nPCI PM 1.2 specifies that the device will perform an internal reset upon\ntransitioning from D3hot to D0 when the NO_SOFT_RESET bit is clear. This\nmethod can be used to reset a function if neither PCIe FLR nor PCI AF FLR\nare supported.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8c1c699fec9e9021bf6ff0285dee086bb27aec90", "tree": "4af7bd96c1b651633ff7b6721959aeacd120e4ee", "parents": [ "c465def6bfe834b62623caa9b98f2d4f4739875a" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Jun 13 15:52:13 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:15 2009 -0700" }, "message": "PCI: cleanup Function Level Reset\n\nThis patch enhances the FLR functions:\n 1) remove disable_irq() so the shared IRQ won\u0027t be disabled.\n 2) replace the 1s wait with 100, 200 and 400ms wait intervals\n for the Pending Transaction.\n 3) replace mdelay() with msleep().\n 4) add might_sleep().\n 5) lock the device to prevent PM suspend from accessing the CSRs\n during the reset.\n 6) coding style fixes.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c465def6bfe834b62623caa9b98f2d4f4739875a", "tree": "00166d8258f91c7f62b2bf84f4b8d775c906a308", "parents": [ "3d5505c56db5c8d1eeca45c325b19e95115afdea" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Mon Jun 15 10:42:57 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:14 2009 -0700" }, "message": "PCI AER: software error injection\n\nDebugging PCIE AER code can be very difficult because it is hard\nto trigger various real hardware errors. This patch provide a\nsoftware based error injection tool, which can fake various PCIE\nerrors with a user space helper tool named \"aer-inject\". Which\ncan be gotten from:\n\n http://www.kernel.org/pub/linux/kernel/people/yhuang/\n\nThe patch fakes AER error by faking some PCIE AER related\nregisters and an AER interrupt for specified the PCIE device.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3d5505c56db5c8d1eeca45c325b19e95115afdea", "tree": "fe3f99f5f38c2b93f7c4421aaeaf3df604dda374", "parents": [ "28eb27cf0839a30948335f9b2edda739f48b7a2e" ], "author": { "name": "Zhang, Yanmin", "email": "yanmin_zhang@linux.intel.com", "time": "Tue Jun 16 13:35:16 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:14 2009 -0700" }, "message": "PCI AER: multiple error support\n\nWhen a root port receives the same errors more than once before the\nkernel process them, the Multiple Error Messages Received flags are set\nby hardware. Because the root port could only save one kind of\ncorrectable error source id and another uncorrectable error source id at\nthe same time, the second message sender id is lost if the 2 messages\nare sent from 2 different devices. This patch makes the kernel search\nall devices under the root port when multiple messages are received.\n\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Zhang Yanmin \u003cyanmin_zhang@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "28eb27cf0839a30948335f9b2edda739f48b7a2e", "tree": "3278825cdfc730c4b44fcf18a41a2d96180030a3", "parents": [ "70298c6e6c1ba68346336b4ea54bd5c0abbf73c8" ], "author": { "name": "Zhang, Yanmin", "email": "yanmin_zhang@linux.intel.com", "time": "Tue Jun 16 13:35:11 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:13 2009 -0700" }, "message": "PCI AER: support invalid error source IDs\n\nWhen the bus id part of error source id is equal to 0 or nosourceid\u003d1,\nmake the kernel probe the AER status registers of all devices under the\nroot port to find the initial error reporter.\n\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Zhang Yanmin \u003cyanmin_zhang@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "70298c6e6c1ba68346336b4ea54bd5c0abbf73c8", "tree": "363d0a784d8a28688c0fda006279563a7fd3629b", "parents": [ "a6c0d5c6ebb3d988b1f18a1612b5188f3f555637" ], "author": { "name": "Zhang, Yanmin", "email": "yanmin_zhang@linux.intel.com", "time": "Tue Jun 16 13:34:38 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:13 2009 -0700" }, "message": "PCI AER: support Multiple Error Received and no error source id\n\nBased on PCI Express AER specs, a root port might receive multiple\nTLP errors while it could only save a correctable error source id\nand an uncorrectable error source id at the same time. In addition,\nsome root port hardware might be unable to provide a correct source\nid, i.e., the source id, or the bus id part of the source id provided\nby root port might be equal to 0.\n\nThe patchset implements the support in kernel by searching the device\ntree under the root port.\n\nPatch 1 changes parameter cb of function pci_walk_bus to return a value.\nWhen cb return non-zero, pci_walk_bus stops more searching on the\ndevice tree.\n\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Zhang Yanmin \u003cyanmin_zhang@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a6c0d5c6ebb3d988b1f18a1612b5188f3f555637", "tree": "a2053da4e1db2604b28d41b17e9315a17889eb02", "parents": [ "c825bc94c8c1908750ab20413eb639c6be029e2d" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Jun 16 11:02:02 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:12 2009 -0700" }, "message": "PCI hotplug: remove redundant .owner initializations\n\nThe \"owner\" field in struct hotplug_slot_ops is initialized by PCI\nhotplug core. So each hotplug controller driver doesn\u0027t need to\ninitialize it.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c825bc94c8c1908750ab20413eb639c6be029e2d", "tree": "6e5800fe52e0f94f42fdcd4c327b8cfaf803978a", "parents": [ "498a8faf2c7eb974f70b7c5a60a31f0d48c35d44" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Jun 16 11:01:25 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:11 2009 -0700" }, "message": "PCI hotplug: create symlink to hotplug driver module\n\nCreate symbolic link to hotplug driver module in the PCI slot\ndirectory (/sys/bus/pci/slots/\u003cSLOT#\u003e). In the past, we need to load\nhotplug drivers one by one to identify the hotplug driver that handles\nthe slot, and it was very inconvenient especially for trouble shooting.\nWith this change, we can easily identify the hotplug driver.\n\nSigned-off-by: Taku Izumi \u003cizumi.taku@jp.fujitsu.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "498a8faf2c7eb974f70b7c5a60a31f0d48c35d44", "tree": "b7703de6971327eacbb5471bb251a05b9c3f56ea", "parents": [ "bd3d99c17039fd05a29587db3f4a180c48da115a" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Jun 16 11:00:47 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:11 2009 -0700" }, "message": "PCI hotplug: fix return value of has_foo() functions\n\nCurrent has_foo() functions in pci_hotplug_core.c returns 0 if the\n\"foo\" property is true. It would cause misunderstanding. In addition,\nthe error code of those functions is never checked, so this patch\nchanges those functions\u0027 error code to \u0027bool\u0027 and return true if the\nproperty \"foo\" is true.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bd3d99c17039fd05a29587db3f4a180c48da115a", "tree": "9eb211ae93977297f56f6e09c628de16d26f1bdb", "parents": [ "1298307736a5882352418b4dc7c65442ab3b8bd4" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Jun 02 13:52:26 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:10 2009 -0700" }, "message": "PCI: Remove untested Electromechanical Interlock (EMI) support in pciehp.\n\nThe EMI support in pciehp is obviously broken. It is implemented using\nstruct hotplug_slot_attribute, but sysfs_ops for pci_slot_ktype is NOT\nfor struct hotplug_slot_attribute, but for struct pci_slot_attribute.\nThis bug had been there for a long time, maybe it was introduced when\nPCI slot framework was introduced. The reason why this bug didn\u0027t\ncause any problem is maybe the EMI support is not tested at all\nbecause of lack of test environment.\n\nAs described above, the EMI support in pciehp seems not to be tested\nat all. So this patch removes EMI support from pciehp, instead of\nfixing the bug.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "634deb028c9188b4144863ea87dde5457fb93e92", "tree": "e73c2e0cc03d7cfdee4cc39b1a375b8024a96183", "parents": [ "a72b46c3849cdb05993015991bde548ab8b6d7ac" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Fri Apr 24 10:45:23 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:29:33 2009 -0700" }, "message": "PCI: PCIE AER: export aer_irq\n\nThis is used by PCIE AER error injection to fake an PCI AER interrupt.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a72b46c3849cdb05993015991bde548ab8b6d7ac", "tree": "a782d4ab9c217792c9a8cefe48db9aebc0734dbe", "parents": [ "1eb3948716f68bdb71509d0175765295f1aca23d" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Fri Apr 24 10:45:17 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:29:33 2009 -0700" }, "message": "PCI: Add pci_bus_set_ops\n\npci_bus_set_ops changes pci_ops associated with a pci_bus. This can be\nused by debug tools such as PCIE AER error injection to fake some PCI\nconfiguration registers.\n\nAcked-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1eb3948716f68bdb71509d0175765295f1aca23d", "tree": "826702fca83450b41168b110017237ee6a70ea05", "parents": [ "8784fd4d497171882319e4b513f5a5949fc8ab43" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue May 26 16:08:36 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:29:32 2009 -0700" }, "message": "PCI: use pci_is_root_bus() in pci_common_swizzle()\n\nUse pci_is_root_bus() in pci_common_swizzle() for checking if the pci\nbus is root, for code consistency.\n\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nReviewed-by: Grant Grundler \u003cgrundler@parisc-linux.org\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8784fd4d497171882319e4b513f5a5949fc8ab43", "tree": "a3cffbfce49e21b00dcebfeab8bc0c2ebd004c20", "parents": [ "9fc39256508c18d2861de11622183dfb6e79de87" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue May 26 16:07:33 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:29:31 2009 -0700" }, "message": "PCI: use pci_is_root_bus() in pci_get_interrupt_pin()\n\nUse pci_is_root_bus() in pci_get_interrupt_pin() for checking if the\npci bus is root, for code consistency.\n\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nReviewed-by: Grant Grundler \u003cgrundler@parisc-linux.org\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9fc39256508c18d2861de11622183dfb6e79de87", "tree": "75c030716b106de4d79e4828f34b8e6b0592b861", "parents": [ "6e3f36df0ffa433e273c89f1447c94382a9db49e" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue May 26 16:06:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:29:31 2009 -0700" }, "message": "PCI: use pci_is_root_bus() in pci_read_bridge_bases()\n\nUse pci_is_root_bus() in pci_read_bridge_bases() to check if the pci\nbus is root, for code consistency.\n\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nReviewed-by: Grant Grundler \u003cgrundler@parisc-linux.org\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6e3f36df0ffa433e273c89f1447c94382a9db49e", "tree": "47f29773dd108bd06d106aaabc7a097bd5373639", "parents": [ "a222b8f83b995e9c6fe2aff2a8125facb49f658e" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue May 26 16:06:10 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:29:30 2009 -0700" }, "message": "PCI: use pci_is_root_bus() in pci_find_upstream_pcie_bridge()\n\nUse pci_is_root_bus() in pci_find_upstream_pcie_bridge() to check if\nthe pci bus is root, for code consistency.\n\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nReviewed-by: Grant Grundler \u003cgrundler@parisc-linux.org\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "74c57428971d28863ec1804b1dd453930bbe1306", "tree": "ea051c151381cc22578343609a031c6823394b42", "parents": [ "26c56dc0c4fbdf3af12ebc48278f09ef65ddb4dd" ], "author": { "name": "Michal Miroslaw", "email": "mirq-linux@rere.qmqm.pl", "time": "Tue May 12 13:49:25 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:29:28 2009 -0700" }, "message": "PCI quirk: HP hides SMBus controller in Compaq nx9500 laptops\n\nI found no references to SMBus in ACPI DSDT disassembly on my laptop\nso this should be safe.\n\nSigned-off-by: Michal Miroslaw \u003cmirq-linux@rere.qmqm.pl\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "26c56dc0c4fbdf3af12ebc48278f09ef65ddb4dd", "tree": "e1312ea1b9a0f44f8c6208930e410cfd308a8f96", "parents": [ "4096ed0fc7c6ed83da44ab27ab7d1c7cd6e8e175" ], "author": { "name": "Michal Miroslaw", "email": "mirq-linux@rere.qmqm.pl", "time": "Tue May 12 13:49:26 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:29:08 2009 -0700" }, "message": "PCI quirk: unhide \u0027Overflow\u0027 device on i828{6,7}5P/PE chipsets\n\nSome BIOSes hide \u0027overflow\u0027 device (dev #6) for i82875P/PE chipsets.\nThe same happens for i82865P/PE. Add a quirk to enable this device.\nThis allows i82875 EDAC driver to bind to chipset\u0027s dev #6 and not\ndev #0 as the latter is used by AGP driver.\n\nOn my laptop (i82865P based) ACPI code is disabling this device\nagain in \\_SB.PCI0._CRS method (called at least at PNP init time).\nThis can be easily worked around by patching DSDT.\n\n[akpm@linux-foundation.org: coding-style fixes]\nSigned-off-by: Michal Miroslaw \u003cmirq-linux@rere.qmqm.pl\u003e\nAcked-by: Doug Thompson \u003cnorsk5@yahoo.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e1f5b94fd0c93c3e27ede88b7ab652d086dc960f", "tree": "e8de7a132eb88521dd1c19e128eba2d5349bdf4f", "parents": [ "6fd03301d76bc439382710e449f58efbb233df1b", "1b6ed69f974f6f32c8be0d9a7fc952822eb83b6f" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Jun 16 13:06:10 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Jun 16 13:06:10 2009 -0700" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6: (143 commits)\n USB: xhci depends on PCI.\n USB: xhci: Add Makefile, MAINTAINERS, and Kconfig entries.\n USB: xhci: Respect critical sections.\n USB: xHCI: Fix interrupt moderation.\n USB: xhci: Remove packed attribute from structures.\n usb; xhci: Fix TRB offset calculations.\n USB: xhci: replace if-elseif-else with switch-case\n USB: xhci: Make xhci-mem.c include linux/dmapool.h\n USB: xhci: drop spinlock in xhci_urb_enqueue() error path.\n USB: Change names of SuperSpeed ep companion descriptor structs.\n USB: xhci: Avoid compiler reordering in Link TRB giveback.\n USB: xhci: Clean up xhci_irq() function.\n USB: xhci: Avoid global namespace pollution.\n USB: xhci: Fix Link TRB handoff bit twiddling.\n USB: xhci: Fix register write order.\n USB: xhci: fix some compiler warnings in xhci.h\n USB: xhci: fix lots of compiler warnings.\n USB: xhci: use xhci_handle_event instead of handle_event\n USB: xhci: URB cancellation support.\n USB: xhci: Scatter gather list support for bulk transfers.\n ...\n" }, { "commit": "00240c3839d843ccf07abd52806f421f7b87bbdc", "tree": "4ad3a8c543a7a3de0893b1289086e62fffb98bc6", "parents": [ "604eb89ffed9fba268582dc44d5b462ea94cc0ca" ], "author": { "name": "Alan Stern", "email": "stern@rowland.harvard.edu", "time": "Mon Apr 27 13:33:16 2009 -0400" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Mon Jun 15 21:44:44 2009 -0700" }, "message": "PCI: add power-state name strings\n\nThis patch (as1235) adds an array of PCI power-state names, together\nwith a simple inline accessor routine.\n\nSigned-off-by: Alan Stern \u003cstern@rowland.harvard.edu\u003e\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "8952f593ea66bff4a30f9e641dc6c79832ca64cf", "tree": "9c77ebad4a513f4fdaea7e22c8cc822ae58c7ff5", "parents": [ "1902a9e62ba34a1071407ab61cef626e019a0923" ], "author": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Thu Apr 30 14:43:31 2009 -0700" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Mon Jun 15 21:30:27 2009 -0700" }, "message": "PCIE: remove driver_data direct access of struct device\n\nIn the near future, the driver core is going to not allow direct access\nto the driver_data pointer in struct device. Instead, the functions\ndev_get_drvdata() and dev_set_drvdata() should be used. These functions\nhave been around since the beginning, so are backwards compatible with\nall older kernel versions.\n\n\nCc: linux-pci@vger.kernel.org\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n" }, { "commit": "2ed0e21b30b53d3a94e204196e523e6c8f732b56", "tree": "de2635426477d86338a9469ce09ba0626052288f", "parents": [ "0fa213310cd8fa7a51071cdcf130e26fa56e9549", "9cbc1cb8cd46ce1f7645b9de249b2ce8460129bb" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 15 09:40:05 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 15 09:40:05 2009 -0700" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1244 commits)\n pkt_sched: Rename PSCHED_US2NS and PSCHED_NS2US\n ipv4: Fix fib_trie rebalancing\n Bluetooth: Fix issue with uninitialized nsh.type in DTL-1 driver\n Bluetooth: Fix Kconfig issue with RFKILL integration\n PIM-SM: namespace changes\n ipv4: update ARPD help text\n net: use a deferred timer in rt_check_expire\n ieee802154: fix kconfig bool/tristate muckup\n bonding: initialization rework\n bonding: use is_zero_ether_addr\n bonding: network device names are case sensative\n bonding: elminate bad refcount code\n bonding: fix style issues\n bonding: fix destructor\n bonding: remove bonding read/write semaphore\n bonding: initialize before registration\n bonding: bond_create always called with default parameters\n x_tables: Convert printk to pr_err\n netfilter: conntrack: optional reliable conntrack event delivery\n list_nulls: add hlist_nulls_add_head and hlist_nulls_del\n ...\n" }, { "commit": "0fa213310cd8fa7a51071cdcf130e26fa56e9549", "tree": "2a7e5cc33c8938ec82604a99c3797a3132fd91ec", "parents": [ "d3bf80bff13597004b5724ee4549cd68eb0badf0", "bc47ab0241c7c86da4f5e5f82fbca7d45387c18d" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 15 09:32:52 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 15 09:32:52 2009 -0700" }, "message": "Merge branch \u0027merge\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc\n\n* \u0027merge\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (103 commits)\n powerpc: Fix bug in move of altivec code to vector.S\n powerpc: Add support for swiotlb on 32-bit\n powerpc/spufs: Remove unused error path\n powerpc: Fix warning when printing a resource_size_t\n powerpc/xmon: Remove unused variable in xmon.c\n powerpc/pseries: Fix warnings when printing resource_size_t\n powerpc: Shield code specific to 64-bit server processors\n powerpc: Separate PACA fields for server CPUs\n powerpc: Split exception handling out of head_64.S\n powerpc: Introduce CONFIG_PPC_BOOK3S\n powerpc: Move VMX and VSX asm code to vector.S\n powerpc: Set init_bootmem_done on NUMA platforms as well\n powerpc/mm: Fix a AB-\u003eBA deadlock scenario with nohash MMU context lock\n powerpc/mm: Fix some SMP issues with MMU context handling\n powerpc: Add PTRACE_SINGLEBLOCK support\n fbdev: Add PLB support and cleanup DCR in xilinxfb driver.\n powerpc/virtex: Add ml510 reference design device tree\n powerpc/virtex: Add Xilinx ML510 reference design support\n powerpc/virtex: refactor intc driver and add support for i8259 cascading\n powerpc/virtex: Add support for Xilinx PCI host bridge\n ...\n" }, { "commit": "9cbc1cb8cd46ce1f7645b9de249b2ce8460129bb", "tree": "8d104ec2a459346b99413b0b77421ca7b9936c1a", "parents": [ "ca44d6e60f9de26281fda203f58b570e1748c015", "45e3e1935e2857c54783291107d33323b3ef33c8" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Jun 15 03:02:23 2009 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Jun 15 03:02:23 2009 -0700" }, "message": "Merge branch \u0027master\u0027 of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6\n\nConflicts:\n\tDocumentation/feature-removal-schedule.txt\n\tdrivers/scsi/fcoe/fcoe.c\n\tnet/core/drop_monitor.c\n\tnet/core/net-traces.c\n" }, { "commit": "db5ed9beabc0a2084ab0e0cc46bf911b8bf16fa8", "tree": "d36ea661685c094a4674489365068dd0c0cd16dc", "parents": [ "ff2f5ff0cf224780c3bd035d3e6ff4a30fcacae7" ], "author": { "name": "Peter Huewe", "email": "peterhuewe@gmx.de", "time": "Sat Jun 06 14:58:56 2009 +0200" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Fri Jun 12 18:01:51 2009 +0200" }, "message": "trivial: pci hotplug: adding __init/__exit macros to sgi_hotplug\n\nTrivial patch which adds the __init and __exit macros to the module_init /\nmodule_exit functions from drivers/pci/hotplug/sgi_hotplug.c\nlinux version 2.6.30-rc8\n\nSigned-off-by: Peter Huewe \u003cpeterhuewe@gmx.de\u003e\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\n" }, { "commit": "bc47ab0241c7c86da4f5e5f82fbca7d45387c18d", "tree": "b9c33ae8b6de43e44cc5fcbaa3e4a15f18a5ed42", "parents": [ "37f9ef553bed630957e025504cdcbc76f5de49d5", "8ebf975608aaebd7feb33d77f07ba21a6380e086" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Fri Jun 12 16:53:38 2009 +1000" }, "committer": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Fri Jun 12 16:53:38 2009 +1000" }, "message": "Merge commit \u0027origin/master\u0027 into next\n\nManual merge of:\n\tarch/powerpc/kernel/asm-offsets.c\n" }, { "commit": "4096ed0fc7c6ed83da44ab27ab7d1c7cd6e8e175", "tree": "6b3df9d0c8d4ed057e3fd1057eafca5edb34205c", "parents": [ "43c16408842b0eeb367c23a6fa540ce69f99e347" ], "author": { "name": "Mats Erik Andersson", "email": "mats.andersson@gisladisker.se", "time": "Tue May 12 12:05:23 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 11 12:04:22 2009 -0700" }, "message": "PCI: expose SMBus on Asus notebook A6L\n\nAddition of one unknown subsystem identifier to the quirks handler for\nchipset i82855GM_HB on notebook Asus A6L. This exposes the otherwise\nhidden SMBus controller within the south bridge ICH4-M.\n\nSigned-off-by: Mats Erik Andersson \u003cmats.andersson@gisladisker.se\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "43c16408842b0eeb367c23a6fa540ce69f99e347", "tree": "25be054b280b430b8bb00ff5f9c1f422bc21a3a0", "parents": [ "f62795f1e892ca9269849fa83de97621da7e02c0" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Wed Apr 22 16:52:09 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 11 12:04:21 2009 -0700" }, "message": "PCI: Add support for turning PCIe ECRC on or off\n\nAdds support for PCI Express transaction layer end-to-end CRC checking\n(ECRC). This patch will enable/disable ECRC checking by setting/clearing\nthe ECRC Check Enable and/or ECRC Generation Enable bits for devices that\nsupport ECRC.\n\nThe ECRC setting is controlled by the \"pci\u003decrc\u003d\u003cpolicy\u003e\" command-line\noption. If this option is not set or is set to \u0027bios\", the enable and\ngeneration bits are left in whatever state that firmware/BIOS set them to.\nThe \"off\" setting turns them off, and the \"on\" option turns them on (if the\ndevice supports it).\n\nTurning ECRC on or off can be a data integrity versus performance\ntradeoff. In theory, turning it on will catch more data errors, turning\nit off means possibly better performance since CRC does not need to be\ncalculated by the PCIe hardware and packet sizes are reduced.\n\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" } ], "next": "f62795f1e892ca9269849fa83de97621da7e02c0" }