)]}' { "log": [ { "commit": "fbf92bea68830c12da9099d7c8a60812194efc4e", "tree": "110e2c2476ac98ae298b90881de1fd015ff33739", "parents": [ "ef3242859fae47e728b50b7ce3d17b201a71779a", "c2e0eb167070a6e9dcb49c84c13c79a30d672431" ], "author": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Thu Feb 24 12:19:43 2011 +1000" }, "committer": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Thu Feb 24 12:19:43 2011 +1000" }, "message": "Merge branch \u0027drm-intel-fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel into drm-fixes\n\n* \u0027drm-intel-fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel:\n drm/i915: fix corruptions on i8xx due to relaxed fencing\n drm/i915: skip FDI \u0026 PCH enabling for DP_A\n agp/intel: Experiment with a 855GM GWB bit\n drm/i915: don\u0027t enable FDI \u0026 transcoder interrupts after all\n drm/i915: Ignore a hung GPU when flushing the framebuffer prior to a switch\n" }, { "commit": "49495d44dfa4ba76cf7d1ed8fe84746dd9552255", "tree": "bce82f11cf9630f7774e051d557596f96fac225c", "parents": [ "45e4039c3aea597ede44a264cea322908cdedfe9" ], "author": { "name": "Florian Mickler", "email": "florian@mickler.org", "time": "Mon Feb 07 23:29:31 2011 +0100" }, "committer": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Wed Feb 23 18:29:17 2011 +1000" }, "message": "amd64-agp: fix crash at second module load\n\nThe module forgot to sometimes unregister some resources.\n\nThis fixes Bug #22882.\n\n[Patch updated to 2.6.38-rc3 by Randy Dunlap.]\nTested-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nSigned-off-by: Florian Mickler \u003cflorian@mickler.org\u003e\nSigned-off-by: Dave Airlie \u003cairlied@redhat.com\u003e\n" }, { "commit": "bdb8b975fc66e081c3f39be6267701f8226d11aa", "tree": "e4ff3068ea0844121372a3f88fa4d1f1a48edc35", "parents": [ "a36dbec57e9a665d69cd2e1a673153ddb2d62785" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Dec 22 11:37:09 2010 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Feb 22 15:52:41 2011 +0000" }, "message": "agp/intel: Experiment with a 855GM GWB bit\n\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id\u003d27187\nTested-by: Thorsten Vollmer \u003cthorsten@thvo.de\u003e (DFI-ACP G5M150-N w/852GME)\nTested-by: Moritz Brunner \u003c2points@gmx.org\u003e (Asus M2400N/i855GM)\nTested-by: Indan Zupancic \u003cindan@nul.nu\u003e (Thinkpad X40/855GM rev 02)\nTested-by: Eric Anholt \u003ceric@anholt.net\u003e (865G)\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "a70b95c017e8b518e1e069853355e4e497453dbb", "tree": "c4264dc861b449f83fc40d9fb942083c5d985870", "parents": [ "cecd1455bc9cbd9568036f502ee8ded0a64354a7" ], "author": { "name": "Stephen Kitt", "email": "steve@sk2.org", "time": "Mon Jan 31 14:25:43 2011 -0800" }, "committer": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Fri Feb 04 09:43:57 2011 +1000" }, "message": "agp: ensure GART has an address before enabling it\n\nSome BIOSs (eg. the AMI BIOS on the Asus P4P800 motherboard) don\u0027t\ninitialise the GART address, and pcibios_assign_resources() can ignore it\nbecause it can be marked as a host bridge (see\nhttps://bugzilla.kernel.org/show_bug.cgi?id\u003d24392#c5 for details). This\nwas handled correctly up to 2.6.35, but the pci_enable_device() cleanup in\n2.6.36 96576a9e1a0cdb8 (\"agp: intel-agp: do not use PCI resources before\npci_enable_device()\") means that the kernel tries to enable the GART\nbefore assigning it an address; in such cases the GART overlaps with other\ndevice assignments and ends up being disabled.\n\nThis patch fixes https://bugzilla.kernel.org/show_bug.cgi?id\u003d24392\n\nNote that I imagine efficeon-agp.c probably has the same problem, but\nI can\u0027t test that and I\u0027d like to make sure this patch is suitable for\n-stable (since 2.6.36 and 2.6.37 are affected).\n\nSigned-off-by: Stephen Kitt \u003csteve@sk2.org\u003e\nCc: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nCc: Maciej Rutecki \u003cmaciej.rutecki@gmail.com\u003e\nCc: \"Rafael J. Wysocki\" \u003crjw@sisk.pl\u003e\nCc: Kulikov Vasiliy \u003csegooon@gmail.com\u003e\nCc: Florian Mickler \u003cflorian@mickler.org\u003e\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dave Airlie \u003cairlied@redhat.com\u003e\n" }, { "commit": "cecd1455bc9cbd9568036f502ee8ded0a64354a7", "tree": "213995f8c44b3cb854e95123297c5c3b381123ad", "parents": [ "4b863b3d3e9b11bb7588b88d13faed75f7711d09" ], "author": { "name": "Matt Turner", "email": "mattst88@gmail.com", "time": "Tue Feb 01 11:54:15 2011 -0500" }, "committer": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Fri Feb 04 09:42:25 2011 +1000" }, "message": "Revert \"agp: AMD AGP is used on UP1100 \u0026 UP1500 alpha boxen\"\n\nThis reverts commit f191f144079b0083c6fa7d01a4acbd7263fb5032.\n\nThe AMD 751 and 761 chipsets are used on the UP1000, UP1100, and UP1500\nOEM motherboards, but they neglect to do anything to make AGP work.\n\nAccording to Ivan Kokshaysky:\nThere is quite fundamental conflict between the Alpha architecture and\nx86 AGP implementation - Alpha is entirely cache coherent by design,\nwhile x86 AGP is not (I mean native AGP DMA transactions, not a PCI over\nAGP). There are no such things as non-cacheable mappings or software\nsupport for cache flushing/invalidation on Alpha, so x86 AGP code won\u0027t\nwork on Nautilus.\n\nSo there\u0027s no point in allowing this driver to be configured on Alpha.\n\nSigned-off-by: Matt Turner \u003cmattst88@gmail.com\u003e\nSigned-off-by: Dave Airlie \u003cairlied@redhat.com\u003e\n" }, { "commit": "4b863b3d3e9b11bb7588b88d13faed75f7711d09", "tree": "c5bae6bda0f2b494cba416224018c5cf37b724f0", "parents": [ "18ff84da29b3f0c073e0ce6e341663cc6bcb0ab7" ], "author": { "name": "Matt Turner", "email": "mattst88@gmail.com", "time": "Tue Feb 01 11:54:16 2011 -0500" }, "committer": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Fri Feb 04 09:42:24 2011 +1000" }, "message": "amd-k7-agp: remove non-x86 code\n\namd-k7-agp can\u0027t be built on Alpha anymore, so remove now unnecessary\ncode.\n\nSigned-off-by: Matt Turner \u003cmattst88@gmail.com\u003e\nSigned-off-by: Dave Airlie \u003cairlied@redhat.com\u003e\n" }, { "commit": "bee4a186c16bed0d7e91425ca9356c2e8c015f8d", "tree": "66d01e18c48fb0dfd9970c169d0f5baa0adaa0fe", "parents": [ "934f992c763ae1e5eefcce8af769c16444085df7" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Fri Jan 21 10:54:32 2011 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Mon Jan 24 18:26:25 2011 +0000" }, "message": "drm/i915,agp/intel: Do not clear stolen entries\n\nWe can only utilize the stolen portion of the GTT if we are in sole\ncharge of the hardware. This is only true if using GEM and KMS,\notherwise VESA continues to access stolen memory.\n\nReported-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nReported-by: Frederic Weisbecker \u003cfweisbec@gmail.com\u003e\nTested-by: Jiri Olsa \u003cjolsa@redhat.com\u003e\nTested-by: Frederic Weisbecker \u003cfweisbec@gmail.com\u003e\nCc: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "53371edaef692bef7eee8070bd680401ccf65706", "tree": "a3169f2beded4d250a19e674ea5ec46b5c29cd61", "parents": [ "1591192d3a17adeebd03be0ce5888b88bddfaf89" ], "author": { "name": "Oswald Buddenhagen", "email": "ossi@kde.org", "time": "Sat Jun 19 23:08:37 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Fri Jan 14 16:36:19 2011 +0000" }, "message": "agp/intel: Fix device names of i845 and 845G\n\nThey got mixed up when the switch was converted to a table in 2007.\n\nSigned-off-by: Oswald Buddenhagen \u003cossi@kde.org\u003e\n[ickle: minor changes for 2.6.37+]\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "d15eda5c6edff4987af6f4423af0bab0c3251e74", "tree": "87400cdc5f74d1258b6456b88beaf6fc3dc5f97a", "parents": [ "a46f3108b1cd8bf11d46ac8a5f30df6f6dbdf738" ], "author": { "name": "Dave Airlie", "email": "airlied@gmail.com", "time": "Wed Jan 12 11:39:48 2011 +1000" }, "committer": { "name": "Dave Airlie", "email": "airlied@gmail.com", "time": "Wed Jan 12 11:39:48 2011 +1000" }, "message": "i915/gtt: fix ordering causing DMAR errors on object teardown.\n\nPrevious to the last GTT rework we always rewrote the GTT then unmapped the\nobject, somehow this got reversed in the rework in 2.6.37-rc5 timeframe.\n\nThis fix needs to go to stable in an alternate form since the code changed.\n\nThis fixes DMAR reports on my Ironlake HP2540p.\n\nSigned-off-by: Dave Airlie \u003cairlied@redhat.com\u003e\n" }, { "commit": "a46f3108b1cd8bf11d46ac8a5f30df6f6dbdf738", "tree": "49d7731e7c1250f28a44aa8d3e62c43292e4bef3", "parents": [ "784fe39fa80d557847baeca2695915d17b09827f" ], "author": { "name": "Dave Airlie", "email": "airlied@gmail.com", "time": "Wed Jan 12 11:38:37 2011 +1000" }, "committer": { "name": "Dave Airlie", "email": "airlied@gmail.com", "time": "Wed Jan 12 11:38:37 2011 +1000" }, "message": "i915/gtt: fix ordering issues with status setup and DMAR\n\nThis code was setting up the status page before setting the DMAR-is-on-bit,\nso we were getting DMAR errors on the status page. Reverse the two bits\nof init code to the correct result.\n\nSigned-off-by: Dave Airlie \u003cairlied@redhat.com\u003e\n" }, { "commit": "c97689d8860f086125e7ff9cd730027a0057ca4f", "tree": "019ab7330af6c975ffba0d7016e0ed6243fbf6b0", "parents": [ "55249baaa5cd188ebd9acdb047eeaed8092e4a93" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Thu Dec 23 10:40:38 2010 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Jan 11 20:35:41 2011 +0000" }, "message": "agp/intel: Flush the chipset write buffers when changing GTT base\n\nFlush the chipset write buffers before and after adjusting the GTT base\nregister, just in case. We only modify this value upon initialisation\n(boot and resume) so there should be no outstanding writes, however\nthere are always those persistent PGTBL_ER that keep getting reported\nupon resume.\n\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "5b2eef966cb2ae307aa4ef1767f7307774bc96ca", "tree": "095a251e145903598dd8d90d5b2eb880f0d6ff93", "parents": [ "8adbf8d46718a8f110de55ec82c40d04d0c362cc", "56bec7c009872ef33fe452ea75fecba481351b44" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jan 10 17:11:39 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jan 10 17:11:39 2011 -0800" }, "message": "Merge branch \u0027drm-core-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6\n\n* \u0027drm-core-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (390 commits)\n drm/radeon/kms: disable underscan by default\n drm/radeon/kms: only enable hdmi features if the monitor supports audio\n drm: Restore the old_fb upon modeset failure\n drm/nouveau: fix hwmon device binding\n radeon: consolidate asic-specific function decls for pre-r600\n vga_switcheroo: comparing too few characters in strncmp()\n drm/radeon/kms: add NI pci ids\n drm/radeon/kms: don\u0027t enable pcie gen2 on NI yet\n drm/radeon/kms: add radeon_asic struct for NI asics\n drm/radeon/kms/ni: load default sclk/mclk/vddc at pm init\n drm/radeon/kms: add ucode loader for NI\n drm/radeon/kms: add support for DCE5 display LUTs\n drm/radeon/kms: add ni_reg.h\n drm/radeon/kms: add bo blit support for NI\n drm/radeon/kms: always use writeback/events for fences on NI\n drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5\n drm/radeon/kms: add backend map workaround for barts\n drm/radeon/kms: fill gpu init for NI asics\n drm/radeon/kms: add disabled vbios accessor for NI asics\n drm/radeon/kms: handle NI thermal controller\n ...\n" }, { "commit": "42cbd8efb0746b55112de45173219f76c54390da", "tree": "3be21847ac861d36897bbb41de9478ddf5142c4d", "parents": [ "dda5f0a372873bca5f0b1d1866d7784dffd8b675", "f658bcfb2607bf0808966a69cf74135ce98e5c2d" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 06 10:50:28 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 06 10:50:28 2011 -0800" }, "message": "Merge branch \u0027x86-amd-nb-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-amd-nb-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n x86, cacheinfo: Cleanup L3 cache index disable support\n x86, amd-nb: Cleanup AMD northbridge caching code\n x86, amd-nb: Complete the rename of AMD NB and related code\n" }, { "commit": "9097eef024db4f1850015e837a84aca0aa40a288", "tree": "0d2cf4b9ca5e1e58aa38c1225338925e675c4a02", "parents": [ "b13c2b96bf15b9dd0f1a45fd788f3a3025c5aec6", "71f4566084eb592fe545f05f7dff41fa9aa42e0b" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Dec 14 11:34:51 2010 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Dec 14 11:34:51 2010 +0000" }, "message": "Merge branch \u0027drm-intel-fixes\u0027 into drm-intel-next\n" }, { "commit": "71f4566084eb592fe545f05f7dff41fa9aa42e0b", "tree": "0fc813df2af7ebda8dea06b6d954eb4cc5bbccfa", "parents": [ "63abf3edaf42d0b9f278df90fe41c7ed4796b6b1" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Dec 14 11:29:23 2010 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Dec 14 11:29:23 2010 +0000" }, "message": "agp/intel: Fix missed cached memory flags setting in i965_write_entry()\n\nThis fixes regression from a6963596a13e62f8e65b1cf3403a330ff2db407c,\nthat missed to set cached memory type in GTT entry.\n\nSigned-off-by: Zhenyu Wang \u003czhenyuw@linux.intel.com\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "5aa7d52aebfc11760bbc5b081ed621227bb77981", "tree": "1bb2542ff9f8f58599325a68f3861f80be27bf26", "parents": [ "382ab78c0e4866eb9a812e9ba20d0f876d9634d6", "bbf0c6b3620b3872929ef7d3c392ce436889110f" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Sun Dec 05 10:43:39 2010 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Sun Dec 05 10:43:39 2010 +0000" }, "message": "Merge branch \u0027drm-intel-fixes\u0027 into drm-intel-next\n\nImmediate merge for the conflicting introduction of HAS_COHERENT_RINGS.\n\nConflicts:\n\tdrivers/gpu/drm/i915/i915_dma.c\n\tinclude/drm/i915_drm.h\n" }, { "commit": "136711be41ec97f7f1a9c3a5e8535eb7da5fea59", "tree": "3be7da8694869adbb894f02b9edc1eab298c77da", "parents": [ "49078f7d108f132582e5af46304c317b55f83948" ], "author": { "name": "Takashi Iwai", "email": "tiwai@suse.de", "time": "Sat Dec 04 16:13:06 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Sun Dec 05 10:40:17 2010 +0000" }, "message": "agp/intel: Fix wrong kunmap in i830_cleanup()\n\nAdd a missing NULL check and fix the wrong address passed to kunmap()\nin i830_cleanup().\n\nCc: stable@kernel.org\nSigned-off-by: Takashi Iwai \u003ctiwai@suse.de\u003e\n[danvet: added cc stable]\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\n\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "7bdc9ab00b1b0fdbb490f41c5c7c2fbc66fed9ee", "tree": "148ac9c6b4c4cb6cf59c948e95d39a16f6d6a62e", "parents": [ "92b88aeb1ad67417c002fdd77409771ca7e5433a" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 09 17:53:20 2010 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:19:13 2010 +0000" }, "message": "agp/intel: Remove duplicate const\n\ndrivers/char/agp/intel-gtt.c:340:48: warning: duplicate const\n\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "4080775b60cc26044e7c4aba5e76e5041b0d7004", "tree": "46ee73a35bb1c99ff7e075e1c9b441faad98dc94", "parents": [ "7c2e6fdf452cddeff6a8ee5156edba39e53246fc" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sat Nov 06 11:18:58 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:14:47 2010 +0000" }, "message": "intel-gtt: export api for drm/i915\n\nJust some minor shuffling to get rid of any agp traces in the\nexported functions.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "cb16b67b5cb33b7d6732e0c416d29d933eea13ce", "tree": "b9e9abd539aea42c86bbc5c44a17456291512ccb", "parents": [ "76aaf22016caa7764f40e792aaca7b4918312b22" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Nov 05 22:27:10 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:14:46 2010 +0000" }, "message": "agp: kill agp_rebind_memory\n\nIts only user, intel-gtt.c is now gone.\n\nCc: Dave Airlie \u003cairlied@gmail.com\u003e\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "76aaf22016caa7764f40e792aaca7b4918312b22", "tree": "88ba0e64ed5c970969df5d70f2ae01fe641d6722", "parents": [ "93a37f20eabeea4039130527b07453038c07f471" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Nov 05 22:23:30 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:14:46 2010 +0000" }, "message": "drm/i915: restore gtt on resume in the drm instead of in intel-gtt.ko\n\nThis still uses the agp functions to actually reinstate the mappings\n(with a gross hack to make agp cooperate), but it wires everything\nup correctly for the switchover.\n\nThe call to agp_rebind_memory can be dropped because all non-kms drivers\ndo all their rebinding on EnterVT.\n\nv2: Be more paranoid and flush the chipset cache after restoring gtt\nmappings.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "f050a8abbda0efcd597c6b1825e3b9ce4d613383", "tree": "61421f0a7355f12babff81fb25c68470f4980f82", "parents": [ "4af72e2865a23ac090884a421bd1a8b19e247a22" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Nov 05 18:40:56 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:14:45 2010 +0000" }, "message": "agp: kill agp_flush_chipset and corresponding ioctl\n\nThe intel drm calls the chipset functions now directly. Userspace\nnever called the corresponding ioctl, hence it can be killed, too.\n\nCc: Dave Airlie \u003cairlied@gmail.com\u003e\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "40ce6575102b23e432932b5ce41c44bf7cc5023b", "tree": "c14bb9bf62a83e35f81d0aaef55536c324bdbb3b", "parents": [ "23ed992a5ebe6964ebe312b54142fbc5e8185cdc" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Nov 05 18:12:18 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:14:44 2010 +0000" }, "message": "drm/i915/gtt: call chipset flush directly\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "23ed992a5ebe6964ebe312b54142fbc5e8185cdc", "tree": "c8ee2fa6f6a51fb1d0b43f19ec15dcc482b914ef", "parents": [ "ff26860fb53f2dcfaaaf1bf017b09dbdfddff5ee" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Nov 05 18:04:52 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:14:43 2010 +0000" }, "message": "drm/i915|intel-gtt: consolidate intel-gtt.h headers\n\n... and a few other defines.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "ff26860fb53f2dcfaaaf1bf017b09dbdfddff5ee", "tree": "2e441a68f636f52f9c158febe23766e6841d1a75", "parents": [ "820647b97a9cbdd976c7177f1b6047fc1f6dd5c0" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Nov 05 15:43:35 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:14:43 2010 +0000" }, "message": "intel-gtt: fold i81x-only dcache support into the generic driver\n\nNow the intel-gtt.c rewrite is complete!\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "820647b97a9cbdd976c7177f1b6047fc1f6dd5c0", "tree": "4d0ec4a52ac3daff3cf797b3578326bb2b27954f", "parents": [ "625dd9d331d8a1ce5ee4e9924a22f3e55b7ac615" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Nov 05 13:30:14 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:14:42 2010 +0000" }, "message": "intel-gtt: switch i81x to the common initialization helpers\n\nStill a separate agp_bridge_driver because of the i81x-only\ndedicated vram support.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "625dd9d331d8a1ce5ee4e9924a22f3e55b7ac615", "tree": "bad37f7ecc7ef90134ea4eb9e51e788a946a654f", "parents": [ "24a6b387af7cd5d1e0e5d15b15104644a5105de7" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Thu Nov 04 20:07:57 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:14:42 2010 +0000" }, "message": "intel-gtt: switch i81x to the write_entry helpers\n\nInitialization is still done with the old code with a few\nadded things sprinkled in to make the intel_fake_agp helper\nfunctions work.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "24a6b387af7cd5d1e0e5d15b15104644a5105de7", "tree": "d8b6af7385d0667fb3469eb454217eb35dd8f50f", "parents": [ "b47cf66f315a258c458ed4345c443dba396fb787" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Thu Nov 04 20:14:15 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:14:42 2010 +0000" }, "message": "intel-gtt: kill unneeded sandybridge memory types\n\nUsed for the now dead agp type_to_mask stuff.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "b47cf66f315a258c458ed4345c443dba396fb787", "tree": "1b602d3c6711e5e04922ce2d348003ff4c323cdf", "parents": [ "e384eafc1c2f4f10155fe25324afe51129ec3e6a" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Thu Nov 04 18:41:50 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 20:14:41 2010 +0000" }, "message": "intel-gtt: drop dcache support for i830 and later\n\ni830_check_flags already disallows it, so no need to implement it\nin the write_entry function. Seems to be a remnant from i810 support.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "c64f7ba5f1006d8c20eacafecf98d4d00a6902a0", "tree": "0309e263e05be06e718d6a07169802ac026aef68", "parents": [ "1b6064d79b9a1c5e5aa6fcc6855f3da5e639ff73" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 14:24:24 2010 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 15:43:18 2010 +0000" }, "message": "agp/intel: Remove confusion of stolen entries not stolen memory\n\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "1b6064d79b9a1c5e5aa6fcc6855f3da5e639ff73", "tree": "948c4ed0770504cb80482333fa708823eddc88f0", "parents": [ "fe669bf88e9108b96a847385df08c9b1e98c1420" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 12:33:54 2010 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 23 15:42:59 2010 +0000" }, "message": "agp/intel: Remove the artificial cap on stolen size\n\nNow that the stolen memory does not also steal entries from the GTT, we\ncan use all the memory the BIOS set aside for the GPU.\n\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "e624ae8e0d4243e71daedce7570e91290438eaca", "tree": "e2b9804379a6aab3d2471898d257fe5590feb70c", "parents": [ "c4a1d9e4dc5d5313cfec2cc0c9d630efe8a6f287", "4ab0fbd3a29067e1540f05093ae4ed07645d18c8" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Mon Nov 22 08:51:36 2010 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Mon Nov 22 08:51:36 2010 +0000" }, "message": "Merge branch \u0027drm-intel-fixes\u0027 into drm-intel-next\n\nConflicts:\n\tdrivers/gpu/drm/i915/i915_gem.c\n" }, { "commit": "9653a5c76c8677b05b45b3b999d3b39988d2a064", "tree": "9224748c69296fc6ac50beae72f20e6e2ae16aca", "parents": [ "eec1d4fa00c6552ae2fdf71d59f1eded7c88dd89" ], "author": { "name": "Hans Rosenfeld", "email": "hans.rosenfeld@amd.com", "time": "Fri Oct 29 17:14:31 2010 +0200" }, "committer": { "name": "Borislav Petkov", "email": "borislav.petkov@amd.com", "time": "Thu Nov 18 15:53:05 2010 +0100" }, "message": "x86, amd-nb: Cleanup AMD northbridge caching code\n\nSupport more than just the \"Misc Control\" part of the northbridges.\nSupport more flags by turning \"gart_supported\" into a single bit flag\nthat is stored in a flags member. Clean up related code by using a set\nof functions (amd_nb_num(), amd_nb_has_feature() and node_to_amd_nb())\ninstead of accessing the NB data structures directly. Reorder the\ninitialization code and put the GART flush words caching in a separate\nfunction.\n\nSigned-off-by: Hans Rosenfeld \u003chans.rosenfeld@amd.com\u003e\nSigned-off-by: Borislav Petkov \u003cborislav.petkov@amd.com\u003e\n" }, { "commit": "eec1d4fa00c6552ae2fdf71d59f1eded7c88dd89", "tree": "ee2c918694e1a01e0826e98c89b703916488bedd", "parents": [ "e53beacd23d9cb47590da6a7a7f6d417b941a994" ], "author": { "name": "Hans Rosenfeld", "email": "hans.rosenfeld@amd.com", "time": "Fri Oct 29 17:14:30 2010 +0200" }, "committer": { "name": "Borislav Petkov", "email": "borislav.petkov@amd.com", "time": "Thu Nov 18 15:53:04 2010 +0100" }, "message": "x86, amd-nb: Complete the rename of AMD NB and related code\n\nNot only the naming of the files was confusing, it was even more so for\nthe function and variable names.\n\nRenamed the K8 NB and NUMA stuff that is also used on other AMD\nplatforms. This also renames the CONFIG_K8_NUMA option to\nCONFIG_AMD_NUMA and the related file k8topology_64.c to\namdtopology_64.c. No functional changes intended.\n\nSigned-off-by: Hans Rosenfeld \u003chans.rosenfeld@amd.com\u003e\nSigned-off-by: Borislav Petkov \u003cborislav.petkov@amd.com\u003e\n" }, { "commit": "451a3c24b0135bce54542009b5fde43846c7cf67", "tree": "f0fbbcc155aef2a1ffcb8aa593fe7a966d0e6900", "parents": [ "55f6561c6941713ab5ae9180525b026dd40b7d14" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Wed Nov 17 16:26:55 2010 +0100" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Nov 17 08:59:32 2010 -0800" }, "message": "BKL: remove extraneous #include \u003csmp_lock.h\u003e\n\nThe big kernel lock has been removed from all these files at some point,\nleaving only the #include.\n\nRemove this too as a cleanup.\n\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "c94f28c383f58c9de74678e0f1624db9c5f8a8cb", "tree": "3281184f026cb79cee6c20fe29c994ba654cbbe4", "parents": [ "df15315899c0641412bd54b29565a70b078a6ac8", "1bb95834bbcdc969e477a9284cf96c17a4c2616f" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Mon Nov 15 06:49:30 2010 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Mon Nov 15 06:49:30 2010 +0000" }, "message": "Merge branch \u0027drm-intel-fixes\u0027 into drm-intel-next\n\nConflicts:\n\tdrivers/gpu/drm/i915/i915_gem.c\n\tdrivers/gpu/drm/i915/intel_ringbuffer.c\n" }, { "commit": "91839fd577abc5fb39fb2238e05e847c70c9dec3", "tree": "86238c628c368aab28e96d61de99b7d739eec1ff", "parents": [ "a7bcf21e60c73cb7f7c13fad928967d7e47c3cac", "3f8ff0e72d75fdbe7f2cba2c4015fd9fdd9e13fd" ], "author": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Tue Nov 09 13:26:13 2010 +1000" }, "committer": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Tue Nov 09 13:26:13 2010 +1000" }, "message": "Merge branch \u0027drm-intel-fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel\n\n* \u0027drm-intel-fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel:\n drm/i915: Fix LVDS fixed-mode regression from 219adae1\n drm/i915/ringbuffer: Use the HEAD auto-reporting mechanism\n drm/i915: Avoid might_fault during pwrite whilst holding our mutex\n agp/intel: fix cache control for sandybridge\n agp/intel: restore cache behavior on sandybridge\n drm/i915; Don\u0027t apply Ironlake FDI clock workaround to Sandybridge\n drm/i915: Fix KMS regression on Sandybridge/CPT\n i915: reprogram power monitoring registers on resume\n drm/i915: SNB BLT workaround\n drm/i915: Fix the graphics frequency clamping at init and when IPS is active.\n drm/i915: Allow powersave modparam to be adjusted at runtime.\n drm/i915: Apply big hammer to serialise buffer access between rings\n drm/i915: opregion_setup: iounmap correct address\n drm/i915: Flush read-only buffers from the active list upon idle as well\n i915: signedness bug in check_overlay_src()\n drm/i915: Fix typo from \"Enable DisplayPort Audio\"\n" }, { "commit": "16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c", "tree": "8a4d083794272b7d7bf82aad75076a7722164b23", "parents": [ "8d0f56708292ca5c256ee3b7187d124afee81d93" ], "author": { "name": "Zhenyu Wang", "email": "zhenyuw@linux.intel.com", "time": "Tue Nov 02 17:30:46 2010 +0800" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Thu Nov 04 09:39:50 2010 +0000" }, "message": "agp/intel: fix cache control for sandybridge\n\nThis is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.\nLet\u0027s set the correct bit for LLC+MLC and LLC only.\n\nSigned-off-by: Zhenyu Wang \u003czhenyuw@linux.intel.com\u003e\nCc: stable@kernel.org\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "8d0f56708292ca5c256ee3b7187d124afee81d93", "tree": "408b76c17505b7607eb0ef7a075c504239e7931f", "parents": [ "e07ac3a0b17ed9dec26b742ea41514063ef12386" ], "author": { "name": "Zhenyu Wang", "email": "zhenyuw@linux.intel.com", "time": "Tue Nov 02 17:30:47 2010 +0800" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Thu Nov 04 09:39:28 2010 +0000" }, "message": "agp/intel: restore cache behavior on sandybridge\n\nThis restores cache behavior for default AGP_USER_MEMORY as\nuncached, and leave default AGP_USER_CACHED_MEMORY as LLC only.\nI\u0027ve seen different cache behavior on one sandybridge desktop CPU vs.\nanother mobile CPU. Until we figure out how to detect the real cache\nconfig, restore back to the original behavior now.\n\nSigned-off-by: Zhenyu Wang \u003czhenyuw@linux.intel.com\u003e\nCc: stable@kernel.org\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "897ef192514a6b0fc10a0ce3fe7e7aa0de09bc52", "tree": "bfa709ceb59f7afaebfa64e057a782e0f99d59a4", "parents": [ "d110852513148a7ec44fad4e036455aeb816d713" ], "author": { "name": "Zhenyu Wang", "email": "zhenyuw@linux.intel.com", "time": "Tue Nov 02 17:30:47 2010 +0800" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 02 10:05:47 2010 +0000" }, "message": "agp/intel: restore cache behavior on sandybridge\n\nThis restores cache behavior for default AGP_USER_MEMORY as\nuncached, and leave default AGP_USER_CACHED_MEMORY as LLC only.\nI\u0027ve seen different cache behavior on one sandybridge desktop CPU vs.\nanother mobile CPU. Until we figure out how to detect the real cache\nconfig, restore back to the original behavior now.\n\nSigned-off-by: Zhenyu Wang \u003czhenyuw@linux.intel.com\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "d110852513148a7ec44fad4e036455aeb816d713", "tree": "5c72fa12fa653804a4d13658a641a713d6849acd", "parents": [ "328fc1325f144027f4a8269b11e9f8dcf1edcb97" ], "author": { "name": "Zhenyu Wang", "email": "zhenyuw@linux.intel.com", "time": "Tue Nov 02 17:30:46 2010 +0800" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Nov 02 10:05:46 2010 +0000" }, "message": "agp/intel: fix cache control for sandybridge\n\nThis is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.\nLet\u0027s set the correct bit for LLC+MLC and LLC only.\n\nSigned-off-by: Zhenyu Wang \u003czhenyuw@linux.intel.com\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "100519e2f1c20286158746f92f27c3aa14f5a893", "tree": "55f05ba1ebda006c438321bb4b7b5e23d2bca2a5", "parents": [ "5eac3ab45955b32f3a9d89e633918c4d6f133dfa" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Sun Oct 31 10:37:02 2010 +0000" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Sun Oct 31 12:31:31 2010 +0000" }, "message": "agp/intel: the GMCH is always enabled for integrated processor graphics\n\n... and trying to set the bit is ineffectual.\n\nFixes the regression from e380f60 which detected that we were trying to\ndo undefined operations on the I830_GMCH_CTRL.\n\nReported-by: Alexey Fisher \u003cbug-track@fisher-privat.net\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "e380f60b22eddec7825224b8d788572c82b63161", "tree": "731ca9b67c0c8cc506924af26f61cf21405c364d", "parents": [ "c584fe47e4d92934c10e5d7f932ee042587dbcff" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Fri Oct 29 18:11:26 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Fri Oct 29 20:30:44 2010 +0100" }, "message": "agp/intel: Sandybridge doesn\u0027t require GMCH enabling\n\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "6a915c2bf073743dd31229f1ec2eaa7a2b13c1c3", "tree": "9e6d1497c53a3c111842c7d8864a19f19cf0c88a", "parents": [ "18cb657ca1bafe635f368346a1676fb04c512edf" ], "author": { "name": "Kyle McMartin", "email": "kyle@mcmartin.ca", "time": "Fri Oct 29 12:48:01 2010 -0400" }, "committer": { "name": "Kyle McMartin", "email": "kyle@mcmartin.ca", "time": "Fri Oct 29 13:26:48 2010 -0400" }, "message": "parisc-agp: fix missing slab.h include\n\nCommit 338e4fab added a missing kfree if the alloc_pci_dev failed\nbut forgot to include \u003clinux/slab.h\u003e for the definition of\nkfree.\n\nSigned-off-by: Kyle McMartin \u003ckyle@redhat.com\u003e\n" }, { "commit": "e430426654c6a99fb1977bae71d4844e876c4a52", "tree": "65a22a59321b6bed5579c2e58371eeb373e1db61", "parents": [ "e732ff707743e5ceba6ae2bfc7e799a0bac30ffa", "650a35f868f809aade56ef960d8a465f57ac74e2" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Oct 28 09:24:14 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Oct 28 09:24:14 2010 -0700" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/kyle/parisc-2.6\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/kyle/parisc-2.6:\n parisc: add tty driver to PDC console\n drivers/parisc/iosapic.c: Remove unnecessary kzalloc cast\n parisc: remove homegrown L1_CACHE_ALIGN macro\n arch/parisc: Removing undead ifdef CONFIG_PA20\n parisc: unwind - optimise linked-list searches for modules\n parisc: change to new flag variable\n drivers/char/agp/parisc-agp.c: eliminate memory leak\n parisc: kill __do_IRQ\n parisc: convert eisa interrupts to flow handlers\n parisc: convert gsc and dino pci interrupts to flow handlers\n parisc: convert suckyio interrupts to flow handlers\n parisc: convert iosapic interrupts to proper flow handlers\n parisc: convert cpu interrupts to proper flow handlers\n parisc: lay groundwork for killing __do_IRQ\n parisc: add prlimit64 syscall\n parisc: squelch warning when using dev_get_stats\n" }, { "commit": "201728429d6cf336cfd7483fcd1bce47291b2901", "tree": "162c9084104373fd587347f5b7b2e20951430d98", "parents": [ "b3eafc5af02a799650757f2c5b2b0d4835dd0a5f" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Sep 24 18:25:59 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Oct 27 23:31:07 2010 +0100" }, "message": "intel-gtt: maximize ggtt size on platforms that support this\n\nOn VT-d supporting platforms the GGTT is allocated in a stolen mem\nsection separate from graphcis stolen mem. The GMCH register contains\na bitfield specifying the size of that region. Docs suggest that this\nregion can only be used for GGTT and PPGTT. Hence ensure that the\nPPGTT is disabled and use the complete area for the GGTT.\n\nUnfortunately the graphics core on G33/Pineview can\u0027t cope with really\nlarge GTTs and the BIOS usually enables the maximum of 512MB. So\ndon\u0027t bother with maximizing the GTT on these platforms.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "b3eafc5af02a799650757f2c5b2b0d4835dd0a5f", "tree": "c20558a017505974e4ef26437af480d1ff04fb21", "parents": [ "53984635a659e360f206a81ada4ae813152d72f1" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Thu Sep 23 20:04:17 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Oct 27 23:31:06 2010 +0100" }, "message": "intel-gtt: save PGETBL_CTL later in the setup process\n\n... and switch to a more classical store-reg-on-suspend, restore-on-resume\nway of doing things. Obviously this is just preparation for the future,\nthe code is not there at all, yet.\n\nThis is needed because the next patch adjusts this register and everything\nin it (not just the pagetable address) needs to be restored on resume.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "c48c43e422c1404fd72c57d1d21a6f6d01e18900", "tree": "48e5d3828b4f5479361986535f71a1ae44e4f3c1", "parents": [ "520045db940a381d2bee1c1b2179f7921b40fb10", "135cba0dc399fdd47bd3ae305c1db75fcd77243f" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Oct 26 18:57:59 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Oct 26 18:57:59 2010 -0700" }, "message": "Merge branch \u0027drm-core-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6\n\n* \u0027drm-core-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (476 commits)\n vmwgfx: Implement a proper GMR eviction mechanism\n drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2\n drm/radeon/kms: properly compute group_size on 6xx/7xx\n drm/radeon/kms: fix 2D tile height alignment in the r600 CS checker\n drm/radeon/kms/evergreen: set the clear state to the blit state\n drm/radeon/kms: don\u0027t poll dac load detect.\n gpu: Add Intel GMA500(Poulsbo) Stub Driver\n drm/radeon/kms: MC vram map needs to be \u003e\u003d pci aperture size\n drm/radeon/kms: implement display watermark support for evergreen\n drm/radeon/kms/evergreen: add some additional safe regs v2\n drm/radeon/r600: fix tiling issues in CS checker.\n drm/i915: Move gpu_write_list to per-ring\n drm/i915: Invalidate the to-ring, flush the old-ring when updating domains\n drm/i915/ringbuffer: Write the value passed in to the tail register\n agp/intel: Restore valid PTE bit for Sandybridge after bdd3072\n drm/i915: Fix flushing regression from 9af90d19f\n drm/i915/sdvo: Remove unused encoding member\n i915: enable AVI infoframe for intel_hdmi.c [v4]\n drm/i915: Fix current fb blocking for page flip\n drm/i915: IS_IRONLAKE is synonymous with gen \u003d\u003d 5\n ...\n\nFix up conflicts in\n - drivers/gpu/drm/i915/{i915_gem.c, i915/intel_overlay.c}: due to the\n new simplified stack-based kmap_atomic() interface\n - drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: added .llseek entry due to BKL\n removal cleanups.\n" }, { "commit": "229aebb873e29726b91e076161649cf45154b0bf", "tree": "acc02a3702215bce8d914f4c8cc3d7a1382b1c67", "parents": [ "8de547e1824437f3c6af180d3ed2162fa4b3f389", "50a23e6eec6f20d55a3a920e47adb455bff6046e" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Oct 24 13:41:39 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Oct 24 13:41:39 2010 -0700" }, "message": "Merge branch \u0027for-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial\n\n* \u0027for-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (39 commits)\n Update broken web addresses in arch directory.\n Update broken web addresses in the kernel.\n Revert \"drivers/usb: Remove unnecessary return\u0027s from void functions\" for musb gadget\n Revert \"Fix typo: configuation \u003d\u003e configuration\" partially\n ida: document IDA_BITMAP_LONGS calculation\n ext2: fix a typo on comment in ext2/inode.c\n drivers/scsi: Remove unnecessary casts of private_data\n drivers/s390: Remove unnecessary casts of private_data\n net/sunrpc/rpc_pipe.c: Remove unnecessary casts of private_data\n drivers/infiniband: Remove unnecessary casts of private_data\n drivers/gpu/drm: Remove unnecessary casts of private_data\n kernel/pm_qos_params.c: Remove unnecessary casts of private_data\n fs/ecryptfs: Remove unnecessary casts of private_data\n fs/seq_file.c: Remove unnecessary casts of private_data\n arm: uengine.c: remove C99 comments\n arm: scoop.c: remove C99 comments\n Fix typo configue \u003d\u003e configure in comments\n Fix typo: configuation \u003d\u003e configuration\n Fix typo interrest[ing|ed] \u003d\u003e interest[ing|ed]\n Fix various typos of valid in comments\n ...\n\nFix up trivial conflicts in:\n\tdrivers/char/ipmi/ipmi_si_intf.c\n\tdrivers/usb/gadget/rndis.c\n\tnet/irda/irnet/irnet_ppp.c\n" }, { "commit": "85ccc35b7e4a5e7894570fe9b4e4b56d82fc3181", "tree": "e0fdb8cf1c837c9f9365e385346d353ca0cc80d5", "parents": [ "878a3c37d36142a192bdf5b6bfcf920832f431d7" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Fri Oct 22 14:59:29 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Fri Oct 22 15:04:09 2010 +0100" }, "message": "agp/intel: Restore valid PTE bit for Sandybridge after bdd3072\n\nIn cleaning up the mask functions in bdd3072, the setting of the PTE\nvalid bit was dropped for Sandybridge.\n\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "338e4fab3d41aa14264e10ce505a7c908633cdad", "tree": "66f754dfe6995eb9456c685143aa0ffc65b1735d", "parents": [ "7da1272547ebe96982a42292dfc833457708f4da" ], "author": { "name": "Julia Lawall", "email": "julia@diku.dk", "time": "Wed Oct 20 15:55:45 2010 -0700" }, "committer": { "name": "Kyle McMartin", "email": "kyle@mcmartin.ca", "time": "Thu Oct 21 21:03:47 2010 -0400" }, "message": "drivers/char/agp/parisc-agp.c: eliminate memory leak\n\nalloc_pci_dev allocates some memory, so that memory should be freed before\nleaving the function in an error case.\n\nA simplified version of the semantic match that finds this problem is:\n(http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@r exists@\nlocal idexpression x;\nexpression E;\nidentifier f1;\niterator I;\n@@\n\nx \u003d alloc_pci_dev(...);\n\u003c... when !\u003d x\n when !\u003d true (x \u003d\u003d NULL || ...)\n when !\u003d if (...) { \u003c+...x...+\u003e }\n when !\u003d I (...) { \u003c+...x...+\u003e }\n(\n x \u003d\u003d NULL\n|\n x \u003d\u003d E\n|\n x-\u003ef1\n)\n...\u003e\n* return ...;\n// \u003c/smpl\u003e\n\nSigned-off-by: Julia Lawall \u003cjulia@diku.dk\u003e\nDan Carpenter \u003cerror27@gmail.com\u003e\nDave Airlie \u003cairlied@linux.ie\u003e\nCc: Helge Deller \u003cdeller@gmx.de\u003e\nCc: \"James E.J. Bottomley\" \u003cjejb@parisc-linux.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Kyle McMartin \u003ckyle@redhat.com\u003e\n" }, { "commit": "2f0384e5fc4766ad909597547d0e2b716c036755", "tree": "bf965a4bee85fa09edec91772647fbc5aafa0fc4", "parents": [ "bc4016f48161454a9a8e5eb209b0693c6cde9f62", "5c80cc78de46aef6cd5e714208da05c3f7f548f8" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Oct 21 13:01:08 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Oct 21 13:01:08 2010 -0700" }, "message": "Merge branch \u0027x86-amd-nb-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-amd-nb-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n x86, amd_nb: Enable GART support for AMD family 0x15 CPUs\n x86, amd: Use compute unit information to determine thread siblings\n x86, amd: Extract compute unit information for AMD CPUs\n x86, amd: Add support for CPUID topology extension of AMD CPUs\n x86, nmi: Support NMI watchdog on newer AMD CPU families\n x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUs\n x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB\n x86, k8-gart: Decouple handling of garts and northbridges\n x86, cacheinfo: Fix dependency of AMD L3 CID\n x86, kvm: add new AMD SVM feature bits\n x86, cpu: Fix allowed CPUID bits for KVM guests\n x86, cpu: Update AMD CPUID feature bits\n x86, cpu: Fix renamed, not-yet-shipping AMD CPUID feature bit\n x86, AMD: Remove needless CPU family check (for L3 cache info)\n x86, tsc: Remove CPU frequency calibration on AMD\n" }, { "commit": "3dde04b0152634d42994b34b86bbf3c70fbc6b19", "tree": "9ceaacc72ae9958fc4567020a5eb19503af6b78c", "parents": [ "4f27b75d56334f33cbccff5da8372dc4aba122ba" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Thu Oct 14 16:30:41 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Oct 19 09:20:04 2010 +0100" }, "message": "agp/intel: Also add B43.1 to list of supported devices\n\nThis was a missing piece from 41a5142 that dropped recognition of the\nAGP module for the second B43 variant.\n\nReported-by: Stefan Bader \u003cstefan.bader@canonical.com\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\nCc: stable@kernel.org\n" }, { "commit": "f6086134d0b17b2c37f537a5429a919b3d2cced8", "tree": "05062712f62bb1ed8984889a104096fcef90622b", "parents": [ "965d38074e6eae71757a8baf9a348139e1e6894d" ], "author": { "name": "Francisco Jerez", "email": "currojerez@riseup.net", "time": "Sat Oct 16 00:45:15 2010 +0000" }, "committer": { "name": "Dave Airlie", "email": "airlied@redhat.com", "time": "Tue Oct 19 14:12:32 2010 +1000" }, "message": "agp/amd-k7: Allow binding user memory to the AGP GART.\n\nTTM-based DRM drivers need to be able to bind user memory to the AGP\naperture. This patch fixes the \"[TTM] AGP Bind memory failed.\" errors\nand the subsequent fallout seen with the nouveau driver.\n\nSigned-off-by: Francisco Jerez \u003ccurrojerez@riseup.net\u003e\nTested-by: Grzesiek Sójka \u003cpld@pfu.pl\u003e\nSigned-off-by: Dave Airlie \u003cairlied@redhat.com\u003e\n" }, { "commit": "631dd1a885b6d7e9f6f51b4e5b311c2bb04c323c", "tree": "c431fa3479c1d35842fb5635ed7ccd487d063a62", "parents": [ "d7eccbbae84b2ee7dbb756e60287c4b47071444e" ], "author": { "name": "Justin P. Mattock", "email": "justinmattock@gmail.com", "time": "Mon Oct 18 11:03:14 2010 +0200" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Mon Oct 18 11:03:14 2010 +0200" }, "message": "Update broken web addresses in the kernel.\n\nThe patch below updates broken web addresses in the kernel\n\nSigned-off-by: Justin P. Mattock \u003cjustinmattock@gmail.com\u003e\nCc: Maciej W. Rozycki \u003cmacro@linux-mips.org\u003e\nCc: Geert Uytterhoeven \u003cgeert@linux-m68k.org\u003e\nCc: Finn Thain \u003cfthain@telegraphics.com.au\u003e\nCc: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nCc: Matt Turner \u003cmattst88@gmail.com\u003e\nCc: Dimitry Torokhov \u003cdmitry.torokhov@gmail.com\u003e\nCc: Mike Frysinger \u003cvapier.adi@gmail.com\u003e\nAcked-by: Ben Pfaff \u003cblp@cs.stanford.edu\u003e\nAcked-by: Hans J. Koch \u003chjk@linutronix.de\u003e\nReviewed-by: Finn Thain \u003cfthain@telegraphics.com.au\u003e\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\n" }, { "commit": "3d8a1a6a8af910cc2da566080d111e062a124ba6", "tree": "0c78b30a5c7aa083e215222989f982313c5141c0", "parents": [ "1b13fe6a6e9986dbc079cbb05090be75edbffa5d", "5d0d71569e671239ae0d905ced9b65cd843f99ee" ], "author": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Wed Oct 13 15:44:24 2010 +0200" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Wed Oct 13 15:44:24 2010 +0200" }, "message": "Merge branch \u0027amd-iommu/2.6.37\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/joro/linux-2.6-iommu into core/iommu\n" }, { "commit": "e61cb0d5fd172ab95a4501917526382f25158e83", "tree": "5620faa45a505e54f61d26d34f8a4b69ad6ed80c", "parents": [ "5ceb0f9bb7bde101d8b07cb803002591dcb8c804" ], "author": { "name": "Jan Beulich", "email": "JBeulich@novell.com", "time": "Fri Sep 24 13:25:30 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Fri Sep 24 14:22:12 2010 +0100" }, "message": "some clean up to intel-gtt.c\n\nIn commit e517a5e97080bbe52857bd0d7df9b66602d53c4d the call to\nmap_page_into_agp() got removed from intel_i830_setup_flush(), but the\ncounterpart call from intel_i830_fini_flush() to unmap_page_from_agp()\nwas left in place.\n\nAdditionally, the page allocated here never gets its physical address\nused for sending to hardware, so there\u0027s no need to allocate it with\nGFP_DMA32. Nor is __GFP_ZERO really necessary, as the page is used\nonly to store data to force flushing of some internal processor state.\n\nSigned-off-by: Jan Beulich \u003cjbeulich@novell.com\u003e\nCc: Eric Anholt \u003ceric@anholt.net\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "ae83dd5c7d80e0f9063739a18e270da7207a91e3", "tree": "2d5e0f7538350998479957d16f4b735fa8a83a3a", "parents": [ "22533b494ff6a812b3e97248cc6c062858396182" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Sep 12 17:11:15 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:40:41 2010 +0100" }, "message": "intel-gtt add a cleanup function for chipset specific stuff\n\nThe old code didn\u0027t clean up the i830 chipset flush page. And it\nlooks nicer.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "22533b494ff6a812b3e97248cc6c062858396182", "tree": "5033e66110618dedbcdc6ff7cd3beab582c92984", "parents": [ "0af9e92e779602bdd6d4d19acf63b4802fab91b6" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Sep 12 16:38:55 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:40:28 2010 +0100" }, "message": "intel-gtt: store the dma mask size in intel_gtt_driver\n\nStoring this explicitly makes for clearer code and hopefully\nless further confusion.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "0af9e92e779602bdd6d4d19acf63b4802fab91b6", "tree": "d508f1db16ab519bc197f9691427455963562cfc", "parents": [ "aaa62591199162e6496b4f47cac4f5923bc571d1" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Sep 12 14:04:03 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:40:06 2010 +0100" }, "message": "intel-gtt: clean up gtt size reporting\n\nConsolidate everything in intel-gtt.c and also kill the export\nof intel_max_stolen.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "aaa62591199162e6496b4f47cac4f5923bc571d1", "tree": "1f3d74c71c3a3c914458af39890a4eb7ad2f324a", "parents": [ "e9b1cc81c2222108d866323c51f482dd6db8d689" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Sep 12 11:07:15 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:39:52 2010 +0100" }, "message": "agp: kill agp_(unmap|map)_memory\n\nDMA remapping was only used by the intel-gtt driver. With that\ncode now folded into the driver, kill the agp generic support for\nit.\n\nCc: Dave Airlie \u003cairlied@linux.ie\u003e\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "e9b1cc81c2222108d866323c51f482dd6db8d689", "tree": "c57efbcc2e43d878ddcac52e4c92589b841613cf", "parents": [ "1b263f246639c4777fbf6cfda932ecd1ea4bebb9" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Sep 12 00:29:26 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:39:19 2010 +0100" }, "message": "intel-gtt: consolidate fake_agp driver structs\n\nThey\u0027re now all the same.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "1b263f246639c4777fbf6cfda932ecd1ea4bebb9", "tree": "a93dfc23657a830015b61daffb9d1d77bfb0bb8a", "parents": [ "bdd30729b68d708c970125aab363931134698f2d" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Sep 12 00:27:24 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:37:31 2010 +0100" }, "message": "intel-gtt: move chipset flush to the gtt driver struct\n\nThis is the last differentiator between the different fake agp drivers.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "bdd30729b68d708c970125aab363931134698f2d", "tree": "e7db7e5d4ebfdee40687f038e67d64e14e4cc563", "parents": [ "90cb149e1a85f8296daa1989c055db18fbf4ea88" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Sep 12 12:34:44 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:37:18 2010 +0100" }, "message": "intel-gtt: kill mask_memory functions\n\nThat indirection mess can now go. Add a dummy i81x gtt_driver to\navoid a NULL pointer check.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "90cb149e1a85f8296daa1989c055db18fbf4ea88", "tree": "a8e4b4c7485baa9bb95dc29e6cd1adc2106dcd4a", "parents": [ "450f2b3d51025a1749b694ee13f0e4e23ed58750" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sat Sep 11 23:55:20 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:37:05 2010 +0100" }, "message": "intel-gtt: generic (insert|remove)_entries for sandybridge\n\nLike before, but now with the added bonus of being able to kill\nquite a bit of no-longer userful code (the old dmar support stuff).\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "450f2b3d51025a1749b694ee13f0e4e23ed58750", "tree": "8cd3a1920a1bf813d52a7458922d96bd40060f5d", "parents": [ "fefaa70f0c7fa406492039e35b69b83fc13e163a" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sat Sep 11 23:48:25 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:36:52 2010 +0100" }, "message": "intel-gtt: generic (insert|remove)_entries for g33/i965\n\nLike for the i915.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "fefaa70f0c7fa406492039e35b69b83fc13e163a", "tree": "c9f721ad19884c401774d926b65a6c4f8b08a037", "parents": [ "5cbecafce4ee8ab73c194911e01a77a7a07f034e" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sat Sep 11 22:12:11 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:36:38 2010 +0100" }, "message": "intel-gtt: generic (insert|remove)_entries for i915\n\nBeef up the generic version to support dmar. Otherwise like for the i830.\n\nv2: Don\u0027t try to DMA remap on resume for already remapped pages.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "5cbecafce4ee8ab73c194911e01a77a7a07f034e", "tree": "1434a04f60faec36094bad48db0f3938367df361", "parents": [ "a87aa5cc0074fea871c8c6d2660d9b6cd7699d3d" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sat Sep 11 21:31:04 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:36:25 2010 +0100" }, "message": "intel-gtt: generic (insert|remove)_entries for i830\n\nWell, not all too generic because it does not yet support dmar.\nAdd a new function check_flags to ensure that non-gem code does\nnot try to screw us over.\n\nv2: Beautify i830_check_flags with an idea from Chris Wilson.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "a87aa5cc0074fea871c8c6d2660d9b6cd7699d3d", "tree": "f28de481abe2577bd6459ecad54b4a44892ad6a1", "parents": [ "d0b6dc4b930e3be9c02cc9638f02e14d271d5f0d" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Thu Sep 09 18:17:34 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:36:11 2010 +0100" }, "message": "agp: kill agp_(map|unmap)_page\n\nOnly used to remap the scratch page. Now that intel-gtt does this\nitself, kill the support code.\n\nCc: Dave Airlie \u003cairlied@linux.ie\u003e\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "d0b6dc4b930e3be9c02cc9638f02e14d271d5f0d", "tree": "ebccc4c31b3b11ae4f3b1009ee44d7d5633e06af", "parents": [ "97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Thu Sep 09 18:11:41 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:35:58 2010 +0100" }, "message": "intel-gtt: drop agp scratch page support stuff\n\nintel-gtt.c now handles the scratch page itself, so drop all that\nwas just there to support it.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3", "tree": "f60e252600d69331f8b209e5935b77bdb415d076", "parents": [ "a6963596a13e62f8e65b1cf3403a330ff2db407c" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Thu Sep 09 17:52:20 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:35:44 2010 +0100" }, "message": "intel-gtt: introduce pte write function for gen6\n\nLike for i830. intel_i9xx_configure is now unused, so kill it.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "a6963596a13e62f8e65b1cf3403a330ff2db407c", "tree": "a384b7f3fa0e8c3b2fadc090e647a5509fa3f6d1", "parents": [ "351bb278d2fd2df93526c15f37500070347328b4" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sat Sep 11 14:01:43 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:35:31 2010 +0100" }, "message": "intel-gtt: introduce pte write function for g33/i965/gm45\n\nLike for the i830.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "351bb278d2fd2df93526c15f37500070347328b4", "tree": "9e351eac4867c206f273e121ab061b0d62ec931f", "parents": [ "0e87d2b06cb4651c874d0b208d31c73addbd638b" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Tue Sep 07 22:41:04 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:35:18 2010 +0100" }, "message": "intel-gtt: introduce pte write function for i8xx/i915/i945\n\nAnd put it to use in the gtt configuration code that writes\nthe scratch page addr in all gtt ptes. This makes intel_i830_configure\ngeneric, hence rename it to intel_fake_agp_configure.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "0e87d2b06cb4651c874d0b208d31c73addbd638b", "tree": "dd933e996f74b67e0e386f1871149f40b0e94855", "parents": [ "f13d3f7311add99d1f874a6b67d56426afa35664" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Tue Sep 07 22:11:15 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:30:21 2010 +0100" }, "message": "intel-gtt: initialize our own scratch page\n\nThe intel gtt fake agp driver is the only agp driver to use dma\naddress remapping. So it makes sense to fold this code back into the\nonly user (and thus reduce the reliance on the agp code).\n\nThis patch does the first step by initializing (and remapping) the\nscratch page in a new function intel_gtt_setup_scratch_page.\nUnfortunately intel_gtt_cleanup had to move to avoid a forward\ndeclaration. The new scratch page is not yet used, though.\n\nv2: Refactor out scratch page teardown. Suggested by Chris Wilson on\nirc. This makes it clear what\u0027s going on and results in a nice\nsymmetry between setup and teardown.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "e9e5f8e8d373e72f5c39dafde1ce110fc7082118", "tree": "2991e33571a59cc2488daef36dcfeab7bddb9d7f", "parents": [ "f899fc64cda8569d0529452aafc0da31c042df2e", "db8c076b9206ea35b1f7299708d5510b17674db2" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:19:32 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 21 11:19:32 2010 +0100" }, "message": "Merge branch \u0027drm-intel-fixes\u0027 into HEAD\n\nConflicts:\n\tdrivers/char/agp/intel-agp.c\n\tdrivers/gpu/drm/i915/intel_crt.c\n" }, { "commit": "23ac4ae827e6264e21b898f2cd3f601450aa02a6", "tree": "d2948304b5be996cbf8ad15ade2e3b3baa760617", "parents": [ "900f9ac9f12dc3dd6fc8e33e16df172eafcaead6" ], "author": { "name": "Andreas Herrmann", "email": "andreas.herrmann3@amd.com", "time": "Fri Sep 17 18:03:43 2010 +0200" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@linux.intel.com", "time": "Mon Sep 20 14:22:58 2010 -0700" }, "message": "x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB\n\nThe file names are somehow misleading as the code is not specific to\nAMD K8 CPUs anymore. The files accomodate code for other AMD CPU\nnorthbridges as well.\n\nSame is true for the config option which is valid for AMD CPU\nnorthbridges in general and not specific to K8.\n\nSigned-off-by: Andreas Herrmann \u003candreas.herrmann3@amd.com\u003e\nLKML-Reference: \u003c20100917160343.GD4958@loge.amd.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@linux.intel.com\u003e\n" }, { "commit": "900f9ac9f12dc3dd6fc8e33e16df172eafcaead6", "tree": "7fb7bf3a150f8a3cc513e1bf6bd842e4ad213473", "parents": [ "3518dd14ca888085797ca8d3a9e11c8ef9e7ae68" ], "author": { "name": "Andreas Herrmann", "email": "andreas.herrmann3@amd.com", "time": "Fri Sep 17 18:02:54 2010 +0200" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@linux.intel.com", "time": "Fri Sep 17 13:26:21 2010 -0700" }, "message": "x86, k8-gart: Decouple handling of garts and northbridges\n\nSo far we only provide num_k8_northbridges. This is required in\ndifferent areas (e.g. L3 cache index disable, GART). But not all AMD\nCPUs provide a GART. Thus it is useful to split off the GART handling\nfrom the generic caching of AMD northbridge misc devices.\n\nSigned-off-by: Andreas Herrmann \u003candreas.herrmann3@amd.com\u003e\nLKML-Reference: \u003c20100917160254.GC4958@loge.amd.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@linux.intel.com\u003e\n" }, { "commit": "41a51428916ab04587bacee2dda61c4a0c4fc02f", "tree": "8c741b166adbfe2219774038a82e08a32ab6b019", "parents": [ "e259befd9013e212648c3bd4f6f1fbf92d0dd51d" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Fri Sep 17 08:22:30 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Fri Sep 17 08:22:30 2010 +0100" }, "message": "drm/i915,agp/intel: Add second set of PCI-IDs for B43\n\nThere is a second revision of B43 (a desktop gen4 part) floating around,\nfunctionally equivalent to the original B43, so simply add the new\nPCI-IDs.\n\nBugzilla: https://bugs.freedesktop.org/show_bugs.cgi?id\u003d30221\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\nCc: stable@kernel.org\n" }, { "commit": "3f08e4ef807c3103ceebf7993c7463c7a90646f3", "tree": "63119dac1d44e097fd8cbcaa3f77eb111757483e", "parents": [ "b1c5b0f8cc16a1d22e2e521c4236a6ceca1b2983" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 14 20:15:22 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 14 21:13:13 2010 +0100" }, "message": "agp/intel: Fix resume regression from 2d2430cf\n\nOn i915 [EeePCs] something scribles over the registers during suspend\nand resume so we must save a copy of the PGETBL_CTL register programmed\nby the BIOS and restore that upon resume.\n\nReported-by: Sitsofe Wheeler \u003csitsofe@yahoo.com\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "b1c5b0f8cc16a1d22e2e521c4236a6ceca1b2983", "tree": "c9d2ae374fb56af57532bb929e0c2e1cb0be7ac7", "parents": [ "819f3fb7fe349d0e6aadbd7088529ab95fe5cd9f" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 14 19:30:13 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 14 21:13:12 2010 +0100" }, "message": "agp/intel: Remove redundant setting of gtt_mappable_entries\n\nTwo calls enter, only one will leave.\n\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "9e76e7b8bd716413cfd722a807aa22723f3a895f", "tree": "3564c55631ee10644aae41783322da09cc2b0711", "parents": [ "0bc23aad3b67ca0cd7480dec0b7652d9b8686432" ], "author": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 14 12:12:11 2010 +0100" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Tue Sep 14 12:12:11 2010 +0100" }, "message": "agp/intel: Use macro to set the count of the size array\n\nIt\u0027s a fixed size array so let the compiler do the hard work of updating\nall the call sites.\n\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "19966754328d99ee003ddfc7a8c31ceb115483ac", "tree": "c057dfaf9f9354168102e5ae450ebefbc158bd28", "parents": [ "ac622a9cdb742cad90648d95f2c4877774518f19" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Mon Sep 06 20:08:44 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:21 2010 +0100" }, "message": "drm/i915: die, i915_probe_agp, die\n\nUse the detection from intel-gtt.ko instead. Hooray!\n\nAlso move the stolen mem allocator to the other gtt stuff in dev_prv-\u003emem.\n\nv2: Chris Wilson noted that my error handling was crap. Fix it. He also\nsaid that this fixes a problem on his i845. Indeed, i915_probe_agp\nmisses a special case for i830/i845 stolen mem detection.\n\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id\u003d25476\nCc: stable@kernel.org\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "239918f7a5ac118ecfe9c55a4cfd25d7767b674a", "tree": "6a38a5ed6dda6ff9341a6cca8a12e71eb0ec3f9d", "parents": [ "3b15a9d7cd59b7ec79f61aafabfbe84116561461" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Tue Aug 31 22:30:43 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:19 2010 +0100" }, "message": "intel-gtt: use chipset generation number some more\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "3b15a9d7cd59b7ec79f61aafabfbe84116561461", "tree": "fa53438e6bee5bedd9ce32a9ba35854dcc6f1b73", "parents": [ "2d2430cf9bf9e8b0ad9ea34a103625f4fe7e4477" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Aug 29 14:18:49 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:19 2010 +0100" }, "message": "intel-gtt: call init_gtt_init in probe function\n\nThis way create_gatt_table become dummy glue functions for the fake\nagp driver - rename them accordingly (and kill the now unnecessary\ni9xx copy).\n\nWith this change, the gtt initialization code is almost independant\nfrom the agp stuff. Two things are still missing:\n- the scratch page is created by the generic agp code.\n- filling the whole gtt with scratch_page ptes is not yet consolidated -\n this needs abstracted pte handling, first.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "2d2430cf9bf9e8b0ad9ea34a103625f4fe7e4477", "tree": "2beac383272109a7db261b88fd3de664f4b5348b", "parents": [ "73800422a30e9b8b6e0e49c27af9e9d196e52fd9" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Aug 29 17:35:30 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:18 2010 +0100" }, "message": "intel-gtt: consolidate i9xx setup\n\nThe only difference between i915 and i965 was the calculation of the\ngtt address. So merge these two paths into one. Otherwise the same\nchanges as in the i830 setup consolidation.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "73800422a30e9b8b6e0e49c27af9e9d196e52fd9", "tree": "1a9d78237a1655c7667ad1f0325eb224f8cb19d8", "parents": [ "f67eab664c47b261517b09812477de9a1780b426" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Aug 29 17:29:50 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:17 2010 +0100" }, "message": "intel-gtt: consolidate i830 setup\n\nSlighlty reordered sequence was necessary. Also don\u0027t set\nagp_bridge-\u003egatt_bus_addr anymore. Only used by generic agp helper\nfunctions, hence unnecessary for the intel fake agp driver.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "f67eab664c47b261517b09812477de9a1780b426", "tree": "84b2cf266d05f16aff57f27e76f2f3363e327c24", "parents": [ "fdfb58a965486d2afea4ef0f9b8153dab9b98b2e" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Aug 29 17:27:36 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:17 2010 +0100" }, "message": "intel-gtt: consolidate the gtt ioremap calls\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "fdfb58a965486d2afea4ef0f9b8153dab9b98b2e", "tree": "a67a1feac243119c776344f5cac582269f018578", "parents": [ "210b23c2f7b9721afb0a57459b7dbac3b094862e" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sun Aug 29 00:15:03 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:16 2010 +0100" }, "message": "intel-gtt: i830: adjust ioremap of regs and gtt to i9xx\n\nThis way around this can be extracted into common code.\n\nAlso use a common cleanup function (and give it a generic name).\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "210b23c2f7b9721afb0a57459b7dbac3b094862e", "tree": "1294b7eff22f03bc10c2a8ffa64333fe56895b7a", "parents": [ "ccc4e67be5ac1bd38c4bfd61aca38366597e8afb" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sat Aug 28 16:14:32 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:15 2010 +0100" }, "message": "intel-gtt: i965: use detected gtt size for mapping\n\nAlso move the Sandybdridge size detection into gtt_total_entries, like\nthe rest.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "ccc4e67be5ac1bd38c4bfd61aca38366597e8afb", "tree": "04c661214c09dd31114ab36f34ef431711b38da9", "parents": [ "1a997ff2a0089a07a5494545d31f4366742dea43" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Wed Sep 08 21:20:12 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:14 2010 +0100" }, "message": "intel-gtt: i915: use detected gtt size for mapping\n\nSlight reordering of the init sequence required.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "1a997ff2a0089a07a5494545d31f4366742dea43", "tree": "31b1922f2922c76ef1aff40cc298fd8a2e49d114", "parents": [ "e5e408fc94595aab897f613b6f4e2f5b36870a6f" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Wed Sep 08 21:18:53 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:14 2010 +0100" }, "message": "intel-gtt: introduce intel_gtt_driver\n\nSame idea as INTEL_INFO from drm/i915. This\n- reduces the dependancy on agp_driver\n- stops the what-does-IS_I965G-mean confusion (here it\u0027s just gen4, in\n drm/i915 it\u0027s gen \u003e\u003d4)\n- further prepares the separation of the fake agp driver from the rest.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "e5e408fc94595aab897f613b6f4e2f5b36870a6f", "tree": "77924470cb3934115db4116e7a4ff5c12da51153", "parents": [ "ffdd7510b0bd5ec663b6b11b39810574f2ce3111" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Sat Aug 28 11:04:32 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:13 2010 +0100" }, "message": "intel-gtt: fix gtt_total_entries detection\n\nIn commit f1befe71 Chris Wilson added some code to clear the full gtt\non g33/pineview instead of just the mappable part. The code looks like\nit was copy-pasted from agp/intel-gtt.c, at least an identical piece\nof code is still there (in intel_i830_init_gtt_entries). This lead to\na regression in 2.6.35 which was supposedly fixed in commit e7b96f28\n\nNow this commit makes absolutely no sense to me. It seems to be\nslightly confused about chipset generations - it references docs for\n4th gen but the regression concerns 3rd gen g33. Luckily the the g33\ngmch docs are available with the GMCH Graphics Control pci config\nregister definitions. The other (bigger problem) is that the new\ncheck in there uses the i830 stolen mem bits (.5M, 1M or 8M of stolen\nmem). They are different since the i855GM.\n\nThe most likely case is that it hits the 512M fallback, which was\nprobably the right thing for the boxes this was tested on.\n\nSo the original approach by Chris Wilson seems to be wrong and the\ncurrent code is definitely wrong. There is a third approach by Jesse\nBarnes from his RFC patch \"Who wants a bigger GTT mapping range?\"\nwhere he simply shoves g33 in the same clause like later chipset\ngenerations.\n\nI\u0027ve asked him and Jesse confirmed that this should work. So implement\nit.\n\nBugzilla: https://bugzilla.kernel.org/show_bug.cgi?id\u003d16891$\nTested-by: Anisse Astier \u003canisse@astier.eu\u003e\nCc: stable@kernel.org\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "ffdd7510b0bd5ec663b6b11b39810574f2ce3111", "tree": "7bfc9cf2676fc5aeddd1dd60dc5b9504c33d5f63", "parents": [ "fbe407836b5c8d82c68195962240a392d0ce64ea" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Aug 27 17:51:29 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:12 2010 +0100" }, "message": "intel-gtt: s/i8[13]0/fake_agp for generic functions\n\nStart to separate the fake agp driver from the rest of intel-gtt.c\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "fbe407836b5c8d82c68195962240a392d0ce64ea", "tree": "243c746f61fae6ecff3f1459408be5909c4e161d", "parents": [ "77ad498ecaeb9a614d2a7bbfaab58a35c0cc577d" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Aug 27 17:12:41 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:12 2010 +0100" }, "message": "intel-gtt: adjust overhead entries in intel_gtt_stolen_entries\n\nagp/intel_gtt.c and drm/i915/i915_dma.c don\u0027t calculate this the same\nway: The intel-gtt code seems to use the actual gtt size, the drm\nmodule just the mappable. Go with the logic from the drm module because\nthat\u0027s the more conservative choice.\n\nBut conserve the original code in intel_gtt_total_size for later use.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "77ad498ecaeb9a614d2a7bbfaab58a35c0cc577d", "tree": "0e146e942233b703fda4241ee67dd2a6969f73d6", "parents": [ "d8d9abcd35aeebd633cba2e99c384f4e004ccb84" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Aug 27 16:25:54 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:11 2010 +0100" }, "message": "intel-gtt: drop unnecessary conditions in intel_gtt_stolen_entries\n\nThe dedection function in drm/i915/i915_dma.c works without it, so\ndrop it here, too. All the values are disdinct, anyway.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "d8d9abcd35aeebd633cba2e99c384f4e004ccb84", "tree": "f3b4fa8f70112fcacf710fe1654b9ee514aa5e0d", "parents": [ "3e921f980fdd5b972efb7f368b2a847a01804184" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Aug 27 16:13:52 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:10 2010 +0100" }, "message": "intel-gtt: sane variable names for intel_gtt_stolen_entries\n\nThis somewhat aligns it with the version in drm/i915/i915_dma.c.\nChanges:\n- s/gtt_entries/stolen_size\n- track overhead entries in a seperate var (the effective gtt size\n calculation will be extracted later on).\n- subtract the overhead at the end instead of in each clause.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "3e921f980fdd5b972efb7f368b2a847a01804184", "tree": "b554b1699b81976938358fed03649c9981cfbccd", "parents": [ "1784a5fb4f7a41b9a5ea066f7782418bfe170c04" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Fri Aug 27 15:33:26 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:09 2010 +0100" }, "message": "intel-gtt: generic intel_fake_agp_fetch_size\n\nThis uses the new mappable gtt size detection from the previous patch.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "1784a5fb4f7a41b9a5ea066f7782418bfe170c04", "tree": "b295e950380bf16dbe54893bd84df56c2b1eca86", "parents": [ "bfde067bebe72293b1f909a8b35ee8d82811f8f5" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Wed Sep 08 21:01:04 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:09 2010 +0100" }, "message": "intel-gtt: new function intel_gtt_mappable_entries\n\nThis implementation is stolen from drm/i915, but is equivalent to\nthe code sprinkled over intel-gtt.c in the various fetch_size functions.\nIt\u0027s not yet used anywhere, though.\n\nAlso introduce intel_gtt_init which only calls intel_gtt_stolen_entries.\nOver the course of the next patches, this will grow untill it contains\nthe complete init sequence starting from the call to gtt_mappable_entries.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "bfde067bebe72293b1f909a8b35ee8d82811f8f5", "tree": "c4b15e42fb1683426e944b589994c52257d2bc49", "parents": [ "d7cca2f7000243ac43a389110c3d8474f582ae3f" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Tue Aug 24 23:07:59 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:08 2010 +0100" }, "message": "intel-gtt: s/intel_i830_init_gtt_entries/intel_gtt_stolen_entries\n\nFirst simple step towards a more generic initialization. This\nis needed to disentangle the agp stuff from the stuff that is\nactually needed by drm/i915.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" }, { "commit": "d7cca2f7000243ac43a389110c3d8474f582ae3f", "tree": "e2e5df744aa066591201aa365c6e24c687b574b8", "parents": [ "0ade638655f0ef4d807295c14a4c97544bd6b9ca" ], "author": { "name": "Daniel Vetter", "email": "daniel.vetter@ffwll.ch", "time": "Tue Aug 24 23:06:19 2010 +0200" }, "committer": { "name": "Chris Wilson", "email": "chris@chris-wilson.co.uk", "time": "Wed Sep 08 21:20:07 2010 +0100" }, "message": "intel-gtt: store a local pointer to the bridge pci dev\n\nWhen the intel-gtt code now longer depends on agp, we cannot rely\non this. So store a local reference in intel-gtt.c.\n\nSigned-off-by: Daniel Vetter \u003cdaniel.vetter@ffwll.ch\u003e\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n" } ], "next": "0ade638655f0ef4d807295c14a4c97544bd6b9ca" }