)]}' { "log": [ { "commit": "56adf7e8127d601b172e180b44551ce83404348f", "tree": "eabcdad1e4b17ea8f7c20a50a44ca859360085d3", "parents": [ "49954c1567cb0d70d28bb5512d471dc5bd4e2c3f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Nov 22 12:10:10 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Nov 22 12:10:10 2009 -0700" }, "message": "shdma: fix initialization error handling\n\n1/ Error handling code following a kzalloc should free the allocated data.\n2/ Report an error when no platform data is detected\n\nBoth problems fixed by moving the platform data check before the allocation,\nand allows a goto to be killed.\n\nReported-by: Julia Lawall \u003cjulia@diku.dk\u003e\nAcked-by: Julia Lawall \u003cjulia@diku.dk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "49954c1567cb0d70d28bb5512d471dc5bd4e2c3f", "tree": "c64b4585518028b5c8ae749b93d9f560d536f649", "parents": [ "7b3cc2b1fc2066391e498f3387204908c4eced21" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:11:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "ioat3: fix pq completion versus channel deallocation race\n\nThe completion of a pq operation is notified with a null descriptor\nappended to the end of the chain. This descriptor needs to be visible\nto dma clients otherwise the client is precluded from ensuring all\noperations are quiesced before freeing channel resources, i.e. due to\ndescriptor polling it may get the completion notification ahead of the\ninterrupt delivered by the null descriptor.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7b3cc2b1fc2066391e498f3387204908c4eced21", "tree": "8a2bc28955710c580201046d04843773cb7d87a1", "parents": [ "4499a24dec00e037da7d09caccad45e7594a9c19" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "async_tx: build-time toggling of async_{syndrome,xor}_val dma support\n\nioat3.2 does not support asynchronous error notifications which makes\nthe driver experience latencies when non-zero pq validate results are\nexpected. Provide a mechanism for turning off async_xor_val and\nasync_syndrome_val via Kconfig. This approach is generally useful for\nany driver that specifies ASYNC_TX_DISABLE_CHANNEL_SWITCH and would like\nto force the async_tx api to fall back to the synchronous path for\ncertain operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "4499a24dec00e037da7d09caccad45e7594a9c19", "tree": "d336eb5f67a2873bcd7e43ef64d5d149283e7e0f", "parents": [ "b57014def9afc2bd8a62299d2f51b77dad5ae0c7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:25 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "dmaengine: include xor/pq validate in device_has_all_tx_types()\n\nA channel must include these capabilities to satisfy\nASYNC_TX_DISABLE_CHANNEL_SWITCH.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b57014def9afc2bd8a62299d2f51b77dad5ae0c7", "tree": "b196078bed3b982475bd0dd22ce0ce8aad2f517a", "parents": [ "de581b65f6fe78168affa552c3bd15b8c80ed614" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:07 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "ioat2,3: report all uncorrectable errors\n\nModify is_ioat_bug() to catch all errors that are uncorrectable, or not\ncurrently handled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "de581b65f6fe78168affa552c3bd15b8c80ed614", "tree": "b980e64cf31ad79c489838310be2e13e626dd05c", "parents": [ "6f82b83b7a56bc6e9dd6d7b93531dde6027c5309" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:08:45 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:08:45 2009 -0700" }, "message": "ioat3: specify valid address for disabled-Q or disabled-P\n\nAlthough disabled, hardware still checks address validity, so duplicate\nthe known address.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6f82b83b7a56bc6e9dd6d7b93531dde6027c5309", "tree": "d6f9fc6064e60711e1d041a48d8ff0927ca819e7", "parents": [ "228c4f5cfbf1cda411d9aa7204a612a63c89b1e8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:57 2009 -0700" }, "message": "ioat2,3: disable asynchronous error notifications\n\nError interrupts and error completions may cause channel hangs, so\npoll the channel status register after a timeout.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "228c4f5cfbf1cda411d9aa7204a612a63c89b1e8", "tree": "0920f900732ce598fef2cdc0c4899860534e837d", "parents": [ "e22dde9904c2d26a522f1a2b89854a8238bf0933" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:10 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:10 2009 -0700" }, "message": "ioat3: dca and raid operations are incompatible\n\nRAID operations cause a system hang on platforms with DCA\n(Direct-Cache-Access) enabled. So turn off RAID capabilities in this\ncase.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e22dde9904c2d26a522f1a2b89854a8238bf0933", "tree": "dbb3b1f2d1d1ddafb3c004819c25c31a73811ae8", "parents": [ "b419148e567728f6af0c3b01965c1cc141e3e13a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Nov 17 11:34:31 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Nov 17 11:34:31 2009 -0700" }, "message": "ioat: silence \"dca disabled\" messages\n\nTurning off dca is not an \"error\", and the dca-enabled state can be\nviewed from sysfs.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "4b3df5668c8ebaebd8d66a5a94374be3e3b2ef0c", "tree": "51a231742e211143f5845edf4b09d1712dcd2771", "parents": [ "1ef04fefe2241087d9db7e9615c3f11b516e36cf", "1f6672d44c1ae7408b43c06170ec34eb0a0e9b9f" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Wed Sep 23 18:31:11 2009 +1000" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Wed Sep 23 18:31:11 2009 +1000" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx into for-linus\n" }, { "commit": "cdef57dbb618608bfffda2fc32c8d0a4012a1d3a", "tree": "e58d3301ea4fb264f713c4602c25e6451d4e6707", "parents": [ "f477f5b3316f39c841aa121a219b82b3a56e7da7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 21 09:22:29 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 21 09:22:29 2009 -0700" }, "message": "ioat3: fix uninitialized var warnings\n\ndrivers/dma/ioat/dma_v3.c: In function \u0027ioat3_prep_memset_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:439: warning: \u0027fill\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:437: warning: \u0027desc\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c: In function \u0027__ioat3_prep_xor_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:489: warning: \u0027xor\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:486: warning: \u0027desc\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c: In function \u0027__ioat3_prep_pq_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:631: warning: \u0027pq\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:628: warning: \u0027desc\u0027 may be used uninitialized in this function\n\ngcc-4.0, unlike gcc-4.3, does not see that these variables are\ninitialized before use. Convert the descriptor loops to do-while make\nthis initialization apparent.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f477f5b3316f39c841aa121a219b82b3a56e7da7", "tree": "392476186ece4084f85b3c5227853d92ecae79a6", "parents": [ "1b6df6930994d5d027375b07ac9da63644eb5758" ], "author": { "name": "Andrew Morton", "email": "akpm@linux-foundation.org", "time": "Mon Sep 21 09:17:58 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 21 09:17:58 2009 -0700" }, "message": "drivers/dma/ioat/dma_v2.c: fix warnings\n\ndrivers/dma/ioat/dma_v2.c: In function \u0027ioat2_dma_prep_memcpy_lock\u0027:\ndrivers/dma/ioat/dma_v2.c:680: warning: \u0027hw\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v2.c:681: warning: \u0027desc\u0027 may be used uninitialized in this function\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "376ec37667b510453f5a62fcd95d762786e6a0a9", "tree": "7352166b585463ce53633e379b96196dff72014f", "parents": [ "6c910a78e495b4c1778a8b136b37fe3c05712730" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 16 15:16:50 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 16 15:16:50 2009 -0700" }, "message": "ioat2: clarify ring size limits\n\nWith the addition of ioat_max_alloc_order it is not clear what the\nmaximum allocation order is, so document that in the modinfo. Also take\nan opportunity to kill a stray semicolon.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "33f82d141c897f39cd8bce592d88cb3c5af58342", "tree": "7765831183d05fb635e60e8f8bf92e0bdfe06b5c", "parents": [ "3eb132c986f04f64b9c360abd67a1e0d18d6d5b4" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 00:06:44 2009 +0200" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Sep 14 20:27:00 2009 +0200" }, "message": "at_hdmac: Rework suspend_late()/resume_early()\n\nThis patch reworks platform driver power management code\nfor at_hdmac from legacy late/early callbacks to dev_pm_ops.\n\nThe callbacks are converted for CONFIG_SUSPEND like this:\n suspend_late() -\u003e suspend_noirq()\n resume_early() -\u003e resume_noirq()\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\n" }, { "commit": "3208ca52f3bfa36914c44db207d0a34071f9897f", "tree": "fb28779eb8ec74fd650f2df085f507353fcd79ce", "parents": [ "1a5aeeecd550ee4344cfba1791f1134739b16dc6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 11:27:36 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 11:27:36 2009 -0700" }, "message": "ioat: driver version 4.0\n\nA new ring implementation and the addition of raid functionality\nconstitutes a bump in the driver major version number.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1a5aeeecd550ee4344cfba1791f1134739b16dc6", "tree": "0b2f1f104d7dbff82130ea1d41c037a74fa6753e", "parents": [ "9a8de639f35ca3951b910d5e3a2f92f4cf3afc8f" ], "author": { "name": "Maciej Sosnowski", "email": "maciej.sosnowski@intel.com", "time": "Thu Sep 10 15:05:58 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 10:00:05 2009 -0700" }, "message": "dca: registering requesters in multiple dca domains\n\nThis patch enables DCA support on multiple-IOH/multiple-IIO architectures.\nIt modifies dca module by replacing single dca_providers list\nwith dca_domains list, each domain containing separate list of providers.\nThis approach lets dca driver manage multiple domains, i.e. sets of providers\nand requesters mapped back to the same PCI root complex device.\nThe driver takes care to register each requester to a provider\nfrom the same domain.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\n" }, { "commit": "9a8de639f35ca3951b910d5e3a2f92f4cf3afc8f", "tree": "58d799166b6facdf25e314885ee7fadd20597482", "parents": [ "d8902adcc1a9fd484c8cb5e575152e32192c1ff8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 15:06:10 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:56:37 2009 -0700" }, "message": "async_tx: remove HIGHMEM64G restriction\n\nThis restriction prevented ASYNC_TX_DMA from being enabled on platform\nconfigurations where DMA address conversion could not be performed in\nplace on the stack. Since commit 04ce9ab3 (\"async_xor: permit callers\nto pass in a \u0027dma/page scribble\u0027 region\") the async_tx api now either\nuses a caller provided \u0027scribble\u0027 buffer, or performs the conversion in\nplace when sizeof(dma_addr_t) \u003c\u003d sizeof(struct page *).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d8902adcc1a9fd484c8cb5e575152e32192c1ff8", "tree": "305109ce60db5ea9710dddce9db8a23f65ff4572", "parents": [ "9134d02bc0af4a8747d448d1f811ec5f8eb96df6" ], "author": { "name": "Nobuhiro Iwamatsu", "email": "iwamatsu.nobuhiro@renesas.com", "time": "Mon Sep 07 03:26:23 2009 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:56:02 2009 -0700" }, "message": "dmaengine: sh: Add Support SuperH DMA Engine driver\n\nThis supported all DMA channels, and it was tested in SH7722,\nSH7780, SH7785 and SH7763.\nThis can not use with SH DMA API.\n\nSigned-off-by: Nobuhiro Iwamatsu \u003ciwamatsu.nobuhiro@renesas.com\u003e\nReviewed-by: Matt Fleming \u003cmatt@console-pimps.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bbb20089a3275a19e475dbc21320c3742e3ca423", "tree": "216fdc1cbef450ca688135c5b8969169482d9a48", "parents": [ "3e48e656903e9fd8bc805c6a2c4264d7808d315b", "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "message": "Merge branch \u0027dmaengine\u0027 into async-tx-next\n\nConflicts:\n\tcrypto/async_tx/async_xor.c\n\tdrivers/dma/ioat/dma_v2.h\n\tdrivers/dma/ioat/pci.c\n\tdrivers/md/raid5.c\n" }, { "commit": "3e48e656903e9fd8bc805c6a2c4264d7808d315b", "tree": "dfee34eb1f317b35f33a02291e65ce6ec46e3a5a", "parents": [ "a6417dd58d6832f123f36c6f22c63ec1ab62ce1c", "f6dbf651615900646fe0ba1ef5ce1027e5b4748d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:57 2009 -0700" }, "message": "Merge branch \u0027iop-raid6\u0027 into async-tx-next\n" }, { "commit": "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843", "tree": "74fd6b5c2c35dcea18928a600ff34c04f8626cb6", "parents": [ "bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7d" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Tue Sep 08 17:53:05 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:05 2009 -0700" }, "message": "dmaengine: Move all map_sg/unmap_sg for slave channel to its client\n\nDan Williams wrote:\n... DMA-slave clients request specific channels and know the hardware\ndetails at a low level, so it should not be too high an expectation to\npush dma mapping responsibility to the client.\n\nAlso this patch includes DMA_COMPL_{SRC,DEST}_UNMAP_SINGLE support for\ndw_dmac driver.\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7d", "tree": "5f2145c023b9145d1461ecb63c839fd32f762378", "parents": [ "e6c7ecb64e08ef346cb7062b4a5421f00bc602bd" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "fsldma: Add DMA_SLAVE support\n\nUse the DMA_SLAVE capability of the DMAEngine API to copy/from a\nscatterlist into an arbitrary list of hardware address/length pairs.\n\nThis allows a single DMA transaction to copy data from several different\ndevices into a scatterlist at the same time.\n\nThis also adds support to enable some controller-specific features such as\nexternal start and external pause for a DMA transaction.\n\n[dan.j.williams@intel.com: rebased on tx_list movement]\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nAcked-by: Li Yang \u003cleoli@freescale.com\u003e\nAcked-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "e6c7ecb64e08ef346cb7062b4a5421f00bc602bd", "tree": "73424d223391302a9a16df65378d78f25fd05929", "parents": [ "162b96e63e518aa6ff029ce23de12d7f027483bf" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "fsldma: split apart external pause and request count features\n\nWhen using the Freescale DMA controller in external control mode, both the\nrequest count and external pause bits need to be setup correctly. This was\nbeing done with the same function.\n\nThe 83xx controller lacks the external pause feature, but has a similar\nfeature called external start. This feature requires that the request count\nbits be setup correctly.\n\nSplit the function into two parts, to make it possible to use the external\nstart feature on the 83xx controller.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "162b96e63e518aa6ff029ce23de12d7f027483bf", "tree": "532191d0cef7cf975b70a07b1c69a293d6f552f7", "parents": [ "0803172778901e24a75ab074798d98c2b7411559" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "ioat2,3: cacheline align software descriptor allocations\n\nAll the necessary fields for handling an ioat2,3 ring entry can fit into\none cacheline. Move -\u003elen prior to -\u003etxd in struct ioat_ring_ent, and\nmove allocation of these entries to a hw-cache-aligned kmem cache to\nreduce the number of cachelines dirtied for descriptor management.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0803172778901e24a75ab074798d98c2b7411559", "tree": "a3e1d0cf4228d65dc1fac2ad56f3beb6b6f3474b", "parents": [ "1979b186b80449ac6574d97c254b694c8a99b703" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "dmaengine: kill tx_list\n\nThe tx_list attribute of struct dma_async_tx_descriptor is common to\nmost, but not all dma driver implementations. None of the upper level\ncode (dmaengine/async_tx) uses it, so allow drivers to implement it\nlocally if they need it. This saves sizeof(struct list_head) bytes for\ndrivers that do not manage descriptors with a linked list (e.g.: ioatdma\nv2,3).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "1979b186b80449ac6574d97c254b694c8a99b703", "tree": "9befdf33c11c0b0e4ce6720c7c81efeb7005ce7c", "parents": [ "285a3c71640ad7101b7237b8fbaa4ead22c6551c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "txx9dmac: implement a private tx_list\n\nDrop txx9dmac\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "285a3c71640ad7101b7237b8fbaa4ead22c6551c", "tree": "d4da48d227f2bc069cb3c1074c6267b5e29426e1", "parents": [ "64203b67274680e95e0c2eec935a22fc94e9ecb5" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "at_hdmac: implement a private tx_list\n\nDrop at_hdmac\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "64203b67274680e95e0c2eec935a22fc94e9ecb5", "tree": "93d56edbf3ecccdd0cffae3a20c3a7b7dd17cd5a", "parents": [ "ea25968a32a621b02c3715d6b649f0c6ef53c24e" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "mv_xor: implement a private tx_list\n\nDrop mv_xor\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Saeed Bishara \u003csaeed@marvell.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "ea25968a32a621b02c3715d6b649f0c6ef53c24e", "tree": "8da75c38c0ac0690eb03e89ccf146d062ba4d855", "parents": [ "308136d1abcb2d759bac40ed4f5d42ac4af59d8b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "ioat: implement a private tx_list\n\nDrop ioatdma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "308136d1abcb2d759bac40ed4f5d42ac4af59d8b", "tree": "c0cf21c5144929332a5f99d1aff8393e6cddcbbb", "parents": [ "eda34234578fd822c950fd06b5c5ff7ac08b3001" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "iop-adma: implement a private tx_list\n \nDrop iop-adma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "eda34234578fd822c950fd06b5c5ff7ac08b3001", "tree": "860b3c9d347ddd57e6884f9f1e019370de4d45b1", "parents": [ "e0bd0f8cb09cf3ccac1425f0f3a6705106c4d65c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "fsldma: implement a private tx_list\n\nDrop fsldma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Li Yang \u003cleoli@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "e0bd0f8cb09cf3ccac1425f0f3a6705106c4d65c", "tree": "664db6534e1654e98142ae01dab0aa223196d3d7", "parents": [ "e12c4fa377ffda2490476caae17f24daaf9c9bd7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "dw_dmac: implement a private tx_list\n\nDrop dw_dmac\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "e12c4fa377ffda2490476caae17f24daaf9c9bd7", "tree": "aa7a19d8f7f931709a8a835a4b0d441f83d759fd", "parents": [ "a348a7e6fdbcd2d5192a09719a479bb238fde727", "4b652f0db3be891c7b76b109c3b55003b920fc96" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:52:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:52:57 2009 -0700" }, "message": "Merge branch \u0027ioat\u0027 into dmaengine\n" }, { "commit": "a6417dd58d6832f123f36c6f22c63ec1ab62ce1c", "tree": "b8aa7273a874904396c79099facd104eeb4074e0", "parents": [ "6506cbca6b5b36d682bd39afcbf3f575c81dddb6" ], "author": { "name": "Roland Dreier", "email": "rdreier@cisco.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "message": "I/OAT: Convert to PCI_VDEVICE()\n\nTrivial cleanup to make the PCI ID table easier to read.\n\n[dan.j.williams@intel.com: extended to v3.2 devices]\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6506cbca6b5b36d682bd39afcbf3f575c81dddb6", "tree": "ea82de689e7712eaa76209afcaf9a8678dac9f3f", "parents": [ "e3232714d465c42ac631929b990f5e35e2d8a955" ], "author": { "name": "Roland Dreier", "email": "rdreier@cisco.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "message": "Add MODULE_DEVICE_TABLE() so ioatdma module is autoloaded\n\nThe ioatdma module is missing aliases for the PCI devices it supports,\nso it is not autoloaded on boot. Add a MODULE_DEVICE_TABLE() to get\nthese aliases.\n\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e3232714d465c42ac631929b990f5e35e2d8a955", "tree": "f6b9fe66bd11cdae420f558bebf7e8d4b89b52b4", "parents": [ "b265b11fc1a0bd6ae5a7fde12e374583a52ab326" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:02 2009 -0700" }, "message": "ioat3: segregate raid engines\n\nThe cleanup routine for the raid cases imposes extra checks for handling\nraid descriptors and extended descriptors. If the channel does not\nsupport raid it can avoid this extra overhead by using the ioat2 cleanup\npath.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b265b11fc1a0bd6ae5a7fde12e374583a52ab326", "tree": "8a864413b52e06f11f7f0299cdefd398999e82fb", "parents": [ "58c8649e0e25de511c4a66ce3fa38891e2ec4e9e" ], "author": { "name": "Tom Picard", "email": "tom.s.picard@intel.com", "time": "Tue Sep 08 17:43:01 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:01 2009 -0700" }, "message": "ioat3: ioat3.2 pci ids for Jasper Forest\n\nJasper Forest introduces raid offload support via ioat3.2 support. When\nraid offload is enabled two (out of 8 channels) will report raid5/raid6\noffload capabilities. The remaining channels will only report ioat3.0\ncapabilities (memcpy).\n\nSigned-off-by: Tom Picard \u003ctom.s.picard@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "58c8649e0e25de511c4a66ce3fa38891e2ec4e9e", "tree": "edb87012a3e42a7bbaa26a1172442da6ea389632", "parents": [ "ae786624c27411c1d38823f640b39f3d97412d5a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "message": "ioat3: interrupt descriptor support\n\nThe async_tx api uses the DMA_INTERRUPT operation type to terminate a\nchain of issued operations with a callback routine.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ae786624c27411c1d38823f640b39f3d97412d5a", "tree": "87ca33dae521c2c5622ea67dde97611e77d77df8", "parents": [ "d69d235b7da2778891640ee95efcd68075978904" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "message": "ioat3: support xor via pq descriptors\n\nIf a platform advertises pq capabilities, but not xor, then use\nioat3_prep_pqxor and ioat3_prep_pqxor_val to simulate xor support.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d69d235b7da2778891640ee95efcd68075978904", "tree": "e7f22d38d8a742ddbca167af123f4987ada8926c", "parents": [ "9de6fc717bdc574cf5faf9d46ce0f9d6265c7952" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:59 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:59 2009 -0700" }, "message": "ioat3: pq support\n\nioat3.2 adds support for raid6 syndrome generation (xor sum of galois\nfield multiplication products) using up to 8 sources. It can also\nperform an pq-zero-sum operation to validate whether the syndrome for a\ngiven set of sources matches a previously computed syndrome.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9de6fc717bdc574cf5faf9d46ce0f9d6265c7952", "tree": "55cb18ecfae85033d61f730b5f32d2ac1fb572bc", "parents": [ "b094ad3be564e7cc59cca4ff0256550d3a55dd3b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:58 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:58 2009 -0700" }, "message": "ioat3: xor self test\n\nThis adds a hardware specific self test to be called from ioat_probe.\nIn the ioat3 case we will have tests for all the different raid\noperations, while ioat1 and ioat2 will continue to just test memcpy.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b094ad3be564e7cc59cca4ff0256550d3a55dd3b", "tree": "d69f515b2ee6af2b0f12bb3028d7c7f5b3390794", "parents": [ "e61dacaeb3918cd00cd642e8fb0828324ac59819" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "message": "ioat3: xor support\n\nioat3.2 adds xor offload support for up to 8 sources. It can also\nperform an xor-zero-sum operation to validate whether all given sources\nsum to zero, without writing to a destination. Xor descriptors differ\nfrom memcpy in that one operation may require multiple descriptors\ndepending on the number of sources. When the number of sources exceeds\n5 an extended descriptor is needed. These descriptors need to be\naccounted for when updating the DMA_COUNT register.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e61dacaeb3918cd00cd642e8fb0828324ac59819", "tree": "70c4acf1cf33502bdca8da16bd88c0daab2bbc29", "parents": [ "5669e31c5a4874f1634bc0ffba268a6e2fa0cdd2" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "message": "ioat3: enable dca for completion writes\n\nTag completion writes for direct cache access to reduce the latency of\nchecking for descriptor completions.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5669e31c5a4874f1634bc0ffba268a6e2fa0cdd2", "tree": "3ef3f6724e7a812ba83b420c3915c4a46762aeb7", "parents": [ "bf40a6869c9198bdf56fe173961feb89e9f0d961" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:56 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:56 2009 -0700" }, "message": "ioat: add \u0027ioat\u0027 sysfs attributes\n\nExport driver attributes for diagnostic purposes:\n\u0027ring_size\u0027: total number of descriptors available to the engine\n\u0027ring_active\u0027: number of descriptors in-flight\n\u0027capabilities\u0027: supported operation types for this channel\n\u0027version\u0027: Intel(R) QuickData specfication revision\n\nThis also allows some chattiness to be removed from the driver startup\nas this information is now available via sysfs.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bf40a6869c9198bdf56fe173961feb89e9f0d961", "tree": "3d1b6bf44647857997113fe1b036fb46e360d8a7", "parents": [ "2aec048cdc4a5a81163a42a61df903f76a27e737" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:55 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:55 2009 -0700" }, "message": "ioat3: split ioat3 support to its own file, add memset\n\nUp until this point the driver for Intel(R) QuickData Technology\nengines, specification versions 2 and 3, were mostly identical save for\na few quirks. Version 3.2 hardware adds many new capabilities (like\nraid offload support) requiring some infrastructure that is not relevant\nfor v2. For better code organization of the new funcionality move v3\nand v3.2 support to its own file dma_v3.c, and export some routines from\nthe base files (dma.c and dma_v2.c) that can be reused directly.\n\nThe first new capability included in this code reorganization is support\nfor v3.2 memset operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "2aec048cdc4a5a81163a42a61df903f76a27e737", "tree": "00347decc9b145f4c805c8475b980d2641b8ec11", "parents": [ "128f2d567f906d38b11d993d8d97b9b988848e26" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:54 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:54 2009 -0700" }, "message": "ioat3: hardware version 3.2 register / descriptor definitions\n\nioat3.2 adds raid5 and raid6 offload capabilities.\n\nSigned-off-by: Tom Picard \u003ctom.s.picard@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "128f2d567f906d38b11d993d8d97b9b988848e26", "tree": "523fd4b737bd44bccddb2425ae0b16f78a819e19", "parents": [ "83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "message": "ioat2+: add fence support\n\nIn preparation for adding more operation types to the ioat3 path the\ndriver needs to honor the DMA_PREP_FENCE flag. For example the async_tx api\nwill hand xor-\u003ememcpy-\u003exor chains to the driver with the \u0027fence\u0027 flag set on\nthe first xor and the memcpy operation. This flag in turn sets the \u0027fence\u0027\nflag in the descriptor control field telling the hardware that future\ndescriptors in the chain depend on the result of the current descriptor, so\nwait for all writes to complete before starting the next operation.\n\nNote that ioat1 does not prefetch the descriptor chain, so does not\nrequire/support fenced operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7", "tree": "bc4b28c2e5bdae01a2c8a250176fcdac6ae7a8ce", "parents": [ "9308add6ea4fedeba37b0d7c4630a542bd34f214" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "message": "dmaengine, async_tx: support alignment checks\n\nSome engines have transfer size and address alignment restrictions. Add\na per-operation alignment property to struct dma_device that the async\nroutines and dmatest can use to check alignment capabilities.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9308add6ea4fedeba37b0d7c4630a542bd34f214", "tree": "5b94b9c8eebc7a7ef6879a7fdfc553c6758312dc", "parents": [ "138f4c359d23d2ec38d18bd70dd9613ae515fe93" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:52 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:52 2009 -0700" }, "message": "dmaengine: cleanup unused transaction types\n\nNo drivers currently implement these operation types, so they can be\ndeleted.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "138f4c359d23d2ec38d18bd70dd9613ae515fe93", "tree": "ad7fafba6eac74d9d92ade839a65171466d67a70", "parents": [ "0403e3827788d878163f9ef0541b748b0f88ca5d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "message": "dmaengine, async_tx: add a \"no channel switch\" allocator\n\nChannel switching is problematic for some dmaengine drivers as the\narchitecture precludes separating the -\u003eprep from -\u003esubmit. In these\ncases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify\nthe async_tx allocator to only return channels that support all of the\nrequired asynchronous operations.\n\nFor example MD_RAID456\u003dy selects support for asynchronous xor, xor\nvalidate, pq, pq validate, and memcpy. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dy any channel with all these\ncapabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to\nquickly locate compatible channels with the guarantee that dependency\nchains will remain on one channel. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dn async_tx_find_channel() may select\nchannels that lead to operation chains that need to cross channel\nboundaries using the async_tx channel switch capability.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f9dd2134374c8de6b911e2b8652c6c9622eaa658", "tree": "c1b8f8d622941606b9e7247ab31d811ba4295011", "parents": [ "4b652f0db3be891c7b76b109c3b55003b920fc96", "07a3b417dc3d00802bd7b4874c3e811f0b015a7d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:29 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:29 2009 -0700" }, "message": "Merge branch \u0027md-raid6-accel\u0027 into ioat3.2\n\nConflicts:\n\tinclude/linux/dmaengine.h\n" }, { "commit": "4b652f0db3be891c7b76b109c3b55003b920fc96", "tree": "a7747543a2076a2f58f423297e0da78b2963a04d", "parents": [ "a309218acee8606f7e235da20cc826eb06d9b0f6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:02:15 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:38:54 2009 -0700" }, "message": "net_dma: poll for a descriptor after allocation failure\n\nHandle descriptor allocation failures by polling for a descriptor. The\ndriver will force forward progress when polled. In the best case this\npolling interval will be the time it takes for one dma memcpy\ntransaction to complete. In the worst case, channel hang, we will need\nto wait 100ms for the cleanup watchdog to fire (ioatdma driver).\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a309218acee8606f7e235da20cc826eb06d9b0f6", "tree": "abf2cc9830b6a5a52a165e6a736e85cd5d7b36c0", "parents": [ "09c8a5b85e5f1e74a19bdd7c85547429d51df1cd" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:02:01 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:38:54 2009 -0700" }, "message": "ioat2,3: dynamically resize descriptor ring\n\nIncrement the allocation order of the descriptor ring every time we run\nout of descriptors up to a maximum of allocation order specified by the\nmodule parameter \u0027ioat_max_alloc_order\u0027. After each idle period\ndecrement the allocation order to a minimum order of\n\u0027ioat_ring_alloc_order\u0027 (i.e. the default ring size, tunable as a module\nparameter).\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "09c8a5b85e5f1e74a19bdd7c85547429d51df1cd", "tree": "9bb255d9f596ab062996de49032875e8b9253971", "parents": [ "ad643f54c8514998333bc6c7b201fda2267496be" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:49 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: switch watchdog and reset handler from workqueue to timer\n\nIn order to support dynamic resizing of the descriptor ring or polling\nfor a descriptor in the presence of a hung channel the reset handler\nneeds to make progress while in a non-preemptible context. The current\nworkqueue implementation precludes polling channel reset completion\nunder spin_lock().\n\nThis conversion also allows us to return to opportunistic cleanup in the\nioat2 case as the timer implementation guarantees at least one cleanup\nafter every descriptor is submitted. This means the worst case\ncompletion latency becomes the timer frequency (for exceptional\ncircumstances), but with the benefit of avoiding busy waiting when the\nlock is contended.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ad643f54c8514998333bc6c7b201fda2267496be", "tree": "c92bbecd74912ada08dfa94662b52e63d4c5df46", "parents": [ "345d852391cf3fdc73f23a9ca522c6e7b5eb5a52" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:38 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat1: trim ioat_dma_desc_sw\n\nSave 4 bytes per software descriptor by transmitting tx_cnt in an unused\nportion of the hardware descriptor.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "345d852391cf3fdc73f23a9ca522c6e7b5eb5a52", "tree": "a029ab0c4e66a6ea7c7a7b76c06bcffe92fab5e8", "parents": [ "f6ab95b55735fa03cad8d0f966647e5df206e207" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:30 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: ___devinit annotate the initialization paths\n\nMark all single use initialization routines with __devinit.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f6ab95b55735fa03cad8d0f966647e5df206e207", "tree": "958127a8b5e171d53d26cd1a40d128e34bf8c7b1", "parents": [ "bb3207863014c7310593146f11fbc6573eab43c8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: preserve chanctrl bits when re-arming interrupts\n\nThe register write in ioat_dma_cleanup_tasklet is unfortunate in two\nways:\n1/ It clears the extra \u0027enable\u0027 bits that we set at alloc_chan_resources time\n2/ It gives the impression that it disables interrupts when it is in\n fact re-arming interrupts\n\n[ Impact: fix, persist the value of the chanctrl register when re-arming ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bb3207863014c7310593146f11fbc6573eab43c8", "tree": "d54da64e459d28969cdd9250cadaaa581cbae43d", "parents": [ "4fb9b9e8d55880523db550043dfb204696dd0422" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: ignore reserved bits for chancnt and xfercap\n\nDon\u0027t trust that the reserved bits are always zero, also sanity check\nthe returned value.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "4fb9b9e8d55880523db550043dfb204696dd0422", "tree": "733a672aeb819bb8133b16329a6b5088cf9ee693", "parents": [ "6df9183a153291a2585a8dfe67597fc18c201147" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: cleanup completion status reads\n\nThe cleanup path makes an effort to only perform an atomic read of the\n64-bit completion address. However in the 32-bit case it does not\nmatter if we read the upper-32 and lower-32 non-atomically because the\nupper-32 will always be zero.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6df9183a153291a2585a8dfe67597fc18c201147", "tree": "5e5f3b3da9308e20f2dda71c85242460bb7cacfa", "parents": [ "38e12f64a165e83617c21dae3c15972fd8d639f5" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:00:55 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:23 2009 -0700" }, "message": "ioat: add some dev_dbg() calls\n\nProvide some output for debugging the driver.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "38e12f64a165e83617c21dae3c15972fd8d639f5", "tree": "43f0951cf0b91b0d831a469d0147c1c4cdd15dfa", "parents": [ "5cbafa65b92ee4f5b8ba915cddf94b91f186b989" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:00:46 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:23 2009 -0700" }, "message": "ioat1: kill unused unmap parameters\n\nThe unified ioat1/ioat2 ioat_dma_unmap() implementation derives the\nsource and dest addresses from the unmap descriptor. There is no longer\na need to track this information in struct ioat_desc_sw.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5cbafa65b92ee4f5b8ba915cddf94b91f186b989", "tree": "f074c9dbcdedf05c5567a4e456a15120895363a6", "parents": [ "dcbc853af6f0c056088e4df0794d9bf36184809e" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Aug 26 13:01:44 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat2,3: convert to a true ring buffer\n\nReplace the current linked list munged into a ring with a native ring\nbuffer implementation. The benefit of this approach is reduced overhead\nas many parameters can be derived from ring position with simple pointer\ncomparisons and descriptor allocation/freeing becomes just a\nmanipulation of head/tail pointers.\n\nIt requires a contiguous allocation for the software descriptor\ninformation.\n\nSince this arrangement is significantly different from the ioat1 chain,\nmove ioat2,3 support into its own file and header. Common routines are\nexported from driver/dma/ioat/dma.[ch].\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "dcbc853af6f0c056088e4df0794d9bf36184809e", "tree": "1cbab40167487cff6dc8984a00756cfc39dff3f3", "parents": [ "a6a39ca1badbeafc16941fcf2c1010c8c65c8ddc" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:50 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat: prepare the code for ioat[12]_dma_chan split\n\nPrepare the code for the conversion of the ioat2 linked-list-ring into a\nnative ring buffer. After this conversion ioat2 channels will share\nless of the ioat1 infrastructure, but there will still be places where\nsharing is possible. struct ioat_chan_common is created to house the\nchannel attributes that will remain common between ioat1 and ioat2\nchannels.\n\nFor every routine that accesses both common and hardware specific fields\nthe old unified \u0027ioat_chan\u0027 pointer is split into an \u0027ioat\u0027 and \u0027chan\u0027\npointer. Where \u0027chan\u0027 references common fields and \u0027ioat\u0027 the\nhardware/version specific.\n\n[ Impact: pure structure member movement/variable renames, no logic changes ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "a6a39ca1badbeafc16941fcf2c1010c8c65c8ddc", "tree": "1f6e4bf5e5ab831ce9cb6de645a1f03545c8cf0a", "parents": [ "a0587bcf3e64029a4da2a5666cad18df38db0d56" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:05 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat: fix self test interrupts\n\nIf a callback is to be attached to a descriptor the channel needs to\nknow at -\u003eprep time so it can set the interrupt enable bit. This is in\npreparation for moving descriptor ioat2 descriptor preparation from\n-\u003esubmit to -\u003eprep.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "a0587bcf3e64029a4da2a5666cad18df38db0d56", "tree": "475b3a2a7cd102f40d7c16fed431c227576c255a", "parents": [ "c7984f4e4e3af3bf8027d636283ea8658c7f80b9" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat1: move descriptor allocation from submit to prep\n\nThe async_tx api assumes that after a successful -\u003eprep a subsequent\n-\u003esubmit will not fail due to a lack of resources.\n\nThis also fixes a bug in the allocation failure case. Previously the\ndescriptors allocated prior to the allocation failure would not be\nreturned to the free list.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "c7984f4e4e3af3bf8027d636283ea8658c7f80b9", "tree": "81fb1adc44173505d447aa93142cc96a4bf03044", "parents": [ "77867fff033ea549096c49d863c564ad7d8be36f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat: define descriptor control bit-field\n\nThis cleans up a mess of and\u0027ing and or\u0027ing bit definitions, and allows\nsimple assignments from the specified dma_ctrl_flags parameter.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "77867fff033ea549096c49d863c564ad7d8be36f", "tree": "d39bce48f29aa9ce6f23f15e73fab8333d91bc75", "parents": [ "f2427e276ffec5ce599c6bc116e0927269a360ef" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: fix type mismatch for -\u003edmacount\n\n-\u003edmacount tracks the sequence number of active descriptors. It is\nwritten to the DMACOUNT register to update the channel\u0027s view of pending\ndescriptors in the chain. The register is 16-bits so -\u003edmacount should\nbe unsigned and 16-bit as well. Also modify -\u003edesccount to maintain\nalignment.\n\nThis was never a problem in practice because we never compared dmacount\nvalues, but this is a bug waiting to happen.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "f2427e276ffec5ce599c6bc116e0927269a360ef", "tree": "d23b47ad7a00daeba720c25bb900fd96bf226f54", "parents": [ "b31b78f1ab7806759622b703357e39a21f757281" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:42:38 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: split ioat_dma_probe into core/version-specific routines\n\nTowards the removal of ioatdma_device.version split the initialization\npath into distinct versions. This conversion:\n1/ moves version specific probe code to version specific routines\n2/ removes the need for ioat_device\n3/ turns off the ioat1 msi quirk if the device is reinitialized for intx\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "b31b78f1ab7806759622b703357e39a21f757281", "tree": "70144a699561184ed9d7bcd0b0f8f2b102204947", "parents": [ "bc3c70258526a635325f1f15138a96297879bc1a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:42:32 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: kill function prototype ifdef guards\n\nThe only .c files that utilize these protected prototypes depend on\nCONFIG_INTEL_IOATDMA\u003dy, so there is no value gained in providing empty\nprototypes.\n\n[ Impact: pure cleanup ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "bc3c70258526a635325f1f15138a96297879bc1a", "tree": "65ced583f975cb19dc12f498f7e97536033fe74f", "parents": [ "e6c0b69a43150c1a37cf342ce5faedf12583bf79" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:33:42 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: cleanup some long deref chains and 80 column collisions\n\n* reduce device-\u003ecommon. to dma-\u003e in ioat_dma_{probe,remove,selftest}\n* ioat_lookup_chan_by_index to ioat_chan_by_index\n* multi-line function definitions\n* ioat_desc_sw.async_tx to ioat_desc_sw.txd\n* desc-\u003etxd. to tx-\u003e in cleanup routine\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "e6c0b69a43150c1a37cf342ce5faedf12583bf79", "tree": "955456982fea62d6557ad5992f19ee3e73e64bc2", "parents": [ "1f27adc2f050836c12deb4d99afe507636537a0b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:44 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:44 2009 -0700" }, "message": "ioat: convert ioat_probe to pcim/devm\n\nThe driver currently duplicates much of what these routines offer, so\njust use the common code. For example -\u003eirq_mode tracks what interrupt\nmode was initialized, which duplicates the -\u003emsix_enabled and\n-\u003emsi_enabled handling in pcim_release.\n\nThis also adds a check to the return value of dma_async_device_register,\nwhich can fail.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "1f27adc2f050836c12deb4d99afe507636537a0b", "tree": "aeb0b1a0896dd1367174a46d29c7ebc18187a4f9", "parents": [ "584ec22759c06cdfc189c03a727f20038526245b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:02 2009 -0700" }, "message": "ioat: move definitions to dma.h\n\nSome of these defines may be useful outside of dma.c and the header is\nprivate so there are no namespace pollution concerns.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "a348a7e6fdbcd2d5192a09719a479bb238fde727", "tree": "5ff94185f4e5a810777469d7fe7832a8ec2d3430", "parents": [ "808347f6a31792079e345ec865e9cfcb6e8ae6b2", "28d0325ce6e0a52f53d8af687e6427fee59004d3" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 14:32:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 14:32:24 2009 -0700" }, "message": "Merge commit \u0027v2.6.31-rc1\u0027 into dmaengine\n" }, { "commit": "f6dbf651615900646fe0ba1ef5ce1027e5b4748d", "tree": "a78d096174765ce893dddfd6fed9e5e92d45aaaa", "parents": [ "7bf649aee8ac93ecc280f8745dcf8ec19d7b9fb1" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:40 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:40 2009 -0700" }, "message": "iop-adma: P+Q self test\n\nEven though the intent is to extend dmatest with P+Q tests there is\nstill value in having an always-on sanity check to prevent an\nunintentionally broken driver from registering.\n\nThis depends on raid6_pq.ko for verification, the side effect being that\nPQ capable channels will fail to register when raid6 is disabled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "7bf649aee8ac93ecc280f8745dcf8ec19d7b9fb1", "tree": "b35282323d278afb16c18a42c8c0db34508cef6c", "parents": [ "72be12f0c39df46832403cbfd82e132a883f5ddc" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Aug 28 14:32:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:39 2009 -0700" }, "message": "iop-adma: P+Q support for iop13xx adma engines\n\niop33x support is not included because that engine is a bit more awkward\nto handle in that it can either be in xor mode or pq mode. The\ndmaengine/async_tx layers currently only comprehend static capabilities.\n\nNote iop13xx does not support hardware PQ continuation so the driver\nmust handle the DMA_PREP_CONTINUE flag for operations across \u003e 16\nsources. From the comment for dma_maxpq:\n\n/* When an engine does not support native continuation we need 3 extra\n * source slots to reuse P and Q with the following coefficients:\n * 1/ {00} * P : remove P from Q\u0027, but use it as a source for P\u0027\n * 2/ {01} * Q : use Q to continue Q\u0027 calculation\n * 3/ {00} * Q : subtract Q from P\u0027 to cancel (2)\n */\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n\n\n" }, { "commit": "72be12f0c39df46832403cbfd82e132a883f5ddc", "tree": "61a4014d28852692464aca3f509d2024e7006f68", "parents": [ "507fbec4cff442ebce6706db34603bfb9cc3b5a9" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 13:38:29 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:39 2009 -0700" }, "message": "iop-adma: fix lockdep false positive\n\nlockdep correctly identifies a potential recursive locking case for\niop_chan-\u003elock, but in the dependency submission case we expect that the same\nclass will be acquired for both the parent dependency and the child channel.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "507fbec4cff442ebce6706db34603bfb9cc3b5a9", "tree": "781901167ab7d2ed2f064d9a0e6faa2e87148165", "parents": [ "cb3c82992f62f838e6476a0bff12909158007fc6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:39 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:39 2009 -0700" }, "message": "iop-adma: cleanup iop_adma_run_tx_complete_actions\n\nReplace \u0027desc-\u003easync_tx.\u0027 with \u0027tx-\u003e\u0027\n\n[ Impact: pure cleanup ]\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "58691d64c44ae41ddf098ecb31e9a994026e3cff", "tree": "93c36b2d244648a9b5880dc97de3cb945fdebda7", "parents": [ "0a82a6239beecc95db6e05fe43ee62d16b381d38" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "dmatest: add pq support\n\nTest raid6 p+q operations with a simple \"always multiply by 1\" q\ncalculation to fit into dmatest\u0027s current destination verification\nscheme.\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "b2f46fd8ef3dff2ab30f31126833f78b7480283a", "tree": "9f111e3e313b4d142c12d2d8156a2704a36904f8", "parents": [ "95475e57113c66aac7583925736ed2e2d58c990d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:20:36 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "async_tx: add support for asynchronous GF multiplication\n\n[ Based on an original patch by Yuri Tikhonov ]\n\nThis adds support for doing asynchronous GF multiplication by adding\ntwo additional functions to the async_tx API:\n\n async_gen_syndrome() does simultaneous XOR and Galois field\n multiplication of sources.\n\n async_syndrome_val() validates the given source buffers against known P\n and Q values.\n\nWhen a request is made to run async_pq against more than the hardware\nmaximum number of supported sources we need to reuse the previous\ngenerated P and Q values as sources into the next operation. Care must\nbe taken to remove Q from P\u0027 and P from Q\u0027. For example to perform a 5\nsource pq op with hardware that only supports 4 sources at a time the\nfollowing approach is taken:\n\np, q \u003d PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))\np\u0027, q\u0027 \u003d PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))\n\np\u0027 \u003d p + q + q + src4 \u003d p + src4\nq\u0027 \u003d {00}*p + {01}*q + {00}*q + {10}*src4 \u003d q + {10}*src4\n\nNote: 4 is the minimum acceptable maxpq otherwise we punt to\nsynchronous-software path.\n\nThe DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as\nsources (in the above manner) and fill the remaining slots up to maxpq\nwith the new sources/coefficients.\n\nNote1: Some devices have native support for P+Q continuation and can skip\nthis extra work. Devices with this capability can advertise it with\ndma_set_maxpq. It is up to each driver how to handle the\nDMA_PREP_CONTINUE flag.\n\nNote2: The api supports disabling the generation of P when generating Q,\nthis is ignored by the synchronous path but is implemented by some dma\ndevices to save unnecessary writes. In this case the continuation\nalgorithm is simplified to only reuse Q as a source.\n\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "95475e57113c66aac7583925736ed2e2d58c990d", "tree": "933aa0ca3bffef5b1457c516fbe3e8690b4c4cb1", "parents": [ "af1f951eb6ef27b01cbfb3f6c21b770af4368a6d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:19:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "async_tx: remove walk of tx-\u003eparent chain in dma_wait_for_async_tx\n\nWe currently walk the parent chain when waiting for a given tx to\ncomplete however this walk may race with the driver cleanup routine.\nThe routines in async_raid6_recov.c may fall back to the synchronous\npath at any point so we need to be prepared to call async_tx_quiesce()\n(which calls dma_wait_for_async_tx). To remove the -\u003eparent walk we\nguarantee that every time a dependency is attached -\u003eissue_pending() is\ninvoked, then we can simply poll the initial descriptor until\ncompletion.\n\nThis also allows for a lighter weight \u0027issue pending\u0027 implementation as\nthere is no longer a requirement to iterate through all the channels\u0027\n-\u003eissue_pending() routines as long as operations have been submitted in\nan ordered chain. async_tx_issue_pending() is added for this case.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "c00aafcd4977769e8728292302ddbbb8b1082fab", "tree": "5766bcfbfd7b24816b54298b8ef34054f8cf0fae", "parents": [ "2e6713c7662cc5ebc7346b033c404cb2f708fd51", "90bc1a658a53f8832ee799685703977a450e5af9" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Aug 05 23:56:54 2009 +0200" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Aug 05 23:56:54 2009 +0200" }, "message": "Merge branch \u0027master\u0027 into for-linus\n" }, { "commit": "db06816cb9ceb21a2bf24122407b7b4fe419c3fc", "tree": "25a96cbc392edfe35ea6dcfaa4b0b2a7601d779d", "parents": [ "784b1d6b21cb25791b68276af27a7c2321d5a86f", "808347f6a31792079e345ec865e9cfcb6e8ae6b2" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jul 30 16:46:31 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jul 30 16:46:31 2009 -0700" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n dmaengine: at_hdmac: add DMA slave transfers\n dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller\n dmaengine: dmatest: correct thread_count while using multiple thread per channel\n dmaengine: dmatest: add a maximum number of test iterations\n drivers/dma: Remove unnecessary semicolons\n drivers/dma/fsldma.c: Remove unnecessary semicolons\n dmaengine: move HIGHMEM64G restriction to ASYNC_TX_DMA\n fsldma: do not clear bandwidth control bits on the 83xx controller\n fsldma: enable external start for the 83xx controller\n fsldma: use PCI Read Multiple command\n" }, { "commit": "584ec22759c06cdfc189c03a727f20038526245b", "tree": "54f4ebb99c3f66f62aeb38d091d1840d88e2ee57", "parents": [ "07a2039b8eb0af4ff464efd3dfd95de5c02648c6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:32:12 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:32:12 2009 -0700" }, "message": "ioat: move to drivers/dma/ioat/\n\nWhen first created the ioat driver was the only inhabitant of\ndrivers/dma/. Now, it is the only multi-file (more than a .c and a .h)\ndriver in the directory. Moving it to an ioat/ subdirectory allows the\nnaming convention to be cleaned up, and allows for future splitting of\nthe source files by hardware version (v1, v2, and v3).\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "808347f6a31792079e345ec865e9cfcb6e8ae6b2", "tree": "05fe2e32712d84ec5dc7553033432712313f6ba2", "parents": [ "dc78baa2b90b289590911b40b6800f77d0dc935a" ], "author": { "name": "Nicolas Ferre", "email": "nicolas.ferre@atmel.com", "time": "Wed Jul 22 20:04:45 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 22 23:15:33 2009 -0700" }, "message": "dmaengine: at_hdmac: add DMA slave transfers\n\nThis patch for at_hdmac adds the slave transfers capability to the Atmel DMA\ncontroller available on some AT91 SOCs. This allow peripheral to memory and\nmemory to peripheral transfers with hardware handshaking.\n\nSlave structure for controller specific information is passed through channel\nprivate data. This at_dma_slave structure is defined in at_hdmac.h header file\nand relative hardware definition are moved to this file from at_hdmac_regs.h.\nDoing this we allow the channel configuration from platform definition code.\n\nThis work is intensively based on dw_dmac and several slave implementations.\n\nSigned-off-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "dc78baa2b90b289590911b40b6800f77d0dc935a", "tree": "db54dedb1e13a413190ad637ccaf6f5557dc9c10", "parents": [ "f1aef8b6e6abf32a3a269542f95a19e2cb319f6c" ], "author": { "name": "Nicolas Ferre", "email": "nicolas.ferre@atmel.com", "time": "Fri Jul 03 19:24:33 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 22 22:41:27 2009 -0700" }, "message": "dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller\n\nThis AHB DMA Controller (aka HDMA or DMAC on AT91 systems) is availlable on\nat91sam9rl chip. It will be used on other products in the future.\n\nThis first release covers only the memory-to-memory tranfer type. This is the\nonly tranfer type supported by this chip. On other products, it will be used\nalso for peripheral DMA transfer (slave API support to come).\n\nI used dmatest client without problem in different configurations to test it.\n\nFull documentation for this controller can be found in the SAM9RL datasheet:\nhttp://www.atmel.com/dyn/products/product_card.asp?part_id\u003d4243\n\nSigned-off-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f1aef8b6e6abf32a3a269542f95a19e2cb319f6c", "tree": "f364595263d6c99487bbbcfb4767326694bb2aff", "parents": [ "0a2ff57d6fba92842272889b4bca447344cd9d36" ], "author": { "name": "Nicolas Ferre", "email": "nicolas.ferre@atmel.com", "time": "Mon Jul 06 18:19:44 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 22 22:11:28 2009 -0700" }, "message": "dmaengine: dmatest: correct thread_count while using multiple thread per channel\n\nIt seems that thread_count is not properly calculated in dmatest.\nIn fact the thread count number that is returned from dmatest_add_threads() is\nnot correctly added to the thread_count and thus not properly printed.\n\nSigned-off-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nAcked-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0a2ff57d6fba92842272889b4bca447344cd9d36", "tree": "91dbcb3d8a668f1aac6c2859921294e74df70b66", "parents": [ "c019894efc9c9ba5939948caa78c133b1ec8ae63" ], "author": { "name": "Nicolas Ferre", "email": "nicolas.ferre@atmel.com", "time": "Fri Jul 03 19:26:51 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 22 22:05:26 2009 -0700" }, "message": "dmaengine: dmatest: add a maximum number of test iterations\n\nThe dmatest usually waits for the killing of its kthreads to stop\nrunning tests. This patch adds a parameter that sets a maximum\nnumber of test iterations.\n\nThis feature is quite interesting for debugging when you set a lot of\ntraces in your dmaengine controller driver.\n\nSigned-off-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "c019894efc9c9ba5939948caa78c133b1ec8ae63", "tree": "4ecec80e15bd9f50598aca7020b630e12a4a149d", "parents": [ "e3d433040ee6077e33d4ad22e2f60a38b085786d" ], "author": { "name": "Joe Perches", "email": "joe@perches.com", "time": "Sun Jun 28 09:26:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 22 21:29:16 2009 -0700" }, "message": "drivers/dma: Remove unnecessary semicolons\n\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e3d433040ee6077e33d4ad22e2f60a38b085786d", "tree": "48fdd979c9062e032b868524082f625d43c97cf6", "parents": [ "daf4219dbcbb2efcd638fcd3c29a622e1c18cc38" ], "author": { "name": "Joe Perches", "email": "joe@perches.com", "time": "Sun Jun 28 09:26:20 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 22 21:29:16 2009 -0700" }, "message": "drivers/dma/fsldma.c: Remove unnecessary semicolons\n\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "4aebac2fb9645e897864e12cdb8d1e4aadf5b2a4", "tree": "45dbbdc9a75cb12bfbf908588f9984a7dad70aae", "parents": [ "4a256b5fc028e6dad0fd1b59745f743ee528c944" ], "author": { "name": "Magnus Damm", "email": "damm@igel.co.jp", "time": "Wed Jul 08 13:22:27 2009 +0200" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Jul 22 00:28:39 2009 +0200" }, "message": "DMA: Rework txx9dmac suspend_late()/resume_early()\n\nThis patch reworks platform driver power management code\nfor txx9dmac from legacy late/early callbacks to dev_pm_ops.\n\nThe callbacks are converted for CONFIG_SUSPEND like this:\n suspend_late() -\u003e suspend_noirq()\n resume_early() -\u003e resume_noirq()\n\nSigned-off-by: Magnus Damm \u003cdamm@igel.co.jp\u003e\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nAcked-by: Pavel Machek \u003cpavel@ucw.cz\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\n" }, { "commit": "4a256b5fc028e6dad0fd1b59745f743ee528c944", "tree": "1c2c17ccb80051c16ee9e16ea74194bd69fac72f", "parents": [ "79ee031ff6fd23a1a2a4f783cfc3421885304ce3" ], "author": { "name": "Magnus Damm", "email": "damm@igel.co.jp", "time": "Wed Jul 08 13:22:18 2009 +0200" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Jul 22 00:28:38 2009 +0200" }, "message": "DMA: Rework dw_dmac suspend_late()/resume_early()\n\nThis patch reworks platform driver power management code\nfor dw_dmac from legacy late/early callbacks to dev_pm_ops.\n\nThe callbacks are converted for CONFIG_SUSPEND like this:\n suspend_late() -\u003e suspend_noirq()\n resume_early() -\u003e resume_noirq()\n\nSigned-off-by: Magnus Damm \u003cdamm@igel.co.jp\u003e\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nAcked-by: Pavel Machek \u003cpavel@ucw.cz\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\n" }, { "commit": "daf4219dbcbb2efcd638fcd3c29a622e1c18cc38", "tree": "8683d86a8a8de2060c83aed7efe5f66b94027a2b", "parents": [ "43a1a3ed6bf5a1b9ae197b4f5f20033baf19db61" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 01 16:12:53 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 01 16:12:53 2009 -0700" }, "message": "dmaengine: move HIGHMEM64G restriction to ASYNC_TX_DMA\n\nOn HIGHMEM64G systems dma_addr_t is known to be larger than (void *)\nwhich precludes async_xor from performing dma address conversions by\nreusing the input parameter address list. However, other parts of the\ndmaengine infrastructure do not suffer this constraint, so the\nHIGHMEM64G restriction can be down-levelled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "4ac4aa5cc3b00cc558575065ae71043e92d1a69a", "tree": "77000115ec386bca50c5519e3695799ebb6915b8", "parents": [ "2e25406fb878e2313a9d8e302ed7ff3c2831198f" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Wed Jun 17 13:08:31 2009 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Jun 24 18:34:40 2009 +0100" }, "message": "DMA: txx9dmac: use dma_unmap_single if DMA_COMPL_{SRC,DEST}_UNMAP_SINGLE set\n\nThis patch does not change actual behaviour since dma_unmap_page is just\nan alias of dma_unmap_single on MIPS.\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ea76f0b3759283ec3cc06c86e266bf0fa6a981d2", "tree": "36719ab69e7d94cc59c909526022219376807313", "parents": [ "a43da03ca4719276b9601730627d20b2a71fb6ba" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Thu Apr 23 00:40:30 2009 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Jun 17 11:06:25 2009 +0100" }, "message": "DMA: TXx9 Soc DMA Controller driver\n\nThis patch adds support for the integrated DMAC of the TXx9 family.\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "43a1a3ed6bf5a1b9ae197b4f5f20033baf19db61", "tree": "e14df96fd17ae32d4d3b77d881de7080947e7fb2", "parents": [ "be30b226f2ae618cd719e40267d9923db1db9001" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Thu May 28 09:26:40 2009 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jun 16 11:43:40 2009 -0700" }, "message": "fsldma: do not clear bandwidth control bits on the 83xx controller\n\nThe 83xx controller does not support the external pause feature. The bit\nin the mode register that controls external pause on the 85xx controller\nhappens to be part of the bandwidth control settings for the 83xx\ncontroller.\n\nThis patch fixes the driver so that it only clears the external pause bit\nif the hardware is the 85xx controller. When driving the 83xx controller,\nthe bit is left untouched. This follows the existing convention that mode\nregisters settings are not touched unless necessary.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "be30b226f2ae618cd719e40267d9923db1db9001", "tree": "3a260d33973214ce50c27d335da37c1eccd04fe3", "parents": [ "a7aea373b4ca428f1be2c1fedd2f26c8e3f2864d" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Thu May 28 09:20:42 2009 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jun 16 11:43:00 2009 -0700" }, "message": "fsldma: enable external start for the 83xx controller\n\nThe 83xx controller has external start capability, but lacks external pause\ncapability. Hook up the external start function pointer for the 83xx\ncontroller.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a7aea373b4ca428f1be2c1fedd2f26c8e3f2864d", "tree": "ca05d01f882aee0f5fd54fd6f649ca0ab566f938", "parents": [ "07a2039b8eb0af4ff464efd3dfd95de5c02648c6" ], "author": { "name": "Ira W. Snyder", "email": "iws@ovro.caltech.edu", "time": "Thu Apr 23 16:17:54 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jun 16 11:29:17 2009 -0700" }, "message": "fsldma: use PCI Read Multiple command\n\nBy default, the Freescale 83xx DMA controller uses the PCI Read Line\ncommand when reading data over the PCI bus. Setting the controller to use\nthe PCI Read Multiple command instead allows the controller to read much\nlarger bursts of data, which provides a drastic speed increase.\n\nThe slowdown due to using PCI Read Line was only observed when a PCI-to-PCI\nbridge was between the devices trying to communicate.\n\nA simple test driver showed an increase from 4MB/sec to 116MB/sec when\nperforming DMA over the PCI bus. Using DMA to transfer between blocks of\nlocal SDRAM showed no change in performance with this patch. The dmatest\ndriver was also used to verify the correctness of the transfers, and showed\nno errors.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nAcked-by: Timur Tabi \u003ctimur@freescale.com\u003e\nAcked-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "04ce9ab385dc97eb55299d533cd3af79b8fc7529", "tree": "9b8d0b9c1eba820a8a107d05abc2e2f8d4d20a59", "parents": [ "a08abd8ca890a377521d65d493d174bebcaf694b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jun 03 14:22:28 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jun 03 14:22:28 2009 -0700" }, "message": "async_xor: permit callers to pass in a \u0027dma/page scribble\u0027 region\n\nasync_xor() needs space to perform dma and page address conversions. In\nmost cases the code can simply reuse the struct page * array because the\nsize of the native pointer matches the size of a dma/page address. In\norder to support archs where sizeof(dma_addr_t) is larger than\nsizeof(struct page *), or to preserve the input parameters, we utilize a\nmemory region passed in by the caller.\n\nSince the code is now prepared to handle the case where it cannot\nperform address conversions on the stack, we no longer need the\n!HIGHMEM64G dependency in drivers/dma/Kconfig.\n\n[ Impact: don\u0027t clobber input buffers for address conversions ]\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "3b798a5231be15411225b99dc1217580e8d6ae1f", "tree": "848bb9a60c0c2cf733b425c31d84c9d651b9e65e", "parents": [ "228b60acaa4529c2208ee7a420f6a12b464ce285", "6afec830acc75a4dc4a7547c66fbf18152c946ef" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat May 30 07:57:44 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat May 30 07:57:44 2009 -0700" }, "message": "Merge branch \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6\n\n* \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6:\n ACPI, i915: build fix (v2)\n acpi-cpufreq: fix printk typo and indentation\n ACPI processor: remove spurious newline from warning message\n drm/i915: acpi/video.c fix section mismatch warning\n ACPI: video: DMI workaround broken Acer 5315 BIOS enabling display brightness\n ACPI: video: DMI workaround broken eMachines E510 BIOS enabling display brightness\n ACPI: sanity check _PSS frequency to prevent cpufreq crash\n i7300_idle: allow testing on i5000-series hardware w/o re-compile\n PCI/ACPI: fix wrong ref count handling in acpi_pci_bind()\n cpuidle: fix AMD C1E suspend hang\n cpuidle: makes AMD C1E work in acpi_idle\n" }, { "commit": "2f102607ac77354b02a76cf2748598ce9f270f08", "tree": "922513b874c12a9fe75bba02e94c24388f21dc35", "parents": [ "cd86a536c81e9300d984327517548ca0652eebf9" ], "author": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed May 27 23:59:58 2009 -0400" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Thu May 28 20:52:40 2009 -0400" }, "message": "i7300_idle: allow testing on i5000-series hardware w/o re-compile\n\nTesting the i7300_idle driver on i5000-series hardware required\nan edit to i7300_idle.h to \"#define SUPPORT_I5000 1\" and a re-build\nof both i7300_idle and ioat_dma.\n\nReplace that build-time scheme with a load-time module parameter:\n\"7300_idle.forceload\u003d1\" to make it easier to test the driver\non hardware that while not officially validated, works fine\nand is much more commonly available.\n\nBy default (no modparam) the driver will continue to load\nonly on the i7300.\n\nNote that ioat_dma runs a copy of i7300_idle\u0027s probe routine\nto know to reserve an IOAT channel for i7300_idle.\nThis change makes ioat_dma do that always on the i5000,\njust like it does on the i7300.\n\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\nAcked-by: Andrew Henroid \u003candrew.d.henroid@intel.com\u003e\n" } ], "next": "b787f2e2a37a373a045f4d9b9bed941ccff01663" }