| /* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| */ |
| |
| #include <linux/init.h> |
| #include <linux/ioport.h> |
| #include <linux/platform_device.h> |
| #include <linux/bootmem.h> |
| #include <linux/gpio.h> |
| #include <asm/mach-types.h> |
| #include <asm/mach/mmc.h> |
| #include <mach/msm_bus_board.h> |
| #include <mach/board.h> |
| #include <mach/gpiomux.h> |
| #include <mach/socinfo.h> |
| #include "devices.h" |
| |
| #include "board-8930.h" |
| #include "board-storage-common-a.h" |
| |
| enum sdcc_controllers { |
| SDCC1, |
| SDCC2, |
| SDCC3, |
| SDCC4, |
| SDCC5, |
| MAX_SDCC_CONTROLLER |
| }; |
| |
| static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = { |
| |
| [SDCC1] = { |
| .name = "sdc_vdd", |
| .high_vol_level = 2950000, |
| .low_vol_level = 2950000, |
| .always_on = 1, |
| .lpm_sup = 1, |
| .lpm_uA = 9000, |
| .hpm_uA = 200000, |
| }, |
| |
| [SDCC2] = { |
| .name = "sdc_vdd", |
| .high_vol_level = 1800000, |
| .low_vol_level = 1800000, |
| .hpm_uA = 200000, |
| }, |
| |
| [SDCC3] = { |
| .name = "sdc_vdd", |
| .high_vol_level = 2950000, |
| .low_vol_level = 2950000, |
| .lpm_sup = 1, |
| .hpm_uA = 800000, |
| .lpm_uA = 9000, |
| }, |
| }; |
| |
| static struct msm_mmc_reg_data mmc_vdd_io_reg_data[MAX_SDCC_CONTROLLER] = { |
| |
| [SDCC1] = { |
| .name = "sdc_vdd_io", |
| .always_on = 1, |
| .high_vol_level = 1800000, |
| .low_vol_level = 1800000, |
| .hpm_uA = 200000, |
| }, |
| |
| [SDCC3] = { |
| .name = "sdc_vdd_io", |
| .high_vol_level = 2950000, |
| .low_vol_level = 1850000, |
| .always_on = 1, |
| .lpm_sup = 1, |
| |
| .hpm_uA = 16000, |
| .lpm_uA = 2000, |
| }, |
| }; |
| |
| static struct msm_mmc_slot_reg_data mmc_slot_vreg_data[MAX_SDCC_CONTROLLER] = { |
| |
| [SDCC1] = { |
| .vdd_data = &mmc_vdd_reg_data[SDCC1], |
| .vdd_io_data = &mmc_vdd_io_reg_data[SDCC1], |
| }, |
| |
| [SDCC2] = { |
| .vdd_data = &mmc_vdd_reg_data[SDCC2], |
| }, |
| |
| [SDCC3] = { |
| .vdd_data = &mmc_vdd_reg_data[SDCC3], |
| .vdd_io_data = &mmc_vdd_io_reg_data[SDCC3], |
| } |
| }; |
| |
| static struct msm_mmc_pad_drv sdc1_pad_drv_on_cfg[] = { |
| {TLMM_HDRV_SDC1_CLK, GPIO_CFG_16MA}, |
| {TLMM_HDRV_SDC1_CMD, GPIO_CFG_10MA}, |
| {TLMM_HDRV_SDC1_DATA, GPIO_CFG_10MA} |
| }; |
| |
| static struct msm_mmc_pad_drv sdc1_pad_drv_off_cfg[] = { |
| {TLMM_HDRV_SDC1_CLK, GPIO_CFG_2MA}, |
| {TLMM_HDRV_SDC1_CMD, GPIO_CFG_2MA}, |
| {TLMM_HDRV_SDC1_DATA, GPIO_CFG_2MA} |
| }; |
| |
| static struct msm_mmc_pad_pull sdc1_pad_pull_on_cfg[] = { |
| {TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL}, |
| {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP}, |
| {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP} |
| }; |
| |
| static struct msm_mmc_pad_pull sdc1_pad_pull_off_cfg[] = { |
| {TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL}, |
| {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP}, |
| {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP} |
| }; |
| |
| static struct msm_mmc_pad_drv sdc3_pad_drv_on_cfg[] = { |
| {TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA}, |
| {TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA}, |
| {TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA} |
| }; |
| |
| static struct msm_mmc_pad_drv sdc3_pad_drv_off_cfg[] = { |
| {TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA}, |
| {TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA}, |
| {TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA} |
| }; |
| |
| static struct msm_mmc_pad_pull sdc3_pad_pull_on_cfg[] = { |
| {TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL}, |
| {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP}, |
| {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP} |
| }; |
| |
| static struct msm_mmc_pad_pull sdc3_pad_pull_off_cfg[] = { |
| {TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL}, |
| {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP}, |
| {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP} |
| }; |
| |
| static struct msm_mmc_gpio sdc2_gpio[] = { |
| {92, "sdc2_dat_3"}, |
| {91, "sdc2_dat_2"}, |
| {90, "sdc2_dat_1"}, |
| {89, "sdc2_dat_0"}, |
| {97, "sdc2_cmd"}, |
| {98, "sdc2_clk"} |
| }; |
| |
| static struct msm_mmc_pad_pull_data mmc_pad_pull_data[MAX_SDCC_CONTROLLER] = { |
| [SDCC1] = { |
| .on = sdc1_pad_pull_on_cfg, |
| .off = sdc1_pad_pull_off_cfg, |
| .size = ARRAY_SIZE(sdc1_pad_pull_on_cfg) |
| }, |
| [SDCC3] = { |
| .on = sdc3_pad_pull_on_cfg, |
| .off = sdc3_pad_pull_off_cfg, |
| .size = ARRAY_SIZE(sdc3_pad_pull_on_cfg) |
| }, |
| }; |
| |
| static struct msm_mmc_pad_drv_data mmc_pad_drv_data[MAX_SDCC_CONTROLLER] = { |
| [SDCC1] = { |
| .on = sdc1_pad_drv_on_cfg, |
| .off = sdc1_pad_drv_off_cfg, |
| .size = ARRAY_SIZE(sdc1_pad_drv_on_cfg) |
| }, |
| [SDCC3] = { |
| .on = sdc3_pad_drv_on_cfg, |
| .off = sdc3_pad_drv_off_cfg, |
| .size = ARRAY_SIZE(sdc3_pad_drv_on_cfg) |
| }, |
| }; |
| |
| static struct msm_mmc_pad_data mmc_pad_data[MAX_SDCC_CONTROLLER] = { |
| [SDCC1] = { |
| .pull = &mmc_pad_pull_data[SDCC1], |
| .drv = &mmc_pad_drv_data[SDCC1] |
| }, |
| [SDCC3] = { |
| .pull = &mmc_pad_pull_data[SDCC3], |
| .drv = &mmc_pad_drv_data[SDCC3] |
| }, |
| }; |
| |
| static struct msm_mmc_gpio_data mmc_gpio_data[MAX_SDCC_CONTROLLER] = { |
| [SDCC2] = { |
| .gpio = sdc2_gpio, |
| .size = ARRAY_SIZE(sdc2_gpio), |
| }, |
| }; |
| |
| static struct msm_mmc_pin_data mmc_slot_pin_data[MAX_SDCC_CONTROLLER] = { |
| [SDCC1] = { |
| .pad_data = &mmc_pad_data[SDCC1], |
| }, |
| [SDCC2] = { |
| .is_gpio = true, |
| .gpio_data = &mmc_gpio_data[SDCC2], |
| }, |
| [SDCC3] = { |
| .pad_data = &mmc_pad_data[SDCC3], |
| }, |
| }; |
| |
| #define MSM_MPM_PIN_SDC1_DAT1 17 |
| #define MSM_MPM_PIN_SDC3_DAT1 21 |
| |
| static unsigned int sdc1_sup_clk_rates[] = { |
| 400000, 24000000, 48000000, 96000000 |
| }; |
| |
| #ifdef CONFIG_MMC_MSM_SDC3_SUPPORT |
| static unsigned int sdc3_sup_clk_rates[] = { |
| 400000, 24000000, 48000000, 96000000, 192000000, |
| }; |
| #endif |
| |
| #ifdef CONFIG_MMC_MSM_SDC1_SUPPORT |
| static struct mmc_platform_data msm8960_sdc1_data = { |
| .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, |
| #ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT |
| .mmc_bus_width = MMC_CAP_8_BIT_DATA, |
| #else |
| .mmc_bus_width = MMC_CAP_4_BIT_DATA, |
| #endif |
| .sup_clk_table = sdc1_sup_clk_rates, |
| .sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates), |
| .nonremovable = 1, |
| .vreg_data = &mmc_slot_vreg_data[SDCC1], |
| .pin_data = &mmc_slot_pin_data[SDCC1], |
| .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC1_DAT1, |
| .msm_bus_voting_data = &sps_to_ddr_bus_voting_data, |
| .uhs_caps2 = MMC_CAP2_HS200_1_8V_SDR, |
| }; |
| #endif |
| |
| #ifdef CONFIG_MMC_MSM_SDC2_SUPPORT |
| static unsigned int sdc2_sup_clk_rates[] = { |
| 400000, 24000000, 48000000 |
| }; |
| |
| static struct mmc_platform_data msm8960_sdc2_data = { |
| .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28 | MMC_VDD_28_29, |
| .mmc_bus_width = MMC_CAP_4_BIT_DATA, |
| .sup_clk_table = sdc2_sup_clk_rates, |
| .sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates), |
| .vreg_data = &mmc_slot_vreg_data[SDCC2], |
| .pin_data = &mmc_slot_pin_data[SDCC2], |
| .sdiowakeup_irq = MSM_GPIO_TO_INT(90), |
| .msm_bus_voting_data = &sps_to_ddr_bus_voting_data, |
| }; |
| #endif |
| |
| #ifdef CONFIG_MMC_MSM_SDC3_SUPPORT |
| static struct mmc_platform_data msm8960_sdc3_data = { |
| .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, |
| .mmc_bus_width = MMC_CAP_4_BIT_DATA, |
| .sup_clk_table = sdc3_sup_clk_rates, |
| .sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates), |
| #ifdef CONFIG_MMC_MSM_SDC3_WP_SUPPORT |
| #ifndef MSM8930_PHASE_2 |
| .wpswitch_gpio = PM8921_GPIO_PM_TO_SYS(16), |
| #else |
| .wpswitch_gpio = 66, |
| .is_wpswitch_active_low = true, |
| #endif |
| #endif |
| .vreg_data = &mmc_slot_vreg_data[SDCC3], |
| .pin_data = &mmc_slot_pin_data[SDCC3], |
| #ifndef MSM8930_PHASE_2 |
| .status_gpio = PM8921_GPIO_PM_TO_SYS(26), |
| .status_irq = PM8921_GPIO_IRQ(PM8921_IRQ_BASE, 26), |
| #else |
| .status_gpio = 94, |
| .status_irq = MSM_GPIO_TO_INT(94), |
| #endif |
| .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, |
| .is_status_gpio_active_low = true, |
| .xpc_cap = 1, |
| .uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | |
| MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | |
| MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_800), |
| .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1, |
| .msm_bus_voting_data = &sps_to_ddr_bus_voting_data, |
| }; |
| #endif |
| |
| void __init msm8930_init_mmc(void) |
| { |
| #ifdef CONFIG_MMC_MSM_SDC1_SUPPORT |
| if (!machine_is_msm8930_cdp()) |
| msm8960_sdc1_data.uhs_caps |= (MMC_CAP_1_8V_DDR | |
| MMC_CAP_UHS_DDR50); |
| |
| msm_add_sdcc(1, &msm8960_sdc1_data); |
| #endif |
| #ifdef CONFIG_MMC_MSM_SDC2_SUPPORT |
| |
| msm_add_sdcc(2, &msm8960_sdc2_data); |
| #endif |
| #ifdef CONFIG_MMC_MSM_SDC3_SUPPORT |
| if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1 && |
| SOCINFO_VERSION_MINOR(socinfo_get_version()) < 2) { |
| msm8960_sdc3_data.vreg_data->vdd_data->always_on = true; |
| msm8960_sdc3_data.vreg_data->vdd_data->reset_at_init = true; |
| } |
| |
| if (!machine_is_msm8930_cdp()) { |
| msm8960_sdc3_data.wpswitch_gpio = 0; |
| msm8960_sdc3_data.is_wpswitch_active_low = false; |
| } |
| |
| msm_add_sdcc(3, &msm8960_sdc3_data); |
| #endif |
| } |