Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
diff --git a/drivers/net/skfp/h/cmtdef.h b/drivers/net/skfp/h/cmtdef.h
new file mode 100644
index 0000000..603982d
--- /dev/null
+++ b/drivers/net/skfp/h/cmtdef.h
@@ -0,0 +1,763 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+#ifndef _CMTDEF_
+#define _CMTDEF_
+
+/* **************************************************************** */
+
+/*
+ * implementation specific constants
+ * MODIIFY THE FOLLWOING THREE DEFINES
+ */
+#define AMDPLC /* if Amd PLC chip used */
+#ifdef CONC
+#define NUMPHYS 12 /* 2 for SAS or DAS, more for Concentrator */
+#else
+#ifdef CONC_II
+#define NUMPHYS 24 /* 2 for SAS or DAS, more for Concentrator */
+#else
+#define NUMPHYS 2 /* 2 for SAS or DAS, more for Concentrator */
+#endif
+#endif
+#define NUMMACS 1 /* only 1 supported at the moment */
+#define NUMPATHS 2 /* primary and secondary path supported */
+
+/*
+ * DO NOT MODIFY BEYOND THIS POINT
+ */
+
+/* **************************************************************** */
+
+#if NUMPHYS > 2
+#define CONCENTRATOR
+#endif
+
+/*
+ * Definitions for comfortable LINT usage
+ */
+#ifdef lint
+#define LINT_USE(x) (x)=(x)
+#else
+#define LINT_USE(x)
+#endif
+
+#ifdef DEBUG
+#define DB_PR(flag,a,b,c) { if (flag) printf(a,b,c) ; }
+#else
+#define DB_PR(flag,a,b,c)
+#endif
+
+#ifdef DEBUG_BRD
+#define DB_ECM(a,b,c) DB_PR((smc->debug.d_smt&1),a,b,c)
+#define DB_ECMN(n,a,b,c) DB_PR((smc->debug.d_ecm >=(n)),a,b,c)
+#define DB_RMT(a,b,c) DB_PR((smc->debug.d_smt&2),a,b,c)
+#define DB_RMTN(n,a,b,c) DB_PR((smc->debug.d_rmt >=(n)),a,b,c)
+#define DB_CFM(a,b,c) DB_PR((smc->debug.d_smt&4),a,b,c)
+#define DB_CFMN(n,a,b,c) DB_PR((smc->debug.d_cfm >=(n)),a,b,c)
+#define DB_PCM(a,b,c) DB_PR((smc->debug.d_smt&8),a,b,c)
+#define DB_PCMN(n,a,b,c) DB_PR((smc->debug.d_pcm >=(n)),a,b,c)
+#define DB_SMT(a,b,c) DB_PR((smc->debug.d_smtf),a,b,c)
+#define DB_SMTN(n,a,b,c) DB_PR((smc->debug.d_smtf >=(n)),a,b,c)
+#define DB_SBA(a,b,c) DB_PR((smc->debug.d_sba),a,b,c)
+#define DB_SBAN(n,a,b,c) DB_PR((smc->debug.d_sba >=(n)),a,b,c)
+#define DB_ESS(a,b,c) DB_PR((smc->debug.d_ess),a,b,c)
+#define DB_ESSN(n,a,b,c) DB_PR((smc->debug.d_ess >=(n)),a,b,c)
+#else
+#define DB_ECM(a,b,c) DB_PR((debug.d_smt&1),a,b,c)
+#define DB_ECMN(n,a,b,c) DB_PR((debug.d_ecm >=(n)),a,b,c)
+#define DB_RMT(a,b,c) DB_PR((debug.d_smt&2),a,b,c)
+#define DB_RMTN(n,a,b,c) DB_PR((debug.d_rmt >=(n)),a,b,c)
+#define DB_CFM(a,b,c) DB_PR((debug.d_smt&4),a,b,c)
+#define DB_CFMN(n,a,b,c) DB_PR((debug.d_cfm >=(n)),a,b,c)
+#define DB_PCM(a,b,c) DB_PR((debug.d_smt&8),a,b,c)
+#define DB_PCMN(n,a,b,c) DB_PR((debug.d_pcm >=(n)),a,b,c)
+#define DB_SMT(a,b,c) DB_PR((debug.d_smtf),a,b,c)
+#define DB_SMTN(n,a,b,c) DB_PR((debug.d_smtf >=(n)),a,b,c)
+#define DB_SBA(a,b,c) DB_PR((debug.d_sba),a,b,c)
+#define DB_SBAN(n,a,b,c) DB_PR((debug.d_sba >=(n)),a,b,c)
+#define DB_ESS(a,b,c) DB_PR((debug.d_ess),a,b,c)
+#define DB_ESSN(n,a,b,c) DB_PR((debug.d_ess >=(n)),a,b,c)
+#endif
+
+#ifndef SS_NOT_DS
+#define SK_LOC_DECL(type,var) type var
+#else
+#define SK_LOC_DECL(type,var) static type var
+#endif
+/*
+ * PHYs and PORTS
+ * Note: Don't touch the definition of PA and PB. Those might be used
+ * by some "for" loops.
+ */
+#define PA 0
+#define PB 1
+#if defined(SUPERNET_3) || defined(CONC_II)
+/*
+ * The port indices have to be different,
+ * because the MAC output goes through the 2. PLC
+ * Conc II: It has to be the first port in the row.
+ */
+#define PS 0 /* Internal PLC which is the same as PA */
+#else
+#define PS 1
+#endif
+#define PM 2 /* PM .. PA+NUM_PHYS-1 */
+
+/*
+ * PHY types - as in path descriptor 'fddiPHYType'
+ */
+#define TA 0 /* A port */
+#define TB 1 /* B port */
+#define TS 2 /* S port */
+#define TM 3 /* M port */
+#define TNONE 4
+
+
+/*
+ * indexes in MIB
+ */
+#define INDEX_MAC 1
+#define INDEX_PATH 1
+#define INDEX_PORT 1
+
+
+/*
+ * policies
+ */
+#define POLICY_AA (1<<0) /* reject AA */
+#define POLICY_AB (1<<1) /* reject AB */
+#define POLICY_AS (1<<2) /* reject AS */
+#define POLICY_AM (1<<3) /* reject AM */
+#define POLICY_BA (1<<4) /* reject BA */
+#define POLICY_BB (1<<5) /* reject BB */
+#define POLICY_BS (1<<6) /* reject BS */
+#define POLICY_BM (1<<7) /* reject BM */
+#define POLICY_SA (1<<8) /* reject SA */
+#define POLICY_SB (1<<9) /* reject SB */
+#define POLICY_SS (1<<10) /* reject SS */
+#define POLICY_SM (1<<11) /* reject SM */
+#define POLICY_MA (1<<12) /* reject MA */
+#define POLICY_MB (1<<13) /* reject MB */
+#define POLICY_MS (1<<14) /* reject MS */
+#define POLICY_MM (1<<15) /* reject MM */
+
+/*
+ * commands
+ */
+
+/*
+ * EVENTS
+ * event classes
+ */
+#define EVENT_ECM 1 /* event class ECM */
+#define EVENT_CFM 2 /* event class CFM */
+#define EVENT_RMT 3 /* event class RMT */
+#define EVENT_SMT 4 /* event class SMT */
+#define EVENT_PCM 5 /* event class PCM */
+#define EVENT_PCMA 5 /* event class PCMA */
+#define EVENT_PCMB 6 /* event class PCMB */
+
+/* WARNING :
+ * EVENT_PCM* must be last in the above list
+ * if more than two ports are used, EVENT_PCM .. EVENT_PCMA+NUM_PHYS-1
+ * are used !
+ */
+
+#define EV_TOKEN(class,event) (((u_long)(class)<<16L)|((u_long)(event)))
+#define EV_T_CLASS(token) ((int)((token)>>16)&0xffff)
+#define EV_T_EVENT(token) ((int)(token)&0xffff)
+
+/*
+ * ECM events
+ */
+#define EC_CONNECT 1 /* connect request */
+#define EC_DISCONNECT 2 /* disconnect request */
+#define EC_TRACE_PROP 3 /* trace propagation */
+#define EC_PATH_TEST 4 /* path test */
+#define EC_TIMEOUT_TD 5 /* timer TD_min */
+#define EC_TIMEOUT_TMAX 6 /* timer trace_max */
+#define EC_TIMEOUT_IMAX 7 /* timer I_max */
+#define EC_TIMEOUT_INMAX 8 /* timer IN_max */
+#define EC_TEST_DONE 9 /* path test done */
+
+/*
+ * CFM events
+ */
+#define CF_LOOP 1 /* cf_loop flag from PCM */
+#define CF_LOOP_A 1 /* cf_loop flag from PCM */
+#define CF_LOOP_B 2 /* cf_loop flag from PCM */
+#define CF_JOIN 3 /* cf_join flag from PCM */
+#define CF_JOIN_A 3 /* cf_join flag from PCM */
+#define CF_JOIN_B 4 /* cf_join flag from PCM */
+
+/*
+ * PCM events
+ */
+#define PC_START 1
+#define PC_STOP 2
+#define PC_LOOP 3
+#define PC_JOIN 4
+#define PC_SIGNAL 5
+#define PC_REJECT 6
+#define PC_MAINT 7
+#define PC_TRACE 8
+#define PC_PDR 9
+#define PC_ENABLE 10
+#define PC_DISABLE 11
+
+/*
+ * must be ordered as in LineStateType
+ */
+#define PC_QLS 12
+#define PC_ILS 13
+#define PC_MLS 14
+#define PC_HLS 15
+#define PC_LS_PDR 16
+#define PC_LS_NONE 17
+#define LS2MIB(x) ((x)-PC_QLS)
+#define MIB2LS(x) ((x)+PC_QLS)
+
+#define PC_TIMEOUT_TB_MAX 18 /* timer TB_max */
+#define PC_TIMEOUT_TB_MIN 19 /* timer TB_min */
+#define PC_TIMEOUT_C_MIN 20 /* timer C_Min */
+#define PC_TIMEOUT_T_OUT 21 /* timer T_Out */
+#define PC_TIMEOUT_TL_MIN 22 /* timer TL_Min */
+#define PC_TIMEOUT_T_NEXT 23 /* timer t_next[] */
+#define PC_TIMEOUT_LCT 24
+#define PC_NSE 25 /* NOISE hardware timer */
+#define PC_LEM 26 /* LEM done */
+
+/*
+ * RMT events meaning from
+ */
+#define RM_RING_OP 1 /* ring operational MAC */
+#define RM_RING_NON_OP 2 /* ring not operational MAC */
+#define RM_MY_BEACON 3 /* recvd my beacon MAC */
+#define RM_OTHER_BEACON 4 /* recvd other beacon MAC */
+#define RM_MY_CLAIM 5 /* recvd my claim MAC */
+#define RM_TRT_EXP 6 /* TRT exp MAC */
+#define RM_VALID_CLAIM 7 /* claim from dup addr MAC */
+#define RM_JOIN 8 /* signal rm_join CFM */
+#define RM_LOOP 9 /* signal rm_loop CFM */
+#define RM_DUP_ADDR 10 /* dup_addr_test hange SMT-NIF */
+#define RM_ENABLE_FLAG 11 /* enable flag */
+
+#define RM_TIMEOUT_NON_OP 12 /* timeout T_Non_OP */
+#define RM_TIMEOUT_T_STUCK 13 /* timeout T_Stuck */
+#define RM_TIMEOUT_ANNOUNCE 14 /* timeout T_Announce */
+#define RM_TIMEOUT_T_DIRECT 15 /* timeout T_Direct */
+#define RM_TIMEOUT_D_MAX 16 /* timeout D_Max */
+#define RM_TIMEOUT_POLL 17 /* claim/beacon poller */
+#define RM_TX_STATE_CHANGE 18 /* To restart timer for D_Max */
+
+/*
+ * SMT events
+ */
+#define SM_TIMER 1 /* timer */
+#define SM_FAST 2 /* smt_force_irq */
+
+/* PC modes */
+#define PM_NONE 0
+#define PM_PEER 1
+#define PM_TREE 2
+
+/*
+ * PCM withhold codes
+ * MIB PC-WithholdType ENUM
+ */
+#define PC_WH_NONE 0 /* ok */
+#define PC_WH_M_M 1 /* M to M */
+#define PC_WH_OTHER 2 /* other incompatible phys */
+#define PC_WH_PATH 3 /* path not available */
+/*
+ * LCT duration
+ */
+#define LC_SHORT 1 /* short LCT */
+#define LC_MEDIUM 2 /* medium LCT */
+#define LC_LONG 3 /* long LCT */
+#define LC_EXTENDED 4 /* extended LCT */
+
+/*
+ * path_test values
+ */
+#define PT_NONE 0
+#define PT_TESTING 1 /* test is running */
+#define PT_PASSED 2 /* test passed */
+#define PT_FAILED 3 /* test failed */
+#define PT_PENDING 4 /* path test follows */
+#define PT_EXITING 5 /* disconnected while in trace/leave */
+
+/*
+ * duplicate address test
+ * MIB DupAddressTest ENUM
+ */
+#define DA_NONE 0 /* */
+#define DA_PASSED 1 /* test passed */
+#define DA_FAILED 2 /* test failed */
+
+
+/*
+ * optical bypass
+ */
+#define BP_DEINSERT 0 /* disable bypass */
+#define BP_INSERT 1 /* enable bypass */
+
+/*
+ * ODL enable/disable
+ */
+#define PM_TRANSMIT_DISABLE 0 /* disable xmit */
+#define PM_TRANSMIT_ENABLE 1 /* enable xmit */
+
+/*
+ * parameter for config_mux
+ * note : number is index in config_endec table !
+ */
+#define MUX_THRUA 0 /* through A */
+#define MUX_THRUB 1 /* through B */
+#define MUX_WRAPA 2 /* wrap A */
+#define MUX_WRAPB 3 /* wrap B */
+#define MUX_ISOLATE 4 /* isolated */
+#define MUX_WRAPS 5 /* SAS */
+
+/*
+ * MAC control
+ */
+#define MA_RESET 0
+#define MA_BEACON 1
+#define MA_CLAIM 2
+#define MA_DIRECTED 3 /* directed beacon */
+#define MA_TREQ 4 /* change T_Req */
+#define MA_OFFLINE 5 /* switch MAC to offline */
+
+
+/*
+ * trace prop
+ * bit map for trace propagation
+ */
+#define ENTITY_MAC (NUMPHYS)
+#define ENTITY_PHY(p) (p)
+#define ENTITY_BIT(m) (1<<(m))
+
+/*
+ * Resource Tag Types
+ */
+#define PATH_ISO 0 /* isolated */
+#define PATH_PRIM 3 /* primary path */
+#define PATH_THRU 5 /* through path */
+
+#define RES_MAC 2 /* resource type MAC */
+#define RES_PORT 4 /* resource type PORT */
+
+
+/*
+ * CFM state
+ * oops: MUST MATCH CF-StateType in SMT7.2 !
+ */
+#define SC0_ISOLATED 0 /* isolated */
+#define SC1_WRAP_A 5 /* wrap A (not used) */
+#define SC2_WRAP_B 6 /* wrap B (not used) */
+#define SC4_THRU_A 12 /* through A */
+#define SC5_THRU_B 7 /* through B (used in SMT 6.2) */
+#define SC7_WRAP_S 8 /* SAS (not used) */
+#define SC9_C_WRAP_A 9 /* c wrap A */
+#define SC10_C_WRAP_B 10 /* c wrap B */
+#define SC11_C_WRAP_S 11 /* c wrap S */
+
+/*
+ * convert MIB time in units of 80nS to uS
+ */
+#define MIB2US(t) ((t)/12)
+#define SEC2MIB(s) ((s)*12500000L)
+/*
+ * SMT timer
+ */
+struct smt_timer {
+ struct smt_timer *tm_next ; /* linked list */
+ struct s_smc *tm_smc ; /* pointer to context */
+ u_long tm_delta ; /* delta time */
+ u_long tm_token ; /* token value */
+ u_short tm_active ; /* flag : active/inactive */
+ u_short tm_pad ; /* pad field */
+} ;
+
+/*
+ * communication structures
+ */
+struct mac_parameter {
+ u_long t_neg ; /* T_Neg parameter */
+ u_long t_pri ; /* T_Pri register in MAC */
+} ;
+
+/*
+ * MAC counters
+ */
+struct mac_counter {
+ u_long mac_nobuf_counter ; /* MAC SW counter: no buffer */
+ u_long mac_r_restart_counter ; /* MAC SW counter: rx restarted */
+} ;
+
+/*
+ * para struct context for SMT parameters
+ */
+struct s_pcon {
+ int pc_len ;
+ int pc_err ;
+ int pc_badset ;
+ void *pc_p ;
+} ;
+
+/*
+ * link error monitor
+ */
+#define LEM_AVG 5
+struct lem_counter {
+#ifdef AM29K
+ int lem_on ;
+ u_long lem_errors ;
+ u_long lem_symbols ;
+ u_long lem_tsymbols ;
+ int lem_s_count ;
+ int lem_n_s ;
+ int lem_values ;
+ int lem_index ;
+ int lem_avg_ber[LEM_AVG] ;
+ int lem_sum ;
+#else
+ u_short lem_float_ber ; /* 10E-nn bit error rate */
+ u_long lem_errors ; /* accumulated error count */
+ u_short lem_on ;
+#endif
+} ;
+
+#define NUMBITS 10
+
+#ifdef AMDPLC
+
+/*
+ * PLC state table
+ */
+struct s_plc {
+ u_short p_state ; /* current state */
+ u_short p_bits ; /* number of bits to send */
+ u_short p_start ; /* first bit pos */
+ u_short p_pad ; /* padding for alignment */
+ u_long soft_err ; /* error counter */
+ u_long parity_err ; /* error counter */
+ u_long ebuf_err ; /* error counter */
+ u_long ebuf_cont ; /* continous error counter */
+ u_long phyinv ; /* error counter */
+ u_long vsym_ctr ; /* error counter */
+ u_long mini_ctr ; /* error counter */
+ u_long tpc_exp ; /* error counter */
+ u_long np_err ; /* error counter */
+ u_long b_pcs ; /* error counter */
+ u_long b_tpc ; /* error counter */
+ u_long b_tne ; /* error counter */
+ u_long b_qls ; /* error counter */
+ u_long b_ils ; /* error counter */
+ u_long b_hls ; /* error counter */
+} ;
+#endif
+
+#ifdef PROTOTYP_INC
+#include "fddi/driver.pro"
+#else /* PROTOTYP_INC */
+/*
+ * function prototypes
+ */
+#include "h/mbuf.h" /* Type definitions for MBUFs */
+#include "h/smtstate.h" /* struct smt_state */
+
+void hwt_restart(struct s_smc *smc); /* hwt.c */
+SMbuf *smt_build_frame(struct s_smc *smc, int class, int type,
+ int length); /* smt.c */
+SMbuf *smt_get_mbuf(struct s_smc *smc); /* drvsr.c */
+void *sm_to_para(struct s_smc *smc, struct smt_header *sm,
+ int para); /* smt.c */
+
+#ifndef SK_UNUSED
+#define SK_UNUSED(var) (void)(var)
+#endif
+
+void queue_event(struct s_smc *smc, int class, int event);
+void ecm(struct s_smc *smc, int event);
+void ecm_init(struct s_smc *smc);
+void rmt(struct s_smc *smc, int event);
+void rmt_init(struct s_smc *smc);
+void pcm(struct s_smc *smc, const int np, int event);
+void pcm_init(struct s_smc *smc);
+void cfm(struct s_smc *smc, int event);
+void cfm_init(struct s_smc *smc);
+void smt_timer_start(struct s_smc *smc, struct smt_timer *timer, u_long time,
+ u_long token);
+void smt_timer_stop(struct s_smc *smc, struct smt_timer *timer);
+void pcm_status_state(struct s_smc *smc, int np, int *type, int *state,
+ int *remote, int *mac);
+void plc_config_mux(struct s_smc *smc, int mux);
+void sm_lem_evaluate(struct s_smc *smc);
+void smt_clear_una_dna(struct s_smc *smc);
+void mac_update_counter(struct s_smc *smc);
+void sm_pm_ls_latch(struct s_smc *smc, int phy, int on_off);
+void sm_ma_control(struct s_smc *smc, int mode);
+void sm_mac_check_beacon_claim(struct s_smc *smc);
+void config_mux(struct s_smc *smc, int mux);
+void smt_agent_init(struct s_smc *smc);
+void smt_timer_init(struct s_smc *smc);
+void smt_received_pack(struct s_smc *smc, SMbuf *mb, int fs);
+void smt_add_para(struct s_smc *smc, struct s_pcon *pcon, u_short para,
+ int index, int local);
+void smt_swap_para(struct smt_header *sm, int len, int direction);
+void ev_init(struct s_smc *smc);
+void hwt_init(struct s_smc *smc);
+u_long hwt_read(struct s_smc *smc);
+void hwt_stop(struct s_smc *smc);
+void hwt_start(struct s_smc *smc, u_long time);
+void smt_send_mbuf(struct s_smc *smc, SMbuf *mb, int fc);
+void smt_free_mbuf(struct s_smc *smc, SMbuf *mb);
+void sm_pm_bypass_req(struct s_smc *smc, int mode);
+void rmt_indication(struct s_smc *smc, int i);
+void cfm_state_change(struct s_smc *smc, int c_state);
+
+#if defined(DEBUG) || !defined(NO_SMT_PANIC)
+void smt_panic(struct s_smc *smc, char *text);
+#else
+#define smt_panic(smc,text)
+#endif /* DEBUG || !NO_SMT_PANIC */
+
+void smt_stat_counter(struct s_smc *smc, int stat);
+void smt_timer_poll(struct s_smc *smc);
+u_long smt_get_time(void);
+u_long smt_get_tid(struct s_smc *smc);
+void smt_timer_done(struct s_smc *smc);
+void smt_set_defaults(struct s_smc *smc);
+void smt_fixup_mib(struct s_smc *smc);
+void smt_reset_defaults(struct s_smc *smc, int level);
+void smt_agent_task(struct s_smc *smc);
+void smt_please_reconnect(struct s_smc *smc, int reconn_time);
+int smt_check_para(struct s_smc *smc, struct smt_header *sm,
+ const u_short list[]);
+void driver_get_bia(struct s_smc *smc, struct fddi_addr *bia_addr);
+
+#ifdef SUPERNET_3
+void drv_reset_indication(struct s_smc *smc);
+#endif /* SUPERNET_3 */
+
+void smt_start_watchdog(struct s_smc *smc);
+void smt_event(struct s_smc *smc, int event);
+void timer_event(struct s_smc *smc, u_long token);
+void ev_dispatcher(struct s_smc *smc);
+void pcm_get_state(struct s_smc *smc, struct smt_state *state);
+void ecm_state_change(struct s_smc *smc, int e_state);
+int sm_pm_bypass_present(struct s_smc *smc);
+void pcm_state_change(struct s_smc *smc, int plc, int p_state);
+void rmt_state_change(struct s_smc *smc, int r_state);
+int sm_pm_get_ls(struct s_smc *smc, int phy);
+int pcm_get_s_port(struct s_smc *smc);
+int pcm_rooted_station(struct s_smc *smc);
+int cfm_get_mac_input(struct s_smc *smc);
+int cfm_get_mac_output(struct s_smc *smc);
+int port_to_mib(struct s_smc *smc, int p);
+int cem_build_path(struct s_smc *smc, char *to, int path_index);
+int sm_mac_get_tx_state(struct s_smc *smc);
+char *get_pcmstate(struct s_smc *smc, int np);
+int smt_action(struct s_smc *smc, int class, int code, int index);
+u_short smt_online(struct s_smc *smc, int on);
+void smt_force_irq(struct s_smc *smc);
+void smt_pmf_received_pack(struct s_smc *smc, SMbuf *mb, int local);
+void smt_send_frame(struct s_smc *smc, SMbuf *mb, int fc, int local);
+void smt_set_timestamp(struct s_smc *smc, u_char *p);
+void mac_set_rx_mode(struct s_smc *smc, int mode);
+int mac_add_multicast(struct s_smc *smc, struct fddi_addr *addr, int can);
+int mac_set_func_addr(struct s_smc *smc, u_long f_addr);
+void mac_del_multicast(struct s_smc *smc, struct fddi_addr *addr, int can);
+void mac_update_multicast(struct s_smc *smc);
+void mac_clear_multicast(struct s_smc *smc);
+void set_formac_tsync(struct s_smc *smc, long sync_bw);
+void formac_reinit_tx(struct s_smc *smc);
+void formac_tx_restart(struct s_smc *smc);
+void process_receive(struct s_smc *smc);
+void init_driver_fplus(struct s_smc *smc);
+void rtm_irq(struct s_smc *smc);
+void rtm_set_timer(struct s_smc *smc);
+void ring_status_indication(struct s_smc *smc, u_long status);
+void llc_recover_tx(struct s_smc *smc);
+void llc_restart_tx(struct s_smc *smc);
+void plc_clear_irq(struct s_smc *smc, int p);
+void plc_irq(struct s_smc *smc, int np, unsigned int cmd);
+int smt_set_mac_opvalues(struct s_smc *smc);
+
+#ifdef TAG_MODE
+void mac_drv_pci_fix(struct s_smc *smc, u_long fix_value);
+void mac_do_pci_fix(struct s_smc *smc);
+void mac_drv_clear_tx_queue(struct s_smc *smc);
+void mac_drv_repair_descr(struct s_smc *smc);
+u_long hwt_quick_read(struct s_smc *smc);
+void hwt_wait_time(struct s_smc *smc, u_long start, long duration);
+#endif
+
+#ifdef SMT_PNMI
+int pnmi_init(struct s_smc* smc);
+int pnmi_process_ndis_id(struct s_smc *smc, u_long ndis_oid, void *buf, int len,
+ int *BytesAccessed, int *BytesNeeded, u_char action);
+#endif
+
+#ifdef SBA
+#ifndef _H2INC
+void sba();
+#endif
+void sba_raf_received_pack();
+void sba_timer_poll();
+void smt_init_sba();
+#endif
+
+#ifdef ESS
+int ess_raf_received_pack(struct s_smc *smc, SMbuf *mb, struct smt_header *sm,
+ int fs);
+void ess_timer_poll(struct s_smc *smc);
+void ess_para_change(struct s_smc *smc);
+#endif
+
+#ifndef BOOT
+void smt_init_evc(struct s_smc *smc);
+void smt_srf_event(struct s_smc *smc, int code, int index, int cond);
+#else
+#define smt_init_evc(smc)
+#define smt_srf_event(smc,code,index,cond)
+#endif
+
+#ifndef SMT_REAL_TOKEN_CT
+void smt_emulate_token_ct(struct s_smc *smc, int mac_index);
+#endif
+
+#if defined(DEBUG) && !defined(BOOT)
+void dump_smt(struct s_smc *smc, struct smt_header *sm, char *text);
+#else
+#define dump_smt(smc,sm,text)
+#endif
+
+#ifdef DEBUG
+char* addr_to_string(struct fddi_addr *addr);
+void dump_hex(char *p, int len);
+#endif
+
+#endif /* PROTOTYP_INC */
+
+/* PNMI default defines */
+#ifndef PNMI_INIT
+#define PNMI_INIT(smc) /* Nothing */
+#endif
+#ifndef PNMI_GET_ID
+#define PNMI_GET_ID( smc, ndis_oid, buf, len, BytesWritten, BytesNeeded ) \
+ ( 1 ? (-1) : (-1) )
+#endif
+#ifndef PNMI_SET_ID
+#define PNMI_SET_ID( smc, ndis_oid, buf, len, BytesRead, BytesNeeded, \
+ set_type) ( 1 ? (-1) : (-1) )
+#endif
+
+/*
+ * SMT_PANIC defines
+ */
+#ifndef SMT_PANIC
+#define SMT_PANIC(smc,nr,msg) smt_panic (smc, msg)
+#endif
+
+#ifndef SMT_ERR_LOG
+#define SMT_ERR_LOG(smc,nr,msg) SMT_PANIC (smc, nr, msg)
+#endif
+
+#ifndef SMT_EBASE
+#define SMT_EBASE 100
+#endif
+
+#define SMT_E0100 SMT_EBASE + 0
+#define SMT_E0100_MSG "cfm FSM: invalid ce_type"
+#define SMT_E0101 SMT_EBASE + 1
+#define SMT_E0101_MSG "CEM: case ???"
+#define SMT_E0102 SMT_EBASE + 2
+#define SMT_E0102_MSG "CEM A: invalid state"
+#define SMT_E0103 SMT_EBASE + 3
+#define SMT_E0103_MSG "CEM B: invalid state"
+#define SMT_E0104 SMT_EBASE + 4
+#define SMT_E0104_MSG "CEM M: invalid state"
+#define SMT_E0105 SMT_EBASE + 5
+#define SMT_E0105_MSG "CEM S: invalid state"
+#define SMT_E0106 SMT_EBASE + 6
+#define SMT_E0106_MSG "CFM : invalid state"
+#define SMT_E0107 SMT_EBASE + 7
+#define SMT_E0107_MSG "ECM : invalid state"
+#define SMT_E0108 SMT_EBASE + 8
+#define SMT_E0108_MSG "prop_actions : NAC in DAS CFM"
+#define SMT_E0109 SMT_EBASE + 9
+#define SMT_E0109_MSG "ST2U.FM_SERRSF error in special frame"
+#define SMT_E0110 SMT_EBASE + 10
+#define SMT_E0110_MSG "ST2U.FM_SRFRCTOV recv. count. overflow"
+#define SMT_E0111 SMT_EBASE + 11
+#define SMT_E0111_MSG "ST2U.FM_SNFSLD NP & FORMAC simult. load"
+#define SMT_E0112 SMT_EBASE + 12
+#define SMT_E0112_MSG "ST2U.FM_SRCVFRM single-frame recv.-mode"
+#define SMT_E0113 SMT_EBASE + 13
+#define SMT_E0113_MSG "FPLUS: Buffer Memory Error"
+#define SMT_E0114 SMT_EBASE + 14
+#define SMT_E0114_MSG "ST2U.FM_SERRSF error in special frame"
+#define SMT_E0115 SMT_EBASE + 15
+#define SMT_E0115_MSG "ST3L: parity error in receive queue 2"
+#define SMT_E0116 SMT_EBASE + 16
+#define SMT_E0116_MSG "ST3L: parity error in receive queue 1"
+#define SMT_E0117 SMT_EBASE + 17
+#define SMT_E0117_MSG "E_SMT_001: RxD count for receive queue 1 = 0"
+#define SMT_E0118 SMT_EBASE + 18
+#define SMT_E0118_MSG "PCM : invalid state"
+#define SMT_E0119 SMT_EBASE + 19
+#define SMT_E0119_MSG "smt_add_para"
+#define SMT_E0120 SMT_EBASE + 20
+#define SMT_E0120_MSG "smt_set_para"
+#define SMT_E0121 SMT_EBASE + 21
+#define SMT_E0121_MSG "invalid event in dispatcher"
+#define SMT_E0122 SMT_EBASE + 22
+#define SMT_E0122_MSG "RMT : invalid state"
+#define SMT_E0123 SMT_EBASE + 23
+#define SMT_E0123_MSG "SBA: state machine has invalid state"
+#define SMT_E0124 SMT_EBASE + 24
+#define SMT_E0124_MSG "sba_free_session() called with NULL pointer"
+#define SMT_E0125 SMT_EBASE + 25
+#define SMT_E0125_MSG "SBA : invalid session pointer"
+#define SMT_E0126 SMT_EBASE + 26
+#define SMT_E0126_MSG "smt_free_mbuf() called with NULL pointer\n"
+#define SMT_E0127 SMT_EBASE + 27
+#define SMT_E0127_MSG "sizeof evcs"
+#define SMT_E0128 SMT_EBASE + 28
+#define SMT_E0128_MSG "evc->evc_cond_state = 0"
+#define SMT_E0129 SMT_EBASE + 29
+#define SMT_E0129_MSG "evc->evc_multiple = 0"
+#define SMT_E0130 SMT_EBASE + 30
+#define SMT_E0130_MSG write_mdr_warning
+#define SMT_E0131 SMT_EBASE + 31
+#define SMT_E0131_MSG cam_warning
+#define SMT_E0132 SMT_EBASE + 32
+#define SMT_E0132_MSG "ST1L.FM_SPCEPDx parity/coding error"
+#define SMT_E0133 SMT_EBASE + 33
+#define SMT_E0133_MSG "ST1L.FM_STBURx tx buffer underrun"
+#define SMT_E0134 SMT_EBASE + 34
+#define SMT_E0134_MSG "ST1L.FM_SPCEPDx parity error"
+#define SMT_E0135 SMT_EBASE + 35
+#define SMT_E0135_MSG "RMT: duplicate MAC address detected. Ring left!"
+#define SMT_E0136 SMT_EBASE + 36
+#define SMT_E0136_MSG "Elasticity Buffer hang-up"
+#define SMT_E0137 SMT_EBASE + 37
+#define SMT_E0137_MSG "SMT: queue overrun"
+#define SMT_E0138 SMT_EBASE + 38
+#define SMT_E0138_MSG "RMT: duplicate MAC address detected. Ring NOT left!"
+#endif /* _CMTDEF_ */
diff --git a/drivers/net/skfp/h/fddi.h b/drivers/net/skfp/h/fddi.h
new file mode 100644
index 0000000..c9a28a8
--- /dev/null
+++ b/drivers/net/skfp/h/fddi.h
@@ -0,0 +1,69 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+#ifndef _FDDI_
+#define _FDDI_
+
+struct fddi_addr {
+ u_char a[6] ;
+} ;
+
+#define GROUP_ADDR 0x80 /* MSB in a[0] */
+
+struct fddi_mac {
+ struct fddi_addr mac_dest ;
+ struct fddi_addr mac_source ;
+ u_char mac_info[4478] ;
+} ;
+
+#define FDDI_MAC_SIZE (12)
+#define FDDI_RAW_MTU (4500-5) /* exl. Pr,SD, ED/FS */
+#define FDDI_RAW (4500)
+
+/*
+ * FC values
+ */
+#define FC_VOID 0x40 /* void frame */
+#define FC_TOKEN 0x80 /* token */
+#define FC_RES_TOKEN 0xc0 /* restricted token */
+#define FC_SMT_INFO 0x41 /* SMT Info frame */
+/*
+ * FC_SMT_LAN_LOC && FC_SMT_LOC are SK specific !
+ */
+#define FC_SMT_LAN_LOC 0x42 /* local SMT Info frame */
+#define FC_SMT_LOC 0x43 /* local SMT Info frame */
+#define FC_SMT_NSA 0x4f /* SMT NSA frame */
+#define FC_MAC 0xc0 /* MAC frame */
+#define FC_BEACON 0xc2 /* MAC beacon frame */
+#define FC_CLAIM 0xc3 /* MAC claim frame */
+#define FC_SYNC_LLC 0xd0 /* sync. LLC frame */
+#define FC_ASYNC_LLC 0x50 /* async. LLC frame */
+#define FC_SYNC_BIT 0x80 /* sync. bit in FC */
+
+#define FC_LLC_PRIOR 0x07 /* priority bits */
+
+#define BEACON_INFO 0 /* beacon type */
+#define DBEACON_INFO 1 /* beacon type DIRECTED */
+
+
+/*
+ * indicator bits
+ */
+#define C_INDICATOR (1<<0)
+#define A_INDICATOR (1<<1)
+#define E_INDICATOR (1<<2)
+#define I_INDICATOR (1<<6) /* SK specific */
+#define L_INDICATOR (1<<7) /* SK specific */
+
+#endif /* _FDDI_ */
diff --git a/drivers/net/skfp/h/fddimib.h b/drivers/net/skfp/h/fddimib.h
new file mode 100644
index 0000000..d1acdc7
--- /dev/null
+++ b/drivers/net/skfp/h/fddimib.h
@@ -0,0 +1,349 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*
+ * FDDI MIB
+ */
+
+/*
+ * typedefs
+ */
+
+typedef u_long Counter ;
+typedef u_char TimeStamp[8] ;
+typedef struct fddi_addr LongAddr ;
+typedef u_long Timer_2 ;
+typedef u_long Timer ;
+typedef u_short ResId ;
+typedef u_short SMTEnum ;
+typedef u_char SMTFlag ;
+
+typedef struct {
+ Counter count ;
+ TimeStamp timestamp ;
+} SetCountType ;
+
+/*
+ * bits for bit string "available_path"
+ */
+#define MIB_PATH_P (1<<0)
+#define MIB_PATH_S (1<<1)
+#define MIB_PATH_L (1<<2)
+
+/*
+ * bits for bit string PermittedPaths & RequestedPaths (SIZE(8))
+ */
+#define MIB_P_PATH_LOCAL (1<<0)
+#define MIB_P_PATH_SEC_ALTER (1<<1)
+#define MIB_P_PATH_PRIM_ALTER (1<<2)
+#define MIB_P_PATH_CON_ALTER (1<<3)
+#define MIB_P_PATH_SEC_PREFER (1<<4)
+#define MIB_P_PATH_PRIM_PREFER (1<<5)
+#define MIB_P_PATH_CON_PREFER (1<<6)
+#define MIB_P_PATH_THRU (1<<7)
+
+/*
+ * enum current path
+ */
+#define MIB_PATH_ISOLATED 0
+#define MIB_PATH_LOCAL 1
+#define MIB_PATH_SECONDARY 2
+#define MIB_PATH_PRIMARY 3
+#define MIB_PATH_CONCATENATED 4
+#define MIB_PATH_THRU 5
+
+/*
+ * enum PMDClass
+ */
+#define MIB_PMDCLASS_MULTI 0
+#define MIB_PMDCLASS_SINGLE1 1
+#define MIB_PMDCLASS_SINGLE2 2
+#define MIB_PMDCLASS_SONET 3
+#define MIB_PMDCLASS_LCF 4
+#define MIB_PMDCLASS_TP 5
+#define MIB_PMDCLASS_UNKNOWN 6
+#define MIB_PMDCLASS_UNSPEC 7
+
+/*
+ * enum SMTStationStatus
+ */
+#define MIB_SMT_STASTA_CON 0
+#define MIB_SMT_STASTA_SEPA 1
+#define MIB_SMT_STASTA_THRU 2
+
+
+struct fddi_mib {
+ /*
+ * private
+ */
+ u_char fddiPRPMFPasswd[8] ;
+ struct smt_sid fddiPRPMFStation ;
+
+#ifdef ESS
+ /*
+ * private variables for static allocation of the
+ * End Station Support
+ */
+ u_long fddiESSPayload ; /* payload for static alloc */
+ u_long fddiESSOverhead ; /* frame ov for static alloc */
+ u_long fddiESSMaxTNeg ; /* maximum of T-NEG */
+ u_long fddiESSMinSegmentSize ; /* min size of the sync frames */
+ u_long fddiESSCategory ; /* category for the Alloc req */
+ short fddiESSSynchTxMode ; /* send all LLC frames as sync */
+#endif /* ESS */
+#ifdef SBA
+ /*
+ * private variables for the Synchronous Bandwidth Allocator
+ */
+ char fddiSBACommand ; /* holds the parsed SBA cmd */
+ u_char fddiSBAAvailable ; /* SBA allocatable value */
+#endif /* SBA */
+
+ /*
+ * SMT standard mib
+ */
+ struct smt_sid fddiSMTStationId ;
+ u_short fddiSMTOpVersionId ;
+ u_short fddiSMTHiVersionId ;
+ u_short fddiSMTLoVersionId ;
+ u_char fddiSMTManufacturerData[32] ;
+ u_char fddiSMTUserData[32] ;
+ u_short fddiSMTMIBVersionId ;
+
+ /*
+ * ConfigGrp
+ */
+ u_char fddiSMTMac_Ct ;
+ u_char fddiSMTNonMaster_Ct ;
+ u_char fddiSMTMaster_Ct ;
+ u_char fddiSMTAvailablePaths ;
+ u_short fddiSMTConfigCapabilities ;
+ u_short fddiSMTConfigPolicy ;
+ u_short fddiSMTConnectionPolicy ;
+ u_short fddiSMTTT_Notify ;
+ u_char fddiSMTStatRptPolicy ;
+ u_long fddiSMTTrace_MaxExpiration ;
+ u_short fddiSMTPORTIndexes[NUMPHYS] ;
+ u_short fddiSMTMACIndexes ;
+ u_char fddiSMTBypassPresent ;
+
+ /*
+ * StatusGrp
+ */
+ SMTEnum fddiSMTECMState ;
+ SMTEnum fddiSMTCF_State ;
+ SMTEnum fddiSMTStationStatus ;
+ u_char fddiSMTRemoteDisconnectFlag ;
+ u_char fddiSMTPeerWrapFlag ;
+
+ /*
+ * MIBOperationGrp
+ */
+ TimeStamp fddiSMTTimeStamp ;
+ TimeStamp fddiSMTTransitionTimeStamp ;
+ SetCountType fddiSMTSetCount ;
+ struct smt_sid fddiSMTLastSetStationId ;
+
+ struct fddi_mib_m {
+ u_short fddiMACFrameStatusFunctions ;
+ Timer_2 fddiMACT_MaxCapabilitiy ;
+ Timer_2 fddiMACTVXCapabilitiy ;
+
+ /* ConfigGrp */
+ u_char fddiMACMultiple_N ; /* private */
+ u_char fddiMACMultiple_P ; /* private */
+ u_char fddiMACDuplicateAddressCond ;/* private */
+ u_char fddiMACAvailablePaths ;
+ u_short fddiMACCurrentPath ;
+ LongAddr fddiMACUpstreamNbr ;
+ LongAddr fddiMACDownstreamNbr ;
+ LongAddr fddiMACOldUpstreamNbr ;
+ LongAddr fddiMACOldDownstreamNbr ;
+ SMTEnum fddiMACDupAddressTest ;
+ u_short fddiMACRequestedPaths ;
+ SMTEnum fddiMACDownstreamPORTType ;
+ ResId fddiMACIndex ;
+
+ /* AddressGrp */
+ LongAddr fddiMACSMTAddress ;
+
+ /* OperationGrp */
+ Timer_2 fddiMACT_Min ; /* private */
+ Timer_2 fddiMACT_ReqMIB ;
+ Timer_2 fddiMACT_Req ; /* private */
+ Timer_2 fddiMACT_Neg ;
+ Timer_2 fddiMACT_MaxMIB ;
+ Timer_2 fddiMACT_Max ; /* private */
+ Timer_2 fddiMACTvxValueMIB ;
+ Timer_2 fddiMACTvxValue ; /* private */
+ Timer_2 fddiMACT_Pri0 ;
+ Timer_2 fddiMACT_Pri1 ;
+ Timer_2 fddiMACT_Pri2 ;
+ Timer_2 fddiMACT_Pri3 ;
+ Timer_2 fddiMACT_Pri4 ;
+ Timer_2 fddiMACT_Pri5 ;
+ Timer_2 fddiMACT_Pri6 ;
+
+ /* CountersGrp */
+ Counter fddiMACFrame_Ct ;
+ Counter fddiMACCopied_Ct ;
+ Counter fddiMACTransmit_Ct ;
+ Counter fddiMACToken_Ct ;
+ Counter fddiMACError_Ct ;
+ Counter fddiMACLost_Ct ;
+ Counter fddiMACTvxExpired_Ct ;
+ Counter fddiMACNotCopied_Ct ;
+ Counter fddiMACRingOp_Ct ;
+
+ Counter fddiMACSMTCopied_Ct ; /* private */
+ Counter fddiMACSMTTransmit_Ct ; /* private */
+
+ /* private for delta ratio */
+ Counter fddiMACOld_Frame_Ct ;
+ Counter fddiMACOld_Copied_Ct ;
+ Counter fddiMACOld_Error_Ct ;
+ Counter fddiMACOld_Lost_Ct ;
+ Counter fddiMACOld_NotCopied_Ct ;
+
+ /* FrameErrorConditionGrp */
+ u_short fddiMACFrameErrorThreshold ;
+ u_short fddiMACFrameErrorRatio ;
+
+ /* NotCopiedConditionGrp */
+ u_short fddiMACNotCopiedThreshold ;
+ u_short fddiMACNotCopiedRatio ;
+
+ /* StatusGrp */
+ SMTEnum fddiMACRMTState ;
+ SMTFlag fddiMACDA_Flag ;
+ SMTFlag fddiMACUNDA_Flag ;
+ SMTFlag fddiMACFrameErrorFlag ;
+ SMTFlag fddiMACNotCopiedFlag ;
+ SMTFlag fddiMACMA_UnitdataAvailable ;
+ SMTFlag fddiMACHardwarePresent ;
+ SMTFlag fddiMACMA_UnitdataEnable ;
+
+ } m[NUMMACS] ;
+#define MAC0 0
+
+ struct fddi_mib_a {
+ ResId fddiPATHIndex ;
+ u_long fddiPATHSbaPayload ;
+ u_long fddiPATHSbaOverhead ;
+ /* fddiPATHConfiguration is built on demand */
+ /* u_long fddiPATHConfiguration ; */
+ Timer fddiPATHT_Rmode ;
+ u_long fddiPATHSbaAvailable ;
+ Timer_2 fddiPATHTVXLowerBound ;
+ Timer_2 fddiPATHT_MaxLowerBound ;
+ Timer_2 fddiPATHMaxT_Req ;
+ } a[NUMPATHS] ;
+#define PATH0 0
+
+ struct fddi_mib_p {
+ /* ConfigGrp */
+ SMTEnum fddiPORTMy_Type ;
+ SMTEnum fddiPORTNeighborType ;
+ u_char fddiPORTConnectionPolicies ;
+ struct {
+ u_char T_val ;
+ u_char R_val ;
+ } fddiPORTMacIndicated ;
+ SMTEnum fddiPORTCurrentPath ;
+ /* must be 4: is 32 bit in SMT format
+ * indices :
+ * 1 none
+ * 2 tree
+ * 3 peer
+ */
+ u_char fddiPORTRequestedPaths[4] ;
+ u_short fddiPORTMACPlacement ;
+ u_char fddiPORTAvailablePaths ;
+ u_char fddiPORTConnectionCapabilities ;
+ SMTEnum fddiPORTPMDClass ;
+ ResId fddiPORTIndex ;
+
+ /* OperationGrp */
+ SMTEnum fddiPORTMaint_LS ;
+ SMTEnum fddiPORTPC_LS ;
+ u_char fddiPORTBS_Flag ;
+
+ /* ErrorCtrsGrp */
+ Counter fddiPORTLCTFail_Ct ;
+ Counter fddiPORTEBError_Ct ;
+ Counter fddiPORTOldEBError_Ct ;
+
+ /* LerGrp */
+ Counter fddiPORTLem_Reject_Ct ;
+ Counter fddiPORTLem_Ct ;
+ u_char fddiPORTLer_Estimate ;
+ u_char fddiPORTLer_Cutoff ;
+ u_char fddiPORTLer_Alarm ;
+
+ /* StatusGrp */
+ SMTEnum fddiPORTConnectState ;
+ SMTEnum fddiPORTPCMState ; /* real value */
+ SMTEnum fddiPORTPCMStateX ; /* value for MIB */
+ SMTEnum fddiPORTPC_Withhold ;
+ SMTFlag fddiPORTHardwarePresent ;
+ u_char fddiPORTLerFlag ;
+
+ u_char fddiPORTMultiple_U ; /* private */
+ u_char fddiPORTMultiple_P ; /* private */
+ u_char fddiPORTEB_Condition ; /* private */
+ } p[NUMPHYS] ;
+ struct {
+ Counter fddiPRIVECF_Req_Rx ; /* ECF req received */
+ Counter fddiPRIVECF_Reply_Rx ; /* ECF repl received */
+ Counter fddiPRIVECF_Req_Tx ; /* ECF req transm */
+ Counter fddiPRIVECF_Reply_Tx ; /* ECF repl transm */
+ Counter fddiPRIVPMF_Get_Rx ; /* PMF Get rec */
+ Counter fddiPRIVPMF_Set_Rx ; /* PMF Set rec */
+ Counter fddiPRIVRDF_Rx ; /* RDF received */
+ Counter fddiPRIVRDF_Tx ; /* RDF transmitted */
+ } priv ;
+} ;
+
+/*
+ * OIDs for statistics
+ */
+#define SMT_OID_CF_STATE 1 /* fddiSMTCF_State */
+#define SMT_OID_PCM_STATE_A 2 /* fddiPORTPCMState port A */
+#define SMT_OID_PCM_STATE_B 17 /* fddiPORTPCMState port B */
+#define SMT_OID_RMT_STATE 3 /* fddiMACRMTState */
+#define SMT_OID_UNA 4 /* fddiMACUpstreamNbr */
+#define SMT_OID_DNA 5 /* fddiMACOldDownstreamNbr */
+#define SMT_OID_ERROR_CT 6 /* fddiMACError_Ct */
+#define SMT_OID_LOST_CT 7 /* fddiMACLost_Ct */
+#define SMT_OID_LEM_CT 8 /* fddiPORTLem_Ct */
+#define SMT_OID_LEM_CT_A 11 /* fddiPORTLem_Ct port A */
+#define SMT_OID_LEM_CT_B 12 /* fddiPORTLem_Ct port B */
+#define SMT_OID_LCT_FAIL_CT 9 /* fddiPORTLCTFail_Ct */
+#define SMT_OID_LCT_FAIL_CT_A 13 /* fddiPORTLCTFail_Ct port A */
+#define SMT_OID_LCT_FAIL_CT_B 14 /* fddiPORTLCTFail_Ct port B */
+#define SMT_OID_LEM_REJECT_CT 10 /* fddiPORTLem_Reject_Ct */
+#define SMT_OID_LEM_REJECT_CT_A 15 /* fddiPORTLem_Reject_Ct port A */
+#define SMT_OID_LEM_REJECT_CT_B 16 /* fddiPORTLem_Reject_Ct port B */
+
+/*
+ * SK MIB
+ */
+#define SMT_OID_ECF_REQ_RX 20 /* ECF requests received */
+#define SMT_OID_ECF_REPLY_RX 21 /* ECF replies received */
+#define SMT_OID_ECF_REQ_TX 22 /* ECF requests transmitted */
+#define SMT_OID_ECF_REPLY_TX 23 /* ECF replies transmitted */
+#define SMT_OID_PMF_GET_RX 24 /* PMF get requests received */
+#define SMT_OID_PMF_SET_RX 25 /* PMF set requests received */
+#define SMT_OID_RDF_RX 26 /* RDF received */
+#define SMT_OID_RDF_TX 27 /* RDF transmitted */
diff --git a/drivers/net/skfp/h/fplustm.h b/drivers/net/skfp/h/fplustm.h
new file mode 100644
index 0000000..98bbf65
--- /dev/null
+++ b/drivers/net/skfp/h/fplustm.h
@@ -0,0 +1,274 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*
+ * AMD Fplus in tag mode data structs
+ * defs for fplustm.c
+ */
+
+#ifndef _FPLUS_
+#define _FPLUS_
+
+#ifndef HW_PTR
+#define HW_PTR void __iomem *
+#endif
+
+/*
+ * fplus error statistic structure
+ */
+struct err_st {
+ u_long err_valid ; /* memory status valid */
+ u_long err_abort ; /* memory status receive abort */
+ u_long err_e_indicator ; /* error indicator */
+ u_long err_crc ; /* error detected (CRC or length) */
+ u_long err_llc_frame ; /* LLC frame */
+ u_long err_mac_frame ; /* MAC frame */
+ u_long err_smt_frame ; /* SMT frame */
+ u_long err_imp_frame ; /* implementer frame */
+ u_long err_no_buf ; /* no buffer available */
+ u_long err_too_long ; /* longer than max. buffer */
+ u_long err_bec_stat ; /* beacon state entered */
+ u_long err_clm_stat ; /* claim state entered */
+ u_long err_sifg_det ; /* short interframe gap detect */
+ u_long err_phinv ; /* PHY invalid */
+ u_long err_tkiss ; /* token issued */
+ u_long err_tkerr ; /* token error */
+} ;
+
+/*
+ * Transmit Descriptor struct
+ */
+struct s_smt_fp_txd {
+ u_int txd_tbctrl ; /* transmit buffer control */
+ u_int txd_txdscr ; /* transmit frame status word */
+ u_int txd_tbadr ; /* physical tx buffer address */
+ u_int txd_ntdadr ; /* physical pointer to the next TxD */
+#ifdef ENA_64BIT_SUP
+ u_int txd_tbadr_hi ; /* physical tx buffer addr (high dword)*/
+#endif
+ char far *txd_virt ; /* virtual pointer to the data frag */
+ /* virt pointer to the next TxD */
+ struct s_smt_fp_txd volatile far *txd_next ;
+ struct s_txd_os txd_os ; /* OS - specific struct */
+} ;
+
+/*
+ * Receive Descriptor struct
+ */
+struct s_smt_fp_rxd {
+ u_int rxd_rbctrl ; /* receive buffer control */
+ u_int rxd_rfsw ; /* receive frame status word */
+ u_int rxd_rbadr ; /* physical rx buffer address */
+ u_int rxd_nrdadr ; /* physical pointer to the next RxD */
+#ifdef ENA_64BIT_SUP
+ u_int rxd_rbadr_hi ; /* physical tx buffer addr (high dword)*/
+#endif
+ char far *rxd_virt ; /* virtual pointer to the data frag */
+ /* virt pointer to the next RxD */
+ struct s_smt_fp_rxd volatile far *rxd_next ;
+ struct s_rxd_os rxd_os ; /* OS - specific struct */
+} ;
+
+/*
+ * Descriptor Union Definition
+ */
+union s_fp_descr {
+ struct s_smt_fp_txd t ; /* pointer to the TxD */
+ struct s_smt_fp_rxd r ; /* pointer to the RxD */
+} ;
+
+/*
+ * TxD Ring Control struct
+ */
+struct s_smt_tx_queue {
+ struct s_smt_fp_txd volatile *tx_curr_put ; /* next free TxD */
+ struct s_smt_fp_txd volatile *tx_prev_put ; /* shadow put pointer */
+ struct s_smt_fp_txd volatile *tx_curr_get ; /* next TxD to release*/
+ u_short tx_free ; /* count of free TxD's */
+ u_short tx_used ; /* count of used TxD's */
+ HW_PTR tx_bmu_ctl ; /* BMU addr for tx start */
+ HW_PTR tx_bmu_dsc ; /* BMU addr for curr dsc. */
+} ;
+
+/*
+ * RxD Ring Control struct
+ */
+struct s_smt_rx_queue {
+ struct s_smt_fp_rxd volatile *rx_curr_put ; /* next RxD to queue into */
+ struct s_smt_fp_rxd volatile *rx_prev_put ; /* shadow put pointer */
+ struct s_smt_fp_rxd volatile *rx_curr_get ; /* next RxD to fill */
+ u_short rx_free ; /* count of free RxD's */
+ u_short rx_used ; /* count of used RxD's */
+ HW_PTR rx_bmu_ctl ; /* BMU addr for rx start */
+ HW_PTR rx_bmu_dsc ; /* BMU addr for curr dsc. */
+} ;
+
+#define VOID_FRAME_OFF 0x00
+#define CLAIM_FRAME_OFF 0x08
+#define BEACON_FRAME_OFF 0x10
+#define DBEACON_FRAME_OFF 0x18
+#define RX_FIFO_OFF 0x21 /* to get a prime number for */
+ /* the RX_FIFO_SPACE */
+
+#define RBC_MEM_SIZE 0x8000
+#define SEND_ASYNC_AS_SYNC 0x1
+#define SYNC_TRAFFIC_ON 0x2
+
+/* big FIFO memory */
+#define RX_FIFO_SPACE 0x4000 - RX_FIFO_OFF
+#define TX_FIFO_SPACE 0x4000
+
+#define TX_SMALL_FIFO 0x0900
+#define TX_MEDIUM_FIFO TX_FIFO_SPACE / 2
+#define TX_LARGE_FIFO TX_FIFO_SPACE - TX_SMALL_FIFO
+
+#define RX_SMALL_FIFO 0x0900
+#define RX_LARGE_FIFO RX_FIFO_SPACE - RX_SMALL_FIFO
+
+struct s_smt_fifo_conf {
+ u_short rbc_ram_start ; /* FIFO start address */
+ u_short rbc_ram_end ; /* FIFO size */
+ u_short rx1_fifo_start ; /* rx queue start address */
+ u_short rx1_fifo_size ; /* rx queue size */
+ u_short rx2_fifo_start ; /* rx queue start address */
+ u_short rx2_fifo_size ; /* rx queue size */
+ u_short tx_s_start ; /* sync queue start address */
+ u_short tx_s_size ; /* sync queue size */
+ u_short tx_a0_start ; /* async queue A0 start address */
+ u_short tx_a0_size ; /* async queue A0 size */
+ u_short fifo_config_mode ; /* FIFO configuration mode */
+} ;
+
+#define FM_ADDRX (FM_ADDET|FM_EXGPA0|FM_EXGPA1)
+
+struct s_smt_fp {
+ u_short mdr2init ; /* mode register 2 init value */
+ u_short mdr3init ; /* mode register 3 init value */
+ u_short frselreg_init ; /* frame selection register init val */
+ u_short rx_mode ; /* address mode broad/multi/promisc */
+ u_short nsa_mode ;
+ u_short rx_prom ;
+ u_short exgpa ;
+
+ struct err_st err_stats ; /* error statistics */
+
+ /*
+ * MAC buffers
+ */
+ struct fddi_mac_sf { /* special frame build buffer */
+ u_char mac_fc ;
+ struct fddi_addr mac_dest ;
+ struct fddi_addr mac_source ;
+ u_char mac_info[0x20] ;
+ } mac_sfb ;
+
+
+ /*
+ * queues
+ */
+#define QUEUE_S 0
+#define QUEUE_A0 1
+#define QUEUE_R1 0
+#define QUEUE_R2 1
+#define USED_QUEUES 2
+
+ /*
+ * queue pointers; points to the queue dependent variables
+ */
+ struct s_smt_tx_queue *tx[USED_QUEUES] ;
+ struct s_smt_rx_queue *rx[USED_QUEUES] ;
+
+ /*
+ * queue dependent variables
+ */
+ struct s_smt_tx_queue tx_q[USED_QUEUES] ;
+ struct s_smt_rx_queue rx_q[USED_QUEUES] ;
+
+ /*
+ * FIFO configuration struct
+ */
+ struct s_smt_fifo_conf fifo ;
+
+ /* last formac status */
+ u_short s2u ;
+ u_short s2l ;
+
+ /* calculated FORMAC+ reg.addr. */
+ HW_PTR fm_st1u ;
+ HW_PTR fm_st1l ;
+ HW_PTR fm_st2u ;
+ HW_PTR fm_st2l ;
+ HW_PTR fm_st3u ;
+ HW_PTR fm_st3l ;
+
+
+ /*
+ * multicast table
+ */
+#define FPMAX_MULTICAST 32
+#define SMT_MAX_MULTI 4
+ struct {
+ struct s_fpmc {
+ struct fddi_addr a ; /* mc address */
+ u_char n ; /* usage counter */
+ u_char perm ; /* flag: permanent */
+ } table[FPMAX_MULTICAST] ;
+ } mc ;
+ struct fddi_addr group_addr ;
+ u_long func_addr ; /* functional address */
+ int smt_slots_used ; /* count of table entries for the SMT */
+ int os_slots_used ; /* count of table entries */
+ /* used by the os-specific module */
+} ;
+
+/*
+ * modes for mac_set_rx_mode()
+ */
+#define RX_ENABLE_ALLMULTI 1 /* enable all multicasts */
+#define RX_DISABLE_ALLMULTI 2 /* disable "enable all multicasts" */
+#define RX_ENABLE_PROMISC 3 /* enable promiscous */
+#define RX_DISABLE_PROMISC 4 /* disable promiscous */
+#define RX_ENABLE_NSA 5 /* enable reception of NSA frames */
+#define RX_DISABLE_NSA 6 /* disable reception of NSA frames */
+
+
+/*
+ * support for byte reversal in AIX
+ * (descriptors and pointers must be byte reversed in memory
+ * CPU is big endian; M-Channel is little endian)
+ */
+#ifdef AIX
+#define MDR_REV
+#define AIX_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
+ (((x)<< 8L)&0x00ff0000L) + \
+ (((x)>> 8L)&0x0000ff00L) + \
+ (((x)>>24L)&0x000000ffL))
+#else
+#ifndef AIX_REVERSE
+#define AIX_REVERSE(x) (x)
+#endif
+#endif
+
+#ifdef MDR_REV
+#define MDR_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
+ (((x)<< 8L)&0x00ff0000L) + \
+ (((x)>> 8L)&0x0000ff00L) + \
+ (((x)>>24L)&0x000000ffL))
+#else
+#ifndef MDR_REVERSE
+#define MDR_REVERSE(x) (x)
+#endif
+#endif
+
+#endif
diff --git a/drivers/net/skfp/h/hwmtm.h b/drivers/net/skfp/h/hwmtm.h
new file mode 100644
index 0000000..4e360af
--- /dev/null
+++ b/drivers/net/skfp/h/hwmtm.h
@@ -0,0 +1,424 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+#ifndef _HWM_
+#define _HWM_
+
+#include "h/mbuf.h"
+
+/*
+ * MACRO for DMA synchronization:
+ * The descriptor 'desc' is flushed for the device 'flag'.
+ * Devices are the CPU (DDI_DMA_SYNC_FORCPU) and the
+ * adapter (DDI_DMA_SYNC_FORDEV).
+ *
+ * 'desc' Pointer to a Rx or Tx descriptor.
+ * 'flag' Flag for direction (view for CPU or DEVICE) that
+ * should be synchronized.
+ *
+ * Empty macros and defines are specified here. The real macro
+ * is os-specific and should be defined in osdef1st.h.
+ */
+#ifndef DRV_BUF_FLUSH
+#define DRV_BUF_FLUSH(desc,flag)
+#define DDI_DMA_SYNC_FORCPU
+#define DDI_DMA_SYNC_FORDEV
+#endif
+
+ /*
+ * hardware modul dependent receive modes
+ */
+#define RX_ENABLE_PASS_SMT 21
+#define RX_DISABLE_PASS_SMT 22
+#define RX_ENABLE_PASS_NSA 23
+#define RX_DISABLE_PASS_NSA 24
+#define RX_ENABLE_PASS_DB 25
+#define RX_DISABLE_PASS_DB 26
+#define RX_DISABLE_PASS_ALL 27
+#define RX_DISABLE_LLC_PROMISC 28
+#define RX_ENABLE_LLC_PROMISC 29
+
+
+#ifndef DMA_RD
+#define DMA_RD 1 /* memory -> hw */
+#endif
+#ifndef DMA_WR
+#define DMA_WR 2 /* hw -> memory */
+#endif
+#define SMT_BUF 0x80
+
+ /*
+ * bits of the frame status byte
+ */
+#define EN_IRQ_EOF 0x02 /* get IRQ after end of frame transmission */
+#define LOC_TX 0x04 /* send frame to the local SMT */
+#define LAST_FRAG 0x08 /* last TxD of the frame */
+#define FIRST_FRAG 0x10 /* first TxD of the frame */
+#define LAN_TX 0x20 /* send frame to network if set */
+#define RING_DOWN 0x40 /* error: unable to send, ring down */
+#define OUT_OF_TXD 0x80 /* error: not enough TxDs available */
+
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#ifdef LITTLE_ENDIAN
+#define HWM_REVERSE(x) (x)
+#else
+#define HWM_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
+ (((x)<< 8L)&0x00ff0000L) + \
+ (((x)>> 8L)&0x0000ff00L) + \
+ (((x)>>24L)&0x000000ffL))
+#endif
+
+#define C_INDIC (1L<<25)
+#define A_INDIC (1L<<26)
+#define RD_FS_LOCAL 0x80
+
+ /*
+ * DEBUG FLAGS
+ */
+#define DEBUG_SMTF 1
+#define DEBUG_SMT 2
+#define DEBUG_ECM 3
+#define DEBUG_RMT 4
+#define DEBUG_CFM 5
+#define DEBUG_PCM 6
+#define DEBUG_SBA 7
+#define DEBUG_ESS 8
+
+#define DB_HWM_RX 10
+#define DB_HWM_TX 11
+#define DB_HWM_GEN 12
+
+struct s_mbuf_pool {
+#ifndef MB_OUTSIDE_SMC
+ SMbuf mb[MAX_MBUF] ; /* mbuf pool */
+#endif
+ SMbuf *mb_start ; /* points to the first mb */
+ SMbuf *mb_free ; /* free queue */
+} ;
+
+struct hwm_r {
+ /*
+ * hardware modul specific receive variables
+ */
+ u_int len ; /* length of the whole frame */
+ char *mb_pos ; /* SMbuf receive position */
+} ;
+
+struct hw_modul {
+ /*
+ * All hardware modul specific variables
+ */
+ struct s_mbuf_pool mbuf_pool ;
+ struct hwm_r r ;
+
+ union s_fp_descr volatile *descr_p ; /* points to the desriptor area */
+
+ u_short pass_SMT ; /* pass SMT frames */
+ u_short pass_NSA ; /* pass all NSA frames */
+ u_short pass_DB ; /* pass Direct Beacon Frames */
+ u_short pass_llc_promisc ; /* pass all llc frames (default ON) */
+
+ SMbuf *llc_rx_pipe ; /* points to the first queued llc fr */
+ SMbuf *llc_rx_tail ; /* points to the last queued llc fr */
+ int queued_rx_frames ; /* number of queued frames */
+
+ SMbuf *txd_tx_pipe ; /* points to first mb in the txd ring */
+ SMbuf *txd_tx_tail ; /* points to last mb in the txd ring */
+ int queued_txd_mb ; /* number of SMT MBufs in txd ring */
+
+ int rx_break ; /* rev. was breaked because ind. off */
+ int leave_isr ; /* leave fddi_isr immedeately if set */
+ int isr_flag ; /* set, when HWM is entered from isr */
+ /*
+ * varaibles for the current transmit frame
+ */
+ struct s_smt_tx_queue *tx_p ; /* pointer to the transmit queue */
+ u_long tx_descr ; /* tx descriptor for FORMAC+ */
+ int tx_len ; /* tx frame length */
+ SMbuf *tx_mb ; /* SMT tx MBuf pointer */
+ char *tx_data ; /* data pointer to the SMT tx Mbuf */
+
+ int detec_count ; /* counter for out of RxD condition */
+ u_long rx_len_error ; /* rx len FORMAC != sum of fragments */
+} ;
+
+
+/*
+ * DEBUG structs and macros
+ */
+
+#ifdef DEBUG
+struct os_debug {
+ int hwm_rx ;
+ int hwm_tx ;
+ int hwm_gen ;
+} ;
+#endif
+
+#ifdef DEBUG
+#ifdef DEBUG_BRD
+#define DB_P smc->debug
+#else
+#define DB_P debug
+#endif
+
+#define DB_RX(a,b,c,lev) if (DB_P.d_os.hwm_rx >= (lev)) printf(a,b,c)
+#define DB_TX(a,b,c,lev) if (DB_P.d_os.hwm_tx >= (lev)) printf(a,b,c)
+#define DB_GEN(a,b,c,lev) if (DB_P.d_os.hwm_gen >= (lev)) printf(a,b,c)
+#else /* DEBUG */
+#define DB_RX(a,b,c,lev)
+#define DB_TX(a,b,c,lev)
+#define DB_GEN(a,b,c,lev)
+#endif /* DEBUG */
+
+#ifndef SK_BREAK
+#define SK_BREAK()
+#endif
+
+
+/*
+ * HWM Macros
+ */
+
+/*
+ * BEGIN_MANUAL_ENTRY(HWM_GET_TX_PHYS)
+ * u_long HWM_GET_TX_PHYS(txd)
+ *
+ * function MACRO (hardware module, hwmtm.h)
+ * This macro may be invoked by the OS-specific module to read
+ * the physical address of the specified TxD.
+ *
+ * para txd pointer to the TxD
+ *
+ * END_MANUAL_ENTRY
+ */
+#define HWM_GET_TX_PHYS(txd) (u_long)AIX_REVERSE((txd)->txd_tbadr)
+
+/*
+ * BEGIN_MANUAL_ENTRY(HWM_GET_TX_LEN)
+ * int HWM_GET_TX_LEN(txd)
+ *
+ * function MACRO (hardware module, hwmtm.h)
+ * This macro may be invoked by the OS-specific module to read
+ * the fragment length of the specified TxD
+ *
+ * para rxd pointer to the TxD
+ *
+ * return the length of the fragment in bytes
+ *
+ * END_MANUAL_ENTRY
+ */
+#define HWM_GET_TX_LEN(txd) ((int)AIX_REVERSE((txd)->txd_tbctrl)& RD_LENGTH)
+
+/*
+ * BEGIN_MANUAL_ENTRY(HWM_GET_TX_USED)
+ * txd *HWM_GET_TX_USED(smc,queue)
+ *
+ * function MACRO (hardware module, hwmtm.h)
+ * This macro may be invoked by the OS-specific module to get the
+ * number of used TxDs for the queue, specified by the index.
+ *
+ * para queue the number of the send queue: Can be specified by
+ * QUEUE_A0, QUEUE_S or (frame_status & QUEUE_A0)
+ *
+ * return number of used TxDs for this send queue
+ *
+ * END_MANUAL_ENTRY
+ */
+#define HWM_GET_TX_USED(smc,queue) (int) (smc)->hw.fp.tx_q[queue].tx_used
+
+/*
+ * BEGIN_MANUAL_ENTRY(HWM_GET_CURR_TXD)
+ * txd *HWM_GET_CURR_TXD(smc,queue)
+ *
+ * function MACRO (hardware module, hwmtm.h)
+ * This macro may be invoked by the OS-specific module to get the
+ * pointer to the TxD which points to the current queue put
+ * position.
+ *
+ * para queue the number of the send queue: Can be specified by
+ * QUEUE_A0, QUEUE_S or (frame_status & QUEUE_A0)
+ *
+ * return pointer to the current TxD
+ *
+ * END_MANUAL_ENTRY
+ */
+#define HWM_GET_CURR_TXD(smc,queue) (struct s_smt_fp_txd volatile *)\
+ (smc)->hw.fp.tx_q[queue].tx_curr_put
+
+/*
+ * BEGIN_MANUAL_ENTRY(HWM_TX_CHECK)
+ * void HWM_TX_CHECK(smc,frame_status,low_water)
+ *
+ * function MACRO (hardware module, hwmtm.h)
+ * This macro is invoked by the OS-specific before it left it's
+ * driver_send function. This macro calls mac_drv_clear_txd
+ * if the free TxDs of the current transmit queue is equal or
+ * lower than the given low water mark.
+ *
+ * para frame_status status of the frame, see design description
+ * low_water low water mark of free TxD's
+ *
+ * END_MANUAL_ENTRY
+ */
+#ifndef HWM_NO_FLOW_CTL
+#define HWM_TX_CHECK(smc,frame_status,low_water) {\
+ if ((low_water)>=(smc)->hw.fp.tx_q[(frame_status)&QUEUE_A0].tx_free) {\
+ mac_drv_clear_txd(smc) ;\
+ }\
+}
+#else
+#define HWM_TX_CHECK(smc,frame_status,low_water) mac_drv_clear_txd(smc)
+#endif
+
+/*
+ * BEGIN_MANUAL_ENTRY(HWM_GET_RX_FRAG_LEN)
+ * int HWM_GET_RX_FRAG_LEN(rxd)
+ *
+ * function MACRO (hardware module, hwmtm.h)
+ * This macro may be invoked by the OS-specific module to read
+ * the fragment length of the specified RxD
+ *
+ * para rxd pointer to the RxD
+ *
+ * return the length of the fragment in bytes
+ *
+ * END_MANUAL_ENTRY
+ */
+#define HWM_GET_RX_FRAG_LEN(rxd) ((int)AIX_REVERSE((rxd)->rxd_rbctrl)& \
+ RD_LENGTH)
+
+/*
+ * BEGIN_MANUAL_ENTRY(HWM_GET_RX_PHYS)
+ * u_long HWM_GET_RX_PHYS(rxd)
+ *
+ * function MACRO (hardware module, hwmtm.h)
+ * This macro may be invoked by the OS-specific module to read
+ * the physical address of the specified RxD.
+ *
+ * para rxd pointer to the RxD
+ *
+ * return the RxD's physical pointer to the data fragment
+ *
+ * END_MANUAL_ENTRY
+ */
+#define HWM_GET_RX_PHYS(rxd) (u_long)AIX_REVERSE((rxd)->rxd_rbadr)
+
+/*
+ * BEGIN_MANUAL_ENTRY(HWM_GET_RX_USED)
+ * int HWM_GET_RX_USED(smc)
+ *
+ * function MACRO (hardware module, hwmtm.h)
+ * This macro may be invoked by the OS-specific module to get
+ * the count of used RXDs in receive queue 1.
+ *
+ * return the used RXD count of receive queue 1
+ *
+ * NOTE: Remember, because of an ASIC bug at least one RXD should be unused
+ * in the descriptor ring !
+ *
+ * END_MANUAL_ENTRY
+ */
+#define HWM_GET_RX_USED(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_used)
+
+/*
+ * BEGIN_MANUAL_ENTRY(HWM_GET_RX_FREE)
+ * int HWM_GET_RX_FREE(smc)
+ *
+ * function MACRO (hardware module, hwmtm.h)
+ * This macro may be invoked by the OS-specific module to get
+ * the rxd_free count of receive queue 1.
+ *
+ * return the rxd_free count of receive queue 1
+ *
+ * END_MANUAL_ENTRY
+ */
+#define HWM_GET_RX_FREE(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_free-1)
+
+/*
+ * BEGIN_MANUAL_ENTRY(HWM_GET_CURR_RXD)
+ * rxd *HWM_GET_CURR_RXD(smc)
+ *
+ * function MACRO (hardware module, hwmtm.h)
+ * This macro may be invoked by the OS-specific module to get the
+ * pointer to the RxD which points to the current queue put
+ * position.
+ *
+ * return pointer to the current RxD
+ *
+ * END_MANUAL_ENTRY
+ */
+#define HWM_GET_CURR_RXD(smc) (struct s_smt_fp_rxd volatile *)\
+ (smc)->hw.fp.rx_q[QUEUE_R1].rx_curr_put
+
+/*
+ * BEGIN_MANUAL_ENTRY(HWM_RX_CHECK)
+ * void HWM_RX_CHECK(smc,low_water)
+ *
+ * function MACRO (hardware module, hwmtm.h)
+ * This macro is invoked by the OS-specific before it left the
+ * function mac_drv_rx_complete. This macro calls mac_drv_fill_rxd
+ * if the number of used RxDs is equal or lower than the
+ * the given low water mark.
+ *
+ * para low_water low water mark of used RxD's
+ *
+ * END_MANUAL_ENTRY
+ */
+#ifndef HWM_NO_FLOW_CTL
+#define HWM_RX_CHECK(smc,low_water) {\
+ if ((low_water) >= (smc)->hw.fp.rx_q[QUEUE_R1].rx_used) {\
+ mac_drv_fill_rxd(smc) ;\
+ }\
+}
+#else
+#define HWM_RX_CHECK(smc,low_water) mac_drv_fill_rxd(smc)
+#endif
+
+#ifndef HWM_EBASE
+#define HWM_EBASE 500
+#endif
+
+#define HWM_E0001 HWM_EBASE + 1
+#define HWM_E0001_MSG "HWM: Wrong size of s_rxd_os struct"
+#define HWM_E0002 HWM_EBASE + 2
+#define HWM_E0002_MSG "HWM: Wrong size of s_txd_os struct"
+#define HWM_E0003 HWM_EBASE + 3
+#define HWM_E0003_MSG "HWM: smt_free_mbuf() called with NULL pointer"
+#define HWM_E0004 HWM_EBASE + 4
+#define HWM_E0004_MSG "HWM: Parity error rx queue 1"
+#define HWM_E0005 HWM_EBASE + 5
+#define HWM_E0005_MSG "HWM: Encoding error rx queue 1"
+#define HWM_E0006 HWM_EBASE + 6
+#define HWM_E0006_MSG "HWM: Encoding error async tx queue"
+#define HWM_E0007 HWM_EBASE + 7
+#define HWM_E0007_MSG "HWM: Encoding error sync tx queue"
+#define HWM_E0008 HWM_EBASE + 8
+#define HWM_E0008_MSG ""
+#define HWM_E0009 HWM_EBASE + 9
+#define HWM_E0009_MSG "HWM: Out of RxD condition detected"
+#define HWM_E0010 HWM_EBASE + 10
+#define HWM_E0010_MSG "HWM: A protocol layer has tried to send a frame with an invalid frame control"
+#define HWM_E0011 HWM_EBASE + 11
+#define HWM_E0011_MSG "HWM: mac_drv_clear_tx_queue was called although the hardware wasn't stopped"
+#define HWM_E0012 HWM_EBASE + 12
+#define HWM_E0012_MSG "HWM: mac_drv_clear_rx_queue was called although the hardware wasn't stopped"
+#define HWM_E0013 HWM_EBASE + 13
+#define HWM_E0013_MSG "HWM: mac_drv_repair_descr was called although the hardware wasn't stopped"
+
+#endif
diff --git a/drivers/net/skfp/h/lnkstat.h b/drivers/net/skfp/h/lnkstat.h
new file mode 100644
index 0000000..c73dcd9
--- /dev/null
+++ b/drivers/net/skfp/h/lnkstat.h
@@ -0,0 +1,84 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*
+ * Definition of the Error Log Structure
+ * This structure will be copied into the Error Log buffer
+ * during the NDIS General Request ReadErrorLog by the MAC Driver
+ */
+
+struct s_error_log {
+
+ /*
+ * place holder for token ring adapter error log (zeros)
+ */
+ u_char reserved_0 ; /* byte 0 inside Error Log */
+ u_char reserved_1 ; /* byte 1 */
+ u_char reserved_2 ; /* byte 2 */
+ u_char reserved_3 ; /* byte 3 */
+ u_char reserved_4 ; /* byte 4 */
+ u_char reserved_5 ; /* byte 5 */
+ u_char reserved_6 ; /* byte 6 */
+ u_char reserved_7 ; /* byte 7 */
+ u_char reserved_8 ; /* byte 8 */
+ u_char reserved_9 ; /* byte 9 */
+ u_char reserved_10 ; /* byte 10 */
+ u_char reserved_11 ; /* byte 11 */
+ u_char reserved_12 ; /* byte 12 */
+ u_char reserved_13 ; /* byte 13 */
+
+ /*
+ * FDDI link statistics
+ */
+/*
+ * smt error low
+ */
+#define SMT_ERL_AEB (1<<15) /* A elast. buffer */
+#define SMT_ERL_BLC (1<<14) /* B link error condition */
+#define SMT_ERL_ALC (1<<13) /* A link error condition */
+#define SMT_ERL_NCC (1<<12) /* not copied condition */
+#define SMT_ERL_FEC (1<<11) /* frame error condition */
+
+/*
+ * smt event low
+ */
+#define SMT_EVL_NCE (1<<5)
+
+ u_short smt_error_low ; /* byte 14/15 */
+ u_short smt_error_high ; /* byte 16/17 */
+ u_short smt_event_low ; /* byte 18/19 */
+ u_short smt_event_high ; /* byte 20/21 */
+ u_short connection_policy_violation ; /* byte 22/23 */
+ u_short port_event ; /* byte 24/25 */
+ u_short set_count_low ; /* byte 26/27 */
+ u_short set_count_high ; /* byte 28/29 */
+ u_short aci_id_code ; /* byte 30/31 */
+ u_short purge_frame_counter ; /* byte 32/33 */
+
+ /*
+ * CMT and RMT state machines
+ */
+ u_short ecm_state ; /* byte 34/35 */
+ u_short pcm_a_state ; /* byte 36/37 */
+ u_short pcm_b_state ; /* byte 38/39 */
+ u_short cfm_state ; /* byte 40/41 */
+ u_short rmt_state ; /* byte 42/43 */
+
+ u_short not_used[30] ; /* byte 44-103 */
+
+ u_short ucode_version_level ; /* byte 104/105 */
+
+ u_short not_used_1 ; /* byte 106/107 */
+ u_short not_used_2 ; /* byte 108/109 */
+} ;
diff --git a/drivers/net/skfp/h/mbuf.h b/drivers/net/skfp/h/mbuf.h
new file mode 100644
index 0000000..b339d1f
--- /dev/null
+++ b/drivers/net/skfp/h/mbuf.h
@@ -0,0 +1,54 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+#ifndef _MBUF_
+#define _MBUF_
+
+#ifndef PCI
+#define M_SIZE 4550
+#else
+#define M_SIZE 4504
+#endif
+
+#ifndef MAX_MBUF
+#define MAX_MBUF 4
+#endif
+
+#ifndef NO_STD_MBUF
+#define sm_next m_next
+#define sm_off m_off
+#define sm_len m_len
+#define sm_data m_data
+#define SMbuf Mbuf
+#define mtod smtod
+#define mtodoff smtodoff
+#endif
+
+struct s_mbuf {
+ struct s_mbuf *sm_next ; /* low level linked list */
+ short sm_off ; /* offset in m_data */
+ u_int sm_len ; /* len of data */
+#ifdef PCI
+ int sm_use_count ;
+#endif
+ char sm_data[M_SIZE] ;
+} ;
+
+typedef struct s_mbuf SMbuf ;
+
+/* mbuf head, to typed data */
+#define smtod(x,t) ((t)((x)->sm_data + (x)->sm_off))
+#define smtodoff(x,t,o) ((t)((x)->sm_data + (o)))
+
+#endif /* _MBUF_ */
diff --git a/drivers/net/skfp/h/osdef1st.h b/drivers/net/skfp/h/osdef1st.h
new file mode 100644
index 0000000..5359eb5
--- /dev/null
+++ b/drivers/net/skfp/h/osdef1st.h
@@ -0,0 +1,123 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*
+ * Operating system-dependent definitions that have to be defined
+ * before any other header files are included.
+ */
+
+// HWM (HardWare Module) Definitions
+// -----------------------
+
+#ifdef __LITTLE_ENDIAN
+#define LITTLE_ENDIAN
+#else
+#define BIG_ENDIAN
+#endif
+
+// this is set in the makefile
+// #define PCI /* only PCI adapters supported by this driver */
+// #define MEM_MAPPED_IO /* use memory mapped I/O */
+
+
+#define USE_CAN_ADDR /* DA and SA in MAC header are canonical. */
+
+#define MB_OUTSIDE_SMC /* SMT Mbufs outside of smc struct. */
+
+// -----------------------
+
+
+// SMT Definitions
+// -----------------------
+#define SYNC /* allow synchronous frames */
+
+// #define SBA /* Synchronous Bandwidth Allocator support */
+ /* not available as free source */
+
+#define ESS /* SBA End Station Support */
+
+#define SMT_PANIC(smc, nr, msg) printk(KERN_INFO "SMT PANIC: code: %d, msg: %s\n",nr,msg)
+
+
+#ifdef DEBUG
+#define printf(s,args...) printk(KERN_INFO s, ## args)
+#endif
+
+// #define HW_PTR u_long
+// -----------------------
+
+
+
+// HWM and OS-specific buffer definitions
+// -----------------------
+
+// default number of receive buffers.
+#define NUM_RECEIVE_BUFFERS 10
+
+// default number of transmit buffers.
+#define NUM_TRANSMIT_BUFFERS 10
+
+// Number of SMT buffers (Mbufs).
+#define NUM_SMT_BUF 4
+
+// Number of TXDs for asynchronous transmit queue.
+#define HWM_ASYNC_TXD_COUNT (NUM_TRANSMIT_BUFFERS + NUM_SMT_BUF)
+
+// Number of TXDs for synchronous transmit queue.
+#define HWM_SYNC_TXD_COUNT HWM_ASYNC_TXD_COUNT
+
+
+// Number of RXDs for receive queue #1.
+// Note: Workaround for ASIC Errata #7: One extra RXD is required.
+#if (NUM_RECEIVE_BUFFERS > 100)
+#define SMT_R1_RXD_COUNT (1 + 100)
+#else
+#define SMT_R1_RXD_COUNT (1 + NUM_RECEIVE_BUFFERS)
+#endif
+
+// Number of RXDs for receive queue #2.
+#define SMT_R2_RXD_COUNT 0 // Not used.
+// -----------------------
+
+
+
+/*
+ * OS-specific part of the transmit/receive descriptor structure (TXD/RXD).
+ *
+ * Note: The size of these structures must follow this rule:
+ *
+ * sizeof(struct) + 2*sizeof(void*) == n * 16, n >= 1
+ *
+ * We use the dma_addr fields under Linux to keep track of the
+ * DMA address of the packet data, for later pci_unmap_single. -DaveM
+ */
+
+struct s_txd_os { // os-specific part of transmit descriptor
+ struct sk_buff *skb;
+ dma_addr_t dma_addr;
+} ;
+
+struct s_rxd_os { // os-specific part of receive descriptor
+ struct sk_buff *skb;
+ dma_addr_t dma_addr;
+} ;
+
+
+/*
+ * So we do not need to make too many modifications to the generic driver
+ * parts, we take advantage of the AIX byte swapping macro interface.
+ */
+
+#define AIX_REVERSE(x) ((u32)le32_to_cpu((u32)(x)))
+#define MDR_REVERSE(x) ((u32)le32_to_cpu((u32)(x)))
diff --git a/drivers/net/skfp/h/sba.h b/drivers/net/skfp/h/sba.h
new file mode 100644
index 0000000..df716cd
--- /dev/null
+++ b/drivers/net/skfp/h/sba.h
@@ -0,0 +1,142 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*
+ * Synchronous Bandwith Allocation (SBA) structs
+ */
+
+#ifndef _SBA_
+#define _SBA_
+
+#include "h/mbuf.h"
+#include "h/sba_def.h"
+
+#ifdef SBA
+
+/* Timer Cell Template */
+struct timer_cell {
+ struct timer_cell *next_ptr ;
+ struct timer_cell *prev_ptr ;
+ u_long start_time ;
+ struct s_sba_node_vars *node_var ;
+} ;
+
+/*
+ * Node variables
+ */
+struct s_sba_node_vars {
+ u_char change_resp_flag ;
+ u_char report_resp_flag ;
+ u_char change_req_flag ;
+ u_char report_req_flag ;
+ long change_amount ;
+ long node_overhead ;
+ long node_payload ;
+ u_long node_status ;
+ u_char deallocate_status ;
+ u_char timer_state ;
+ u_short report_cnt ;
+ long lastrep_req_tranid ;
+ struct fddi_addr mac_address ;
+ struct s_sba_sessions *node_sessions ;
+ struct timer_cell timer ;
+} ;
+
+/*
+ * Session variables
+ */
+struct s_sba_sessions {
+ u_long deallocate_status ;
+ long session_overhead ;
+ u_long min_segment_size ;
+ long session_payload ;
+ u_long session_status ;
+ u_long sba_category ;
+ long lastchg_req_tranid ;
+ u_short session_id ;
+ u_char class ;
+ u_char fddi2 ;
+ u_long max_t_neg ;
+ struct s_sba_sessions *next_session ;
+} ;
+
+struct s_sba {
+
+ struct s_sba_node_vars node[MAX_NODES] ;
+ struct s_sba_sessions session[MAX_SESSIONS] ;
+
+ struct s_sba_sessions *free_session ; /* points to the first */
+ /* free session */
+
+ struct timer_cell *tail_timer ; /* points to the last timer cell */
+
+ /*
+ * variables for allocation actions
+ */
+ long total_payload ; /* Total Payload */
+ long total_overhead ; /* Total Overhead */
+ long sba_allocatable ; /* allocatable sync bandwidth */
+
+ /*
+ * RAF message receive parameters
+ */
+ long msg_path_index ; /* Path Type */
+ long msg_sba_pl_req ; /* Payload Request */
+ long msg_sba_ov_req ; /* Overhead Request */
+ long msg_mib_pl ; /* Current Payload for this Path */
+ long msg_mib_ov ; /* Current Overhead for this Path*/
+ long msg_category ; /* Category of the Allocation */
+ u_long msg_max_t_neg ; /* longest T_Neg acceptable */
+ u_long msg_min_seg_siz ; /* minimum segement size */
+ struct smt_header *sm ; /* points to the rec message */
+ struct fddi_addr *msg_alloc_addr ; /* Allocation Address */
+
+ /*
+ * SBA variables
+ */
+ u_long sba_t_neg ; /* holds the last T_NEG */
+ long sba_max_alloc ; /* the parsed value of SBAAvailable */
+
+ /*
+ * SBA state machine variables
+ */
+ short sba_next_state ; /* the next state of the SBA */
+ char sba_command ; /* holds the execuded SBA cmd */
+ u_char sba_available ; /* parsed value after possible check */
+} ;
+
+#endif /* SBA */
+
+ /*
+ * variables for the End Station Support
+ */
+struct s_ess {
+
+ /*
+ * flags and counters
+ */
+ u_char sync_bw_available ; /* is set if sync bw is allocated */
+ u_char local_sba_active ; /* set when a local sba is available */
+ char raf_act_timer_poll ; /* activate the timer to send allc req */
+ char timer_count ; /* counts every timer function call */
+
+ SMbuf *sba_reply_pend ; /* local reply for the sba is pending */
+
+ /*
+ * variables for the ess bandwidth control
+ */
+ long sync_bw ; /* holds the allocaed sync bw */
+ u_long alloc_trans_id ; /* trans id of the last alloc req */
+} ;
+#endif
diff --git a/drivers/net/skfp/h/sba_def.h b/drivers/net/skfp/h/sba_def.h
new file mode 100644
index 0000000..0459a09
--- /dev/null
+++ b/drivers/net/skfp/h/sba_def.h
@@ -0,0 +1,76 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+#define PHYS 0 /* physical addr */
+#define PERM_ADDR 0x80 /* permanet address */
+#define SB_STATIC 0x00000001
+#define MAX_PAYLOAD 1562
+#define PRIMARY_RING 0x00000001
+#ifndef NULL
+#define NULL 0x00
+#endif
+
+/*********************** SB_Input Variable Values ***********************/
+/* may be needed when ever the SBA state machine is called */
+
+#define UNKNOWN_SYNC_SOURCE 0x0001
+#define REQ_ALLOCATION 0x0002
+#define REPORT_RESP 0x0003
+#define CHANGE_RESP 0x0004
+#define TNEG 0x0005
+#define NIF 0x0006
+#define SB_STOP 0x0007
+#define SB_START 0x0008
+#define REPORT_TIMER 0x0009
+#define CHANGE_REQUIRED 0x000A
+
+#define DEFAULT_OV 50
+
+#ifdef SBA
+/**************************** SBA STATES *****************************/
+
+#define SBA_STANDBY 0x00000000
+#define SBA_ACTIVE 0x00000001
+#define SBA_RECOVERY 0x00000002
+#define SBA_REPORT 0x00000003
+#define SBA_CHANGE 0x00000004
+
+/**************************** OTHERS *********************************/
+
+#define FIFTY_PERCENT 50 /* bytes per second */
+#define MAX_SESSIONS 150
+#define TWO_MINUTES 13079 /* 9.175 ms/tick */
+#define FIFTY_BYTES 50
+#define SBA_DENIED 0x0000000D
+#define I_NEED_ONE 0x00000000
+#define MAX_NODES 50
+/*#define T_REPORT 0x59682F00L*/ /* 120s/80ns in Hex */
+#define TWO_MIN 120 /* seconds */
+#define SBA_ST_UNKNOWN 0x00000002
+#define SBA_ST_ACTIVE 0x00000001
+#define S_CLEAR 0x00000000L
+#define ZERO 0x00000000
+#define FULL 0x00000000 /* old: 0xFFFFFFFFF */
+#define S_SET 0x00000001L
+#define LOW_PRIO 0x02 /* ??????? */
+#define OK 0x01 /* ??????? */
+#define NOT_OK 0x00 /* ??????? */
+
+/****************************************/
+/* deallocate_status[ni][si] values */
+/****************************************/
+#define TX_CHANGE 0X00000001L
+#define PENDING 0x00000002L
+#define NONE 0X00000000L
+#endif
diff --git a/drivers/net/skfp/h/skfbi.h b/drivers/net/skfp/h/skfbi.h
new file mode 100644
index 0000000..ba347d6
--- /dev/null
+++ b/drivers/net/skfp/h/skfbi.h
@@ -0,0 +1,1919 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+#ifndef _SKFBI_H_
+#define _SKFBI_H_
+
+#ifdef SYNC
+#define exist_board_far exist_board
+#define get_board_para_far get_board_para
+#endif
+
+/*
+ * physical address offset + IO-Port base address
+ */
+#ifndef PCI
+#define ADDR(a) ((a)+smc->hw.iop)
+#define ADDRS(smc,a) ((a)+(smc)->hw.iop)
+#endif
+
+/*
+ * FDDI-Fx (x := {I(SA), E(ISA), M(CA), P(CI)})
+ * address calculation & function defines
+ */
+
+#ifdef EISA
+
+/*
+ * Configuration PROM: !! all 8-Bit IO's !!
+ * |<- MAC-Address ->|
+ * /-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-/
+ * val: |PROD_ID0..3| | free | |00|00|5A|40| |nn|mm|00|00|
+ * /-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-/
+ * IO- ^ ^ ^ ^ ^
+ * port 0C80 0C83 0C88 0C90 0C98
+ * | \
+ * | \
+ * | \______________________________________________
+ * EISA Expansion Board Product ID: \
+ * BIT: |7 6 5 4 3 2 1 0| \
+ * | PROD_ID0 | PROD_ID1 | PROD_ID2 | PROD_ID3 |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |0| MAN_C0 | MAN_C1 | MAN_C2 | PROD1 | PROD0 | REV1 | REV0 |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * ^=reserved | product numb. | revision numb |
+ * MAN_Cx = compressed manufacterer code (x:=0..2)
+ * ASCII : 'A'..'Z' : 0x41..0x5A -> compr.(c-0x40) : 0x01..0x1A (5Bits!)
+ */
+
+#ifndef MULT_OEM
+#ifndef OEM_CONCEPT
+#define MAN_C0 ('S'-0x40)
+#define MAN_C1 ('K'-0x40)
+#define MAN_C2 ('D'-0x40)
+#define PROD_ID0 (u_char)((MAN_C0<<2) | (MAN_C1>>3))
+#define PROD_ID1 (u_char)(((MAN_C1<<5) & 0xff) | MAN_C2)
+#define PROD_ID2 (u_char)(1) /* prod. nr. */
+#define PROD_ID3 (u_char)(0) /* rev. nr. */
+
+#ifndef OEM_USER_DATA
+#define OEM_USER_DATA "SK-NET FDDI V2.0 Userdata"
+#endif
+#else /* OEM_CONCEPT */
+
+/* MAN_C(0|1|2) no longer present (ra). */
+#define PROD_ID0 (u_char)OEM_PROD_ID0
+#define PROD_ID1 (u_char)OEM_PROD_ID1
+#define PROD_ID2 (u_char)OEM_PROD_ID2
+#define PROD_ID3 (u_char)OEM_PROD_ID3
+#endif /* OEM_CONCEPT */
+
+#define SKLOGO PROD_ID0, PROD_ID1, PROD_ID2, PROD_ID3
+#endif /* MULT_OEM */
+
+#define SADDRL (0) /* start address SKLOGO */
+#define SA_MAC (0x10) /* start addr. MAC_AD within the PROM */
+#define PRA_OFF (4)
+#define SA_PMD_TYPE (8) /* start addr. PMD-Type */
+
+#define SKFDDI_PSZ 32 /* address PROM size */
+
+/*
+ * address transmission from logical to physical offset address on board
+ */
+#define FMA(a) (0x0400|((a)<<1)) /* FORMAC+ (r/w) */
+#define P1A(a) (0x0800|((a)<<1)) /* PLC1 (r/w) */
+#define P2A(a) (0x0840|((a)<<1)) /* PLC2 (r/w) */
+#define TIA(a) (0x0880|((a)<<1)) /* Timer (r/w) */
+#define PRA(a) (0x0c80| (a)) /* configuration PROM */
+#define C0A(a) (0x0c84| (a)) /* config. RAM */
+#define C1A(a) (0x0ca0| (a)) /* IRQ-, DMA-nr., EPROM type */
+#define C2A(a) (0x0ca4| (a)) /* EPROM and PAGE selector */
+
+#define CONF C0A(0) /* config RAM (card enable bit port) */
+#define PGRA C2A(0) /* Flash page register */
+#define CDID PRA(0) /* Card ID I/O port addr. offset */
+
+
+/*
+ * physical address offset + slot specific IO-Port base address
+ */
+#define FM_A(a) (FMA(a)+smc->hw.iop) /* FORMAC Plus physical addr */
+#define P1_A(a) (P1A(a)+smc->hw.iop) /* PLC1 (r/w) */
+#define P2_A(a) (P2A(a)+smc->hw.iop) /* PLC2 (r/w) */
+#define TI_A(a) (TIA(a)+smc->hw.iop) /* Timer (r/w) */
+#define PR_A(a) (PRA(a)+smc->hw.iop) /* config. PROM */
+#define C0_A(a) (C0A(a)+smc->hw.iop) /* config. RAM */
+#define C1_A(a) (C1A(a)+smc->hw.iop) /* config. RAM */
+#define C2_A(a) (C2A(a)+smc->hw.iop) /* config. RAM */
+
+
+#define CSRA 0x0008 /* control/status register address (r/w) */
+#define ISRA 0x0008 /* int. source register address (upper 8Bits) */
+#define PLC1I 0x001a /* clear PLC1 interrupt (write only) */
+#define PLC2I 0x0020 /* clear PLC2 interrupt (write only) */
+#define CSFA 0x001c /* control/status FIFO BUSY flags (read only) */
+#define RQAA 0x001c /* Request reg. (write only) */
+#define WCTA 0x001e /* word counter (r/w) */
+#define FFLAG 0x005e /* FLAG/V_FULL (FIFO almost full, write only)*/
+
+#define CSR_A (CSRA+smc->hw.iop) /* control/status register address (r/w) */
+#ifdef UNIX
+#define CSR_AS(smc) (CSRA+(smc)->hw.iop) /* control/status register address (r/w) */
+#endif
+#define ISR_A (ISRA+smc->hw.iop) /* int. source register address (upper 8Bits) */
+#define PLC1_I (PLC1I+smc->hw.iop) /* clear PLC1 internupt (write only) */
+#define PLC2_I (PLC2I+smc->hw.iop) /* clear PLC2 interrupt (write only) */
+#define CSF_A (CSFA+smc->hw.iop) /* control/status FIFO BUSY flags (r/w) */
+#define RQA_A (RQAA+smc->hw.iop) /* Request reg. (write only) */
+#define WCT_A (WCTA+smc->hw.iop) /* word counter (r/w) */
+#define FFLAG_A (FFLAG+smc->hw.iop) /* FLAG/V_FULL (FIFO almost full, write only)*/
+
+/*
+ * control/status register CSRA bits
+ */
+/* write */
+#define CS_CRESET 0x01 /* Card reset (0=reset) */
+#define CS_RESET_FIFO 0x02 /* FIFO reset (0=reset) */
+#define CS_IMSK 0x04 /* enable IRQ (1=enable, 0=disable) */
+#define CS_EN_IRQ_TC 0x08 /* enable IRQ from transfer counter */
+#define CS_BYPASS 0x20 /* bypass switch (0=remove, 1=insert)*/
+#define CS_LED_0 0x40 /* switch LED 0 */
+#define CS_LED_1 0x80 /* switch LED 1 */
+/* read */
+#define CS_BYSTAT 0x40 /* 0=Bypass exist, 1= ..not */
+#define CS_SAS 0x80 /* single attachement station (=1) */
+
+/*
+ * control/status register CSFA bits (FIFO)
+ */
+#define CSF_MUX0 0x01
+#define CSF_MUX1 0x02
+#define CSF_HSREQ0 0x04
+#define CSF_HSREQ1 0x08
+#define CSF_HSREQ2 0x10
+#define CSF_BUSY_DMA 0x40
+#define CSF_BUSY_FIFO 0x80
+
+/*
+ * Interrupt source register ISRA (upper 8 data bits) read only & low activ.
+ */
+#define IS_MINTR1 0x0100 /* FORMAC ST1U/L & ~IMSK1U/L*/
+#define IS_MINTR2 0x0200 /* FORMAC ST2U/L & ~IMSK2U/L*/
+#define IS_PLINT1 0x0400 /* PLC1 */
+#define IS_PLINT2 0x0800 /* PLC2 */
+#define IS_TIMINT 0x1000 /* Timer 82C54-2 */
+#define IS_TC 0x2000 /* transf. counter */
+
+#define ALL_IRSR (IS_MINTR1|IS_MINTR2|IS_PLINT1|IS_PLINT2|IS_TIMINT|IS_TC)
+
+/*
+ * CONFIG<0> RAM (C0_A())
+ */
+#define CFG_CARD_EN 0x01 /* card enable */
+
+/*
+ * CONFIG<1> RAM (C1_A())
+ */
+#define CFG_IRQ_SEL 0x03 /* IRQ select (4 nr.) */
+#define CFG_IRQ_TT 0x04 /* IRQ trigger type (LEVEL/EDGE) */
+#define CFG_DRQ_SEL 0x18 /* DMA requ. (4 nr.) */
+#define CFG_BOOT_EN 0x20 /* 0=BOOT-, 1=Application Software */
+#define CFG_PROG_EN 0x40 /* V_Prog for FLASH_PROM (1=on) */
+
+/*
+ * CONFIG<2> RAM (C2_A())
+ */
+#define CFG_EPROM_SEL 0x0f /* FPROM start address selection */
+#define CFG_PAGE 0xf0 /* FPROM page selection */
+
+
+#define READ_PROM(a) ((u_char)inp(a))
+#define GET_PAGE(i) outp(C2_A(0),((int)(i)<<4) | (inp(C2_A(0)) & ~CFG_PAGE))
+#define FPROM_SW() (inp(C1_A(0)) & CFG_BOOT_EN)
+
+#define MAX_PAGES 16 /* 16 pages */
+#define MAX_FADDR 0x2000 /* 8K per page */
+#define VPP_ON() outp(C1_A(0),inp(C1_A(0)) | CFG_PROG_EN)
+#define VPP_OFF() outp(C1_A(0),inp(C1_A(0)) & ~CFG_PROG_EN)
+
+#define DMA_BUSY() (inpw(CSF_A) & CSF_BUSY_DMA)
+#define FIFO_BUSY() (inpw(CSF_A) & CSF_BUSY_FIFO)
+#define DMA_FIFO_BUSY() (inpw(CSF_A) & (CSF_BUSY_DMA | CSF_BUSY_FIFO))
+#define BUS_CHECK()
+
+#ifdef UNISYS
+/* For UNISYS use another macro with drv_usecewait function */
+#define CHECK_DMA() {u_long k = 1000000; \
+ while (k && (DMA_BUSY())) { k--; drv_usecwait(20); } \
+ if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
+#else
+#define CHECK_DMA() {u_long k = 1000000 ;\
+ while (k && (DMA_BUSY())) k-- ;\
+ if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
+#endif
+
+#define CHECK_FIFO() {u_long k = 1000000 ;\
+ while (k && (FIFO_BUSY())) k-- ;\
+ if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; }
+
+#define CHECK_DMA_FIFO() {u_long k = 1000000 ;\
+ while (k && (DMA_FIFO_BUSY())) k-- ;\
+ if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; }
+
+#define GET_ISR() ~inpw(ISR_A)
+#define CHECK_ISR() ~inpw(ISR_A)
+
+#ifndef UNIX
+#ifndef WINNT
+#define CLI_FBI() outpw(CSR_A,(inpw(CSR_A)&\
+ (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led)
+#else /* WINNT */
+#define CLI_FBI() outpw(CSR_A,(l_inpw(CSR_A)&\
+ (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led)
+#endif /* WINNT */
+#else /* UNIX */
+#define CLI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\
+ (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|(smc)->hw.led)
+#endif
+
+#ifndef UNIX
+#define STI_FBI() outpw(CSR_A,(inpw(CSR_A)&\
+ (CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|smc->hw.led)
+#else
+#define STI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\
+ (CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|(smc)->hw.led)
+#endif
+
+/* EISA DMA Controller */
+#define DMA_WRITE_SINGLE_MASK_BIT_M 0x0a /* Master DMA Controller */
+#define DMA_WRITE_SINGLE_MASK_BIT_S 0xd4 /* Slave DMA Controller */
+#define DMA_CLEAR_BYTE_POINTER_M 0x0c
+#define DMA_CLEAR_BYTE_POINTER_S 0xd8
+
+#endif /* EISA */
+
+#ifdef MCA
+
+/*
+ * POS Register: !! all I/O's are 8-Bit !!
+ */
+#define POS_SYS_SETUP 0x94 /* system setup register */
+#define POS_SYSTEM 0xff /* system mode */
+
+#define POS_CHANNEL_POS 0x96 /* register slot ID */
+#define POS_CHANNEL_BIT 0x08 /* mask for -"- */
+
+#define POS_BASE 0x100 /* POS base address */
+#define POS_ID_LOW POS_BASE /* card ID low */
+#define POS_ID_HIGH (POS_BASE+1) /* card ID high */
+#define POS_102 (POS_BASE+2) /* card en., arbitration level .. */
+#define POS_103 (POS_BASE+3) /* FPROM addr, page */
+#define POS_104 (POS_BASE+4) /* I/O, IRQ */
+#define POS_105 (POS_BASE+5) /* POS_CHCK */
+#define POS_106 (POS_BASE+6) /* to read VPD */
+#define POS_107 (POS_BASE+7) /* added without function */
+
+/* FM1 card IDs */
+#define FM1_CARD_ID0 0x83
+#define FM1_CARD_ID1 0
+
+#define FM1_IBM_ID0 0x9c
+#define FM1_IBM_ID1 0x8f
+
+
+/* FM2 card IDs */
+#define FM2_CARD_ID0 0xab
+#define FM2_CARD_ID1 0
+
+#define FM2_IBM_ID0 0x7e
+#define FM2_IBM_ID1 0x8f
+
+/* Board revision. */
+#define FM1_REV 0
+#define FM2_REV 1
+
+#define MAX_SLOT 8
+
+/*
+ * POS_102
+ */
+#define POS_CARD_EN 0x01 /* card enable =1 */
+#define POS_SDAT_EN 0x02 /* enable 32-bit streaming data mode */
+#define POS_EN_CHKINT 0x04 /* enable int. from check line asserted */
+#define POS_EN_BUS_ERR 0x08 /* enable int. on invalid busmaster transf. */
+#define POS_FAIRNESS 0x10 /* fairnes on =1 */
+/* attention: arbitration level used with bit 0 POS 105 */
+#define POS_LARBIT 0xe0 /* arbitration level (0,0,0)->level = 0x8
+ (1,1,1)->level = 0xf */
+/*
+ * POS_103
+ */
+#define POS_PAGE 0x07 /* FPROM page selection */
+#define POS_BOOT_EN 0x08 /* boot PROM enable =1 */
+#define POS_MSEL 0x70 /* memory start address for FPROM mapping */
+#define PROG_EN 0x80 /* FM1: Vpp prog on/off */
+#define POS_SDR 0x80 /* FM2: Streaming data bit */
+
+/*
+ * POS_104
+ */
+#define POS_IOSEL 0x3f /* selected I/O base address */
+#define POS_IRQSEL 0xc0 /* selected interrupt */
+
+/*
+ * POS_105
+ */
+#define POS_CHCK 0x80
+#define POS_SYNC_ERR 0x20 /* FM2: synchronous error reporting */
+#define POS_PAR_DATA 0x10 /* FM2: data parity enable bit */
+#define POS_PAR_ADDR 0x08 /* FM2: address parity enable bit */
+#define POS_IRQHSEL 0x02 /* FM2: Highest bit for IRQ_selection */
+#define POS_HARBIT 0x01 /* Highest bit in Bus arbitration selection */
+
+#define SA_MAC (0) /* start addr. MAC_AD within the PROM */
+#define PRA_OFF (0)
+#define SA_PMD_TYPE (8) /* start addr. PMD-Type */
+
+/*
+ * address transmission from logical to physical offset address on board
+ */
+#define FMA(a) (0x0100|((a)<<1)) /* FORMAC+ (r/w) */
+#define P2(a) (0x00c0|((a)<<1)) /* PLC2 (r/w) (DAS) */
+#define P1(a) (0x0080|((a)<<1)) /* PLC1 (r/w) */
+#define TI(a) (0x0060|((a)<<1)) /* Timer (r/w) */
+#define PR(a) (0x0040|((a)<<1)) /* configuration PROM */
+#define CS(a) (0x0020| (a)) /* control/status */
+#define FF(a) (0x0010|((a)<<1)) /* FIFO ASIC */
+#define CT(a) (0x0000|((a)<<1)) /* counter */
+
+/*
+ * counter
+ */
+#define ACLA CT(0) /* address counter low */
+#define ACHA CT(1) /* address counter high */
+#define BCN CT(2) /* byte counter */
+#define MUX CT(3) /* MUX-register */
+#define WCN CT(0x08) /* word counter */
+#define FFLG CT(0x09) /* FIFO Flags */
+
+/*
+ * test/control register (FM2 only)
+ */
+#define CNT_TST 0x018 /* Counter test control register */
+#define CNT_STP 0x01a /* Counter test step reg. (8 Bit) */
+
+/*
+ * CS register (read only)
+ */
+#define CSRA CS(0) /* control/status register address */
+#define CSFA CS(2) /* control/status FIFO BUSY ... */
+#define ISRA CS(4) /* first int. source register address */
+#define ISR2 CS(6) /* second int. source register address */
+#define LEDR CS(0x0c) /* LED register r/w */
+#define CSIL CS(0x10) /* I/O mapped POS_ID_low (100) */
+#define CSIH CS(0x12) /* - " - POS_ID_HIGH (101) */
+#define CSA CS(0x14) /* - " - POS_102 */
+#define CSM CS(0x0e) /* - " - POS_103 */
+#define CSM_FM1 CS(0x16) /* - " - POS_103 (copy in FM1) */
+#define CSI CS(0x18) /* - " - POS_104 */
+#define CSS CS(0x1a) /* - " - POS_105 */
+#define CSP_06 CS(0x1c) /* - " - POS_106 */
+#define WDOG_ST 0x1c /* Watchdog status (FM2 only) */
+#define WDOG_EN 0x1c /* Watchdog enabling (FM2 only, 8Bit) */
+#define WDOG_DIS 0x1e /* Watchdog disabling (FM2 only, 8Bit) */
+
+#define PGRA CSM /* Flash page register */
+
+
+#define WCTA FF(0) /* word counter */
+#define FFLAG FF(1) /* FLAG/V_FULL (FIFO almost full, write only)*/
+
+/*
+ * Timer register (FM2 only)
+ */
+#define RTM_CNT 0x28 /* RTM Counter */
+#define TI_DIV 0x60 /* Timer Prescaler */
+#define TI_CH1 0x62 /* Timer channel 1 counter */
+#define TI_STOP 0x64 /* Stop timer on channel 1 */
+#define TI_STRT 0x66 /* Start timer on channel 1 */
+#define TI_INI2 0x68 /* Timer: Bus master preemption */
+#define TI_CNT2 0x6a /* Timer */
+#define TI_INI3 0x6c /* Timer: Streaming data */
+#define TI_CNT3 0x6e /* Timer */
+#define WDOG_LO 0x70 /* Watchdog counter low */
+#define WDOG_HI 0x72 /* Watchdog counter high */
+#define RTM_PRE 0x74 /* restr. token prescaler */
+#define RTM_TIM 0x76 /* restr. token timer */
+
+/*
+ * Recommended Timeout values (for FM2 timer only)
+ */
+#define TOUT_BM_PRE 188 /* 3.76 usec */
+#define TOUT_S_DAT 374 /* 7.48 usec */
+
+/*
+ * CS register (write only)
+ */
+#define HSR(p) CS(0x18|(p)) /* Host request register */
+
+#define RTM_PUT 0x36 /* restr. token counter write */
+#define RTM_GET 0x28 /* - " - clear */
+#define RTM_CLEAR 0x34 /* - " - read */
+
+/*
+ * BCN Bit definitions
+ */
+#define BCN_BUSY 0x8000 /* DMA Busy flag */
+#define BCN_AZERO 0x4000 /* Almost zero flag (BCN < 4) */
+#define BCN_STREAM 0x2000 /* Allow streaming data (BCN >= 8) */
+
+/*
+ * WCN Bit definitions
+ */
+#define WCN_ZERO 0x2000 /* Zero flag (counted to zero) */
+#define WCN_AZERO 0x1000 /* Almost zero flag (BCN < 4) */
+
+/*
+ * CNT_TST Bit definitions
+ */
+#define CNT_MODE 0x01 /* Go into test mode */
+#define CNT_D32 0x02 /* 16/32 BIT test mode */
+
+/*
+ * FIFO Flag FIFO Flags/Vfull register
+ */
+#define FF_VFULL 0x003f /* V_full value mask */
+#define FFLG_FULL 0x2000 /* FULL flag */
+#define FFLG_A_FULL 0x1000 /* Almost full flag */
+#define FFLG_VFULL 0x0800 /* V_full Flag */
+#define FFLG_A_EMP 0x0400 /* almost empty flag */
+#define FFLG_EMP 0x0200 /* empty flag */
+#define FFLG_T_EMP 0x0100 /* totally empty flag */
+
+/*
+ * WDOG Watchdog status register
+ */
+#define WDOG_ALM 0x01 /* Watchdog alarm Bit */
+#define WDOG_ACT 0x02 /* Watchdog active Bit */
+
+/*
+ * CS(0) CONTROLS
+ */
+#define CS_CRESET 0x0001
+#define FIFO_RST 0x0002
+#define CS_IMSK 0x0004
+#define EN_IRQ_CHCK 0x0008
+#define EN_IRQ_TOKEN 0x0010
+#define EN_IRQ_TC 0x0020
+#define TOKEN_STATUS 0x0040
+#define RTM_CHANGE 0x0080
+
+#define CS_SAS 0x0100
+#define CS_BYSTAT 0x0200 /* bypass connected (0=conn.) */
+#define CS_BYPASS 0x0400 /* bypass on/off indication */
+
+/*
+ * CS(2) FIFOSTAT
+ */
+#define HSREQ 0x0007
+#define BIGDIR 0x0008
+#define CSF_BUSY_FIFO 0x0010
+#define CSF_BUSY_DMA 0x0020
+#define SLOT_32 0x0040
+
+#define LED_0 0x0001
+#define LED_1 0x0002
+#define LED_2 0x0100
+
+#define MAX_PAGES 8 /* pages */
+#define MAX_FADDR 0x4000 /* 16K per page */
+
+/*
+ * IRQ = ISRA || ISR2 ;
+ *
+ * ISRA = IRQ_OTH_EN && (IS_LAN | IS_BUS) ;
+ * ISR2 = IRQ_TC_EN && IS_TC ;
+ *
+ * IS_LAN = (IS_MINTR1 | IS_MINTR2 | IS_PLINT1 | IS_PLINT2 | IS_TIMINT) ||
+ * (IRQ_EN_TOKEN && IS_TOKEN) ;
+ * IS_BUS = IRQ_CHCK_EN && (IS_BUSERR | IS_CHCK_L) ;
+ */
+/*
+ * ISRA !!! activ high !!!
+ */
+#define IS_MINTR1 0x0001 /* FORMAC ST1U/L & ~IMSK1U/L*/
+#define IS_MINTR2 0x0002 /* FORMAC ST2U/L & ~IMSK2U/L*/
+#define IS_PLINT1 0x0004 /* PLC1 */
+#define IS_PLINT2 0x0008 /* PLC2 */
+#define IS_TIMINT 0x0010 /* Timer 82C54-2 */
+#define IS_TOKEN 0x0020 /* restrictet token monitoring */
+#define IS_CHCK_L 0x0040 /* check line asserted */
+#define IS_BUSERR 0x0080 /* bus error */
+/*
+ * ISR2
+ */
+#define IS_TC 0x0001 /* terminal count irq */
+#define IS_SFDBKRTN 0x0002 /* selected feedback return */
+#define IS_D16 0x0004 /* DS16 */
+#define IS_D32 0x0008 /* DS32 */
+#define IS_DPEI 0x0010 /* Data Parity Indication */
+
+#define ALL_IRSR 0x00ff
+
+#define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */
+#define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */
+#define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */
+#define TI_A(a) ADDR(TI(a)) /* Timer (r/w) FM1 only! */
+#define PR_A(a) ADDR(PR(a)) /* config. PROM */
+#define CS_A(a) ADDR(CS(a)) /* control/status */
+
+#define ISR1_A ADDR(ISRA) /* first int. source register address */
+#define ISR2_A ADDR(ISR2) /* second -"- */
+#define CSR_A ADDR(CSRA) /* control/status register address */
+#define CSF_A ADDR(CSFA) /* control/status FIFO BUSY flags (r/w) */
+
+#define CSIL_A ADDR(CSIL) /* I/O mapped POS_ID_low (102) */
+#define CSIH_A ADDR(CSIH) /* - " - POS_ID_HIGH (101) */
+#define CSA_A ADDR(CSA) /* - " - POS_102 */
+#define CSI_A ADDR(CSI) /* - " - POS_104 */
+#define CSM_A ADDR(CSM) /* - " - POS_103 */
+#define CSM_FM1_A ADDR(CSM_FM1) /* - " - POS_103 (2nd copy, FM1) */
+#define CSP_06_A ADDR(CSP_06) /* - " - POS_106 */
+
+#define WCT_A ADDR(WCTA) /* word counter (r/w) */
+#define FFLAG_A ADDR(FFLAG) /* FLAG/V_FULL (FIFO almost full, write only)*/
+
+#define ACL_A ADDR(ACLA) /* address counter low */
+#define ACH_A ADDR(ACHA) /* address counter high */
+#define BCN_A ADDR(BCN) /* byte counter */
+#define MUX_A ADDR(MUX) /* MUX-register */
+
+#define ISR_A ADDR(ISRA) /* Interrupt Source Register */
+#define FIFO_RESET_A ADDR(FIFO_RESET) /* reset the FIFO */
+#define FIFO_EN_A ADDR(FIFO_EN) /* enable the FIFO */
+
+#define WDOG_EN_A ADDR(WDOG_EN) /* reset and start the WDOG */
+#define WDOG_DIS_A ADDR(WDOG_DIS) /* disable the WDOG */
+/*
+ * all control reg. (read!) are 8 bit (except PAGE_RG_A and LEDR_A)
+ */
+#define HSR_A(p) ADDR(HSR(p)) /* Host request register */
+
+#define STAT_BYP 0 /* bypass station */
+#define STAT_INS 2 /* insert station */
+#define BYPASS(o) CS(0x10|(o)) /* o=STAT_BYP || STAT_INS */
+
+#define IRQ_TC_EN CS(0x0b) /* enable/disable IRQ on TC */
+#define IRQ_TC_DIS CS(0x0a)
+#define IRQ_TOKEN_EN CS(9) /* enable/disable IRQ on restr. Token */
+#define IRQ_TOKEN_DIS CS(8)
+#define IRQ_CHCK_EN CS(7) /* -"- IRQ after CHCK line */
+#define IRQ_CHCK_DIS CS(6)
+#define IRQ_OTH_EN CS(5) /* -"- other IRQ's */
+#define IRQ_OTH_DIS CS(4)
+#define FIFO_EN CS(3) /* disable (reset), enable FIFO */
+#define FIFO_RESET CS(2)
+#define CARD_EN CS(1) /* disable (reset), enable card */
+#define CARD_DIS CS(0)
+
+#define LEDR_A ADDR(LEDR) /* D0=green, D1=yellow, D8=L2 */
+#define PAGE_RG_A ADDR(CSM) /* D<2..0> */
+#define IRQ_CHCK_EN_A ADDR(IRQ_CHCK_EN)
+#define IRQ_CHCK_DIS_A ADDR(IRQ_CHCK_DIS)
+
+#define GET_PAGE(bank) outpw(PAGE_RG_A,(inpw(PAGE_RG_A) &\
+ (~POS_PAGE)) |(int) (bank))
+#define VPP_ON() if (smc->hw.rev == FM1_REV) { \
+ outpw(PAGE_RG_A, \
+ (inpw(PAGE_RG_A) & POS_PAGE) | PROG_EN); \
+ }
+#define VPP_OFF() if (smc->hw.rev == FM1_REV) { \
+ outpw(PAGE_RG_A,(inpw(PAGE_RG_A) & POS_PAGE)); \
+ }
+
+#define SKFDDI_PSZ 16 /* address PROM size */
+
+#define READ_PROM(a) ((u_char)inp(a))
+
+#define GET_ISR() ~inpw(ISR1_A)
+#ifndef TCI
+#define CHECK_ISR() ~inpw(ISR1_A)
+#define CHECK_ISR_SMP(iop) ~inpw((iop)+ISRA)
+#else
+#define CHECK_ISR() (~inpw(ISR1_A) | ~inpw(ISR2_A))
+#define CHECK_ISR_SMP(iop) (~inpw((iop)+ISRA) | ~inpw((iop)+ISR2))
+#endif
+
+#define DMA_BUSY() (inpw(CSF_A) & CSF_BUSY_DMA)
+#define FIFO_BUSY() (inpw(CSF_A) & CSF_BUSY_FIFO)
+#define DMA_FIFO_BUSY() (inpw(CSF_A) & (CSF_BUSY_DMA | CSF_BUSY_FIFO))
+#define BUS_CHECK() { int i ; \
+ if ((i = GET_ISR()) & IS_BUSERR) \
+ SMT_PANIC(smc,HWM_E0020,HWM_E0020_MSG) ; \
+ if (i & IS_CHCK_L) \
+ SMT_PANIC(smc,HWM_E0014,HWM_E0014_MSG) ; \
+ }
+
+#define CHECK_DMA() { u_long k = 10000 ; \
+ while (k && (DMA_BUSY())) { \
+ k-- ; \
+ BUS_CHECK() ; \
+ } \
+ if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
+
+#define CHECK_FIFO() {u_long k = 1000000 ;\
+ while (k && (FIFO_BUSY())) k-- ;\
+ if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; }
+
+#define CHECK_DMA_FIFO() {u_long k = 1000000 ;\
+ while (k && (DMA_FIFO_BUSY())) { \
+ k-- ;\
+ BUS_CHECK() ; \
+ } \
+ if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; }
+
+#ifndef UNIX
+#define CLI_FBI() outp(ADDR(IRQ_OTH_DIS),0)
+#else
+#define CLI_FBI(smc) outp(ADDRS((smc),IRQ_OTH_DIS),0)
+#endif
+
+#ifndef TCI
+#define CLI_FBI_SMP(iop) outp((iop)+IRQ_OTH_DIS,0)
+#else
+#define CLI_FBI_SMP(iop) outp((iop)+IRQ_OTH_DIS,0) ;\
+ outp((iop)+IRQ_TC_DIS,0)
+#endif
+
+#ifndef UNIX
+#define STI_FBI() outp(ADDR(IRQ_OTH_EN),0)
+#else
+#define STI_FBI(smc) outp(ADDRS((smc),IRQ_OTH_EN),0)
+#endif
+
+/*
+ * Terminal count primitives
+ */
+#define CLI_TCI(smc) outp(ADDRS((smc),IRQ_TC_DIS),0)
+#define STI_TCI(smc) outp(ADDRS((smc),IRQ_TC_EN),0)
+#define CHECK_TC(smc,k) {(k) = 10000 ;\
+ while ((k) && (~inpw(ISR2_A) & IS_TC)) (k)-- ;\
+ if (!k) SMT_PANIC(smc,HWM_E0018,HWM_E0018_MSG) ; }
+
+#endif /* MCA */
+
+#ifdef ISA
+
+/*
+ * address transmission from logic NPADDR6-0 to physical offset address on board
+ */
+#define FMA(a) (0x8000|(((a)&0x07)<<1)|(((a)&0x78)<<7)) /* FORMAC+ (r/w) */
+#define PRA(a) (0x1000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PROM (read only)*/
+#define P1A(a) (0x4000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PLC1 (r/w) */
+#define P2A(a) (0x5000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PLC2 (r/w) */
+#define TIA(a) (0x6000|(((a)&0x03)<<1)) /* Timer (r/w) */
+
+#define ISRA 0x0000 /* int. source register address (read only) */
+#define ACLA 0x0000 /* address counter low address (write only) */
+#define ACHA 0x0002 /* address counter high address (write only) */
+#define TRCA 0x0004 /* transfer counter address (write only) */
+#define PGRA 0x0006 /* page register address (write only) */
+#define RQAA 0x2000 /* Request reg. (write only) */
+#define CSRA 0x3000 /* control/status register address (r/w) */
+
+/*
+ * physical address offset + IO-Port base address
+ */
+#define FM_A(a) (FMA(a)+smc->hw.iop) /* FORMAC Plus physical addr */
+#define PR_A(a) (PRA(a)+smc->hw.iop) /* PROM (read only)*/
+#define P1_A(a) (P1A(a)+smc->hw.iop) /* PLC1 (r/w) */
+#define P2_A(a) (P2A(a)+smc->hw.iop) /* PLC2 (r/w) */
+#define TI_A(a) (TIA(a)+smc->hw.iop) /* Timer (r/w) */
+
+#define ISR_A (0x0000+smc->hw.iop) /* int. source register address (read only) */
+#define ACL_A (0x0000+smc->hw.iop) /* address counter low address (write only) */
+#define ACH_A (0x0002+smc->hw.iop) /* address counter high address (write only)*/
+#define TRC_A (0x0004+smc->hw.iop) /* transfer counter address (write only) */
+#define PGR_A (0x0006+smc->hw.iop) /* page register address (write only) */
+#define RQA_A (0x2000+smc->hw.iop) /* Request reg. (write only) */
+#define CSR_A (0x3000+smc->hw.iop) /* control/status register address (r/w) */
+#ifdef UNIX
+#define CSR_AS(smc) (0x3000+(smc)->hw.iop) /* control/status register address */
+#endif
+#define PLC1_I (0x3400+smc->hw.iop) /* clear PLC1 interrupt bit */
+#define PLC2_I (0x3800+smc->hw.iop) /* clear PLC2 interrupt bit */
+
+#ifndef MULT_OEM
+#ifndef OEM_CONCEPT
+#define SKLOGO_STR "SKFDDI"
+#else /* OEM_CONCEPT */
+#define SKLOGO_STR OEM_FDDI_LOGO
+#endif /* OEM_CONCEPT */
+#endif /* MULT_OEM */
+#define SADDRL (24) /* start address SKLOGO */
+#define SA_MAC (0) /* start addr. MAC_AD within the PROM */
+#define PRA_OFF (0)
+#define SA_PMD_TYPE (8) /* start addr. PMD-Type */
+
+#define CDID (PRA(SADDRL)) /* Card ID int/O port addr. offset */
+#define NEXT_CDID ((PRA(SADDRL+1)) - CDID)
+
+#define SKFDDI_PSZ 32 /* address PROM size */
+
+#define READ_PROM(a) ((u_char)inpw(a))
+#define GET_PAGE(i) outpw(PGR_A,(int)(i))
+
+#define MAX_PAGES 16 /* 16 pages */
+#define MAX_FADDR 0x2000 /* 8K per page */
+#define VPP_OFF() outpw(CSR_A,(inpw(CSR_A) & (CS_CRESET|CS_BYPASS)))
+#define VPP_ON() outpw(CSR_A,(inpw(CSR_A) & (CS_CRESET|CS_BYPASS)) | \
+ CS_VPPSW)
+
+/*
+ * control/status register CSRA bits (log. addr: 0x3000)
+ */
+/* write */
+#define CS_CRESET 0x01 /* Card reset (0=reset) */
+#define CS_IMSK 0x02 /* enable IRQ (1=enable, 0=disable) */
+#define CS_RESINT1 0x04 /* PLINT1 reset */
+#define CS_VPPSW 0x10 /* 12V power switch (0=off, 1=on) */
+#define CS_BYPASS 0x20 /* bypass switch (0=remove, 1=insert)*/
+#define CS_RESINT2 0x40 /* PLINT2 reset */
+/* read */
+#define CS_BUSY 0x04 /* master transfer activ (=1) */
+#define CS_SW_EPROM 0x08 /* 0=Application Soft. 1=BOOT-EPROM */
+#define CS_BYSTAT 0x40 /* 0=Bypass exist, 1= ..not */
+#define CS_SAS 0x80 /* single attachement station (=1) */
+
+/*
+ * Interrupt source register ISRA (log. addr: 0x0000) read only & low activ.
+ */
+#define IS_MINTR1 0x01 /* FORMAC ST1U/L && ~IMSK1U/L*/
+#define IS_MINTR2 0x02 /* FORMAC ST2U/L && ~IMSK2U/L*/
+#define IS_PLINT1 0x04 /* PLC1 */
+#define IS_PLINT2 0x08 /* PLC2 */
+#define IS_TIMINT 0x10 /* Timer 82C54-2 */
+
+#define ALL_IRSR (IS_MINTR1|IS_MINTR2|IS_PLINT1|IS_PLINT2|IS_TIMINT)
+
+#define FPROM_SW() (inpw(CSR_A)&CS_SW_EPROM)
+#define DMA_BUSY() (inpw(CSR_A)&CS_BUSY)
+#define CHECK_FIFO()
+#define BUS_CHECK()
+
+/*
+ * set Host Request register (wr.)
+ */
+#define SET_HRQ(qup) outpw(RQA_A+((qup)<<1),0)
+
+#ifndef UNIX
+#ifndef WINNT
+#define CLI_FBI() outpw(CSR_A,(inpw(CSR_A)&(CS_CRESET|CS_BYPASS|CS_VPPSW)))
+#else
+#define CLI_FBI() outpw(CSR_A,(l_inpw(CSR_A) & \
+ (CS_CRESET|CS_BYPASS|CS_VPPSW)))
+#endif
+#else
+#define CLI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))& \
+ (CS_CRESET|CS_BYPASS|CS_VPPSW)))
+#endif
+
+#ifndef UNIX
+#define STI_FBI() outpw(CSR_A,(inpw(CSR_A) & \
+ (CS_CRESET|CS_BYPASS|CS_VPPSW)) | CS_IMSK)
+#else
+#define STI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc)) & \
+ (CS_CRESET|CS_BYPASS|CS_VPPSW)) | CS_IMSK)
+#endif
+
+#define CHECK_DMA() {unsigned k = 10000 ;\
+ while (k && (DMA_BUSY())) k-- ;\
+ if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
+
+#define GET_ISR() ~inpw(ISR_A)
+
+#endif /* ISA */
+
+/*--------------------------------------------------------------------------*/
+#ifdef PCI
+
+/*
+ * (DV) = only defined for Da Vinci
+ * (ML) = only defined for Monalisa
+ */
+
+/*
+ * Configuration Space header
+ */
+#define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */
+#define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */
+#define PCI_COMMAND 0x04 /* 16 bit Command */
+#define PCI_STATUS 0x06 /* 16 bit Status */
+#define PCI_REV_ID 0x08 /* 8 bit Revision ID */
+#define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */
+#define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */
+#define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */
+#define PCI_HEADER_T 0x0e /* 8 bit Header Type */
+#define PCI_BIST 0x0f /* 8 bit Built-in selftest */
+#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
+#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
+/* Byte 18..2b: Reserved */
+#define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
+#define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
+#define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
+/* Byte 34..33: Reserved */
+#define PCI_CAP_PTR 0x34 /* 8 bit (ML) Capabilities Ptr */
+/* Byte 35..3b: Reserved */
+#define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
+#define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
+#define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
+#define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
+/* Device Dependent Region */
+#define PCI_OUR_REG 0x40 /* 32 bit (DV) Our Register */
+#define PCI_OUR_REG_1 0x40 /* 32 bit (ML) Our Register 1 */
+#define PCI_OUR_REG_2 0x44 /* 32 bit (ML) Our Register 2 */
+/* Power Management Region */
+#define PCI_PM_CAP_ID 0x48 /* 8 bit (ML) Power Management Cap. ID */
+#define PCI_PM_NITEM 0x49 /* 8 bit (ML) Next Item Ptr */
+#define PCI_PM_CAP_REG 0x4a /* 16 bit (ML) Power Management Capabilities */
+#define PCI_PM_CTL_STS 0x4c /* 16 bit (ML) Power Manag. Control/Status */
+/* Byte 0x4e: Reserved */
+#define PCI_PM_DAT_REG 0x4f /* 8 bit (ML) Power Manag. Data Register */
+/* VPD Region */
+#define PCI_VPD_CAP_ID 0x50 /* 8 bit (ML) VPD Cap. ID */
+#define PCI_VPD_NITEM 0x51 /* 8 bit (ML) Next Item Ptr */
+#define PCI_VPD_ADR_REG 0x52 /* 16 bit (ML) VPD Address Register */
+#define PCI_VPD_DAT_REG 0x54 /* 32 bit (ML) VPD Data Register */
+/* Byte 58..ff: Reserved */
+
+/*
+ * I2C Address (PCI Config)
+ *
+ * Note: The temperature and voltage sensors are relocated on a different
+ * I2C bus.
+ */
+#define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */
+
+/*
+ * Define Bits and Values of the registers
+ */
+/* PCI_VENDOR_ID 16 bit Vendor ID */
+/* PCI_DEVICE_ID 16 bit Device ID */
+/* Values for Vendor ID and Device ID shall be patched into the code */
+/* PCI_COMMAND 16 bit Command */
+#define PCI_FBTEN 0x0200 /* Bit 9: Fast Back-To-Back enable */
+#define PCI_SERREN 0x0100 /* Bit 8: SERR enable */
+#define PCI_ADSTEP 0x0080 /* Bit 7: Address Stepping */
+#define PCI_PERREN 0x0040 /* Bit 6: Parity Report Response enable */
+#define PCI_VGA_SNOOP 0x0020 /* Bit 5: VGA palette snoop */
+#define PCI_MWIEN 0x0010 /* Bit 4: Memory write an inv cycl ena */
+#define PCI_SCYCEN 0x0008 /* Bit 3: Special Cycle enable */
+#define PCI_BMEN 0x0004 /* Bit 2: Bus Master enable */
+#define PCI_MEMEN 0x0002 /* Bit 1: Memory Space Access enable */
+#define PCI_IOEN 0x0001 /* Bit 0: IO Space Access enable */
+
+/* PCI_STATUS 16 bit Status */
+#define PCI_PERR 0x8000 /* Bit 15: Parity Error */
+#define PCI_SERR 0x4000 /* Bit 14: Signaled SERR */
+#define PCI_RMABORT 0x2000 /* Bit 13: Received Master Abort */
+#define PCI_RTABORT 0x1000 /* Bit 12: Received Target Abort */
+#define PCI_STABORT 0x0800 /* Bit 11: Sent Target Abort */
+#define PCI_DEVSEL 0x0600 /* Bit 10..9: DEVSEL Timing */
+#define PCI_DEV_FAST (0<<9) /* fast */
+#define PCI_DEV_MEDIUM (1<<9) /* medium */
+#define PCI_DEV_SLOW (2<<9) /* slow */
+#define PCI_DATAPERR 0x0100 /* Bit 8: DATA Parity error detected */
+#define PCI_FB2BCAP 0x0080 /* Bit 7: Fast Back-to-Back Capability */
+#define PCI_UDF 0x0040 /* Bit 6: User Defined Features */
+#define PCI_66MHZCAP 0x0020 /* Bit 5: 66 MHz PCI bus clock capable */
+#define PCI_NEWCAP 0x0010 /* Bit 4: New cap. list implemented */
+
+#define PCI_ERRBITS (PCI_PERR|PCI_SERR|PCI_RMABORT|PCI_STABORT|PCI_DATAPERR)
+
+/* PCI_REV_ID 8 bit Revision ID */
+/* PCI_CLASS_CODE 24 bit Class Code */
+/* Byte 2: Base Class (02) */
+/* Byte 1: SubClass (02) */
+/* Byte 0: Programming Interface (00) */
+
+/* PCI_CACHE_LSZ 8 bit Cache Line Size */
+/* Possible values: 0,2,4,8,16 */
+
+/* PCI_LAT_TIM 8 bit Latency Timer */
+
+/* PCI_HEADER_T 8 bit Header Type */
+#define PCI_HD_MF_DEV 0x80 /* Bit 7: 0= single, 1= multi-func dev */
+#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
+
+/* PCI_BIST 8 bit Built-in selftest */
+#define PCI_BIST_CAP 0x80 /* Bit 7: BIST Capable */
+#define PCI_BIST_ST 0x40 /* Bit 6: Start BIST */
+#define PCI_BIST_RET 0x0f /* Bit 3..0: Completion Code */
+
+/* PCI_BASE_1ST 32 bit 1st Base address */
+#define PCI_MEMSIZE 0x800L /* use 2 kB Memory Base */
+#define PCI_MEMBASE_BITS 0xfffff800L /* Bit 31..11: Memory Base Address */
+#define PCI_MEMSIZE_BIIS 0x000007f0L /* Bit 10..4: Memory Size Req. */
+#define PCI_PREFEN 0x00000008L /* Bit 3: Prefetchable */
+#define PCI_MEM_TYP 0x00000006L /* Bit 2..1: Memory Type */
+#define PCI_MEM32BIT (0<<1) /* Base addr anywhere in 32 Bit range */
+#define PCI_MEM1M (1<<1) /* Base addr below 1 MegaByte */
+#define PCI_MEM64BIT (2<<1) /* Base addr anywhere in 64 Bit range */
+#define PCI_MEMSPACE 0x00000001L /* Bit 0: Memory Space Indic. */
+
+/* PCI_BASE_2ND 32 bit 2nd Base address */
+#define PCI_IOBASE 0xffffff00L /* Bit 31..8: I/O Base address */
+#define PCI_IOSIZE 0x000000fcL /* Bit 7..2: I/O Size Requirements */
+#define PCI_IOSPACE 0x00000001L /* Bit 0: I/O Space Indicator */
+
+/* PCI_SUB_VID 16 bit Subsystem Vendor ID */
+/* PCI_SUB_ID 16 bit Subsystem ID */
+
+/* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
+#define PCI_ROMBASE 0xfffe0000L /* Bit 31..17: ROM BASE address (1st) */
+#define PCI_ROMBASZ 0x0001c000L /* Bit 16..14: Treat as BASE or SIZE */
+#define PCI_ROMSIZE 0x00003800L /* Bit 13..11: ROM Size Requirements */
+#define PCI_ROMEN 0x00000001L /* Bit 0: Address Decode enable */
+
+/* PCI_CAP_PTR 8 bit New Capabilities Pointers */
+/* PCI_IRQ_LINE 8 bit Interrupt Line */
+/* PCI_IRQ_PIN 8 bit Interrupt Pin */
+/* PCI_MIN_GNT 8 bit Min_Gnt */
+/* PCI_MAX_LAT 8 bit Max_Lat */
+/* Device Dependent Region */
+/* PCI_OUR_REG (DV) 32 bit Our Register */
+/* PCI_OUR_REG_1 (ML) 32 bit Our Register 1 */
+ /* Bit 31..29: reserved */
+#define PCI_PATCH_DIR (3L<<27) /*(DV) Bit 28..27: Ext Patchs direction */
+#define PCI_PATCH_DIR_0 (1L<<27) /*(DV) Type of the pins EXT_PATCHS<1..0> */
+#define PCI_PATCH_DIR_1 (1L<<28) /* 0 = input */
+ /* 1 = output */
+#define PCI_EXT_PATCHS (3L<<25) /*(DV) Bit 26..25: Extended Patches */
+#define PCI_EXT_PATCH_0 (1L<<25) /*(DV) */
+#define PCI_EXT_PATCH_1 (1L<<26) /* CLK for MicroWire (ML) */
+#define PCI_VIO (1L<<25) /*(ML) */
+#define PCI_EN_BOOT (1L<<24) /* Bit 24: Enable BOOT via ROM */
+ /* 1 = Don't boot with ROM */
+ /* 0 = Boot with ROM */
+#define PCI_EN_IO (1L<<23) /* Bit 23: Mapping to IO space */
+#define PCI_EN_FPROM (1L<<22) /* Bit 22: FLASH mapped to mem? */
+ /* 1 = Map Flash to Memory */
+ /* 0 = Disable all addr. decoding */
+#define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */
+#define PCI_PAGE_16 (0L<<20) /* 16 k pages */
+#define PCI_PAGE_32K (1L<<20) /* 32 k pages */
+#define PCI_PAGE_64K (2L<<20) /* 64 k pages */
+#define PCI_PAGE_128K (3L<<20) /* 128 k pages */
+ /* Bit 19: reserved (ML) and (DV) */
+#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
+ /* Bit 15: reserved */
+#define PCI_FORCE_BE (1L<<14) /* Bit 14: Assert all BEs on MR */
+#define PCI_DIS_MRL (1L<<13) /* Bit 13: Disable Mem R Line */
+#define PCI_DIS_MRM (1L<<12) /* Bit 12: Disable Mem R multip */
+#define PCI_DIS_MWI (1L<<11) /* Bit 11: Disable Mem W & inv */
+#define PCI_DISC_CLS (1L<<10) /* Bit 10: Disc: cacheLsz bound */
+#define PCI_BURST_DIS (1L<<9) /* Bit 9: Burst Disable */
+#define PCI_BYTE_SWAP (1L<<8) /*(DV) Bit 8: Byte Swap in DATA */
+#define PCI_SKEW_DAS (0xfL<<4) /* Bit 7..4: Skew Ctrl, DAS Ext */
+#define PCI_SKEW_BASE (0xfL<<0) /* Bit 3..0: Skew Ctrl, Base */
+
+/* PCI_OUR_REG_2 (ML) 32 bit Our Register 2 (Monalisa only) */
+#define PCI_VPD_WR_TH (0xffL<<24) /* Bit 24..31 VPD Write Threshold */
+#define PCI_DEV_SEL (0x7fL<<17) /* Bit 17..23 EEPROM Device Select */
+#define PCI_VPD_ROM_SZ (7L<<14) /* Bit 14..16 VPD ROM Size */
+ /* Bit 12..13 reserved */
+#define PCI_PATCH_DIR2 (0xfL<<8) /* Bit 8..11 Ext Patchs dir 2..5 */
+#define PCI_PATCH_DIR_2 (1L<<8) /* Bit 8 CS for MicroWire */
+#define PCI_PATCH_DIR_3 (1L<<9)
+#define PCI_PATCH_DIR_4 (1L<<10)
+#define PCI_PATCH_DIR_5 (1L<<11)
+#define PCI_EXT_PATCHS2 (0xfL<<4) /* Bit 4..7 Extended Patches */
+#define PCI_EXT_PATCH_2 (1L<<4) /* Bit 4 CS for MicroWire */
+#define PCI_EXT_PATCH_3 (1L<<5)
+#define PCI_EXT_PATCH_4 (1L<<6)
+#define PCI_EXT_PATCH_5 (1L<<7)
+#define PCI_EN_DUMMY_RD (1L<<3) /* Bit 3 Enable Dummy Read */
+#define PCI_REV_DESC (1L<<2) /* Bit 2 Reverse Desc. Bytes */
+#define PCI_USEADDR64 (1L<<1) /* Bit 1 Use 64 Bit Addresse */
+#define PCI_USEDATA64 (1L<<0) /* Bit 0 Use 64 Bit Data bus ext*/
+
+/* Power Management Region */
+/* PCI_PM_CAP_ID 8 bit (ML) Power Management Cap. ID */
+/* PCI_PM_NITEM 8 bit (ML) Next Item Ptr */
+/* PCI_PM_CAP_REG 16 bit (ML) Power Management Capabilities*/
+#define PCI_PME_SUP (0x1f<<11) /* Bit 11..15 PM Manag. Event Support*/
+#define PCI_PM_D2_SUB (1<<10) /* Bit 10 D2 Support Bit */
+#define PCI_PM_D1_SUB (1<<9) /* Bit 9 D1 Support Bit */
+ /* Bit 6..8 reserved */
+#define PCI_PM_DSI (1<<5) /* Bit 5 Device Specific Init.*/
+#define PCI_PM_APS (1<<4) /* Bit 4 Auxialiary Power Src */
+#define PCI_PME_CLOCK (1<<3) /* Bit 3 PM Event Clock */
+#define PCI_PM_VER (7<<0) /* Bit 0..2 PM PCI Spec. version */
+
+/* PCI_PM_CTL_STS 16 bit (ML) Power Manag. Control/Status */
+#define PCI_PME_STATUS (1<<15) /* Bit 15 PFA doesn't sup. PME#*/
+#define PCI_PM_DAT_SCL (3<<13) /* Bit 13..14 dat reg Scaling factor */
+#define PCI_PM_DAT_SEL (0xf<<9) /* Bit 9..12 PM data selector field */
+ /* Bit 7.. 2 reserved */
+#define PCI_PM_STATE (3<<0) /* Bit 0.. 1 Power Management State */
+#define PCI_PM_STATE_D0 (0<<0) /* D0: Operational (default) */
+#define PCI_PM_STATE_D1 (1<<0) /* D1: not supported */
+#define PCI_PM_STATE_D2 (2<<0) /* D2: not supported */
+#define PCI_PM_STATE_D3 (3<<0) /* D3: HOT, Power Down and Reset */
+
+/* PCI_PM_DAT_REG 8 bit (ML) Power Manag. Data Register */
+/* VPD Region */
+/* PCI_VPD_CAP_ID 8 bit (ML) VPD Cap. ID */
+/* PCI_VPD_NITEM 8 bit (ML) Next Item Ptr */
+/* PCI_VPD_ADR_REG 16 bit (ML) VPD Address Register */
+#define PCI_VPD_FLAG (1<<15) /* Bit 15 starts VPD rd/wd cycle*/
+
+/* PCI_VPD_DAT_REG 32 bit (ML) VPD Data Register */
+
+/*
+ * Control Register File:
+ * Bank 0
+ */
+#define B0_RAP 0x0000 /* 8 bit register address port */
+ /* 0x0001 - 0x0003: reserved */
+#define B0_CTRL 0x0004 /* 8 bit control register */
+#define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
+#define B0_LED 0x0006 /* 8 Bit LED register */
+#define B0_TST_CTRL 0x0007 /* 8 bit test control register */
+#define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
+#define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
+
+/* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
+#define B0_CMDREG1 0x0010 /* write command reg 1 instruction */
+#define B0_CMDREG2 0x0014 /* write command reg 2 instruction */
+#define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
+#define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
+#define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
+#define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */
+
+#define B0_MARR 0x0020 /* r/w the memory read addr register */
+#define B0_MARW 0x0024 /* r/w the memory write addr register*/
+#define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */
+#define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */
+
+#define B0_MDREG3 0x0030 /* r/w Mode Register 3 */
+#define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */
+#define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */
+#define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */
+#define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */
+#define B0_IVR 0x0044 /* read Interrupt Vector register */
+#define B0_IMR 0x0048 /* r/w Interrupt mask register */
+/* 0x4c Hidden */
+
+#define B0_CNTRL_A 0x0050 /* control register A (r/w) */
+#define B0_CNTRL_B 0x0054 /* control register B (r/w) */
+#define B0_INTR_MASK 0x0058 /* interrupt mask (r/w) */
+#define B0_XMIT_VECTOR 0x005c /* transmit vector register (r/w) */
+
+#define B0_STATUS_A 0x0060 /* status register A (read only) */
+#define B0_STATUS_B 0x0064 /* status register B (read only) */
+#define B0_CNTRL_C 0x0068 /* control register C (r/w) */
+#define B0_MDREG1 0x006c /* r/w Mode Register 1 */
+
+#define B0_R1_CSR 0x0070 /* 32 bit BMU control/status reg (rec q 1) */
+#define B0_R2_CSR 0x0074 /* 32 bit BMU control/status reg (rec q 2)(DV)*/
+#define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */
+#define B0_XS_CSR 0x007c /* 32 bit BMU control/status reg (s xmit q) */
+
+/*
+ * Bank 1
+ * - completely empty (this is the RAP Block window)
+ * Note: if RAP = 1 this page is reserved
+ */
+
+/*
+ * Bank 2
+ */
+#define B2_MAC_0 0x0100 /* 8 bit MAC address Byte 0 */
+#define B2_MAC_1 0x0101 /* 8 bit MAC address Byte 1 */
+#define B2_MAC_2 0x0102 /* 8 bit MAC address Byte 2 */
+#define B2_MAC_3 0x0103 /* 8 bit MAC address Byte 3 */
+#define B2_MAC_4 0x0104 /* 8 bit MAC address Byte 4 */
+#define B2_MAC_5 0x0105 /* 8 bit MAC address Byte 5 */
+#define B2_MAC_6 0x0106 /* 8 bit MAC address Byte 6 (== 0) (DV) */
+#define B2_MAC_7 0x0107 /* 8 bit MAC address Byte 7 (== 0) (DV) */
+
+#define B2_CONN_TYP 0x0108 /* 8 bit Connector type */
+#define B2_PMD_TYP 0x0109 /* 8 bit PMD type */
+ /* 0x010a - 0x010b: reserved */
+ /* Eprom registers are currently of no use */
+#define B2_E_0 0x010c /* 8 bit EPROM Byte 0 */
+#define B2_E_1 0x010d /* 8 bit EPROM Byte 1 */
+#define B2_E_2 0x010e /* 8 bit EPROM Byte 2 */
+#define B2_E_3 0x010f /* 8 bit EPROM Byte 3 */
+#define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */
+#define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */
+ /* 0x0115 - 0x0117: reserved */
+#define B2_LD_CRTL 0x0118 /* 8 bit loader control */
+#define B2_LD_TEST 0x0119 /* 8 bit loader test */
+ /* 0x011a - 0x011f: reserved */
+#define B2_TI_INI 0x0120 /* 32 bit Timer init value */
+#define B2_TI_VAL 0x0124 /* 32 bit Timer value */
+#define B2_TI_CRTL 0x0128 /* 8 bit Timer control */
+#define B2_TI_TEST 0x0129 /* 8 Bit Timer Test */
+ /* 0x012a - 0x012f: reserved */
+#define B2_WDOG_INI 0x0130 /* 32 bit Watchdog init value */
+#define B2_WDOG_VAL 0x0134 /* 32 bit Watchdog value */
+#define B2_WDOG_CRTL 0x0138 /* 8 bit Watchdog control */
+#define B2_WDOG_TEST 0x0139 /* 8 Bit Watchdog Test */
+ /* 0x013a - 0x013f: reserved */
+#define B2_RTM_INI 0x0140 /* 32 bit RTM init value */
+#define B2_RTM_VAL 0x0144 /* 32 bit RTM value */
+#define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */
+#define B2_RTM_TEST 0x0149 /* 8 Bit RTM Test */
+
+#define B2_TOK_COUNT 0x014c /* (ML) 32 bit Token Counter */
+#define B2_DESC_ADDR_H 0x0150 /* (ML) 32 bit Desciptor Base Addr Reg High */
+#define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */
+#define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */
+ /* 0x0156: reserved */
+#define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */
+#define B2_I2C_CTRL 0x0158 /* (ML) 32 bit I2C Control Register */
+#define B2_I2C_DATA 0x015c /* (ML) 32 bit I2C Data Register */
+
+#define B2_IRQ_MOD_INI 0x0160 /* (ML) 32 bit IRQ Moderation Timer Init Reg. */
+#define B2_IRQ_MOD_VAL 0x0164 /* (ML) 32 bit IRQ Moderation Timer Value */
+#define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */
+#define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */
+ /* 0x016a - 0x017f: reserved */
+
+/*
+ * Bank 3
+ */
+/*
+ * This is a copy of the Configuration register file (lower half)
+ */
+#define B3_CFG_SPC 0x180
+
+/*
+ * Bank 4
+ */
+#define B4_R1_D 0x0200 /* 4*32 bit current receive Descriptor */
+#define B4_R1_DA 0x0210 /* 32 bit current rec desc address */
+#define B4_R1_AC 0x0214 /* 32 bit current receive Address Count */
+#define B4_R1_BC 0x0218 /* 32 bit current receive Byte Counter */
+#define B4_R1_CSR 0x021c /* 32 bit BMU Control/Status Register */
+#define B4_R1_F 0x0220 /* 32 bit flag register */
+#define B4_R1_T1 0x0224 /* 32 bit Test Register 1 */
+#define B4_R1_T1_TR 0x0224 /* 8 bit Test Register 1 TR */
+#define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */
+#define B4_R1_T1_RD 0x0226 /* 8 bit Test Register 1 RD */
+#define B4_R1_T1_SV 0x0227 /* 8 bit Test Register 1 SV */
+#define B4_R1_T2 0x0228 /* 32 bit Test Register 2 */
+#define B4_R1_T3 0x022c /* 32 bit Test Register 3 */
+#define B4_R1_DA_H 0x0230 /* (ML) 32 bit Curr Rx Desc Address High */
+#define B4_R1_AC_H 0x0234 /* (ML) 32 bit Curr Addr Counter High dword */
+ /* 0x0238 - 0x023f: reserved */
+ /* Receive queue 2 is removed on Monalisa */
+#define B4_R2_D 0x0240 /* 4*32 bit current receive Descriptor (q2) */
+#define B4_R2_DA 0x0250 /* 32 bit current rec desc address (q2) */
+#define B4_R2_AC 0x0254 /* 32 bit current receive Address Count (q2) */
+#define B4_R2_BC 0x0258 /* 32 bit current receive Byte Counter (q2) */
+#define B4_R2_CSR 0x025c /* 32 bit BMU Control/Status Register (q2) */
+#define B4_R2_F 0x0260 /* 32 bit flag register (q2) */
+#define B4_R2_T1 0x0264 /* 32 bit Test Register 1 (q2) */
+#define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */
+#define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */
+#define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */
+#define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */
+#define B4_R2_T2 0x0268 /* 32 bit Test Register 2 (q2) */
+#define B4_R2_T3 0x026c /* 32 bit Test Register 3 (q2) */
+ /* 0x0270 - 0x027c: reserved */
+
+/*
+ * Bank 5
+ */
+#define B5_XA_D 0x0280 /* 4*32 bit current transmit Descriptor (xa) */
+#define B5_XA_DA 0x0290 /* 32 bit current tx desc address (xa) */
+#define B5_XA_AC 0x0294 /* 32 bit current tx Address Count (xa) */
+#define B5_XA_BC 0x0298 /* 32 bit current tx Byte Counter (xa) */
+#define B5_XA_CSR 0x029c /* 32 bit BMU Control/Status Register (xa) */
+#define B5_XA_F 0x02a0 /* 32 bit flag register (xa) */
+#define B5_XA_T1 0x02a4 /* 32 bit Test Register 1 (xa) */
+#define B5_XA_T1_TR 0x02a4 /* 8 bit Test Register 1 TR (xa) */
+#define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */
+#define B5_XA_T1_RD 0x02a6 /* 8 bit Test Register 1 RD (xa) */
+#define B5_XA_T1_SV 0x02a7 /* 8 bit Test Register 1 SV (xa) */
+#define B5_XA_T2 0x02a8 /* 32 bit Test Register 2 (xa) */
+#define B5_XA_T3 0x02ac /* 32 bit Test Register 3 (xa) */
+#define B5_XA_DA_H 0x02b0 /* (ML) 32 bit Curr Tx Desc Address High */
+#define B5_XA_AC_H 0x02b4 /* (ML) 32 bit Curr Addr Counter High dword */
+ /* 0x02b8 - 0x02bc: reserved */
+#define B5_XS_D 0x02c0 /* 4*32 bit current transmit Descriptor (xs) */
+#define B5_XS_DA 0x02d0 /* 32 bit current tx desc address (xs) */
+#define B5_XS_AC 0x02d4 /* 32 bit current transmit Address Count(xs) */
+#define B5_XS_BC 0x02d8 /* 32 bit current transmit Byte Counter (xs) */
+#define B5_XS_CSR 0x02dc /* 32 bit BMU Control/Status Register (xs) */
+#define B5_XS_F 0x02e0 /* 32 bit flag register (xs) */
+#define B5_XS_T1 0x02e4 /* 32 bit Test Register 1 (xs) */
+#define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */
+#define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */
+#define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */
+#define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */
+#define B5_XS_T2 0x02e8 /* 32 bit Test Register 2 (xs) */
+#define B5_XS_T3 0x02ec /* 32 bit Test Register 3 (xs) */
+#define B5_XS_DA_H 0x02f0 /* (ML) 32 bit Curr Tx Desc Address High */
+#define B5_XS_AC_H 0x02f4 /* (ML) 32 bit Curr Addr Counter High dword */
+ /* 0x02f8 - 0x02fc: reserved */
+
+/*
+ * Bank 6
+ */
+/* External PLC-S registers (SN2 compatibility for DV) */
+/* External registers (ML) */
+#define B6_EXT_REG 0x300
+
+/*
+ * Bank 7
+ */
+/* DAS PLC-S Registers */
+
+/*
+ * Bank 8 - 15
+ */
+/* IFCP registers */
+
+/*---------------------------------------------------------------------------*/
+/* Definitions of the Bits in the registers */
+
+/* B0_RAP 16 bit register address port */
+#define RAP_RAP 0x0f /* Bit 3..0: 0 = block0, .., f = block15 */
+
+/* B0_CTRL 8 bit control register */
+#define CTRL_FDDI_CLR (1<<7) /* Bit 7: (ML) Clear FDDI Reset */
+#define CTRL_FDDI_SET (1<<6) /* Bit 6: (ML) Set FDDI Reset */
+#define CTRL_HPI_CLR (1<<5) /* Bit 5: Clear HPI SM reset */
+#define CTRL_HPI_SET (1<<4) /* Bit 4: Set HPI SM reset */
+#define CTRL_MRST_CLR (1<<3) /* Bit 3: Clear Master reset */
+#define CTRL_MRST_SET (1<<2) /* Bit 2: Set Master reset */
+#define CTRL_RST_CLR (1<<1) /* Bit 1: Clear Software reset */
+#define CTRL_RST_SET (1<<0) /* Bit 0: Set Software reset */
+
+/* B0_DAS 8 Bit control register (DAS) */
+#define BUS_CLOCK (1<<7) /* Bit 7: (ML) Bus Clock 0/1 = 33/66MHz */
+#define BUS_SLOT_SZ (1<<6) /* Bit 6: (ML) Slot Size 0/1 = 32/64 bit slot*/
+ /* Bit 5..4: reserved */
+#define DAS_AVAIL (1<<3) /* Bit 3: 1 = DAS, 0 = SAS */
+#define DAS_BYP_ST (1<<2) /* Bit 2: 1 = avail,SAS, 0 = not avail */
+#define DAS_BYP_INS (1<<1) /* Bit 1: 1 = insert Bypass */
+#define DAS_BYP_RMV (1<<0) /* Bit 0: 1 = remove Bypass */
+
+/* B0_LED 8 Bit LED register */
+ /* Bit 7..6: reserved */
+#define LED_2_ON (1<<5) /* Bit 5: 1 = switch LED_2 on (left,gn)*/
+#define LED_2_OFF (1<<4) /* Bit 4: 1 = switch LED_2 off */
+#define LED_1_ON (1<<3) /* Bit 3: 1 = switch LED_1 on (mid,yel)*/
+#define LED_1_OFF (1<<2) /* Bit 2: 1 = switch LED_1 off */
+#define LED_0_ON (1<<1) /* Bit 1: 1 = switch LED_0 on (rght,gn)*/
+#define LED_0_OFF (1<<0) /* Bit 0: 1 = switch LED_0 off */
+/* This hardware defines are very ugly therefore we define some others */
+
+#define LED_GA_ON LED_2_ON /* S port = A port */
+#define LED_GA_OFF LED_2_OFF /* S port = A port */
+#define LED_MY_ON LED_1_ON
+#define LED_MY_OFF LED_1_OFF
+#define LED_GB_ON LED_0_ON
+#define LED_GB_OFF LED_0_OFF
+
+/* B0_TST_CTRL 8 bit test control register */
+#define TST_FRC_DPERR_MR (1<<7) /* Bit 7: force DATAPERR on MST RE. */
+#define TST_FRC_DPERR_MW (1<<6) /* Bit 6: force DATAPERR on MST WR. */
+#define TST_FRC_DPERR_TR (1<<5) /* Bit 5: force DATAPERR on TRG RE. */
+#define TST_FRC_DPERR_TW (1<<4) /* Bit 4: force DATAPERR on TRG WR. */
+#define TST_FRC_APERR_M (1<<3) /* Bit 3: force ADDRPERR on MST */
+#define TST_FRC_APERR_T (1<<2) /* Bit 2: force ADDRPERR on TRG */
+#define TST_CFG_WRITE_ON (1<<1) /* Bit 1: ena configuration reg. WR */
+#define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: dis configuration reg. WR */
+
+/* B0_ISRC 32 bit Interrupt source register */
+ /* Bit 31..28: reserved */
+#define IS_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */
+#define IS_IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */
+#define IS_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/
+#define IS_IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */
+ /* PERR, RMABORT, RTABORT DATAPERR */
+#define IS_IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */
+ /* RMABORT, RTABORT, DATAPERR */
+#define IS_TIMINT (1L<<22) /* Bit 22: IRQ_TIMER */
+#define IS_TOKEN (1L<<21) /* Bit 21: IRQ_RTM */
+/*
+ * Note: The DAS is our First Port (!=PA)
+ */
+#define IS_PLINT1 (1L<<20) /* Bit 20: IRQ_PHY_DAS */
+#define IS_PLINT2 (1L<<19) /* Bit 19: IRQ_IFCP_4 */
+#define IS_MINTR3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */
+#define IS_MINTR2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */
+#define IS_MINTR1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */
+/* Receive Queue 1 */
+#define IS_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */
+#define IS_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */
+#define IS_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */
+#define IS_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */
+/* Receive Queue 2 */
+#define IS_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */
+#define IS_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */
+#define IS_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */
+#define IS_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
+/* Asynchronous Transmit queue */
+ /* Bit 7: reserved */
+#define IS_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */
+#define IS_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */
+#define IS_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */
+/* Synchronous Transmit queue */
+ /* Bit 3: reserved */
+#define IS_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */
+#define IS_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */
+#define IS_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
+
+/*
+ * Define all valid interrupt source Bits from GET_ISR ()
+ */
+#define ALL_IRSR 0x01ffff77L /* (DV) */
+#define ALL_IRSR_ML 0x0ffff077L /* (ML) */
+
+
+/* B0_IMSK 32 bit Interrupt mask register */
+/*
+ * The Bit definnition of this register are the same as of the interrupt
+ * source register. These definition are directly derived from the Hardware
+ * spec.
+ */
+ /* Bit 31..28: reserved */
+#define IRQ_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */
+#define IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */
+#define IRQ_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/
+#define IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */
+ /* PERR, RMABORT, RTABORT DATAPERR */
+#define IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */
+ /* RMABORT, RTABORT, DATAPERR */
+#define IRQ_TIMER (1L<<22) /* Bit 22: IRQ_TIMER */
+#define IRQ_RTM (1L<<21) /* Bit 21: IRQ_RTM */
+#define IRQ_DAS (1L<<20) /* Bit 20: IRQ_PHY_DAS */
+#define IRQ_IFCP_4 (1L<<19) /* Bit 19: IRQ_IFCP_4 */
+#define IRQ_IFCP_3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */
+#define IRQ_IFCP_2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */
+#define IRQ_IFCP_1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */
+/* Receive Queue 1 */
+#define IRQ_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */
+#define IRQ_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */
+#define IRQ_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */
+#define IRQ_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */
+/* Receive Queue 2 */
+#define IRQ_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */
+#define IRQ_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */
+#define IRQ_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */
+#define IRQ_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
+/* Asynchronous Transmit queue */
+ /* Bit 7: reserved */
+#define IRQ_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */
+#define IRQ_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */
+#define IRQ_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */
+/* Synchronous Transmit queue */
+ /* Bit 3: reserved */
+#define IRQ_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */
+#define IRQ_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */
+#define IRQ_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
+
+/* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
+/* B0_R1_CSR 32 bit BMU control/status reg (rec q 1 ) */
+/* B0_R2_CSR 32 bit BMU control/status reg (rec q 2 ) */
+/* B0_XA_CSR 32 bit BMU control/status reg (a xmit q ) */
+/* B0_XS_CSR 32 bit BMU control/status reg (s xmit q ) */
+/* The registers are the same as B4_R1_CSR, B4_R2_CSR, B5_Xa_CSR, B5_XS_CSR */
+
+/* B2_MAC_0 8 bit MAC address Byte 0 */
+/* B2_MAC_1 8 bit MAC address Byte 1 */
+/* B2_MAC_2 8 bit MAC address Byte 2 */
+/* B2_MAC_3 8 bit MAC address Byte 3 */
+/* B2_MAC_4 8 bit MAC address Byte 4 */
+/* B2_MAC_5 8 bit MAC address Byte 5 */
+/* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */
+/* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */
+
+/* B2_CONN_TYP 8 bit Connector type */
+/* B2_PMD_TYP 8 bit PMD type */
+/* Values of connector and PMD type comply to SysKonnect internal std */
+
+/* The EPROM register are currently of no use */
+/* B2_E_0 8 bit EPROM Byte 0 */
+/* B2_E_1 8 bit EPROM Byte 1 */
+/* B2_E_2 8 bit EPROM Byte 2 */
+/* B2_E_3 8 bit EPROM Byte 3 */
+
+/* B2_FAR 32 bit Flash-Prom Address Register/Counter */
+#define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */
+
+/* B2_FDP 8 bit Flash-Prom Data Port */
+
+/* B2_LD_CRTL 8 bit loader control */
+/* Bits are currently reserved */
+
+/* B2_LD_TEST 8 bit loader test */
+#define LD_T_ON (1<<3) /* Bit 3: Loader Testmode on */
+#define LD_T_OFF (1<<2) /* Bit 2: Loader Testmode off */
+#define LD_T_STEP (1<<1) /* Bit 1: Decrement FPROM addr. Counter */
+#define LD_START (1<<0) /* Bit 0: Start loading FPROM */
+
+/* B2_TI_INI 32 bit Timer init value */
+/* B2_TI_VAL 32 bit Timer value */
+/* B2_TI_CRTL 8 bit Timer control */
+/* B2_TI_TEST 8 Bit Timer Test */
+/* B2_WDOG_INI 32 bit Watchdog init value */
+/* B2_WDOG_VAL 32 bit Watchdog value */
+/* B2_WDOG_CRTL 8 bit Watchdog control */
+/* B2_WDOG_TEST 8 Bit Watchdog Test */
+/* B2_RTM_INI 32 bit RTM init value */
+/* B2_RTM_VAL 32 bit RTM value */
+/* B2_RTM_CRTL 8 bit RTM control */
+/* B2_RTM_TEST 8 Bit RTM Test */
+/* B2_<TIM>_CRTL 8 bit <TIM> control */
+/* B2_IRQ_MOD_INI 32 bit IRQ Moderation Timer Init Reg. (ML) */
+/* B2_IRQ_MOD_VAL 32 bit IRQ Moderation Timer Value (ML) */
+/* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */
+/* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */
+#define GET_TOK_CT (1<<4) /* Bit 4: Get the Token Counter (RTM) */
+#define TIM_RES_TOK (1<<3) /* Bit 3: RTM Status: 1 == restricted */
+#define TIM_ALARM (1<<3) /* Bit 3: Timer Alarm (WDOG) */
+#define TIM_START (1<<2) /* Bit 2: Start Timer (TI,WDOG,RTM,IRQ_MOD)*/
+#define TIM_STOP (1<<1) /* Bit 1: Stop Timer (TI,WDOG,RTM,IRQ_MOD) */
+#define TIM_CL_IRQ (1<<0) /* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */
+/* B2_<TIM>_TEST 8 Bit <TIM> Test */
+#define TIM_T_ON (1<<2) /* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */
+#define TIM_T_OFF (1<<1) /* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */
+#define TIM_T_STEP (1<<0) /* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */
+
+/* B2_TOK_COUNT 0x014c (ML) 32 bit Token Counter */
+/* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */
+/* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */
+ /* Bit 7..5: reserved */
+#define CTRL_CL_I2C_IRQ (1<<4) /* Bit 4: Clear I2C IRQ */
+#define CTRL_ST_SW_IRQ (1<<3) /* Bit 3: Set IRQ SW Request */
+#define CTRL_CL_SW_IRQ (1<<2) /* Bit 2: Clear IRQ SW Request */
+#define CTRL_STOP_DONE (1<<1) /* Bit 1: Stop Master is finished */
+#define CTRL_STOP_MAST (1<<0) /* Bit 0: Command Bit to stop the master*/
+
+/* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */
+ /* Bit 7..3: reserved */
+#define IF_I2C_DATA_DIR (1<<2) /* Bit 2: direction of IF_I2C_DATA*/
+#define IF_I2C_DATA (1<<1) /* Bit 1: I2C Data Port */
+#define IF_I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */
+
+ /* 0x0156: reserved */
+/* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */
+ /* Bit 7..4: reserved */
+ /* force the following error on */
+ /* the next master read/write */
+#define TST_FRC_DPERR_MR64 (1<<3) /* Bit 3: DataPERR RD 64 */
+#define TST_FRC_DPERR_MW64 (1<<2) /* Bit 2: DataPERR WR 64 */
+#define TST_FRC_APERR_1M64 (1<<1) /* Bit 1: AddrPERR on 1. phase */
+#define TST_FRC_APERR_2M64 (1<<0) /* Bit 0: AddrPERR on 2. phase */
+
+/* B2_I2C_CTRL 0x0158 (ML) 32 bit I2C Control Register */
+#define I2C_FLAG (1L<<31) /* Bit 31: Start read/write if WR */
+#define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be read/written*/
+#define I2C_DEV_SEL (0x7fL<<9) /* Bit 9..15: I2C Device Select */
+ /* Bit 5.. 8: reserved */
+#define I2C_BURST_LEN (1L<<4) /* Bit 4 Burst Len, 1/4 bytes */
+#define I2C_DEV_SIZE (7L<<1) /* Bit 1.. 3: I2C Device Size */
+#define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smaller*/
+#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */
+#define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */
+#define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */
+#define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */
+#define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */
+#define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */
+#define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */
+#define I2C_STOP_BIT (1<<0) /* Bit 0: Interrupt I2C transfer */
+
+/*
+ * I2C Addresses
+ *
+ * The temperature sensor and the voltage sensor are on the same I2C bus.
+ * Note: The voltage sensor (Micorwire) will be selected by PCI_EXT_PATCH_1
+ * in PCI_OUR_REG 1.
+ */
+#define I2C_ADDR_TEMP 0x90 /* I2C Address Temperature Sensor */
+
+/* B2_I2C_DATA 0x015c (ML) 32 bit I2C Data Register */
+
+/* B4_R1_D 4*32 bit current receive Descriptor (q1) */
+/* B4_R1_DA 32 bit current rec desc address (q1) */
+/* B4_R1_AC 32 bit current receive Address Count (q1) */
+/* B4_R1_BC 32 bit current receive Byte Counter (q1) */
+/* B4_R1_CSR 32 bit BMU Control/Status Register (q1) */
+/* B4_R1_F 32 bit flag register (q1) */
+/* B4_R1_T1 32 bit Test Register 1 (q1) */
+/* B4_R1_T2 32 bit Test Register 2 (q1) */
+/* B4_R1_T3 32 bit Test Register 3 (q1) */
+/* B4_R2_D 4*32 bit current receive Descriptor (q2) */
+/* B4_R2_DA 32 bit current rec desc address (q2) */
+/* B4_R2_AC 32 bit current receive Address Count (q2) */
+/* B4_R2_BC 32 bit current receive Byte Counter (q2) */
+/* B4_R2_CSR 32 bit BMU Control/Status Register (q2) */
+/* B4_R2_F 32 bit flag register (q2) */
+/* B4_R2_T1 32 bit Test Register 1 (q2) */
+/* B4_R2_T2 32 bit Test Register 2 (q2) */
+/* B4_R2_T3 32 bit Test Register 3 (q2) */
+/* B5_XA_D 4*32 bit current receive Descriptor (xa) */
+/* B5_XA_DA 32 bit current rec desc address (xa) */
+/* B5_XA_AC 32 bit current receive Address Count (xa) */
+/* B5_XA_BC 32 bit current receive Byte Counter (xa) */
+/* B5_XA_CSR 32 bit BMU Control/Status Register (xa) */
+/* B5_XA_F 32 bit flag register (xa) */
+/* B5_XA_T1 32 bit Test Register 1 (xa) */
+/* B5_XA_T2 32 bit Test Register 2 (xa) */
+/* B5_XA_T3 32 bit Test Register 3 (xa) */
+/* B5_XS_D 4*32 bit current receive Descriptor (xs) */
+/* B5_XS_DA 32 bit current rec desc address (xs) */
+/* B5_XS_AC 32 bit current receive Address Count (xs) */
+/* B5_XS_BC 32 bit current receive Byte Counter (xs) */
+/* B5_XS_CSR 32 bit BMU Control/Status Register (xs) */
+/* B5_XS_F 32 bit flag register (xs) */
+/* B5_XS_T1 32 bit Test Register 1 (xs) */
+/* B5_XS_T2 32 bit Test Register 2 (xs) */
+/* B5_XS_T3 32 bit Test Register 3 (xs) */
+/* B5_<xx>_CSR 32 bit BMU Control/Status Register (xx) */
+#define CSR_DESC_CLEAR (1L<<21) /* Bit 21: Clear Reset for Descr */
+#define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */
+#define CSR_FIFO_CLEAR (1L<<19) /* Bit 19: Clear Reset for FIFO */
+#define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */
+#define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */
+#define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */
+#define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */
+#define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */
+#define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */
+#define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */
+#define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */
+#define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */
+#define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */
+#define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */
+ /* Bit 7..5: reserved */
+#define CSR_START (1L<<4) /* Bit 4: Start Rec/Xmit Queue */
+#define CSR_IRQ_CL_P (1L<<3) /* Bit 3: Clear Parity IRQ, Rcv */
+#define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */
+#define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */
+#define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */
+
+#define CSR_SET_RESET (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\
+ CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST)
+#define CSR_CLR_RESET (CSR_DESC_CLEAR|CSR_FIFO_CLEAR|CSR_HPI_RUN|CSR_SV_RUN|\
+ CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN)
+
+
+/* B5_<xx>_F 32 bit flag register (xx) */
+ /* Bit 28..31: reserved */
+#define F_ALM_FULL (1L<<27) /* Bit 27: (ML) FIFO almost full */
+#define F_FIFO_EOF (1L<<26) /* Bit 26: (ML) Fag bit in FIFO */
+#define F_WM_REACHED (1L<<25) /* Bit 25: (ML) Watermark reached */
+#define F_UP_DW_USED (1L<<24) /* Bit 24: (ML) Upper Dword used (bug)*/
+ /* Bit 23: reserved */
+#define F_FIFO_LEVEL (0x1fL<<16) /* Bit 16..22:(ML) # of Qwords in FIFO*/
+ /* Bit 8..15: reserved */
+#define F_ML_WATER_M 0x0000ffL /* Bit 0.. 7:(ML) Watermark */
+#define FLAG_WATER 0x00001fL /* Bit 4..0:(DV) Level of req data tr.*/
+
+/* B5_<xx>_T1 32 bit Test Register 1 (xx) */
+/* Holds four State Machine control Bytes */
+#define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */
+#define SM_CRTL_RD (0xffL<<16) /* Bit 23..16: Control Read Desc SM */
+#define SM_CRTL_WR (0xffL<<8) /* Bit 15..8: Control Write Desc SM */
+#define SM_CRTL_TR (0xffL<<0) /* Bit 7..0: Control Transfer SM */
+
+/* B4_<xx>_T1_TR 8 bit Test Register 1 TR (xx) */
+/* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */
+/* B4_<xx>_T1_RD 8 bit Test Register 1 RD (xx) */
+/* B4_<xx>_T1_SV 8 bit Test Register 1 SV (xx) */
+/* The control status byte of each machine looks like ... */
+#define SM_STATE 0xf0 /* Bit 7..4: State which shall be loaded */
+#define SM_LOAD 0x08 /* Bit 3: Load the SM with SM_STATE */
+#define SM_TEST_ON 0x04 /* Bit 2: Switch on SM Test Mode */
+#define SM_TEST_OFF 0x02 /* Bit 1: Go off the Test Mode */
+#define SM_STEP 0x01 /* Bit 0: Step the State Machine */
+
+/* The coding of the states */
+#define SM_SV_IDLE 0x0 /* Supervisor Idle Tr/Re */
+#define SM_SV_RES_START 0x1 /* Supervisor Res_Start Tr/Re */
+#define SM_SV_GET_DESC 0x3 /* Supervisor Get_Desc Tr/Re */
+#define SM_SV_CHECK 0x2 /* Supervisor Check Tr/Re */
+#define SM_SV_MOV_DATA 0x6 /* Supervisor Move_Data Tr/Re */
+#define SM_SV_PUT_DESC 0x7 /* Supervisor Put_Desc Tr/Re */
+#define SM_SV_SET_IRQ 0x5 /* Supervisor Set_Irq Tr/Re */
+
+#define SM_RD_IDLE 0x0 /* Read Desc. Idle Tr/Re */
+#define SM_RD_LOAD 0x1 /* Read Desc. Load Tr/Re */
+#define SM_RD_WAIT_TC 0x3 /* Read Desc. Wait_TC Tr/Re */
+#define SM_RD_RST_EOF 0x6 /* Read Desc. Reset_EOF Re */
+#define SM_RD_WDONE_R 0x2 /* Read Desc. Wait_Done Re */
+#define SM_RD_WDONE_T 0x4 /* Read Desc. Wait_Done Tr */
+
+#define SM_TR_IDLE 0x0 /* Trans. Data Idle Tr/Re */
+#define SM_TR_LOAD 0x3 /* Trans. Data Load Tr/Re */
+#define SM_TR_LOAD_R_ML 0x1 /* Trans. Data Load /Re (ML) */
+#define SM_TR_WAIT_TC 0x2 /* Trans. Data Wait_TC Tr/Re */
+#define SM_TR_WDONE 0x4 /* Trans. Data Wait_Done Tr/Re */
+
+#define SM_WR_IDLE 0x0 /* Write Desc. Idle Tr/Re */
+#define SM_WR_ABLEN 0x1 /* Write Desc. Act_Buf_Length Tr/Re */
+#define SM_WR_LD_A4 0x2 /* Write Desc. Load_A4 Re */
+#define SM_WR_RES_OWN 0x2 /* Write Desc. Res_OWN Tr */
+#define SM_WR_WAIT_EOF 0x3 /* Write Desc. Wait_EOF Re */
+#define SM_WR_LD_N2C_R 0x4 /* Write Desc. Load_N2C Re */
+#define SM_WR_WAIT_TC_R 0x5 /* Write Desc. Wait_TC Re */
+#define SM_WR_WAIT_TC4 0x6 /* Write Desc. Wait_TC4 Re */
+#define SM_WR_LD_A_T 0x6 /* Write Desc. Load_A Tr */
+#define SM_WR_LD_A_R 0x7 /* Write Desc. Load_A Re */
+#define SM_WR_WAIT_TC_T 0x7 /* Write Desc. Wait_TC Tr */
+#define SM_WR_LD_N2C_T 0xc /* Write Desc. Load_N2C Tr */
+#define SM_WR_WDONE_T 0x9 /* Write Desc. Wait_Done Tr */
+#define SM_WR_WDONE_R 0xc /* Write Desc. Wait_Done Re */
+#define SM_WR_LD_D_AD 0xe /* Write Desc. Load_Dumr_A Re (ML) */
+#define SM_WR_WAIT_D_TC 0xf /* Write Desc. Wait_Dumr_TC Re (ML) */
+
+/* B5_<xx>_T2 32 bit Test Register 2 (xx) */
+/* Note: This register is only defined for the transmit queues */
+ /* Bit 31..8: reserved */
+#define AC_TEST_ON (1<<7) /* Bit 7: Address Counter Test Mode on */
+#define AC_TEST_OFF (1<<6) /* Bit 6: Address Counter Test Mode off*/
+#define BC_TEST_ON (1<<5) /* Bit 5: Byte Counter Test Mode on */
+#define BC_TEST_OFF (1<<4) /* Bit 4: Byte Counter Test Mode off */
+#define TEST_STEP04 (1<<3) /* Bit 3: Inc AC/Dec BC by 4 */
+#define TEST_STEP03 (1<<2) /* Bit 2: Inc AC/Dec BC by 3 */
+#define TEST_STEP02 (1<<1) /* Bit 1: Inc AC/Dec BC by 2 */
+#define TEST_STEP01 (1<<0) /* Bit 0: Inc AC/Dec BC by 1 */
+
+/* B5_<xx>_T3 32 bit Test Register 3 (xx) */
+/* Note: This register is only defined for the transmit queues */
+ /* Bit 31..8: reserved */
+#define T3_MUX_2 (1<<7) /* Bit 7: (ML) Mux position MSB */
+#define T3_VRAM_2 (1<<6) /* Bit 6: (ML) Virtual RAM buffer addr MSB */
+#define T3_LOOP (1<<5) /* Bit 5: Set Loopback (Xmit) */
+#define T3_UNLOOP (1<<4) /* Bit 4: Unset Loopback (Xmit) */
+#define T3_MUX (3<<2) /* Bit 3..2: Mux position */
+#define T3_VRAM (3<<0) /* Bit 1..0: Virtual RAM buffer Address */
+
+/* PCI card IDs */
+/*
+ * Note: The following 4 byte definitions shall not be used! Use OEM Concept!
+ */
+#define PCI_VEND_ID0 0x48 /* PCI vendor ID (SysKonnect) */
+#define PCI_VEND_ID1 0x11 /* PCI vendor ID (SysKonnect) */
+ /* (High byte) */
+#define PCI_DEV_ID0 0x00 /* PCI device ID */
+#define PCI_DEV_ID1 0x40 /* PCI device ID (High byte) */
+
+/*#define PCI_CLASS 0x02*/ /* PCI class code: network device */
+#define PCI_NW_CLASS 0x02 /* PCI class code: network device */
+#define PCI_SUB_CLASS 0x02 /* PCI subclass ID: FDDI device */
+#define PCI_PROG_INTFC 0x00 /* PCI programming Interface (=0) */
+
+/*
+ * address transmission from logical to physical offset address on board
+ */
+#define FMA(a) (0x0400|((a)<<2)) /* FORMAC+ (r/w) (SN3) */
+#define P1(a) (0x0380|((a)<<2)) /* PLC1 (r/w) (DAS) */
+#define P2(a) (0x0600|((a)<<2)) /* PLC2 (r/w) (covered by the SN3) */
+#define PRA(a) (B2_MAC_0 + (a)) /* configuration PROM (MAC address) */
+
+/*
+ * FlashProm specification
+ */
+#define MAX_PAGES 0x20000L /* Every byte has a single page */
+#define MAX_FADDR 1 /* 1 byte per page */
+
+/*
+ * Receive / Transmit Buffer Control word
+ */
+#define BMU_OWN (1UL<<31) /* OWN bit: 0 == host, 1 == adapter */
+#define BMU_STF (1L<<30) /* Start of Frame ? */
+#define BMU_EOF (1L<<29) /* End of Frame ? */
+#define BMU_EN_IRQ_EOB (1L<<28) /* Enable "End of Buffer" IRQ */
+#define BMU_EN_IRQ_EOF (1L<<27) /* Enable "End of Frame" IRQ */
+#define BMU_DEV_0 (1L<<26) /* RX: don't transfer to system mem */
+#define BMU_SMT_TX (1L<<25) /* TX: if set, buffer type SMT_MBuf */
+#define BMU_ST_BUF (1L<<25) /* RX: copy of start of frame */
+#define BMU_UNUSED (1L<<24) /* Set if the Descr is curr unused */
+#define BMU_SW (3L<<24) /* 2 Bits reserved for SW usage */
+#define BMU_CHECK 0x00550000L /* To identify the control word */
+#define BMU_BBC 0x0000FFFFL /* R/T Buffer Byte Count */
+
+/*
+ * physical address offset + IO-Port base address
+ */
+#ifdef MEM_MAPPED_IO
+#define ADDR(a) (char far *) smc->hw.iop+(a)
+#define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a)
+#else
+#define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \
+ (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
+ (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
+#define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \
+ ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
+ ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
+#endif
+
+/*
+ * Define a macro to access the configuration space
+ */
+#define PCI_C(a) ADDR(B3_CFG_SPC + (a)) /* PCI Config Space */
+
+#define EXT_R(a) ADDR(B6_EXT_REG + (a)) /* External Registers */
+
+/*
+ * Define some values needed for the MAC address (PROM)
+ */
+#define SA_MAC (0) /* start addr. MAC_AD within the PROM */
+#define PRA_OFF (0) /* offset correction when 4th byte reading */
+
+#define SKFDDI_PSZ 8 /* address PROM size */
+
+#define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */
+#define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */
+#define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */
+#define PR_A(a) ADDR(PRA(a)) /* config. PROM (MAC address) */
+
+/*
+ * Macro to read the PROM
+ */
+#define READ_PROM(a) ((u_char)inp(a))
+
+#define GET_PAGE(bank) outpd(ADDR(B2_FAR),bank)
+#define VPP_ON()
+#define VPP_OFF()
+
+/*
+ * Note: Values of the Interrupt Source Register are defined above
+ */
+#define ISR_A ADDR(B0_ISRC)
+#define GET_ISR() inpd(ISR_A)
+#define GET_ISR_SMP(iop) inpd((iop)+B0_ISRC)
+#define CHECK_ISR() (inpd(ISR_A) & inpd(ADDR(B0_IMSK)))
+#define CHECK_ISR_SMP(iop) (inpd((iop)+B0_ISRC) & inpd((iop)+B0_IMSK))
+
+#define BUS_CHECK()
+
+/*
+ * CLI_FBI: Disable Board Interrupts
+ * STI_FBI: Enable Board Interrupts
+ */
+#ifndef UNIX
+#define CLI_FBI() outpd(ADDR(B0_IMSK),0)
+#else
+#define CLI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),0)
+#endif
+
+#ifndef UNIX
+#define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask)
+#else
+#define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
+#endif
+
+#define CLI_FBI_SMP(iop) outpd((iop)+B0_IMSK,0)
+#define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask)
+
+#endif /* PCI */
+/*--------------------------------------------------------------------------*/
+
+/*
+ * 12 bit transfer (dword) counter:
+ * (ISA: 2*trc = number of byte)
+ * (EISA: 4*trc = number of byte)
+ * (MCA: 4*trc = number of byte)
+ */
+#define MAX_TRANS (0x0fff)
+
+/*
+ * PC PIC
+ */
+#define MST_8259 (0x20)
+#define SLV_8259 (0xA0)
+
+#define TPS (18) /* ticks per second */
+
+/*
+ * error timer defs
+ */
+#define TN (4) /* number of supported timer = TN+1 */
+#define SNPPND_TIME (5) /* buffer memory access over mem. data reg. */
+
+#define MAC_AD 0x405a0000
+
+#define MODR1 FM_A(FM_MDREG1) /* mode register 1 */
+#define MODR2 FM_A(FM_MDREG2) /* mode register 2 */
+
+#define CMDR1 FM_A(FM_CMDREG1) /* command register 1 */
+#define CMDR2 FM_A(FM_CMDREG2) /* command register 2 */
+
+
+/*
+ * function defines
+ */
+#define CLEAR(io,mask) outpw((io),inpw(io)&(~(mask)))
+#define SET(io,mask) outpw((io),inpw(io)|(mask))
+#define GET(io,mask) (inpw(io)&(mask))
+#define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val))
+
+/*
+ * PHY Port A (PA) = PLC 1
+ * With SuperNet 3 PHY-A and PHY S are identical.
+ */
+#define PLC(np,reg) (((np) == PA) ? P2_A(reg) : P1_A(reg))
+
+/*
+ * set memory address register for write and read
+ */
+#define MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma))
+#define MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma))
+
+/*
+ * read/write from/to memory data register
+ */
+/* write double word */
+#define MDRW(dd) outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\
+ outpw(FM_A(FM_MDRL),(unsigned int)(dd))
+
+#ifndef WINNT
+/* read double word */
+#define MDRR() (((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL)))
+
+/* read FORMAC+ 32-bit status register */
+#define GET_ST1() (((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L)))
+#define GET_ST2() (((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L)))
+#ifdef SUPERNET_3
+#define GET_ST3() (((long)inpw(FM_A(FM_ST3U))<<16) + inpw(FM_A(FM_ST3L)))
+#endif
+#else
+/* read double word */
+#define MDRR() inp2w((FM_A(FM_MDRU)),(FM_A(FM_MDRL)))
+
+/* read FORMAC+ 32-bit status register */
+#define GET_ST1() inp2w((FM_A(FM_ST1U)),(FM_A(FM_ST1L)))
+#define GET_ST2() inp2w((FM_A(FM_ST2U)),(FM_A(FM_ST2L)))
+#ifdef SUPERNET_3
+#define GET_ST3() inp2w((FM_A(FM_ST3U)),(FM_A(FM_ST3L)))
+#endif
+#endif
+
+/* Special timer macro for 82c54 */
+ /* timer access over data bus bit 8..15 */
+#define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8)
+#define IN_82c54_TIMER(port) ((inpw(TI_A(port))>>8) & 0xff)
+
+
+#ifdef DEBUG
+#define DB_MAC(mac,st) {if (debug_mac & 0x1)\
+ printf("M") ;\
+ if (debug_mac & 0x2)\
+ printf("\tMAC %d status 0x%08lx\n",mac,st) ;\
+ if (debug_mac & 0x4)\
+ dp_mac(mac,st) ;\
+}
+
+#define DB_PLC(p,iev) { if (debug_plc & 0x1)\
+ printf("P") ;\
+ if (debug_plc & 0x2)\
+ printf("\tPLC %s Int 0x%04x\n", \
+ (p == PA) ? "A" : "B", iev) ;\
+ if (debug_plc & 0x4)\
+ dp_plc(p,iev) ;\
+}
+
+#define DB_TIMER() { if (debug_timer & 0x1)\
+ printf("T") ;\
+ if (debug_timer & 0x2)\
+ printf("\tTimer ISR\n") ;\
+}
+
+#else /* no DEBUG */
+
+#define DB_MAC(mac,st)
+#define DB_PLC(p,iev)
+#define DB_TIMER()
+
+#endif /* no DEBUG */
+
+#define INC_PTR(sp,cp,ep) if (++cp == ep) cp = sp
+/*
+ * timer defs
+ */
+#define COUNT(t) ((t)<<6) /* counter */
+#define RW_OP(o) ((o)<<4) /* read/write operation */
+#define TMODE(m) ((m)<<1) /* timer mode */
+
+#endif
diff --git a/drivers/net/skfp/h/skfbiinc.h b/drivers/net/skfp/h/skfbiinc.h
new file mode 100644
index 0000000..79d55ad
--- /dev/null
+++ b/drivers/net/skfp/h/skfbiinc.h
@@ -0,0 +1,123 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+#ifndef _SKFBIINC_
+#define _SKFBIINC_
+
+#include "h/supern_2.h"
+
+/*
+ * special defines for use into .asm files
+ */
+#define ERR_FLAGS (FS_MSRABT | FS_SEAC2 | FS_SFRMERR | FS_SFRMTY1)
+
+#ifdef ISA
+#define DMA_BUSY_CHECK CSRA
+#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT)
+#define HRQR (RQAA+(RQ_RRQ<<1))
+#define HRQW (RQAA+(RQ_WA2<<1))
+#define HRQA0 (RQAA+(RQ_WA0<<1))
+#define HRQSQ (RQAA+(RQ_WSQ<<1))
+#endif
+
+#ifdef EISA
+#define DMA_BUSY_CHECK CSRA
+#define DMA_HIGH_WORD 0x0400
+#define DMA_MASK_M 0x0a
+#define DMA_MODE_M 0x0b
+#define DMA_BYTE_PTR_M 0x0c
+#define DMA_MASK_S 0x0d4
+#define DMA_MODE_S 0x0d6
+#define DMA_BYTE_PTR_S 0x0d8
+#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TC)
+#endif /* EISA */
+
+#ifdef MCA
+#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
+ IS_CHCK_L | IS_BUSERR)
+#endif
+
+#ifdef PCI
+#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
+ IS_MINTR2 | IS_MINTR3 | IS_R1_P | \
+ IS_R1_C | IS_XA_C | IS_XS_C)
+#endif
+
+#ifdef PCI
+#define ISR_MASK (IS_MINTR1 | IS_R1_F | IS_XS_F| IS_XA_F | IMASK_FAST)
+#else
+#define ISR_MASK (IS_MINTR1 | IS_MINTR2 | IMASK_FAST)
+#endif
+
+#define FMA_FM_CMDREG1 FMA(FM_CMDREG1)
+#define FMA_FM_CMDREG2 FMA(FM_CMDREG2)
+#define FMA_FM_STMCHN FMA(FM_STMCHN)
+#define FMA_FM_RPR FMA(FM_RPR)
+#define FMA_FM_WPXA0 FMA(FM_WPXA0)
+#define FMA_FM_WPXA2 FMA(FM_WPXA2)
+#define FMA_FM_MARR FMA(FM_MARR)
+#define FMA_FM_MARW FMA(FM_MARW)
+#define FMA_FM_MDRU FMA(FM_MDRU)
+#define FMA_FM_MDRL FMA(FM_MDRL)
+#define FMA_ST1L FMA(FM_ST1L)
+#define FMA_ST1U FMA(FM_ST1U)
+#define FMA_ST2L FMA(FM_ST2L)
+#define FMA_ST2U FMA(FM_ST2U)
+#ifdef SUPERNET_3
+#define FMA_ST3L FMA(FM_ST3L)
+#define FMA_ST3U FMA(FM_ST3U)
+#endif
+
+#define TMODE_RRQ RQ_RRQ
+#define TMODE_WAQ2 RQ_WA2
+#define HSRA HSR(0)
+
+
+#define FMA_FM_ST1L FMA_ST1L
+#define FMA_FM_ST1U FMA_ST1U
+#define FMA_FM_ST2L FMA_ST2L
+#define FMA_FM_ST2U FMA_ST2U
+#ifdef SUPERNET_3
+#define FMA_FM_ST3L FMA_ST3L
+#define FMA_FM_ST3U FMA_ST3U
+#endif
+
+#define FMA_FM_SWPR FMA(FM_SWPR)
+
+#define FMA_FM_RPXA0 FMA(FM_RPXA0)
+
+#define FMA_FM_RPXS FMA(FM_RPXS)
+#define FMA_FM_WPXS FMA(FM_WPXS)
+
+#define FMA_FM_IMSK1U FMA(FM_IMSK1U)
+#define FMA_FM_IMSK1L FMA(FM_IMSK1L)
+
+#define FMA_FM_EAS FMA(FM_EAS)
+#define FMA_FM_EAA0 FMA(FM_EAA0)
+
+#define TMODE_WAQ0 RQ_WA0
+#define TMODE_WSQ RQ_WSQ
+
+/* Define default for DRV_PCM_STATE_CHANGE */
+#ifndef DRV_PCM_STATE_CHANGE
+#define DRV_PCM_STATE_CHANGE(smc,plc,p_state) /* nothing */
+#endif
+
+/* Define default for DRV_RMT_INDICATION */
+#ifndef DRV_RMT_INDICATION
+#define DRV_RMT_INDICATION(smc,i) /* nothing */
+#endif
+
+#endif /* n_SKFBIINC_ */
+
diff --git a/drivers/net/skfp/h/smc.h b/drivers/net/skfp/h/smc.h
new file mode 100644
index 0000000..9432591
--- /dev/null
+++ b/drivers/net/skfp/h/smc.h
@@ -0,0 +1,471 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+#ifndef _SCMECM_
+#define _SCMECM_
+
+#if defined(PCI) && !defined(OSDEF)
+/*
+ * In the case of the PCI bus the file osdef1st.h must be present
+ */
+#define OSDEF
+#endif
+
+#ifdef PCI
+#ifndef SUPERNET_3
+#define SUPERNET_3
+#endif
+#ifndef TAG_MODE
+#define TAG_MODE
+#endif
+#endif
+
+/*
+ * include all other files in required order
+ * the following files must have been included before:
+ * types.h
+ * fddi.h
+ */
+#ifdef OSDEF
+#include "h/osdef1st.h"
+#endif /* OSDEF */
+#ifdef OEM_CONCEPT
+#include "oemdef.h"
+#endif /* OEM_CONCEPT */
+#include "h/smt.h"
+#include "h/cmtdef.h"
+#include "h/fddimib.h"
+#include "h/targethw.h" /* all target hw dependencies */
+#include "h/targetos.h" /* all target os dependencies */
+#ifdef ESS
+#include "h/sba.h"
+#endif
+
+/*
+ * Event Queue
+ * queue.c
+ * events are class/value pairs
+ * class is addressee, e.g. RMT, PCM etc.
+ * value is command, e.g. line state change, ring op change etc.
+ */
+struct event_queue {
+ u_short class ; /* event class */
+ u_short event ; /* event value */
+} ;
+
+/*
+ * define event queue as circular buffer
+ */
+#ifdef CONCENTRATOR
+#define MAX_EVENT 128
+#else /* nCONCENTRATOR */
+#define MAX_EVENT 64
+#endif /* nCONCENTRATOR */
+
+struct s_queue {
+
+ struct event_queue ev_queue[MAX_EVENT];
+ struct event_queue *ev_put ;
+ struct event_queue *ev_get ;
+} ;
+
+/*
+ * ECM - Entity Coordination Management
+ * ecm.c
+ */
+struct s_ecm {
+ u_char path_test ; /* ECM path test variable */
+ u_char sb_flag ; /* ECM stuck bypass */
+ u_char DisconnectFlag ; /* jd 05-Aug-1999 Bug #10419
+ * ECM disconnected */
+ u_char ecm_line_state ; /* flag to dispatcher : line states */
+ u_long trace_prop ; /* ECM Trace_Prop flag >= 16 bits !! */
+ /* NUMPHYS note:
+ * this variable must have enough bits to hold all entiies in
+ * the station. So NUMPHYS may not be greater than 31.
+ */
+ char ec_pad[2] ;
+ struct smt_timer ecm_timer ; /* timer */
+} ;
+
+
+/*
+ * RMT - Ring Management
+ * rmt.c
+ */
+struct s_rmt {
+ u_char dup_addr_test ; /* state of dupl. addr. test */
+ u_char da_flag ; /* flag : duplicate address det. */
+ u_char loop_avail ; /* flag : MAC available for loopback */
+ u_char sm_ma_avail ; /* flag : MAC available for SMT */
+ u_char no_flag ; /* flag : ring not operational */
+ u_char bn_flag ; /* flag : MAC reached beacon state */
+ u_char jm_flag ; /* flag : jamming in NON_OP_DUP */
+ u_char rm_join ; /* CFM flag RM_Join */
+ u_char rm_loop ; /* CFM flag RM_Loop */
+
+ long fast_rm_join ; /* bit mask of active ports */
+ /*
+ * timer and flags
+ */
+ struct smt_timer rmt_timer0 ; /* timer 0 */
+ struct smt_timer rmt_timer1 ; /* timer 1 */
+ struct smt_timer rmt_timer2 ; /* timer 2 */
+ u_char timer0_exp ; /* flag : timer 0 expired */
+ u_char timer1_exp ; /* flag : timer 1 expired */
+ u_char timer2_exp ; /* flag : timer 2 expired */
+
+ u_char rm_pad1[1] ;
+} ;
+
+/*
+ * CFM - Configuration Management
+ * cfm.c
+ * used for SAS and DAS
+ */
+struct s_cfm {
+ u_char cf_state; /* CFM state machine current state */
+ u_char cf_pad[3] ;
+} ;
+
+/*
+ * CEM - Configuration Element Management
+ * cem.c
+ * used for Concentrator
+ */
+#ifdef CONCENTRATOR
+struct s_cem {
+ int ce_state ; /* CEM state */
+ int ce_port ; /* PA PB PM PM+1 .. */
+ int ce_type ; /* TA TB TS TM */
+} ;
+
+/*
+ * linked list of CCEs in current token path
+ */
+struct s_c_ring {
+ struct s_c_ring *c_next ;
+ char c_entity ;
+} ;
+
+struct mib_path_config {
+ u_long fddimibPATHConfigSMTIndex;
+ u_long fddimibPATHConfigPATHIndex;
+ u_long fddimibPATHConfigTokenOrder;
+ u_long fddimibPATHConfigResourceType;
+#define SNMP_RES_TYPE_MAC 2 /* Resource is a MAC */
+#define SNMP_RES_TYPE_PORT 4 /* Resource is a PORT */
+ u_long fddimibPATHConfigResourceIndex;
+ u_long fddimibPATHConfigCurrentPath;
+#define SNMP_PATH_ISOLATED 1 /* Current path is isolated */
+#define SNMP_PATH_LOCAL 2 /* Current path is local */
+#define SNMP_PATH_SECONDARY 3 /* Current path is secondary */
+#define SNMP_PATH_PRIMARY 4 /* Current path is primary */
+#define SNMP_PATH_CONCATENATED 5 /* Current path is concatenated */
+#define SNMP_PATH_THRU 6 /* Current path is thru */
+};
+
+
+#endif
+
+/*
+ * PCM connect states
+ */
+#define PCM_DISABLED 0
+#define PCM_CONNECTING 1
+#define PCM_STANDBY 2
+#define PCM_ACTIVE 3
+
+struct s_pcm {
+ u_char pcm_pad[3] ;
+} ;
+
+/*
+ * PHY struct
+ * one per physical port
+ */
+struct s_phy {
+ /* Inter Module Globals */
+ struct fddi_mib_p *mib ;
+
+ u_char np ; /* index 0 .. NUMPHYS */
+ u_char cf_join ;
+ u_char cf_loop ;
+ u_char wc_flag ; /* withhold connection flag */
+ u_char pc_mode ; /* Holds the negotiated mode of the PCM */
+ u_char pc_lem_fail ; /* flag : LCT failed */
+ u_char lc_test ;
+ u_char scrub ; /* CFM flag Scrub -> PCM */
+ char phy_name ;
+ u_char pmd_type[2] ; /* SK connector/transceiver type codes */
+#define PMD_SK_CONN 0 /* pmd_type[PMD_SK_CONN] = Connector */
+#define PMD_SK_PMD 1 /* pmd_type[PMD_SK_PMD] = Xver */
+ u_char pmd_scramble ; /* scrambler on/off */
+
+ /* inner Module Globals */
+ u_char curr_ls ; /* current line state */
+ u_char ls_flag ;
+ u_char rc_flag ;
+ u_char tc_flag ;
+ u_char td_flag ;
+ u_char bitn ;
+ u_char tr_flag ; /* trace recvd while in active */
+ u_char twisted ; /* flag to indicate an A-A or B-B connection */
+ u_char t_val[NUMBITS] ; /* transmit bits for signaling */
+ u_char r_val[NUMBITS] ; /* receive bits for signaling */
+ u_long t_next[NUMBITS] ;
+ struct smt_timer pcm_timer0 ;
+ struct smt_timer pcm_timer1 ;
+ struct smt_timer pcm_timer2 ;
+ u_char timer0_exp ;
+ u_char timer1_exp ;
+ u_char timer2_exp ;
+ u_char pcm_pad1[1] ;
+ int cem_pst ; /* CEM privae state; used for dual homing */
+ struct lem_counter lem ;
+#ifdef AMDPLC
+ struct s_plc plc ;
+#endif
+} ;
+
+/*
+ * timer package
+ * smttimer.c
+ */
+struct s_timer {
+ struct smt_timer *st_queue ;
+ struct smt_timer st_fast ;
+} ;
+
+/*
+ * SRF types and data
+ */
+#define SMT_EVENT_BASE 1
+#define SMT_EVENT_MAC_PATH_CHANGE (SMT_EVENT_BASE+0)
+#define SMT_EVENT_MAC_NEIGHBOR_CHANGE (SMT_EVENT_BASE+1)
+#define SMT_EVENT_PORT_PATH_CHANGE (SMT_EVENT_BASE+2)
+#define SMT_EVENT_PORT_CONNECTION (SMT_EVENT_BASE+3)
+
+#define SMT_IS_CONDITION(x) ((x)>=SMT_COND_BASE)
+
+#define SMT_COND_BASE (SMT_EVENT_PORT_CONNECTION+1)
+#define SMT_COND_SMT_PEER_WRAP (SMT_COND_BASE+0)
+#define SMT_COND_SMT_HOLD (SMT_COND_BASE+1)
+#define SMT_COND_MAC_FRAME_ERROR (SMT_COND_BASE+2)
+#define SMT_COND_MAC_DUP_ADDR (SMT_COND_BASE+3)
+#define SMT_COND_MAC_NOT_COPIED (SMT_COND_BASE+4)
+#define SMT_COND_PORT_EB_ERROR (SMT_COND_BASE+5)
+#define SMT_COND_PORT_LER (SMT_COND_BASE+6)
+
+#define SR0_WAIT 0
+#define SR1_HOLDOFF 1
+#define SR2_DISABLED 2
+
+struct s_srf {
+ u_long SRThreshold ; /* threshold value */
+ u_char RT_Flag ; /* report transmitted flag */
+ u_char sr_state ; /* state-machine */
+ u_char any_report ; /* any report required */
+ u_long TSR ; /* timer */
+ u_short ring_status ; /* IBM ring status */
+} ;
+
+/*
+ * IBM token ring status
+ */
+#define RS_RES15 (1<<15) /* reserved */
+#define RS_HARDERROR (1<<14) /* ring down */
+#define RS_SOFTERROR (1<<13) /* sent SRF */
+#define RS_BEACON (1<<12) /* transmitted beacon */
+#define RS_PATHTEST (1<<11) /* path test failed */
+#define RS_SELFTEST (1<<10) /* selftest required */
+#define RS_RES9 (1<< 9) /* reserved */
+#define RS_DISCONNECT (1<< 8) /* remote disconnect */
+#define RS_RES7 (1<< 7) /* reserved */
+#define RS_DUPADDR (1<< 6) /* duplicate address */
+#define RS_NORINGOP (1<< 5) /* no ring op */
+#define RS_VERSION (1<< 4) /* SMT version mismatch */
+#define RS_STUCKBYPASSS (1<< 3) /* stuck bypass */
+#define RS_EVENT (1<< 2) /* FDDI event occurred */
+#define RS_RINGOPCHANGE (1<< 1) /* ring op changed */
+#define RS_RES0 (1<< 0) /* reserved */
+
+#define RS_SET(smc,bit) \
+ ring_status_indication(smc,smc->srf.ring_status |= bit)
+#define RS_CLEAR(smc,bit) \
+ ring_status_indication(smc,smc->srf.ring_status &= ~bit)
+
+#define RS_CLEAR_EVENT (0xffff & ~(RS_NORINGOP))
+
+/* Define the AIX-event-Notification as null function if it isn't defined */
+/* in the targetos.h file */
+#ifndef AIX_EVENT
+#define AIX_EVENT(smc,opt0,opt1,opt2,opt3) /* nothing */
+#endif
+
+struct s_srf_evc {
+ u_char evc_code ; /* event code type */
+ u_char evc_index ; /* index for mult. instances */
+ u_char evc_rep_required ; /* report required */
+ u_short evc_para ; /* SMT Para Number */
+ u_char *evc_cond_state ; /* condition state */
+ u_char *evc_multiple ; /* multiple occurrence */
+} ;
+
+/*
+ * Values used by frame based services
+ * smt.c
+ */
+#define SMT_MAX_TEST 5
+#define SMT_TID_NIF 0 /* pending NIF request */
+#define SMT_TID_NIF_TEST 1 /* pending NIF test */
+#define SMT_TID_ECF_UNA 2 /* pending ECF UNA test */
+#define SMT_TID_ECF_DNA 3 /* pending ECF DNA test */
+#define SMT_TID_ECF 4 /* pending ECF test */
+
+struct smt_values {
+ u_long smt_tvu ; /* timer valid una */
+ u_long smt_tvd ; /* timer valid dna */
+ u_long smt_tid ; /* transaction id */
+ u_long pend[SMT_MAX_TEST] ; /* TID of requests */
+ u_long uniq_time ; /* unique time stamp */
+ u_short uniq_ticks ; /* unique time stamp */
+ u_short please_reconnect ; /* flag : reconnect */
+ u_long smt_last_lem ;
+ u_long smt_last_notify ;
+ struct smt_timer smt_timer ; /* SMT NIF timer */
+ u_long last_tok_time[NUMMACS]; /* token cnt emulation */
+} ;
+
+/*
+ * SMT/CMT configurable parameters
+ */
+#define SMT_DAS 0 /* dual attach */
+#define SMT_SAS 1 /* single attach */
+#define SMT_NAC 2 /* null attach concentrator */
+
+struct smt_config {
+ u_char attach_s ; /* CFM attach to secondary path */
+ u_char sas ; /* SMT_DAS/SAS/NAC */
+ u_char build_ring_map ; /* build ringmap if TRUE */
+ u_char numphys ; /* number of active phys */
+ u_char sc_pad[1] ;
+
+ u_long pcm_tb_min ; /* PCM : TB_Min timer value */
+ u_long pcm_tb_max ; /* PCM : TB_Max timer value */
+ u_long pcm_c_min ; /* PCM : C_Min timer value */
+ u_long pcm_t_out ; /* PCM : T_Out timer value */
+ u_long pcm_tl_min ; /* PCM : TL_min timer value */
+ u_long pcm_lc_short ; /* PCM : LC_Short timer value */
+ u_long pcm_lc_medium ; /* PCM : LC_Medium timer value */
+ u_long pcm_lc_long ; /* PCM : LC_Long timer value */
+ u_long pcm_lc_extended ; /* PCM : LC_Extended timer value */
+ u_long pcm_t_next_9 ; /* PCM : T_Next[9] timer value */
+ u_long pcm_ns_max ; /* PCM : NS_Max timer value */
+
+ u_long ecm_i_max ; /* ECM : I_Max timer value */
+ u_long ecm_in_max ; /* ECM : IN_Max timer value */
+ u_long ecm_td_min ; /* ECM : TD_Min timer */
+ u_long ecm_test_done ; /* ECM : path test done timer */
+ u_long ecm_check_poll ; /* ECM : check bypass poller */
+
+ u_long rmt_t_non_op ; /* RMT : T_Non_OP timer value */
+ u_long rmt_t_stuck ; /* RMT : T_Stuck timer value */
+ u_long rmt_t_direct ; /* RMT : T_Direct timer value */
+ u_long rmt_t_jam ; /* RMT : T_Jam timer value */
+ u_long rmt_t_announce ; /* RMT : T_Announce timer value */
+ u_long rmt_t_poll ; /* RMT : claim/beacon poller */
+ u_long rmt_dup_mac_behavior ; /* Flag for the beavior of SMT if
+ * a Duplicate MAC Address was detected.
+ * FALSE: SMT will leave finaly the ring
+ * TRUE: SMT will reinstert into the ring
+ */
+ u_long mac_d_max ; /* MAC : D_Max timer value */
+
+ u_long lct_short ; /* LCT : error threshhold */
+ u_long lct_medium ; /* LCT : error threshhold */
+ u_long lct_long ; /* LCT : error threshhold */
+ u_long lct_extended ; /* LCT : error threshhold */
+} ;
+
+#ifdef DEBUG
+/*
+ * Debugging struct sometimes used in smc
+ */
+struct smt_debug {
+ int d_smtf ;
+ int d_smt ;
+ int d_ecm ;
+ int d_rmt ;
+ int d_cfm ;
+ int d_pcm ;
+ int d_plc ;
+#ifdef ESS
+ int d_ess ;
+#endif
+#ifdef SBA
+ int d_sba ;
+#endif
+ struct os_debug d_os; /* Include specific OS DEBUG struct */
+} ;
+
+#ifndef DEBUG_BRD
+/* all boards shall be debugged with one debug struct */
+extern struct smt_debug debug; /* Declaration of debug struct */
+#endif /* DEBUG_BRD */
+
+#endif /* DEBUG */
+
+/*
+ * the SMT Context Struct SMC
+ * this struct contains ALL global variables of SMT
+ */
+struct s_smc {
+ struct s_smt_os os ; /* os specific */
+ struct s_smt_hw hw ; /* hardware */
+
+/*
+ * NOTE: os and hw MUST BE the first two structs
+ * anything beyond hw WILL BE SET TO ZERO in smt_set_defaults()
+ */
+ struct smt_config s ; /* smt constants */
+ struct smt_values sm ; /* smt variables */
+ struct s_ecm e ; /* ecm */
+ struct s_rmt r ; /* rmt */
+ struct s_cfm cf ; /* cfm/cem */
+#ifdef CONCENTRATOR
+ struct s_cem ce[NUMPHYS] ; /* cem */
+ struct s_c_ring cr[NUMPHYS+NUMMACS] ;
+#endif
+ struct s_pcm p ; /* pcm */
+ struct s_phy y[NUMPHYS] ; /* phy */
+ struct s_queue q ; /* queue */
+ struct s_timer t ; /* timer */
+ struct s_srf srf ; /* SRF */
+ struct s_srf_evc evcs[6+NUMPHYS*4] ;
+ struct fddi_mib mib ; /* __THE_MIB__ */
+#ifdef SBA
+ struct s_sba sba ; /* SBA variables */
+#endif
+#ifdef ESS
+ struct s_ess ess ; /* Ess variables */
+#endif
+#if defined(DEBUG) && defined(DEBUG_BRD)
+ /* If you want all single board to be debugged separately */
+ struct smt_debug debug; /* Declaration of debug struct */
+#endif /* DEBUG_BRD && DEBUG */
+} ;
+
+#endif /* _SCMECM_ */
+
diff --git a/drivers/net/skfp/h/smt.h b/drivers/net/skfp/h/smt.h
new file mode 100644
index 0000000..1ff5899
--- /dev/null
+++ b/drivers/net/skfp/h/smt.h
@@ -0,0 +1,882 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*
+ * SMT 7.2 frame definitions
+ */
+
+#ifndef _SMT_
+#define _SMT_
+
+/* #define SMT5_10 */
+#define SMT6_10
+#define SMT7_20
+
+#define OPT_PMF /* if parameter management is supported */
+#define OPT_SRF /* if status report is supported */
+
+/*
+ * SMT frame version 5.1
+ */
+
+#define SMT_VID 0x0001 /* V 5.1 .. 6.1 */
+#define SMT_VID_2 0x0002 /* V 7.2 */
+
+struct smt_sid {
+ u_char sid_oem[2] ; /* implementation spec. */
+ struct fddi_addr sid_node ; /* node address */
+} ;
+
+typedef u_char t_station_id[8] ;
+
+/*
+ * note on alignment :
+ * sizeof(struct smt_header) = 32
+ * all parameters are long aligned
+ * if struct smt_header starts at offset 0, all longs are aligned correctly
+ * (FC starts at offset 3)
+ */
+_packed struct smt_header {
+ struct fddi_addr smt_dest ; /* destination address */
+ struct fddi_addr smt_source ; /* source address */
+ u_char smt_class ; /* NIF, SIF ... */
+ u_char smt_type ; /* req., response .. */
+ u_short smt_version ; /* version id */
+ u_int smt_tid ; /* transaction ID */
+ struct smt_sid smt_sid ; /* station ID */
+ u_short smt_pad ; /* pad with 0 */
+ u_short smt_len ; /* length of info field */
+} ;
+#define SWAP_SMTHEADER "662sl8ss"
+
+#if 0
+/*
+ * MAC FC values
+ */
+#define FC_SMT_INFO 0x41 /* SMT info */
+#define FC_SMT_NSA 0x4f /* SMT Next Station Addressing */
+#endif
+
+
+/*
+ * type codes
+ */
+#define SMT_ANNOUNCE 0x01 /* announcement */
+#define SMT_REQUEST 0x02 /* request */
+#define SMT_REPLY 0x03 /* reply */
+
+/*
+ * class codes
+ */
+#define SMT_NIF 0x01 /* neighbor information frames */
+#define SMT_SIF_CONFIG 0x02 /* station information configuration */
+#define SMT_SIF_OPER 0x03 /* station information operation */
+#define SMT_ECF 0x04 /* echo frames */
+#define SMT_RAF 0x05 /* resource allocation */
+#define SMT_RDF 0x06 /* request denied */
+#define SMT_SRF 0x07 /* status report */
+#define SMT_PMF_GET 0x08 /* parameter management get */
+#define SMT_PMF_SET 0x09 /* parameter management set */
+#define SMT_ESF 0xff /* extended service */
+
+#define SMT_MAX_ECHO_LEN 4458 /* max length of SMT Echo */
+#if defined(CONC) || defined(CONC_II)
+#define SMT_TEST_ECHO_LEN 50 /* test length of SMT Echo */
+#else
+#define SMT_TEST_ECHO_LEN SMT_MAX_ECHO_LEN /* test length */
+#endif
+
+#define SMT_MAX_INFO_LEN (4352-20) /* max length for SMT info */
+
+
+/*
+ * parameter types
+ */
+
+struct smt_para {
+ u_short p_type ; /* type */
+ u_short p_len ; /* length of parameter */
+} ;
+
+#define PARA_LEN (sizeof(struct smt_para))
+
+#define SMTSETPARA(p,t) (p)->para.p_type = (t),\
+ (p)->para.p_len = sizeof(*(p)) - PARA_LEN
+
+/*
+ * P01 : Upstream Neighbor Address, UNA
+ */
+#define SMT_P_UNA 0x0001 /* upstream neighbor address */
+#define SWAP_SMT_P_UNA "s6"
+
+struct smt_p_una {
+ struct smt_para para ; /* generic parameter header */
+ u_short una_pad ;
+ struct fddi_addr una_node ; /* node address, zero if unknown */
+} ;
+
+/*
+ * P02 : Station Descriptor
+ */
+#define SMT_P_SDE 0x0002 /* station descriptor */
+#define SWAP_SMT_P_SDE "1111"
+
+#define SMT_SDE_STATION 0 /* end node */
+#define SMT_SDE_CONCENTRATOR 1 /* concentrator */
+
+struct smt_p_sde {
+ struct smt_para para ; /* generic parameter header */
+ u_char sde_type ; /* station type */
+ u_char sde_mac_count ; /* number of MACs */
+ u_char sde_non_master ; /* number of A,B or S ports */
+ u_char sde_master ; /* number of S ports on conc. */
+} ;
+
+/*
+ * P03 : Station State
+ */
+#define SMT_P_STATE 0x0003 /* station state */
+#define SWAP_SMT_P_STATE "scc"
+
+struct smt_p_state {
+ struct smt_para para ; /* generic parameter header */
+ u_short st_pad ;
+ u_char st_topology ; /* topology */
+ u_char st_dupl_addr ; /* duplicate address detected */
+} ;
+#define SMT_ST_WRAPPED (1<<0) /* station wrapped */
+#define SMT_ST_UNATTACHED (1<<1) /* unattached concentrator */
+#define SMT_ST_TWISTED_A (1<<2) /* A-A connection, twisted ring */
+#define SMT_ST_TWISTED_B (1<<3) /* B-B connection, twisted ring */
+#define SMT_ST_ROOTED_S (1<<4) /* rooted station */
+#define SMT_ST_SRF (1<<5) /* SRF protocol supported */
+#define SMT_ST_SYNC_SERVICE (1<<6) /* use synchronous bandwidth */
+
+#define SMT_ST_MY_DUPA (1<<0) /* my station detected dupl. */
+#define SMT_ST_UNA_DUPA (1<<1) /* my UNA detected duplicate */
+
+/*
+ * P04 : timestamp
+ */
+#define SMT_P_TIMESTAMP 0x0004 /* time stamp */
+#define SWAP_SMT_P_TIMESTAMP "8"
+struct smt_p_timestamp {
+ struct smt_para para ; /* generic parameter header */
+ u_char ts_time[8] ; /* time, resolution 80nS, unique */
+} ;
+
+/*
+ * P05 : station policies
+ */
+#define SMT_P_POLICY 0x0005 /* station policies */
+#define SWAP_SMT_P_POLICY "ss"
+
+struct smt_p_policy {
+ struct smt_para para ; /* generic parameter header */
+ u_short pl_config ;
+ u_short pl_connect ; /* bit string POLICY_AA ... */
+} ;
+#define SMT_PL_HOLD 1 /* hold policy supported (Dual MAC) */
+
+/*
+ * P06 : latency equivalent
+ */
+#define SMT_P_LATENCY 0x0006 /* latency */
+#define SWAP_SMT_P_LATENCY "ssss"
+
+/*
+ * note: latency has two phy entries by definition
+ * for a SAS, the 2nd one is null
+ */
+struct smt_p_latency {
+ struct smt_para para ; /* generic parameter header */
+ u_short lt_phyout_idx1 ; /* index */
+ u_short lt_latency1 ; /* latency , unit : byte clock */
+ u_short lt_phyout_idx2 ; /* 0 if SAS */
+ u_short lt_latency2 ; /* 0 if SAS */
+} ;
+
+/*
+ * P07 : MAC neighbors
+ */
+#define SMT_P_NEIGHBORS 0x0007 /* MAC neighbor description */
+#define SWAP_SMT_P_NEIGHBORS "ss66"
+
+struct smt_p_neighbor {
+ struct smt_para para ; /* generic parameter header */
+ u_short nb_mib_index ; /* MIB index */
+ u_short nb_mac_index ; /* n+1 .. n+m, m = #MACs, n = #PHYs */
+ struct fddi_addr nb_una ; /* UNA , 0 for unknown */
+ struct fddi_addr nb_dna ; /* DNA , 0 for unknown */
+} ;
+
+/*
+ * PHY record
+ */
+#define SMT_PHY_A 0 /* A port */
+#define SMT_PHY_B 1 /* B port */
+#define SMT_PHY_S 2 /* slave port */
+#define SMT_PHY_M 3 /* master port */
+
+#define SMT_CS_DISABLED 0 /* connect state : disabled */
+#define SMT_CS_CONNECTING 1 /* connect state : connecting */
+#define SMT_CS_STANDBY 2 /* connect state : stand by */
+#define SMT_CS_ACTIVE 3 /* connect state : active */
+
+#define SMT_RM_NONE 0
+#define SMT_RM_MAC 1
+
+struct smt_phy_rec {
+ u_short phy_mib_index ; /* MIB index */
+ u_char phy_type ; /* A/B/S/M */
+ u_char phy_connect_state ; /* disabled/connecting/active */
+ u_char phy_remote_type ; /* A/B/S/M */
+ u_char phy_remote_mac ; /* none/remote */
+ u_short phy_resource_idx ; /* 1 .. n */
+} ;
+
+/*
+ * MAC record
+ */
+struct smt_mac_rec {
+ struct fddi_addr mac_addr ; /* MAC address */
+ u_short mac_resource_idx ; /* n+1 .. n+m */
+} ;
+
+/*
+ * P08 : path descriptors
+ * should be really an array ; however our environment has a fixed number of
+ * PHYs and MACs
+ */
+#define SMT_P_PATH 0x0008 /* path descriptor */
+#define SWAP_SMT_P_PATH "[6s]"
+
+struct smt_p_path {
+ struct smt_para para ; /* generic parameter header */
+ struct smt_phy_rec pd_phy[2] ; /* PHY A */
+ struct smt_mac_rec pd_mac ; /* MAC record */
+} ;
+
+/*
+ * P09 : MAC status
+ */
+#define SMT_P_MAC_STATUS 0x0009 /* MAC status */
+#define SWAP_SMT_P_MAC_STATUS "sslllllllll"
+
+struct smt_p_mac_status {
+ struct smt_para para ; /* generic parameter header */
+ u_short st_mib_index ; /* MIB index */
+ u_short st_mac_index ; /* n+1 .. n+m */
+ u_int st_t_req ; /* T_Req */
+ u_int st_t_neg ; /* T_Neg */
+ u_int st_t_max ; /* T_Max */
+ u_int st_tvx_value ; /* TVX_Value */
+ u_int st_t_min ; /* T_Min */
+ u_int st_sba ; /* synchr. bandwidth alloc */
+ u_int st_frame_ct ; /* frame counter */
+ u_int st_error_ct ; /* error counter */
+ u_int st_lost_ct ; /* lost frames counter */
+} ;
+
+/*
+ * P0A : PHY link error rate monitoring
+ */
+#define SMT_P_LEM 0x000a /* link error monitor */
+#define SWAP_SMT_P_LEM "ssccccll"
+/*
+ * units of lem_cutoff,lem_alarm,lem_estimate : 10**-x
+ */
+struct smt_p_lem {
+ struct smt_para para ; /* generic parameter header */
+ u_short lem_mib_index ; /* MIB index */
+ u_short lem_phy_index ; /* 1 .. n */
+ u_char lem_pad2 ; /* be nice and make it even . */
+ u_char lem_cutoff ; /* 0x4 .. 0xf, default 0x7 */
+ u_char lem_alarm ; /* 0x4 .. 0xf, default 0x8 */
+ u_char lem_estimate ; /* 0x0 .. 0xff */
+ u_int lem_reject_ct ; /* 0x00000000 .. 0xffffffff */
+ u_int lem_ct ; /* 0x00000000 .. 0xffffffff */
+} ;
+
+/*
+ * P0B : MAC frame counters
+ */
+#define SMT_P_MAC_COUNTER 0x000b /* MAC frame counters */
+#define SWAP_SMT_P_MAC_COUNTER "ssll"
+
+struct smt_p_mac_counter {
+ struct smt_para para ; /* generic parameter header */
+ u_short mc_mib_index ; /* MIB index */
+ u_short mc_index ; /* mac index */
+ u_int mc_receive_ct ; /* receive counter */
+ u_int mc_transmit_ct ; /* transmit counter */
+} ;
+
+/*
+ * P0C : MAC frame not copied counter
+ */
+#define SMT_P_MAC_FNC 0x000c /* MAC frame not copied counter */
+#define SWAP_SMT_P_MAC_FNC "ssl"
+
+struct smt_p_mac_fnc {
+ struct smt_para para ; /* generic parameter header */
+ u_short nc_mib_index ; /* MIB index */
+ u_short nc_index ; /* mac index */
+ u_int nc_counter ; /* not copied counter */
+} ;
+
+
+/*
+ * P0D : MAC priority values
+ */
+#define SMT_P_PRIORITY 0x000d /* MAC priority values */
+#define SWAP_SMT_P_PRIORITY "ssl"
+
+struct smt_p_priority {
+ struct smt_para para ; /* generic parameter header */
+ u_short pr_mib_index ; /* MIB index */
+ u_short pr_index ; /* mac index */
+ u_int pr_priority[7] ; /* priority values */
+} ;
+
+/*
+ * P0E : PHY elasticity buffer status
+ */
+#define SMT_P_EB 0x000e /* PHY EB status */
+#define SWAP_SMT_P_EB "ssl"
+
+struct smt_p_eb {
+ struct smt_para para ; /* generic parameter header */
+ u_short eb_mib_index ; /* MIB index */
+ u_short eb_index ; /* phy index */
+ u_int eb_error_ct ; /* # of eb overflows */
+} ;
+
+/*
+ * P0F : manufacturer field
+ */
+#define SMT_P_MANUFACTURER 0x000f /* manufacturer field */
+#define SWAP_SMT_P_MANUFACTURER ""
+
+struct smp_p_manufacturer {
+ struct smt_para para ; /* generic parameter header */
+ u_char mf_data[32] ; /* OUI + arbitrary data */
+} ;
+
+/*
+ * P10 : user field
+ */
+#define SMT_P_USER 0x0010 /* manufacturer field */
+#define SWAP_SMT_P_USER ""
+
+struct smp_p_user {
+ struct smt_para para ; /* generic parameter header */
+ u_char us_data[32] ; /* arbitrary data */
+} ;
+
+
+
+/*
+ * P11 : echo data
+ */
+#define SMT_P_ECHODATA 0x0011 /* echo data */
+#define SWAP_SMT_P_ECHODATA ""
+
+struct smt_p_echo {
+ struct smt_para para ; /* generic parameter header */
+ u_char ec_data[SMT_MAX_ECHO_LEN-4] ; /* echo data */
+} ;
+
+/*
+ * P12 : reason code
+ */
+#define SMT_P_REASON 0x0012 /* reason code */
+#define SWAP_SMT_P_REASON "l"
+
+struct smt_p_reason {
+ struct smt_para para ; /* generic parameter header */
+ u_int rdf_reason ; /* CLASS/VERSION */
+} ;
+#define SMT_RDF_CLASS 0x00000001 /* class not supported */
+#define SMT_RDF_VERSION 0x00000002 /* version not supported */
+#define SMT_RDF_SUCCESS 0x00000003 /* success (PMF) */
+#define SMT_RDF_BADSET 0x00000004 /* bad set count (PMF) */
+#define SMT_RDF_ILLEGAL 0x00000005 /* read only (PMF) */
+#define SMT_RDF_NOPARAM 0x6 /* paramter not supported (PMF) */
+#define SMT_RDF_RANGE 0x8 /* out of range */
+#define SMT_RDF_AUTHOR 0x9 /* not autohorized */
+#define SMT_RDF_LENGTH 0x0a /* length error */
+#define SMT_RDF_TOOLONG 0x0b /* length error */
+#define SMT_RDF_SBA 0x0d /* SBA denied */
+
+/*
+ * P13 : refused frame beginning
+ */
+#define SMT_P_REFUSED 0x0013 /* refused frame beginning */
+#define SWAP_SMT_P_REFUSED "l"
+
+struct smt_p_refused {
+ struct smt_para para ; /* generic parameter header */
+ u_int ref_fc ; /* 3 bytes 0 + FC */
+ struct smt_header ref_header ; /* refused header */
+} ;
+
+/*
+ * P14 : supported SMT versions
+ */
+#define SMT_P_VERSION 0x0014 /* SMT supported versions */
+#define SWAP_SMT_P_VERSION "sccss"
+
+struct smt_p_version {
+ struct smt_para para ; /* generic parameter header */
+ u_short v_pad ;
+ u_char v_n ; /* 1 .. 0xff, #versions */
+ u_char v_index ; /* 1 .. 0xff, index of op. v. */
+ u_short v_version[1] ; /* list of min. 1 version */
+ u_short v_pad2 ; /* pad if necessary */
+} ;
+
+/*
+ * P15 : Resource Type
+ */
+#define SWAP_SMT_P0015 "l"
+
+struct smt_p_0015 {
+ struct smt_para para ; /* generic parameter header */
+ u_int res_type ; /* recsource type */
+} ;
+
+#define SYNC_BW 0x00000001L /* Synchronous Bandwidth */
+
+/*
+ * P16 : SBA Command
+ */
+#define SWAP_SMT_P0016 "l"
+
+struct smt_p_0016 {
+ struct smt_para para ; /* generic parameter header */
+ u_int sba_cmd ; /* command for the SBA */
+} ;
+
+#define REQUEST_ALLOCATION 0x1 /* req allocation of sync bandwidth */
+#define REPORT_ALLOCATION 0x2 /* rep of sync bandwidth allocation */
+#define CHANGE_ALLOCATION 0x3 /* forces a station using sync band-*/
+ /* width to change its current allo-*/
+ /* cation */
+
+/*
+ * P17 : SBA Payload Request
+ */
+#define SWAP_SMT_P0017 "l"
+
+struct smt_p_0017 {
+ struct smt_para para ; /* generic parameter header */
+ int sba_pl_req ; /* total sync bandwidth measured in */
+} ; /* bytes per 125 us */
+
+/*
+ * P18 : SBA Overhead Request
+ */
+#define SWAP_SMT_P0018 "l"
+
+struct smt_p_0018 {
+ struct smt_para para ; /* generic parameter header */
+ int sba_ov_req ; /* total sync bandwidth req for overhead*/
+} ; /* measuered in bytes per T_Neg */
+
+/*
+ * P19 : SBA Allocation Address
+ */
+#define SWAP_SMT_P0019 "s6"
+
+struct smt_p_0019 {
+ struct smt_para para ; /* generic parameter header */
+ u_short sba_pad ;
+ struct fddi_addr alloc_addr ; /* Allocation Address */
+} ;
+
+/*
+ * P1A : SBA Category
+ */
+#define SWAP_SMT_P001A "l"
+
+struct smt_p_001a {
+ struct smt_para para ; /* generic parameter header */
+ u_int category ; /* Allocator defined classification */
+} ;
+
+/*
+ * P1B : Maximum T_Neg
+ */
+#define SWAP_SMT_P001B "l"
+
+struct smt_p_001b {
+ struct smt_para para ; /* generic parameter header */
+ u_int max_t_neg ; /* longest T_NEG for the sync service*/
+} ;
+
+/*
+ * P1C : Minimum SBA Segment Size
+ */
+#define SWAP_SMT_P001C "l"
+
+struct smt_p_001c {
+ struct smt_para para ; /* generic parameter header */
+ u_int min_seg_siz ; /* smallest number of bytes per frame*/
+} ;
+
+/*
+ * P1D : SBA Allocatable
+ */
+#define SWAP_SMT_P001D "l"
+
+struct smt_p_001d {
+ struct smt_para para ; /* generic parameter header */
+ u_int allocatable ; /* total sync bw available for alloc */
+} ;
+
+/*
+ * P20 0B : frame status capabilities
+ * NOTE: not in swap table, is used by smt.c AND PMF table
+ */
+#define SMT_P_FSC 0x200b
+/* #define SWAP_SMT_P_FSC "ssss" */
+
+struct smt_p_fsc {
+ struct smt_para para ; /* generic parameter header */
+ u_short fsc_pad0 ;
+ u_short fsc_mac_index ; /* mac index 1 .. ff */
+ u_short fsc_pad1 ;
+ u_short fsc_value ; /* FSC_TYPE[0-2] */
+} ;
+
+#define FSC_TYPE0 0 /* "normal" node (A/C handling) */
+#define FSC_TYPE1 1 /* Special A/C indicator forwarding */
+#define FSC_TYPE2 2 /* Special A/C indicator forwarding */
+
+/*
+ * P00 21 : user defined authoriziation (see pmf.c)
+ */
+#define SMT_P_AUTHOR 0x0021
+
+/*
+ * notification parameters
+ */
+#define SWAP_SMT_P1048 "ll"
+struct smt_p_1048 {
+ u_int p1048_flag ;
+ u_int p1048_cf_state ;
+} ;
+
+/*
+ * NOTE: all 2xxx 3xxx and 4xxx must include the INDEX in the swap string,
+ * even so the INDEX is NOT part of the struct.
+ * INDEX is already swapped in pmf.c, format in string is '4'
+ */
+#define SWAP_SMT_P208C "4lss66"
+struct smt_p_208c {
+ u_int p208c_flag ;
+ u_short p208c_pad ;
+ u_short p208c_dupcondition ;
+ struct fddi_addr p208c_fddilong ;
+ struct fddi_addr p208c_fddiunalong ;
+} ;
+
+#define SWAP_SMT_P208D "4lllll"
+struct smt_p_208d {
+ u_int p208d_flag ;
+ u_int p208d_frame_ct ;
+ u_int p208d_error_ct ;
+ u_int p208d_lost_ct ;
+ u_int p208d_ratio ;
+} ;
+
+#define SWAP_SMT_P208E "4llll"
+struct smt_p_208e {
+ u_int p208e_flag ;
+ u_int p208e_not_copied ;
+ u_int p208e_copied ;
+ u_int p208e_not_copied_ratio ;
+} ;
+
+#define SWAP_SMT_P208F "4ll6666s6"
+
+struct smt_p_208f {
+ u_int p208f_multiple ;
+ u_int p208f_nacondition ;
+ struct fddi_addr p208f_old_una ;
+ struct fddi_addr p208f_new_una ;
+ struct fddi_addr p208f_old_dna ;
+ struct fddi_addr p208f_new_dna ;
+ u_short p208f_curren_path ;
+ struct fddi_addr p208f_smt_address ;
+} ;
+
+#define SWAP_SMT_P2090 "4lssl"
+
+struct smt_p_2090 {
+ u_int p2090_multiple ;
+ u_short p2090_availablepaths ;
+ u_short p2090_currentpath ;
+ u_int p2090_requestedpaths ;
+} ;
+
+/*
+ * NOTE:
+ * special kludge for parameters 320b,320f,3210
+ * these parameters are part of RAF frames
+ * RAF frames are parsed in SBA.C and must be swapped
+ * PMF.C has special code to avoid double swapping
+ */
+#ifdef LITTLE_ENDIAN
+#define SBAPATHINDEX (0x01000000L)
+#else
+#define SBAPATHINDEX (0x01L)
+#endif
+
+#define SWAP_SMT_P320B "42s"
+
+struct smt_p_320b {
+ struct smt_para para ; /* generic parameter header */
+ u_int mib_index ;
+ u_short path_pad ;
+ u_short path_index ;
+} ;
+
+#define SWAP_SMT_P320F "4l"
+
+struct smt_p_320f {
+ struct smt_para para ; /* generic parameter header */
+ u_int mib_index ;
+ u_int mib_payload ;
+} ;
+
+#define SWAP_SMT_P3210 "4l"
+
+struct smt_p_3210 {
+ struct smt_para para ; /* generic parameter header */
+ u_int mib_index ;
+ u_int mib_overhead ;
+} ;
+
+#define SWAP_SMT_P4050 "4l1111ll"
+
+struct smt_p_4050 {
+ u_int p4050_flag ;
+ u_char p4050_pad ;
+ u_char p4050_cutoff ;
+ u_char p4050_alarm ;
+ u_char p4050_estimate ;
+ u_int p4050_reject_ct ;
+ u_int p4050_ct ;
+} ;
+
+#define SWAP_SMT_P4051 "4lssss"
+struct smt_p_4051 {
+ u_int p4051_multiple ;
+ u_short p4051_porttype ;
+ u_short p4051_connectstate ;
+ u_short p4051_pc_neighbor ;
+ u_short p4051_pc_withhold ;
+} ;
+
+#define SWAP_SMT_P4052 "4ll"
+struct smt_p_4052 {
+ u_int p4052_flag ;
+ u_int p4052_eberrorcount ;
+} ;
+
+#define SWAP_SMT_P4053 "4lsslss"
+
+struct smt_p_4053 {
+ u_int p4053_multiple ;
+ u_short p4053_availablepaths ;
+ u_short p4053_currentpath ;
+ u_int p4053_requestedpaths ;
+ u_short p4053_mytype ;
+ u_short p4053_neighbortype ;
+} ;
+
+
+#define SMT_P_SETCOUNT 0x1035
+#define SWAP_SMT_P_SETCOUNT "l8"
+
+struct smt_p_setcount {
+ struct smt_para para ; /* generic parameter header */
+ u_int count ;
+ u_char timestamp[8] ;
+} ;
+
+/*
+ * SMT FRAMES
+ */
+
+/*
+ * NIF : neighbor information frames
+ */
+struct smt_nif {
+ struct smt_header smt ; /* generic header */
+ struct smt_p_una una ; /* UNA */
+ struct smt_p_sde sde ; /* station descriptor */
+ struct smt_p_state state ; /* station state */
+#ifdef SMT6_10
+ struct smt_p_fsc fsc ; /* frame status cap. */
+#endif
+} ;
+
+/*
+ * SIF : station information frames
+ */
+struct smt_sif_config {
+ struct smt_header smt ; /* generic header */
+ struct smt_p_timestamp ts ; /* time stamp */
+ struct smt_p_sde sde ; /* station descriptor */
+ struct smt_p_version version ; /* supported versions */
+ struct smt_p_state state ; /* station state */
+ struct smt_p_policy policy ; /* station policy */
+ struct smt_p_latency latency ; /* path latency */
+ struct smt_p_neighbor neighbor ; /* neighbors, we have only one*/
+#ifdef OPT_PMF
+ struct smt_p_setcount setcount ; /* Set Count mandatory */
+#endif
+ /* WARNING : path MUST BE LAST FIELD !!! (see smt.c:smt_fill_path) */
+ struct smt_p_path path ; /* path descriptor */
+} ;
+#define SIZEOF_SMT_SIF_CONFIG (sizeof(struct smt_sif_config)- \
+ sizeof(struct smt_p_path))
+
+struct smt_sif_operation {
+ struct smt_header smt ; /* generic header */
+ struct smt_p_timestamp ts ; /* time stamp */
+ struct smt_p_mac_status status ; /* mac status */
+ struct smt_p_mac_counter mc ; /* MAC counter */
+ struct smt_p_mac_fnc fnc ; /* MAC frame not copied */
+ struct smp_p_manufacturer man ; /* manufacturer field */
+ struct smp_p_user user ; /* user field */
+#ifdef OPT_PMF
+ struct smt_p_setcount setcount ; /* Set Count mandatory */
+#endif
+ /* must be last */
+ struct smt_p_lem lem[1] ; /* phy lem status */
+} ;
+#define SIZEOF_SMT_SIF_OPERATION (sizeof(struct smt_sif_operation)- \
+ sizeof(struct smt_p_lem))
+
+/*
+ * ECF : echo frame
+ */
+struct smt_ecf {
+ struct smt_header smt ; /* generic header */
+ struct smt_p_echo ec_echo ; /* echo parameter */
+} ;
+#define SMT_ECF_LEN (sizeof(struct smt_header)+sizeof(struct smt_para))
+
+/*
+ * RDF : request denied frame
+ */
+struct smt_rdf {
+ struct smt_header smt ; /* generic header */
+ struct smt_p_reason reason ; /* reason code */
+ struct smt_p_version version ; /* supported versions */
+ struct smt_p_refused refused ; /* refused frame fragment */
+} ;
+
+/*
+ * SBA Request Allocation Responce Frame
+ */
+struct smt_sba_alc_res {
+ struct smt_header smt ; /* generic header */
+ struct smt_p_0015 s_type ; /* resource type */
+ struct smt_p_0016 cmd ; /* SBA command */
+ struct smt_p_reason reason ; /* reason code */
+ struct smt_p_320b path ; /* path type */
+ struct smt_p_320f payload ; /* current SBA payload */
+ struct smt_p_3210 overhead ; /* current SBA overhead */
+ struct smt_p_0019 a_addr ; /* Allocation Address */
+ struct smt_p_001a cat ; /* Category - from the request */
+ struct smt_p_001d alloc ; /* SBA Allocatable */
+} ;
+
+/*
+ * SBA Request Allocation Request Frame
+ */
+struct smt_sba_alc_req {
+ struct smt_header smt ; /* generic header */
+ struct smt_p_0015 s_type ; /* resource type */
+ struct smt_p_0016 cmd ; /* SBA command */
+ struct smt_p_320b path ; /* path type */
+ struct smt_p_0017 pl_req ; /* requested payload */
+ struct smt_p_0018 ov_req ; /* requested SBA overhead */
+ struct smt_p_320f payload ; /* current SBA payload */
+ struct smt_p_3210 overhead ; /* current SBA overhead */
+ struct smt_p_0019 a_addr ; /* Allocation Address */
+ struct smt_p_001a cat ; /* Category - from the request */
+ struct smt_p_001b tneg ; /* max T-NEG */
+ struct smt_p_001c segm ; /* minimum segment size */
+} ;
+
+/*
+ * SBA Change Allocation Request Frame
+ */
+struct smt_sba_chg {
+ struct smt_header smt ; /* generic header */
+ struct smt_p_0015 s_type ; /* resource type */
+ struct smt_p_0016 cmd ; /* SBA command */
+ struct smt_p_320b path ; /* path type */
+ struct smt_p_320f payload ; /* current SBA payload */
+ struct smt_p_3210 overhead ; /* current SBA overhead */
+ struct smt_p_001a cat ; /* Category - from the request */
+} ;
+
+/*
+ * SBA Report Allocation Request Frame
+ */
+struct smt_sba_rep_req {
+ struct smt_header smt ; /* generic header */
+ struct smt_p_0015 s_type ; /* resource type */
+ struct smt_p_0016 cmd ; /* SBA command */
+} ;
+
+/*
+ * SBA Report Allocation Response Frame
+ */
+struct smt_sba_rep_res {
+ struct smt_header smt ; /* generic header */
+ struct smt_p_0015 s_type ; /* resource type */
+ struct smt_p_0016 cmd ; /* SBA command */
+ struct smt_p_320b path ; /* path type */
+ struct smt_p_320f payload ; /* current SBA payload */
+ struct smt_p_3210 overhead ; /* current SBA overhead */
+} ;
+
+/*
+ * actions
+ */
+#define SMT_STATION_ACTION 1
+#define SMT_STATION_ACTION_CONNECT 0
+#define SMT_STATION_ACTION_DISCONNECT 1
+#define SMT_STATION_ACTION_PATHTEST 2
+#define SMT_STATION_ACTION_SELFTEST 3
+#define SMT_STATION_ACTION_DISABLE_A 4
+#define SMT_STATION_ACTION_DISABLE_B 5
+#define SMT_STATION_ACTION_DISABLE_M 6
+
+#define SMT_PORT_ACTION 2
+#define SMT_PORT_ACTION_MAINT 0
+#define SMT_PORT_ACTION_ENABLE 1
+#define SMT_PORT_ACTION_DISABLE 2
+#define SMT_PORT_ACTION_START 3
+#define SMT_PORT_ACTION_STOP 4
+
+#endif /* _SMT_ */
diff --git a/drivers/net/skfp/h/smt_p.h b/drivers/net/skfp/h/smt_p.h
new file mode 100644
index 0000000..99f9be9
--- /dev/null
+++ b/drivers/net/skfp/h/smt_p.h
@@ -0,0 +1,326 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*
+ * defines for all SMT attributes
+ */
+
+/*
+ * this boring file was produced by perl
+ * thanks Larry !
+ */
+#define SMT_P0012 0x0012
+
+#define SMT_P0015 0x0015
+#define SMT_P0016 0x0016
+#define SMT_P0017 0x0017
+#define SMT_P0018 0x0018
+#define SMT_P0019 0x0019
+
+#define SMT_P001A 0x001a
+#define SMT_P001B 0x001b
+#define SMT_P001C 0x001c
+#define SMT_P001D 0x001d
+
+#define SMT_P100A 0x100a
+#define SMT_P100B 0x100b
+#define SMT_P100C 0x100c
+#define SMT_P100D 0x100d
+#define SMT_P100E 0x100e
+#define SMT_P100F 0x100f
+#define SMT_P1010 0x1010
+#define SMT_P1011 0x1011
+#define SMT_P1012 0x1012
+#define SMT_P1013 0x1013
+#define SMT_P1014 0x1014
+#define SMT_P1015 0x1015
+#define SMT_P1016 0x1016
+#define SMT_P1017 0x1017
+#define SMT_P1018 0x1018
+#define SMT_P1019 0x1019
+#define SMT_P101A 0x101a
+#define SMT_P101B 0x101b
+#define SMT_P101C 0x101c
+#define SMT_P101D 0x101d
+#define SMT_P101E 0x101e
+#define SMT_P101F 0x101f
+#define SMT_P1020 0x1020
+#define SMT_P1021 0x1021
+#define SMT_P1022 0x1022
+#define SMT_P1023 0x1023
+#define SMT_P1024 0x1024
+#define SMT_P1025 0x1025
+#define SMT_P1026 0x1026
+#define SMT_P1027 0x1027
+#define SMT_P1028 0x1028
+#define SMT_P1029 0x1029
+#define SMT_P102A 0x102a
+#define SMT_P102B 0x102b
+#define SMT_P102C 0x102c
+#define SMT_P102D 0x102d
+#define SMT_P102E 0x102e
+#define SMT_P102F 0x102f
+#define SMT_P1030 0x1030
+#define SMT_P1031 0x1031
+#define SMT_P1032 0x1032
+#define SMT_P1033 0x1033
+#define SMT_P1034 0x1034
+#define SMT_P1035 0x1035
+#define SMT_P1036 0x1036
+#define SMT_P1037 0x1037
+#define SMT_P1038 0x1038
+#define SMT_P1039 0x1039
+#define SMT_P103A 0x103a
+#define SMT_P103B 0x103b
+#define SMT_P103C 0x103c
+#define SMT_P103D 0x103d
+#define SMT_P103E 0x103e
+#define SMT_P103F 0x103f
+#define SMT_P1040 0x1040
+#define SMT_P1041 0x1041
+#define SMT_P1042 0x1042
+#define SMT_P1043 0x1043
+#define SMT_P1044 0x1044
+#define SMT_P1045 0x1045
+#define SMT_P1046 0x1046
+#define SMT_P1047 0x1047
+#define SMT_P1048 0x1048
+#define SMT_P1049 0x1049
+#define SMT_P104A 0x104a
+#define SMT_P104B 0x104b
+#define SMT_P104C 0x104c
+#define SMT_P104D 0x104d
+#define SMT_P104E 0x104e
+#define SMT_P104F 0x104f
+#define SMT_P1050 0x1050
+#define SMT_P1051 0x1051
+#define SMT_P1052 0x1052
+#define SMT_P1053 0x1053
+#define SMT_P1054 0x1054
+
+#define SMT_P10F0 0x10f0
+#define SMT_P10F1 0x10f1
+#ifdef ESS
+#define SMT_P10F2 0x10f2
+#define SMT_P10F3 0x10f3
+#define SMT_P10F4 0x10f4
+#define SMT_P10F5 0x10f5
+#define SMT_P10F6 0x10f6
+#define SMT_P10F7 0x10f7
+#endif
+#ifdef SBA
+#define SMT_P10F8 0x10f8
+#define SMT_P10F9 0x10f9
+#endif
+
+#define SMT_P200A 0x200a
+#define SMT_P200B 0x200b
+#define SMT_P200C 0x200c
+#define SMT_P200D 0x200d
+#define SMT_P200E 0x200e
+#define SMT_P200F 0x200f
+#define SMT_P2010 0x2010
+#define SMT_P2011 0x2011
+#define SMT_P2012 0x2012
+#define SMT_P2013 0x2013
+#define SMT_P2014 0x2014
+#define SMT_P2015 0x2015
+#define SMT_P2016 0x2016
+#define SMT_P2017 0x2017
+#define SMT_P2018 0x2018
+#define SMT_P2019 0x2019
+#define SMT_P201A 0x201a
+#define SMT_P201B 0x201b
+#define SMT_P201C 0x201c
+#define SMT_P201D 0x201d
+#define SMT_P201E 0x201e
+#define SMT_P201F 0x201f
+#define SMT_P2020 0x2020
+#define SMT_P2021 0x2021
+#define SMT_P2022 0x2022
+#define SMT_P2023 0x2023
+#define SMT_P2024 0x2024
+#define SMT_P2025 0x2025
+#define SMT_P2026 0x2026
+#define SMT_P2027 0x2027
+#define SMT_P2028 0x2028
+#define SMT_P2029 0x2029
+#define SMT_P202A 0x202a
+#define SMT_P202B 0x202b
+#define SMT_P202C 0x202c
+#define SMT_P202D 0x202d
+#define SMT_P202E 0x202e
+#define SMT_P202F 0x202f
+#define SMT_P2030 0x2030
+#define SMT_P2031 0x2031
+#define SMT_P2032 0x2032
+#define SMT_P2033 0x2033
+#define SMT_P2034 0x2034
+#define SMT_P2035 0x2035
+#define SMT_P2036 0x2036
+#define SMT_P2037 0x2037
+#define SMT_P2038 0x2038
+#define SMT_P2039 0x2039
+#define SMT_P203A 0x203a
+#define SMT_P203B 0x203b
+#define SMT_P203C 0x203c
+#define SMT_P203D 0x203d
+#define SMT_P203E 0x203e
+#define SMT_P203F 0x203f
+#define SMT_P2040 0x2040
+#define SMT_P2041 0x2041
+#define SMT_P2042 0x2042
+#define SMT_P2043 0x2043
+#define SMT_P2044 0x2044
+#define SMT_P2045 0x2045
+#define SMT_P2046 0x2046
+#define SMT_P2047 0x2047
+#define SMT_P2048 0x2048
+#define SMT_P2049 0x2049
+#define SMT_P204A 0x204a
+#define SMT_P204B 0x204b
+#define SMT_P204C 0x204c
+#define SMT_P204D 0x204d
+#define SMT_P204E 0x204e
+#define SMT_P204F 0x204f
+#define SMT_P2050 0x2050
+#define SMT_P2051 0x2051
+#define SMT_P2052 0x2052
+#define SMT_P2053 0x2053
+#define SMT_P2054 0x2054
+#define SMT_P2055 0x2055
+#define SMT_P2056 0x2056
+#define SMT_P2057 0x2057
+#define SMT_P2058 0x2058
+#define SMT_P2059 0x2059
+#define SMT_P205A 0x205a
+#define SMT_P205B 0x205b
+#define SMT_P205C 0x205c
+#define SMT_P205D 0x205d
+#define SMT_P205E 0x205e
+#define SMT_P205F 0x205f
+#define SMT_P2060 0x2060
+#define SMT_P2061 0x2061
+#define SMT_P2062 0x2062
+#define SMT_P2063 0x2063
+#define SMT_P2064 0x2064
+#define SMT_P2065 0x2065
+#define SMT_P2066 0x2066
+#define SMT_P2067 0x2067
+#define SMT_P2068 0x2068
+#define SMT_P2069 0x2069
+#define SMT_P206A 0x206a
+#define SMT_P206B 0x206b
+#define SMT_P206C 0x206c
+#define SMT_P206D 0x206d
+#define SMT_P206E 0x206e
+#define SMT_P206F 0x206f
+#define SMT_P2070 0x2070
+#define SMT_P2071 0x2071
+#define SMT_P2072 0x2072
+#define SMT_P2073 0x2073
+#define SMT_P2074 0x2074
+#define SMT_P2075 0x2075
+#define SMT_P2076 0x2076
+
+#define SMT_P208C 0x208c
+#define SMT_P208D 0x208d
+#define SMT_P208E 0x208e
+#define SMT_P208F 0x208f
+#define SMT_P2090 0x2090
+
+#define SMT_P20F0 0x20F0
+#define SMT_P20F1 0x20F1
+
+#define SMT_P320A 0x320a
+#define SMT_P320B 0x320b
+#define SMT_P320C 0x320c
+#define SMT_P320D 0x320d
+#define SMT_P320E 0x320e
+#define SMT_P320F 0x320f
+#define SMT_P3210 0x3210
+#define SMT_P3211 0x3211
+#define SMT_P3212 0x3212
+#define SMT_P3213 0x3213
+#define SMT_P3214 0x3214
+#define SMT_P3215 0x3215
+#define SMT_P3216 0x3216
+#define SMT_P3217 0x3217
+
+#define SMT_P400A 0x400a
+#define SMT_P400B 0x400b
+#define SMT_P400C 0x400c
+#define SMT_P400D 0x400d
+#define SMT_P400E 0x400e
+#define SMT_P400F 0x400f
+#define SMT_P4010 0x4010
+#define SMT_P4011 0x4011
+#define SMT_P4012 0x4012
+#define SMT_P4013 0x4013
+#define SMT_P4014 0x4014
+#define SMT_P4015 0x4015
+#define SMT_P4016 0x4016
+#define SMT_P4017 0x4017
+#define SMT_P4018 0x4018
+#define SMT_P4019 0x4019
+#define SMT_P401A 0x401a
+#define SMT_P401B 0x401b
+#define SMT_P401C 0x401c
+#define SMT_P401D 0x401d
+#define SMT_P401E 0x401e
+#define SMT_P401F 0x401f
+#define SMT_P4020 0x4020
+#define SMT_P4021 0x4021
+#define SMT_P4022 0x4022
+#define SMT_P4023 0x4023
+#define SMT_P4024 0x4024
+#define SMT_P4025 0x4025
+#define SMT_P4026 0x4026
+#define SMT_P4027 0x4027
+#define SMT_P4028 0x4028
+#define SMT_P4029 0x4029
+#define SMT_P402A 0x402a
+#define SMT_P402B 0x402b
+#define SMT_P402C 0x402c
+#define SMT_P402D 0x402d
+#define SMT_P402E 0x402e
+#define SMT_P402F 0x402f
+#define SMT_P4030 0x4030
+#define SMT_P4031 0x4031
+#define SMT_P4032 0x4032
+#define SMT_P4033 0x4033
+#define SMT_P4034 0x4034
+#define SMT_P4035 0x4035
+#define SMT_P4036 0x4036
+#define SMT_P4037 0x4037
+#define SMT_P4038 0x4038
+#define SMT_P4039 0x4039
+#define SMT_P403A 0x403a
+#define SMT_P403B 0x403b
+#define SMT_P403C 0x403c
+#define SMT_P403D 0x403d
+#define SMT_P403E 0x403e
+#define SMT_P403F 0x403f
+#define SMT_P4040 0x4040
+#define SMT_P4041 0x4041
+#define SMT_P4042 0x4042
+#define SMT_P4043 0x4043
+#define SMT_P4044 0x4044
+#define SMT_P4045 0x4045
+#define SMT_P4046 0x4046
+
+#define SMT_P4050 0x4050
+#define SMT_P4051 0x4051
+#define SMT_P4052 0x4052
+#define SMT_P4053 0x4053
diff --git a/drivers/net/skfp/h/smtstate.h b/drivers/net/skfp/h/smtstate.h
new file mode 100644
index 0000000..62fe695
--- /dev/null
+++ b/drivers/net/skfp/h/smtstate.h
@@ -0,0 +1,106 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+#ifndef _SKFP_H_SMTSTATE_H_
+#define _SKFP_H_SMTSTATE_H_
+
+/*
+ * SMT state definitions
+ */
+
+#ifndef KERNEL
+/*
+ * PCM states
+ */
+#define PC0_OFF 0
+#define PC1_BREAK 1
+#define PC2_TRACE 2
+#define PC3_CONNECT 3
+#define PC4_NEXT 4
+#define PC5_SIGNAL 5
+#define PC6_JOIN 6
+#define PC7_VERIFY 7
+#define PC8_ACTIVE 8
+#define PC9_MAINT 9
+
+/*
+ * PCM modes
+ */
+#define PM_NONE 0
+#define PM_PEER 1
+#define PM_TREE 2
+
+/*
+ * PCM type
+ */
+#define TA 0
+#define TB 1
+#define TS 2
+#define TM 3
+#define TNONE 4
+
+/*
+ * CFM states
+ */
+#define SC0_ISOLATED 0 /* isolated */
+#define SC1_WRAP_A 5 /* wrap A */
+#define SC2_WRAP_B 6 /* wrap B */
+#define SC4_THRU_A 12 /* through A */
+#define SC5_THRU_B 7 /* through B (SMt 6.2) */
+#define SC7_WRAP_S 8 /* SAS */
+
+/*
+ * ECM states
+ */
+#define EC0_OUT 0
+#define EC1_IN 1
+#define EC2_TRACE 2
+#define EC3_LEAVE 3
+#define EC4_PATH_TEST 4
+#define EC5_INSERT 5
+#define EC6_CHECK 6
+#define EC7_DEINSERT 7
+
+/*
+ * RMT states
+ */
+#define RM0_ISOLATED 0
+#define RM1_NON_OP 1 /* not operational */
+#define RM2_RING_OP 2 /* ring operational */
+#define RM3_DETECT 3 /* detect dupl addresses */
+#define RM4_NON_OP_DUP 4 /* dupl. addr detected */
+#define RM5_RING_OP_DUP 5 /* ring oper. with dupl. addr */
+#define RM6_DIRECTED 6 /* sending directed beacons */
+#define RM7_TRACE 7 /* trace initiated */
+#endif
+
+struct pcm_state {
+ unsigned char pcm_type ; /* TA TB TS TM */
+ unsigned char pcm_state ; /* state PC[0-9]_* */
+ unsigned char pcm_mode ; /* PM_{NONE,PEER,TREE} */
+ unsigned char pcm_neighbor ; /* TA TB TS TM */
+ unsigned char pcm_bsf ; /* flag bs : TRUE/FALSE */
+ unsigned char pcm_lsf ; /* flag ls : TRUE/FALSE */
+ unsigned char pcm_lct_fail ; /* counter lct_fail */
+ unsigned char pcm_ls_rx ; /* rx line state */
+ short pcm_r_val ; /* signaling bits */
+ short pcm_t_val ; /* signaling bits */
+} ;
+
+struct smt_state {
+ struct pcm_state pcm_state[NUMPHYS] ; /* port A & port B */
+} ;
+
+#endif
+
diff --git a/drivers/net/skfp/h/supern_2.h b/drivers/net/skfp/h/supern_2.h
new file mode 100644
index 0000000..5ba0b83
--- /dev/null
+++ b/drivers/net/skfp/h/supern_2.h
@@ -0,0 +1,1059 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*
+ defines for AMD Supernet II chip set
+ the chips are refered to as
+ FPLUS Formac Plus
+ PLC Physical Layer
+
+ added defines for AMD Supernet III chip set
+ added comments on differences between Supernet II and Supernet III
+ added defines for the Motorola ELM (MOT_ELM)
+*/
+
+#ifndef _SUPERNET_
+#define _SUPERNET_
+
+/*
+ * Define Supernet 3 when used
+ */
+#ifdef PCI
+#ifndef SUPERNET_3
+#define SUPERNET_3
+#endif
+#define TAG
+#endif
+
+#define MB 0xff
+#define MW 0xffff
+#define MD 0xffffffff
+
+/*
+ * FORMAC frame status (rx_msext)
+ */
+#define FS_EI (1<<2)
+#define FS_AI (1<<1)
+#define FS_CI (1<<0)
+
+#define FS_MSVALID (1<<15) /* end of queue */
+#define FS_MSRABT (1<<14) /* frame was aborted during reception*/
+#define FS_SSRCRTG (1<<12) /* if SA has set MSB (source-routing)*/
+#define FS_SEAC2 (FS_EI<<9) /* error indicator */
+#define FS_SEAC1 (FS_AI<<9) /* address indicator */
+#define FS_SEAC0 (FS_CI<<9) /* copy indicator */
+#define FS_SFRMERR (1<<8) /* error detected (CRC or length) */
+#define FS_SADRRG (1<<7) /* address recognized */
+#define FS_SFRMTY2 (1<<6) /* frame-class bit */
+#define FS_SFRMTY1 (1<<5) /* frame-type bit (impementor) */
+#define FS_SFRMTY0 (1<<4) /* frame-type bit (LLC) */
+#define FS_ERFBB1 (1<<1) /* byte offset (depends on LSB bit) */
+#define FS_ERFBB0 (1<<0) /* - " - */
+
+/*
+ * status frame type
+ */
+#define FRM_SMT (0) /* asynchr. frames */
+#define FRM_LLCA (1)
+#define FRM_IMPA (2)
+#define FRM_MAC (4) /* synchr. frames */
+#define FRM_LLCS (5)
+#define FRM_IMPS (6)
+
+/*
+ * bits in rx_descr.i (receive frame status word)
+ */
+#define RX_MSVALID ((long)1<<31) /* memory status valid */
+#define RX_MSRABT ((long)1<<30) /* memory status receive abort */
+#define RX_FS_E ((long)FS_SEAC2<<16) /* error indicator */
+#define RX_FS_A ((long)FS_SEAC1<<16) /* address indicator */
+#define RX_FS_C ((long)FS_SEAC0<<16) /* copy indicator */
+#define RX_FS_CRC ((long)FS_SFRMERR<<16)/* error detected */
+#define RX_FS_ADDRESS ((long)FS_SADRRG<<16) /* address recognized */
+#define RX_FS_MAC ((long)FS_SFRMTY2<<16)/* MAC frame */
+#define RX_FS_SMT ((long)0<<16) /* SMT frame */
+#define RX_FS_IMPL ((long)FS_SFRMTY1<<16)/* implementer frame */
+#define RX_FS_LLC ((long)FS_SFRMTY0<<16)/* LLC frame */
+
+/*
+ * receive frame descriptor
+ */
+union rx_descr {
+ struct {
+#ifdef LITTLE_ENDIAN
+ unsigned rx_length :16 ; /* frame length lower/upper byte */
+ unsigned rx_erfbb :2 ; /* received frame byte boundary */
+ unsigned rx_reserv2:2 ; /* reserved */
+ unsigned rx_sfrmty :3 ; /* frame type bits */
+ unsigned rx_sadrrg :1 ; /* DA == MA or broad-/multicast */
+ unsigned rx_sfrmerr:1 ; /* received frame not valid */
+ unsigned rx_seac0 :1 ; /* frame-copied C-indicator */
+ unsigned rx_seac1 :1 ; /* address-match A-indicator */
+ unsigned rx_seac2 :1 ; /* frame-error E-indicator */
+ unsigned rx_ssrcrtg:1 ; /* == 1 SA has MSB set */
+ unsigned rx_reserv1:1 ; /* reserved */
+ unsigned rx_msrabt :1 ; /* memory status receive abort */
+ unsigned rx_msvalid:1 ; /* memory status valid */
+#else
+ unsigned rx_msvalid:1 ; /* memory status valid */
+ unsigned rx_msrabt :1 ; /* memory status receive abort */
+ unsigned rx_reserv1:1 ; /* reserved */
+ unsigned rx_ssrcrtg:1 ; /* == 1 SA has MSB set */
+ unsigned rx_seac2 :1 ; /* frame-error E-indicator */
+ unsigned rx_seac1 :1 ; /* address-match A-indicator */
+ unsigned rx_seac0 :1 ; /* frame-copied C-indicator */
+ unsigned rx_sfrmerr:1 ; /* received frame not valid */
+ unsigned rx_sadrrg :1 ; /* DA == MA or broad-/multicast */
+ unsigned rx_sfrmty :3 ; /* frame type bits */
+ unsigned rx_erfbb :2 ; /* received frame byte boundary */
+ unsigned rx_reserv2:2 ; /* reserved */
+ unsigned rx_length :16 ; /* frame length lower/upper byte */
+#endif
+ } r ;
+ long i ;
+} ;
+
+/* defines for Receive Frame Descriptor access */
+#define RD_S_ERFBB 0x00030000L /* received frame byte boundary */
+#define RD_S_RES2 0x000c0000L /* reserved */
+#define RD_S_SFRMTY 0x00700000L /* frame type bits */
+#define RD_S_SADRRG 0x00800000L /* DA == MA or broad-/multicast */
+#define RD_S_SFRMERR 0x01000000L /* received frame not valid */
+#define RD_S_SEAC 0x0e000000L /* frame status indicators */
+#define RD_S_SEAC0 0x02000000L /* frame-copied case-indicator */
+#define RD_S_SEAC1 0x04000000L /* address-match A-indicator */
+#define RD_S_SEAC2 0x08000000L /* frame-error E-indicator */
+#define RD_S_SSRCRTG 0x10000000L /* == 1 SA has MSB set */
+#define RD_S_RES1 0x20000000L /* reserved */
+#define RD_S_MSRABT 0x40000000L /* memory status receive abort */
+#define RD_S_MSVALID 0x80000000L /* memory status valid */
+
+#define RD_STATUS 0xffff0000L
+#define RD_LENGTH 0x0000ffffL
+
+/* defines for Receive Frames Status Word values */
+/*RD_S_SFRMTY*/
+#define RD_FRM_SMT (unsigned long)(0<<20) /* asynchr. frames */
+#define RD_FRM_LLCA (unsigned long)(1<<20)
+#define RD_FRM_IMPA (unsigned long)(2<<20)
+#define RD_FRM_MAC (unsigned long)(4<<20) /* synchr. frames */
+#define RD_FRM_LLCS (unsigned long)(5<<20)
+#define RD_FRM_IMPS (unsigned long)(6<<20)
+
+#define TX_DESCRIPTOR 0x40000000L
+#define TX_OFFSET_3 0x18000000L
+
+#define TXP1 2
+
+/*
+ * transmit frame descriptor
+ */
+union tx_descr {
+ struct {
+#ifdef LITTLE_ENDIAN
+ unsigned tx_length:16 ; /* frame length lower/upper byte */
+ unsigned tx_res :8 ; /* reserved (bit 16..23) */
+ unsigned tx_xmtabt:1 ; /* transmit abort */
+ unsigned tx_nfcs :1 ; /* no frame check sequence */
+ unsigned tx_xdone :1 ; /* give up token */
+ unsigned tx_rpxm :2 ; /* byte offset */
+ unsigned tx_pat1 :2 ; /* must be TXP1 */
+ unsigned tx_more :1 ; /* more frame in chain */
+#else
+ unsigned tx_more :1 ; /* more frame in chain */
+ unsigned tx_pat1 :2 ; /* must be TXP1 */
+ unsigned tx_rpxm :2 ; /* byte offset */
+ unsigned tx_xdone :1 ; /* give up token */
+ unsigned tx_nfcs :1 ; /* no frame check sequence */
+ unsigned tx_xmtabt:1 ; /* transmit abort */
+ unsigned tx_res :8 ; /* reserved (bit 16..23) */
+ unsigned tx_length:16 ; /* frame length lower/upper byte */
+#endif
+ } t ;
+ long i ;
+} ;
+
+/* defines for Transmit Descriptor access */
+#define TD_C_MORE 0x80000000L /* more frame in chain */
+#define TD_C_DESCR 0x60000000L /* must be TXP1 */
+#define TD_C_TXFBB 0x18000000L /* byte offset */
+#define TD_C_XDONE 0x04000000L /* give up token */
+#define TD_C_NFCS 0x02000000L /* no frame check sequence */
+#define TD_C_XMTABT 0x01000000L /* transmit abort */
+
+#define TD_C_LNCNU 0x0000ff00L
+#define TD_C_LNCNL 0x000000ffL
+#define TD_C_LNCN 0x0000ffffL /* frame length lower/upper byte */
+
+/*
+ * transmit pointer
+ */
+union tx_pointer {
+ struct t {
+#ifdef LITTLE_ENDIAN
+ unsigned tp_pointer:16 ; /* pointer to tx_descr (low/high) */
+ unsigned tp_res :8 ; /* reserved (bit 16..23) */
+ unsigned tp_pattern:8 ; /* fixed pattern (bit 24..31) */
+#else
+ unsigned tp_pattern:8 ; /* fixed pattern (bit 24..31) */
+ unsigned tp_res :8 ; /* reserved (bit 16..23) */
+ unsigned tp_pointer:16 ; /* pointer to tx_descr (low/high) */
+#endif
+ } t ;
+ long i ;
+} ;
+
+/* defines for Nontag Mode Pointer access */
+#define TD_P_CNTRL 0xff000000L
+#define TD_P_RPXU 0x0000ff00L
+#define TD_P_RPXL 0x000000ffL
+#define TD_P_RPX 0x0000ffffL
+
+
+#define TX_PATTERN 0xa0
+#define TX_POINTER_END 0xa0000000L
+#define TX_INT_PATTERN 0xa0000000L
+
+struct tx_queue {
+ struct tx_queue *tq_next ;
+ u_short tq_pack_offset ; /* offset buffer memory */
+ u_char tq_pad[2] ;
+} ;
+
+/*
+ defines for FORMAC Plus (Am79C830)
+*/
+
+/*
+ * FORMAC+ read/write (r/w) registers
+ */
+#define FM_CMDREG1 0x00 /* write command reg 1 instruction */
+#define FM_CMDREG2 0x01 /* write command reg 2 instruction */
+#define FM_ST1U 0x00 /* read upper 16-bit of status reg 1 */
+#define FM_ST1L 0x01 /* read lower 16-bit of status reg 1 */
+#define FM_ST2U 0x02 /* read upper 16-bit of status reg 2 */
+#define FM_ST2L 0x03 /* read lower 16-bit of status reg 2 */
+#define FM_IMSK1U 0x04 /* r/w upper 16-bit of IMSK 1 */
+#define FM_IMSK1L 0x05 /* r/w lower 16-bit of IMSK 1 */
+#define FM_IMSK2U 0x06 /* r/w upper 16-bit of IMSK 2 */
+#define FM_IMSK2L 0x07 /* r/w lower 16-bit of IMSK 2 */
+#define FM_SAID 0x08 /* r/w short addr.-individual */
+#define FM_LAIM 0x09 /* r/w long addr.-ind. (MSW of LAID) */
+#define FM_LAIC 0x0a /* r/w long addr.-ind. (middle)*/
+#define FM_LAIL 0x0b /* r/w long addr.-ind. (LSW) */
+#define FM_SAGP 0x0c /* r/w short address-group */
+#define FM_LAGM 0x0d /* r/w long addr.-gr. (MSW of LAGP) */
+#define FM_LAGC 0x0e /* r/w long addr.-gr. (middle) */
+#define FM_LAGL 0x0f /* r/w long addr.-gr. (LSW) */
+#define FM_MDREG1 0x10 /* r/w 16-bit mode reg 1 */
+#define FM_STMCHN 0x11 /* read state-machine reg */
+#define FM_MIR1 0x12 /* read upper 16-bit of MAC Info Reg */
+#define FM_MIR0 0x13 /* read lower 16-bit of MAC Info Reg */
+#define FM_TMAX 0x14 /* r/w 16-bit TMAX reg */
+#define FM_TVX 0x15 /* write 8-bit TVX reg with NP7-0
+ read TVX on NP7-0, timer on NP15-8*/
+#define FM_TRT 0x16 /* r/w upper 16-bit of TRT timer */
+#define FM_THT 0x17 /* r/w upper 16-bit of THT timer */
+#define FM_TNEG 0x18 /* read upper 16-bit of TNEG (TTRT) */
+#define FM_TMRS 0x19 /* read lower 5-bit of TNEG,TRT,THT */
+ /* F E D C B A 9 8 7 6 5 4 3 2 1 0
+ x |-TNEG4-0| |-TRT4-0-| |-THT4-0-| (x-late count) */
+#define FM_TREQ0 0x1a /* r/w 16-bit TREQ0 reg (LSW of TRT) */
+#define FM_TREQ1 0x1b /* r/w 16-bit TREQ1 reg (MSW of TRT) */
+#define FM_PRI0 0x1c /* r/w priority r. for asyn.-queue 0 */
+#define FM_PRI1 0x1d /* r/w priority r. for asyn.-queue 1 */
+#define FM_PRI2 0x1e /* r/w priority r. for asyn.-queue 2 */
+#define FM_TSYNC 0x1f /* r/w 16-bit of the TSYNC register */
+#define FM_MDREG2 0x20 /* r/w 16-bit mode reg 2 */
+#define FM_FRMTHR 0x21 /* r/w the frame threshold register */
+#define FM_EACB 0x22 /* r/w end addr of claim/beacon area */
+#define FM_EARV 0x23 /* r/w end addr of receive queue */
+/* Supernet 3 */
+#define FM_EARV1 FM_EARV
+
+#define FM_EAS 0x24 /* r/w end addr of synchr. queue */
+#define FM_EAA0 0x25 /* r/w end addr of asyn. queue 0 */
+#define FM_EAA1 0x26 /* r/w end addr of asyn. queue 1 */
+#define FM_EAA2 0x27 /* r/w end addr of asyn. queue 2 */
+#define FM_SACL 0x28 /* r/w start addr of claim frame */
+#define FM_SABC 0x29 /* r/w start addr of beacon frame */
+#define FM_WPXSF 0x2a /* r/w the write ptr. for special fr.*/
+#define FM_RPXSF 0x2b /* r/w the read ptr. for special fr. */
+#define FM_RPR 0x2d /* r/w the read ptr. for receive qu. */
+#define FM_WPR 0x2e /* r/w the write ptr. for receive qu.*/
+#define FM_SWPR 0x2f /* r/w the shadow wr.-ptr. for rec.q.*/
+/* Supernet 3 */
+#define FM_RPR1 FM_RPR
+#define FM_WPR1 FM_WPR
+#define FM_SWPR1 FM_SWPR
+
+#define FM_WPXS 0x30 /* r/w the write ptr. for synchr. qu.*/
+#define FM_WPXA0 0x31 /* r/w the write ptr. for asyn. qu.0 */
+#define FM_WPXA1 0x32 /* r/w the write ptr. for asyn. qu.1 */
+#define FM_WPXA2 0x33 /* r/w the write ptr. for asyn. qu.2 */
+#define FM_SWPXS 0x34 /* r/w the shadow wr.-ptr. for syn.q.*/
+#define FM_SWPXA0 0x35 /* r/w the shad. wr.-ptr. for asyn.q0*/
+#define FM_SWPXA1 0x36 /* r/w the shad. wr.-ptr. for asyn.q1*/
+#define FM_SWPXA2 0x37 /* r/w the shad. wr.-ptr. for asyn.q2*/
+#define FM_RPXS 0x38 /* r/w the read ptr. for synchr. qu. */
+#define FM_RPXA0 0x39 /* r/w the read ptr. for asyn. qu. 0 */
+#define FM_RPXA1 0x3a /* r/w the read ptr. for asyn. qu. 1 */
+#define FM_RPXA2 0x3b /* r/w the read ptr. for asyn. qu. 2 */
+#define FM_MARR 0x3c /* r/w the memory read addr register */
+#define FM_MARW 0x3d /* r/w the memory write addr register*/
+#define FM_MDRU 0x3e /* r/w upper 16-bit of mem. data reg */
+#define FM_MDRL 0x3f /* r/w lower 16-bit of mem. data reg */
+
+/* following instructions relate to MAC counters and timer */
+#define FM_TMSYNC 0x40 /* r/w upper 16 bits of TMSYNC timer */
+#define FM_FCNTR 0x41 /* r/w the 16-bit frame counter */
+#define FM_LCNTR 0x42 /* r/w the 16-bit lost counter */
+#define FM_ECNTR 0x43 /* r/w the 16-bit error counter */
+
+/* Supernet 3: extensions to old register block */
+#define FM_FSCNTR 0x44 /* r/? Frame Strip Counter */
+#define FM_FRSELREG 0x45 /* r/w Frame Selection Register */
+
+/* Supernet 3: extensions for 2. receive queue etc. */
+#define FM_MDREG3 0x60 /* r/w Mode Register 3 */
+#define FM_ST3U 0x61 /* read upper 16-bit of status reg 3 */
+#define FM_ST3L 0x62 /* read lower 16-bit of status reg 3 */
+#define FM_IMSK3U 0x63 /* r/w upper 16-bit of IMSK reg 3 */
+#define FM_IMSK3L 0x64 /* r/w lower 16-bit of IMSK reg 3 */
+#define FM_IVR 0x65 /* read Interrupt Vector register */
+#define FM_IMR 0x66 /* r/w Interrupt mask register */
+/* 0x67 Hidden */
+#define FM_RPR2 0x68 /* r/w the read ptr. for rec. qu. 2 */
+#define FM_WPR2 0x69 /* r/w the write ptr. for rec. qu. 2 */
+#define FM_SWPR2 0x6a /* r/w the shadow wptr. for rec. q. 2 */
+#define FM_EARV2 0x6b /* r/w end addr of rec. qu. 2 */
+#define FM_UNLCKDLY 0x6c /* r/w Auto Unlock Delay register */
+ /* Bit 15-8: RECV2 unlock threshold */
+ /* Bit 7-0: RECV1 unlock threshold */
+/* 0x6f-0x73 Hidden */
+#define FM_LTDPA1 0x79 /* r/w Last Trans desc ptr for A1 qu. */
+/* 0x80-0x9a PLCS registers of built-in PLCS (Supernet 3 only) */
+
+/* Supernet 3: Adderss Filter Registers */
+#define FM_AFCMD 0xb0 /* r/w Address Filter Command Reg */
+#define FM_AFSTAT 0xb2 /* r/w Address Filter Status Reg */
+#define FM_AFBIST 0xb4 /* r/w Address Filter BIST signature */
+#define FM_AFCOMP2 0xb6 /* r/w Address Filter Comparand 2 */
+#define FM_AFCOMP1 0xb8 /* r/w Address Filter Comparand 1 */
+#define FM_AFCOMP0 0xba /* r/w Address Filter Comparand 0 */
+#define FM_AFMASK2 0xbc /* r/w Address Filter Mask 2 */
+#define FM_AFMASK1 0xbe /* r/w Address Filter Mask 1 */
+#define FM_AFMASK0 0xc0 /* r/w Address Filter Mask 0 */
+#define FM_AFPERS 0xc2 /* r/w Address Filter Personality Reg */
+
+/* Supernet 3: Orion (PDX?) Registers */
+#define FM_ORBIST 0xd0 /* r/w Orion BIST signature */
+#define FM_ORSTAT 0xd2 /* r/w Orion Status Register */
+
+
+/*
+ * Mode Register 1 (MDREG1)
+ */
+#define FM_RES0 0x0001 /* reserved */
+ /* SN3: other definition */
+#define FM_XMTINH_HOLD 0x0002 /* transmit-inhibit/hold bit */
+ /* SN3: other definition */
+#define FM_HOFLXI 0x0003 /* SN3: Hold / Flush / Inhibit */
+#define FM_FULL_HALF 0x0004 /* full-duplex/half-duplex bit */
+#define FM_LOCKTX 0x0008 /* lock-transmit-asynchr.-queues bit */
+#define FM_EXGPA0 0x0010 /* extended-group-addressing bit 0 */
+#define FM_EXGPA1 0x0020 /* extended-group-addressing bit 1 */
+#define FM_DISCRY 0x0040 /* disable-carry bit */
+ /* SN3: reserved */
+#define FM_SELRA 0x0080 /* select input from PHY (1=RA,0=RB) */
+
+#define FM_ADDET 0x0700 /* address detection */
+#define FM_MDAMA (0<<8) /* address detection : DA = MA */
+#define FM_MDASAMA (1<<8) /* address detection : DA=MA||SA=MA */
+#define FM_MRNNSAFNMA (2<<8) /* rec. non-NSA frames DA=MA&&SA!=MA */
+#define FM_MRNNSAF (3<<8) /* rec. non-NSA frames DA = MA */
+#define FM_MDISRCV (4<<8) /* disable receive function */
+#define FM_MRES0 (5<<8) /* reserve */
+#define FM_MLIMPROM (6<<8) /* limited-promiscuous mode */
+#define FM_MPROMISCOUS (7<<8) /* address detection : promiscous */
+
+#define FM_SELSA 0x0800 /* select-short-address bit */
+
+#define FM_MMODE 0x7000 /* mode select */
+#define FM_MINIT (0<<12) /* initialize */
+#define FM_MMEMACT (1<<12) /* memory activate */
+#define FM_MONLINESP (2<<12) /* on-line special */
+#define FM_MONLINE (3<<12) /* on-line (FDDI operational mode) */
+#define FM_MILOOP (4<<12) /* internal loopback */
+#define FM_MRES1 (5<<12) /* reserved */
+#define FM_MRES2 (6<<12) /* reserved */
+#define FM_MELOOP (7<<12) /* external loopback */
+
+#define FM_SNGLFRM 0x8000 /* single-frame-receive mode */
+ /* SN3: reserved */
+
+#define MDR1INIT (FM_MINIT | FM_MDAMA)
+
+/*
+ * Mode Register 2 (MDREG2)
+ */
+#define FM_AFULL 0x000f /* 4-bit value (empty loc.in txqueue)*/
+#define FM_RCVERR 0x0010 /* rec.-errored-frames bit */
+#define FM_SYMCTL 0x0020 /* sysmbol-control bit */
+ /* SN3: reserved */
+#define FM_SYNPRQ 0x0040 /* synchron.-NP-DMA-request bit */
+#define FM_ENNPRQ 0x0080 /* enable-NP-DMA-request bit */
+#define FM_ENHSRQ 0x0100 /* enable-host-request bit */
+#define FM_RXFBB01 0x0600 /* rec. frame byte boundary bit0 & 1 */
+#define FM_LSB 0x0800 /* determ. ordering of bytes in buffer*/
+#define FM_PARITY 0x1000 /* 1 = even, 0 = odd */
+#define FM_CHKPAR 0x2000 /* 1 = parity of 32-bit buffer BD-bus*/
+#define FM_STRPFCS 0x4000 /* 1 = strips FCS field of rec.frame */
+#define FM_BMMODE 0x8000 /* Buffer-Memory-Mode (1 = tag mode) */
+ /* SN3: 1 = tag, 0 = modified tag */
+
+/*
+ * Status Register 1, Upper 16 Bits (ST1U)
+ */
+#define FM_STEFRMS 0x0001 /* transmit end of frame: synchr. qu.*/
+#define FM_STEFRMA0 0x0002 /* transmit end of frame: asyn. qu.0 */
+#define FM_STEFRMA1 0x0004 /* transmit end of frame: asyn. qu.1 */
+#define FM_STEFRMA2 0x0008 /* transmit end of frame: asyn. qu.2 */
+ /* SN3: reserved */
+#define FM_STECFRMS 0x0010 /* transmit end of chain of syn. qu. */
+ /* SN3: reserved */
+#define FM_STECFRMA0 0x0020 /* transmit end of chain of asyn. q0 */
+ /* SN3: reserved */
+#define FM_STECFRMA1 0x0040 /* transmit end of chain of asyn. q1 */
+ /* SN3: STECMDA1 */
+#define FM_STECMDA1 0x0040 /* SN3: 'no description' */
+#define FM_STECFRMA2 0x0080 /* transmit end of chain of asyn. q2 */
+ /* SN3: reserved */
+#define FM_STEXDONS 0x0100 /* transmit until XDONE in syn. qu. */
+#define FM_STBFLA 0x0200 /* asynchr.-queue trans. buffer full */
+#define FM_STBFLS 0x0400 /* synchr.-queue transm. buffer full */
+#define FM_STXABRS 0x0800 /* synchr. queue transmit-abort */
+#define FM_STXABRA0 0x1000 /* asynchr. queue 0 transmit-abort */
+#define FM_STXABRA1 0x2000 /* asynchr. queue 1 transmit-abort */
+#define FM_STXABRA2 0x4000 /* asynchr. queue 2 transmit-abort */
+ /* SN3: reserved */
+#define FM_SXMTABT 0x8000 /* transmit abort */
+
+/*
+ * Status Register 1, Lower 16 Bits (ST1L)
+ */
+#define FM_SQLCKS 0x0001 /* queue lock for synchr. queue */
+#define FM_SQLCKA0 0x0002 /* queue lock for asynchr. queue 0 */
+#define FM_SQLCKA1 0x0004 /* queue lock for asynchr. queue 1 */
+#define FM_SQLCKA2 0x0008 /* queue lock for asynchr. queue 2 */
+ /* SN3: reserved */
+#define FM_STXINFLS 0x0010 /* transmit instruction full: syn. */
+ /* SN3: reserved */
+#define FM_STXINFLA0 0x0020 /* transmit instruction full: asyn.0 */
+ /* SN3: reserved */
+#define FM_STXINFLA1 0x0040 /* transmit instruction full: asyn.1 */
+ /* SN3: reserved */
+#define FM_STXINFLA2 0x0080 /* transmit instruction full: asyn.2 */
+ /* SN3: reserved */
+#define FM_SPCEPDS 0x0100 /* parity/coding error: syn. queue */
+#define FM_SPCEPDA0 0x0200 /* parity/coding error: asyn. queue0 */
+#define FM_SPCEPDA1 0x0400 /* parity/coding error: asyn. queue1 */
+#define FM_SPCEPDA2 0x0800 /* parity/coding error: asyn. queue2 */
+ /* SN3: reserved */
+#define FM_STBURS 0x1000 /* transmit buffer underrun: syn. q. */
+#define FM_STBURA0 0x2000 /* transmit buffer underrun: asyn.0 */
+#define FM_STBURA1 0x4000 /* transmit buffer underrun: asyn.1 */
+#define FM_STBURA2 0x8000 /* transmit buffer underrun: asyn.2 */
+ /* SN3: reserved */
+
+/*
+ * Status Register 2, Upper 16 Bits (ST2U)
+ */
+#define FM_SOTRBEC 0x0001 /* other beacon received */
+#define FM_SMYBEC 0x0002 /* my beacon received */
+#define FM_SBEC 0x0004 /* beacon state entered */
+#define FM_SLOCLM 0x0008 /* low claim received */
+#define FM_SHICLM 0x0010 /* high claim received */
+#define FM_SMYCLM 0x0020 /* my claim received */
+#define FM_SCLM 0x0040 /* claim state entered */
+#define FM_SERRSF 0x0080 /* error in special frame */
+#define FM_SNFSLD 0x0100 /* NP and FORMAC+ simultaneous load */
+#define FM_SRFRCTOV 0x0200 /* receive frame counter overflow */
+ /* SN3: reserved */
+#define FM_SRCVFRM 0x0400 /* receive frame */
+ /* SN3: reserved */
+#define FM_SRCVOVR 0x0800 /* receive FIFO overflow */
+#define FM_SRBFL 0x1000 /* receive buffer full */
+#define FM_SRABT 0x2000 /* receive abort */
+#define FM_SRBMT 0x4000 /* receive buffer empty */
+#define FM_SRCOMP 0x8000 /* receive complete. Nontag mode */
+
+/*
+ * Status Register 2, Lower 16 Bits (ST2L)
+ * Attention: SN3 docu shows these bits the other way around
+ */
+#define FM_SRES0 0x0001 /* reserved */
+#define FM_SESTRIPTK 0x0001 /* SN3: 'no description' */
+#define FM_STRTEXR 0x0002 /* TRT expired in claim | beacon st. */
+#define FM_SDUPCLM 0x0004 /* duplicate claim received */
+#define FM_SSIFG 0x0008 /* short interframe gap */
+#define FM_SFRMCTR 0x0010 /* frame counter overflow */
+#define FM_SERRCTR 0x0020 /* error counter overflow */
+#define FM_SLSTCTR 0x0040 /* lost counter overflow */
+#define FM_SPHINV 0x0080 /* PHY invalid */
+#define FM_SADET 0x0100 /* address detect */
+#define FM_SMISFRM 0x0200 /* missed frame */
+#define FM_STRTEXP 0x0400 /* TRT expired and late count > 0 */
+#define FM_STVXEXP 0x0800 /* TVX expired */
+#define FM_STKISS 0x1000 /* token issued */
+#define FM_STKERR 0x2000 /* token error */
+#define FM_SMULTDA 0x4000 /* multiple destination address */
+#define FM_SRNGOP 0x8000 /* ring operational */
+
+/*
+ * Supernet 3:
+ * Status Register 3, Upper 16 Bits (ST3U)
+ */
+#define FM_SRQUNLCK1 0x0001 /* receive queue unlocked queue 1 */
+#define FM_SRQUNLCK2 0x0002 /* receive queue unlocked queue 2 */
+#define FM_SRPERRQ1 0x0004 /* receive parity error rx queue 1 */
+#define FM_SRPERRQ2 0x0008 /* receive parity error rx queue 2 */
+ /* Bit 4-10: reserved */
+#define FM_SRCVOVR2 0x0800 /* receive FIFO overfull rx queue 2 */
+#define FM_SRBFL2 0x1000 /* receive buffer full rx queue 2 */
+#define FM_SRABT2 0x2000 /* receive abort rx queue 2 */
+#define FM_SRBMT2 0x4000 /* receive buf empty rx queue 2 */
+#define FM_SRCOMP2 0x8000 /* receive comp rx queue 2 */
+
+/*
+ * Supernet 3:
+ * Status Register 3, Lower 16 Bits (ST3L)
+ */
+#define FM_AF_BIST_DONE 0x0001 /* Address Filter BIST is done */
+#define FM_PLC_BIST_DONE 0x0002 /* internal PLC Bist is done */
+#define FM_PDX_BIST_DONE 0x0004 /* PDX BIST is done */
+ /* Bit 3: reserved */
+#define FM_SICAMDAMAT 0x0010 /* Status internal CAM DA match */
+#define FM_SICAMDAXACT 0x0020 /* Status internal CAM DA exact match */
+#define FM_SICAMSAMAT 0x0040 /* Status internal CAM SA match */
+#define FM_SICAMSAXACT 0x0080 /* Status internal CAM SA exact match */
+
+/*
+ * MAC State-Machine Register FM_STMCHN
+ */
+#define FM_MDRTAG 0x0004 /* tag bit of long word read */
+#define FM_SNPPND 0x0008 /* r/w from buffer mem. is pending */
+#define FM_TXSTAT 0x0070 /* transmitter state machine state */
+#define FM_RCSTAT 0x0380 /* receiver state machine state */
+#define FM_TM01 0x0c00 /* indicate token mode */
+#define FM_SIM 0x1000 /* indicate send immediate-mode */
+#define FM_REV 0xe000 /* FORMAC Plus revision number */
+
+/*
+ * Supernet 3
+ * Mode Register 3
+ */
+#define FM_MENRS 0x0001 /* Ena enhanced rec status encoding */
+#define FM_MENXS 0x0002 /* Ena enhanced xmit status encoding */
+#define FM_MENXCT 0x0004 /* Ena EXACT/INEXACT matching */
+#define FM_MENAFULL 0x0008 /* Ena enh QCTRL encoding for AFULL */
+#define FM_MEIND 0x0030 /* Ena enh A,C indicator settings */
+#define FM_MENQCTRL 0x0040 /* Ena enh QCTRL encoding */
+#define FM_MENRQAUNLCK 0x0080 /* Ena rec q auto unlock */
+#define FM_MENDAS 0x0100 /* Ena DAS connections by cntr MUX */
+#define FM_MENPLCCST 0x0200 /* Ena Counter Segm test in PLC blck */
+#define FM_MENSGLINT 0x0400 /* Ena Vectored Interrupt reading */
+#define FM_MENDRCV 0x0800 /* Ena dual receive queue operation */
+#define FM_MENFCLOC 0x3000 /* Ena FC location within frm data */
+#define FM_MENTRCMD 0x4000 /* Ena ASYNC1 xmit only after command */
+#define FM_MENTDLPBK 0x8000 /* Ena TDAT to RDAT lkoopback */
+
+/*
+ * Supernet 3
+ * Frame Selection Register
+ */
+#define FM_RECV1 0x000f /* options for receive queue 1 */
+#define FM_RCV1_ALL (0<<0) /* receive all frames */
+#define FM_RCV1_LLC (1<<0) /* rec all LLC frames */
+#define FM_RCV1_SMT (2<<0) /* rec all SMT frames */
+#define FM_RCV1_NSMT (3<<0) /* rec non-SMT frames */
+#define FM_RCV1_IMP (4<<0) /* rec Implementor frames */
+#define FM_RCV1_MAC (5<<0) /* rec all MAC frames */
+#define FM_RCV1_SLLC (6<<0) /* rec all sync LLC frames */
+#define FM_RCV1_ALLC (7<<0) /* rec all async LLC frames */
+#define FM_RCV1_VOID (8<<0) /* rec all void frames */
+#define FM_RCV1_ALSMT (9<<0) /* rec all async LLC & SMT frames */
+#define FM_RECV2 0x00f0 /* options for receive queue 2 */
+#define FM_RCV2_ALL (0<<4) /* receive all other frames */
+#define FM_RCV2_LLC (1<<4) /* rec all LLC frames */
+#define FM_RCV2_SMT (2<<4) /* rec all SMT frames */
+#define FM_RCV2_NSMT (3<<4) /* rec non-SMT frames */
+#define FM_RCV2_IMP (4<<4) /* rec Implementor frames */
+#define FM_RCV2_MAC (5<<4) /* rec all MAC frames */
+#define FM_RCV2_SLLC (6<<4) /* rec all sync LLC frames */
+#define FM_RCV2_ALLC (7<<4) /* rec all async LLC frames */
+#define FM_RCV2_VOID (8<<4) /* rec all void frames */
+#define FM_RCV2_ALSMT (9<<4) /* rec all async LLC & SMT frames */
+#define FM_ENXMTADSWAP 0x4000 /* enh rec addr swap (phys -> can) */
+#define FM_ENRCVADSWAP 0x8000 /* enh tx addr swap (can -> phys) */
+
+/*
+ * Supernet 3:
+ * Address Filter Command Register (AFCMD)
+ */
+#define FM_INST 0x0007 /* Address Filter Operation */
+#define FM_IINV_CAM (0<<0) /* Invalidate CAM */
+#define FM_IWRITE_CAM (1<<0) /* Write CAM */
+#define FM_IREAD_CAM (2<<0) /* Read CAM */
+#define FM_IRUN_BIST (3<<0) /* Run BIST */
+#define FM_IFIND (4<<0) /* Find */
+#define FM_IINV (5<<0) /* Invalidate */
+#define FM_ISKIP (6<<0) /* Skip */
+#define FM_ICL_SKIP (7<<0) /* Clear all SKIP bits */
+
+/*
+ * Supernet 3:
+ * Address Filter Status Register (AFSTAT)
+ */
+ /* Bit 0-4: reserved */
+#define FM_REV_NO 0x00e0 /* Revision Number of Address Filter */
+#define FM_BIST_DONE 0x0100 /* BIST complete */
+#define FM_EMPTY 0x0200 /* CAM empty */
+#define FM_ERROR 0x0400 /* Error (improper operation) */
+#define FM_MULT 0x0800 /* Multiple Match */
+#define FM_EXACT 0x1000 /* Exact Match */
+#define FM_FOUND 0x2000 /* Comparand found in CAM */
+#define FM_FULL 0x4000 /* CAM full */
+#define FM_DONE 0x8000 /* DONE indicator */
+
+/*
+ * Supernet 3:
+ * BIST Signature Register (AFBIST)
+ */
+#define AF_BIST_SIGNAT 0x0553 /* Address Filter BIST Signature */
+
+/*
+ * Supernet 3:
+ * Personality Register (AFPERS)
+ */
+#define FM_VALID 0x0001 /* CAM Entry Valid */
+#define FM_DA 0x0002 /* Destination Address */
+#define FM_DAX 0x0004 /* Destination Address Exact */
+#define FM_SA 0x0008 /* Source Address */
+#define FM_SAX 0x0010 /* Source Address Exact */
+#define FM_SKIP 0x0020 /* Skip this entry */
+
+/*
+ * instruction set for command register 1 (NPADDR6-0 = 0x00)
+ */
+#define FM_IRESET 0x01 /* software reset */
+#define FM_IRMEMWI 0x02 /* load Memory Data Reg., inc MARR */
+#define FM_IRMEMWO 0x03 /* load MDR from buffer memory, n.i. */
+#define FM_IIL 0x04 /* idle/listen */
+#define FM_ICL 0x05 /* claim/listen */
+#define FM_IBL 0x06 /* beacon/listen */
+#define FM_ILTVX 0x07 /* load TVX timer from TVX reg */
+#define FM_INRTM 0x08 /* nonrestricted token mode */
+#define FM_IENTM 0x09 /* enter nonrestricted token mode */
+#define FM_IERTM 0x0a /* enter restricted token mode */
+#define FM_IRTM 0x0b /* restricted token mode */
+#define FM_ISURT 0x0c /* send unrestricted token */
+#define FM_ISRT 0x0d /* send restricted token */
+#define FM_ISIM 0x0e /* enter send-immediate mode */
+#define FM_IESIM 0x0f /* exit send-immediate mode */
+#define FM_ICLLS 0x11 /* clear synchronous queue lock */
+#define FM_ICLLA0 0x12 /* clear asynchronous queue 0 lock */
+#define FM_ICLLA1 0x14 /* clear asynchronous queue 1 lock */
+#define FM_ICLLA2 0x18 /* clear asynchronous queue 2 lock */
+ /* SN3: reserved */
+#define FM_ICLLR 0x20 /* clear receive queue (SN3:1) lock */
+#define FM_ICLLR2 0x21 /* SN3: clear receive queue 2 lock */
+#define FM_ITRXBUS 0x22 /* SN3: Tristate X-Bus (SAS only) */
+#define FM_IDRXBUS 0x23 /* SN3: drive X-Bus */
+#define FM_ICLLAL 0x3f /* clear all queue locks */
+
+/*
+ * instruction set for command register 2 (NPADDR6-0 = 0x01)
+ */
+#define FM_ITRS 0x01 /* transmit synchronous queue */
+ /* SN3: reserved */
+#define FM_ITRA0 0x02 /* transmit asynchronous queue 0 */
+ /* SN3: reserved */
+#define FM_ITRA1 0x04 /* transmit asynchronous queue 1 */
+ /* SN3: reserved */
+#define FM_ITRA2 0x08 /* transmit asynchronous queue 2 */
+ /* SN3: reserved */
+#define FM_IACTR 0x10 /* abort current transmit activity */
+#define FM_IRSTQ 0x20 /* reset transmit queues */
+#define FM_ISTTB 0x30 /* set tag bit */
+#define FM_IERSF 0x40 /* enable receive single frame */
+ /* SN3: reserved */
+#define FM_ITR 0x50 /* SN3: Transmit Command */
+
+
+/*
+ * defines for PLC (Am79C864)
+ */
+
+/*
+ * PLC read/write (r/w) registers
+ */
+#define PL_CNTRL_A 0x00 /* control register A (r/w) */
+#define PL_CNTRL_B 0x01 /* control register B (r/w) */
+#define PL_INTR_MASK 0x02 /* interrupt mask (r/w) */
+#define PL_XMIT_VECTOR 0x03 /* transmit vector register (r/w) */
+#define PL_VECTOR_LEN 0x04 /* transmit vector length (r/w) */
+#define PL_LE_THRESHOLD 0x05 /* link error event threshold (r/w) */
+#define PL_C_MIN 0x06 /* minimum connect state time (r/w) */
+#define PL_TL_MIN 0x07 /* min. line state transmit t. (r/w) */
+#define PL_TB_MIN 0x08 /* minimum break time (r/w) */
+#define PL_T_OUT 0x09 /* signal timeout (r/w) */
+#define PL_CNTRL_C 0x0a /* control register C (r/w) */
+#define PL_LC_LENGTH 0x0b /* link confidence test time (r/w) */
+#define PL_T_SCRUB 0x0c /* scrub time = MAC TVX (r/w) */
+#define PL_NS_MAX 0x0d /* max. noise time before break (r/w)*/
+#define PL_TPC_LOAD_V 0x0e /* TPC timer load value (write only) */
+#define PL_TNE_LOAD_V 0x0f /* TNE timer load value (write only) */
+#define PL_STATUS_A 0x10 /* status register A (read only) */
+#define PL_STATUS_B 0x11 /* status register B (read only) */
+#define PL_TPC 0x12 /* timer for PCM (ro) [20.48 us] */
+#define PL_TNE 0x13 /* time of noise event [0.32 us] */
+#define PL_CLK_DIV 0x14 /* TNE clock divider (read only) */
+#define PL_BIST_SIGNAT 0x15 /* built in self test signature (ro)*/
+#define PL_RCV_VECTOR 0x16 /* receive vector reg. (read only) */
+#define PL_INTR_EVENT 0x17 /* interrupt event reg. (read only) */
+#define PL_VIOL_SYM_CTR 0x18 /* violation symbol count. (read o) */
+#define PL_MIN_IDLE_CTR 0x19 /* minimum idle counter (read only) */
+#define PL_LINK_ERR_CTR 0x1a /* link error event ctr.(read only) */
+#ifdef MOT_ELM
+#define PL_T_FOT_ASS 0x1e /* FOTOFF Assert Timer */
+#define PL_T_FOT_DEASS 0x1f /* FOTOFF Deassert Timer */
+#endif /* MOT_ELM */
+
+#ifdef MOT_ELM
+/*
+ * Special Quad-Elm Registers.
+ * A Quad-ELM consists of for ELMs and these additional registers.
+ */
+#define QELM_XBAR_W 0x80 /* Crossbar Control ELM W */
+#define QELM_XBAR_X 0x81 /* Crossbar Control ELM X */
+#define QELM_XBAR_Y 0x82 /* Crossbar Control ELM Y */
+#define QELM_XBAR_Z 0x83 /* Crossbar Control ELM Z */
+#define QELM_XBAR_P 0x84 /* Crossbar Control Bus P */
+#define QELM_XBAR_S 0x85 /* Crossbar Control Bus S */
+#define QELM_XBAR_R 0x86 /* Crossbar Control Bus R */
+#define QELM_WR_XBAR 0x87 /* Write the Crossbar now (write) */
+#define QELM_CTR_W 0x88 /* Counter W */
+#define QELM_CTR_X 0x89 /* Counter X */
+#define QELM_CTR_Y 0x8a /* Counter Y */
+#define QELM_CTR_Z 0x8b /* Counter Z */
+#define QELM_INT_MASK 0x8c /* Interrupt mask register */
+#define QELM_INT_DATA 0x8d /* Interrupt data (event) register */
+#define QELM_ELMB 0x00 /* Elm base */
+#define QELM_ELM_SIZE 0x20 /* ELM size */
+#endif /* MOT_ELM */
+/*
+ * PLC control register A (PL_CNTRL_A: log. addr. 0x00)
+ * It is used for timer configuration, specification of PCM MAINT state option,
+ * counter interrupt frequency, PLC data path config. and Built In Self Test.
+ */
+#define PL_RUN_BIST 0x0001 /* begin running its Built In Self T.*/
+#define PL_RF_DISABLE 0x0002 /* disable the Repeat Filter state m.*/
+#define PL_SC_REM_LOOP 0x0004 /* remote loopback path */
+#define PL_SC_BYPASS 0x0008 /* by providing a physical bypass */
+#define PL_LM_LOC_LOOP 0x0010 /* loop path just after elastic buff.*/
+#define PL_EB_LOC_LOOP 0x0020 /* loop path just prior to PDT/PDR IF*/
+#define PL_FOT_OFF 0x0040 /* assertion of /FOTOFF pin of PLC */
+#define PL_LOOPBACK 0x0080 /* it cause the /LPBCK pin ass. low */
+#define PL_MINI_CTR_INT 0x0100 /* partially contr. when bit is ass. */
+#define PL_VSYM_CTR_INT 0x0200 /* controls when int bit is asserted */
+#define PL_ENA_PAR_CHK 0x0400 /* enable parity check */
+#define PL_REQ_SCRUB 0x0800 /* limited access to scrub capability*/
+#define PL_TPC_16BIT 0x1000 /* causes the TPC as a 16 bit timer */
+#define PL_TNE_16BIT 0x2000 /* causes the TNE as a 16 bit timer */
+#define PL_NOISE_TIMER 0x4000 /* allows the noise timing function */
+
+/*
+ * PLC control register B (PL_CNTRL_B: log. addr. 0x01)
+ * It contains signals and requeste to direct the process of PCM and it is also
+ * used to control the Line State Match interrupt.
+ */
+#define PL_PCM_CNTRL 0x0003 /* control PCM state machine */
+#define PL_PCM_NAF (0) /* state is not affected */
+#define PL_PCM_START (1) /* goes to the BREAK state */
+#define PL_PCM_TRACE (2) /* goes to the TRACE state */
+#define PL_PCM_STOP (3) /* goes to the OFF state */
+
+#define PL_MAINT 0x0004 /* if OFF state --> MAINT state */
+#define PL_LONG 0x0008 /* perf. a long Link Confid.Test(LCT)*/
+#define PL_PC_JOIN 0x0010 /* if NEXT state --> JOIN state */
+
+#define PL_PC_LOOP 0x0060 /* loopback used in the LCT */
+#define PL_NOLCT (0<<5) /* no LCT is performed */
+#define PL_TPDR (1<<5) /* PCM asserts transmit PDR */
+#define PL_TIDLE (2<<5) /* PCM asserts transmit idle */
+#define PL_RLBP (3<<5) /* trans. PDR & remote loopb. path */
+
+#define PL_CLASS_S 0x0080 /* signif. that single att. station */
+
+#define PL_MAINT_LS 0x0700 /* line state while in the MAINT st. */
+#define PL_M_QUI0 (0<<8) /* transmit QUIET line state */
+#define PL_M_IDLE (1<<8) /* transmit IDLE line state */
+#define PL_M_HALT (2<<8) /* transmit HALT line state */
+#define PL_M_MASTR (3<<8) /* transmit MASTER line state */
+#define PL_M_QUI1 (4<<8) /* transmit QUIET line state */
+#define PL_M_QUI2 (5<<8) /* transmit QUIET line state */
+#define PL_M_TPDR (6<<8) /* tr. PHY_DATA requ.-symbol is tr.ed*/
+#define PL_M_QUI3 (7<<8) /* transmit QUIET line state */
+
+#define PL_MATCH_LS 0x7800 /* line state to be comp. with curr.*/
+#define PL_I_ANY (0<<11) /* Int. on any change in *_LINE_ST */
+#define PL_I_IDLE (1<<11) /* Interrupt on IDLE line state */
+#define PL_I_HALT (2<<11) /* Interrupt on HALT line state */
+#define PL_I_MASTR (4<<11) /* Interrupt on MASTER line state */
+#define PL_I_QUIET (8<<11) /* Interrupt on QUIET line state */
+
+#define PL_CONFIG_CNTRL 0x8000 /* control over scrub, byp. & loopb.*/
+
+/*
+ * PLC control register C (PL_CNTRL_C: log. addr. 0x0a)
+ * It contains the scrambling control registers (PLC-S only)
+ */
+#define PL_C_CIPHER_ENABLE (1<<0) /* enable scrambler */
+#define PL_C_CIPHER_LPBCK (1<<1) /* loopback scrambler */
+#define PL_C_SDOFF_ENABLE (1<<6) /* enable SDOFF timer */
+#define PL_C_SDON_ENABLE (1<<7) /* enable SDON timer */
+#ifdef MOT_ELM
+#define PL_C_FOTOFF_CTRL (3<<2) /* FOTOFF timer control */
+#define PL_C_FOTOFF_TIM (0<<2) /* FOTOFF use timer for (de)-assert */
+#define PL_C_FOTOFF_INA (2<<2) /* FOTOFF forced inactive */
+#define PL_C_FOTOFF_ACT (3<<2) /* FOTOFF forced active */
+#define PL_C_FOTOFF_SRCE (1<<4) /* FOTOFF source is PCM state != OFF */
+#define PL_C_RXDATA_EN (1<<5) /* Rec scr data forced to 0 */
+#define PL_C_SDNRZEN (1<<8) /* Monitor rec descr. data for act */
+#else /* nMOT_ELM */
+#define PL_C_FOTOFF_CTRL (3<<8) /* FOTOFF timer control */
+#define PL_C_FOTOFF_0 (0<<8) /* timer off */
+#define PL_C_FOTOFF_30 (1<<8) /* 30uS */
+#define PL_C_FOTOFF_50 (2<<8) /* 50uS */
+#define PL_C_FOTOFF_NEVER (3<<8) /* never */
+#define PL_C_SDON_TIMER (3<<10) /* SDON timer control */
+#define PL_C_SDON_084 (0<<10) /* 0.84 uS */
+#define PL_C_SDON_132 (1<<10) /* 1.32 uS */
+#define PL_C_SDON_252 (2<<10) /* 2.52 uS */
+#define PL_C_SDON_512 (3<<10) /* 5.12 uS */
+#define PL_C_SOFF_TIMER (3<<12) /* SDOFF timer control */
+#define PL_C_SOFF_076 (0<<12) /* 0.76 uS */
+#define PL_C_SOFF_132 (1<<12) /* 1.32 uS */
+#define PL_C_SOFF_252 (2<<12) /* 2.52 uS */
+#define PL_C_SOFF_512 (3<<12) /* 5.12 uS */
+#define PL_C_TSEL (3<<14) /* scrambler path select */
+#endif /* nMOT_ELM */
+
+/*
+ * PLC status register A (PL_STATUS_A: log. addr. 0x10)
+ * It is used to report status information to the Node Processor about the
+ * Line State Machine (LSM).
+ */
+#ifdef MOT_ELM
+#define PLC_INT_MASK 0xc000 /* ELM integration bits in status A */
+#define PLC_INT_C 0x0000 /* ELM Revision Band C */
+#define PLC_INT_CAMEL 0x4000 /* ELM integrated into CAMEL */
+#define PLC_INT_QE 0x8000 /* ELM integrated into Quad ELM */
+#define PLC_REV_MASK 0x3800 /* revision bits in status A */
+#define PLC_REVISION_B 0x0000 /* rev bits for ELM Rev B */
+#define PLC_REVISION_QA 0x0800 /* rev bits for ELM core in QELM-A */
+#else /* nMOT_ELM */
+#define PLC_REV_MASK 0xf800 /* revision bits in status A */
+#define PLC_REVISION_A 0x0000 /* revision bits for PLC */
+#define PLC_REVISION_S 0xf800 /* revision bits for PLC-S */
+#define PLC_REV_SN3 0x7800 /* revision bits for PLC-S in IFCP */
+#endif /* nMOT_ELM */
+#define PL_SYM_PR_CTR 0x0007 /* contains the LSM symbol pair Ctr. */
+#define PL_UNKN_LINE_ST 0x0008 /* unknown line state bit from LSM */
+#define PL_LSM_STATE 0x0010 /* state bit of LSM */
+
+#define PL_LINE_ST 0x00e0 /* contains recogn. line state of LSM*/
+#define PL_L_NLS (0<<5) /* noise line state */
+#define PL_L_ALS (1<<5) /* activ line state */
+#define PL_L_UND (2<<5) /* undefined */
+#define PL_L_ILS4 (3<<5) /* idle l. s. (after 4 idle symbols) */
+#define PL_L_QLS (4<<5) /* quiet line state */
+#define PL_L_MLS (5<<5) /* master line state */
+#define PL_L_HLS (6<<5) /* halt line state */
+#define PL_L_ILS16 (7<<5) /* idle line state (after 16 idle s.)*/
+
+#define PL_PREV_LINE_ST 0x0300 /* value of previous line state */
+#define PL_P_QLS (0<<8) /* quiet line state */
+#define PL_P_MLS (1<<8) /* master line state */
+#define PL_P_HLS (2<<8) /* halt line state */
+#define PL_P_ILS16 (3<<8) /* idle line state (after 16 idle s.)*/
+
+#define PL_SIGNAL_DET 0x0400 /* 1=that signal detect is deasserted*/
+
+
+/*
+ * PLC status register B (PL_STATUS_B: log. addr. 0x11)
+ * It contains signals and status from the repeat filter and PCM state machine.
+ */
+#define PL_BREAK_REASON 0x0007 /* reason for PCM state mach.s to br.*/
+#define PL_B_NOT (0) /* PCM SM has not gone to BREAK state*/
+#define PL_B_PCS (1) /* PC_Start issued */
+#define PL_B_TPC (2) /* TPC timer expired after T_OUT */
+#define PL_B_TNE (3) /* TNE timer expired after NS_MAX */
+#define PL_B_QLS (4) /* quit line state detected */
+#define PL_B_ILS (5) /* idle line state detected */
+#define PL_B_HLS (6) /* halt line state detected */
+
+#define PL_TCF 0x0008 /* transmit code flag (start exec.) */
+#define PL_RCF 0x0010 /* receive code flag (start exec.) */
+#define PL_LSF 0x0020 /* line state flag (l.s. has been r.)*/
+#define PL_PCM_SIGNAL 0x0040 /* indic. that XMIT_VECTOR hb.written*/
+
+#define PL_PCM_STATE 0x0780 /* state bits of PCM state machine */
+#define PL_PC0 (0<<7) /* OFF - when /RST or PCM_CNTRL */
+#define PL_PC1 (1<<7) /* BREAK - entry point in start PCM*/
+#define PL_PC2 (2<<7) /* TRACE - to localize stuck Beacon*/
+#define PL_PC3 (3<<7) /* CONNECT - synchronize ends of conn*/
+#define PL_PC4 (4<<7) /* NEXT - to separate the signalng*/
+#define PL_PC5 (5<<7) /* SIGNAL - PCM trans/rec. bit infos*/
+#define PL_PC6 (6<<7) /* JOIN - 1. state to activ conn. */
+#define PL_PC7 (7<<7) /* VERIFY - 2. - " - (3. ACTIVE) */
+#define PL_PC8 (8<<7) /* ACTIVE - PHY has been incorporated*/
+#define PL_PC9 (9<<7) /* MAINT - for test purposes or so
+ that PCM op. completely in softw. */
+
+#define PL_PCI_SCRUB 0x0800 /* scrubbing function is being exec. */
+
+#define PL_PCI_STATE 0x3000 /* Physical Connect. Insertion SM */
+#define PL_CI_REMV (0<<12) /* REMOVED */
+#define PL_CI_ISCR (1<<12) /* INSERT_SCRUB */
+#define PL_CI_RSCR (2<<12) /* REMOVE_SCRUB */
+#define PL_CI_INS (3<<12) /* INSERTED */
+
+#define PL_RF_STATE 0xc000 /* state bit of repeate filter SM */
+#define PL_RF_REPT (0<<14) /* REPEAT */
+#define PL_RF_IDLE (1<<14) /* IDLE */
+#define PL_RF_HALT1 (2<<14) /* HALT1 */
+#define PL_RF_HALT2 (3<<14) /* HALT2 */
+
+
+/*
+ * PLC interrupt event register (PL_INTR_EVENT: log. addr. 0x17)
+ * It is read only and is clearde whenever it is read!
+ * It is used by the PLC to report events to the node processor.
+ */
+#define PL_PARITY_ERR 0x0001 /* p. error h.b.detected on TX9-0 inp*/
+#define PL_LS_MATCH 0x0002 /* l.s.== l.s. PLC_CNTRL_B's MATCH_LS*/
+#define PL_PCM_CODE 0x0004 /* transmit&receive | LCT complete */
+#define PL_TRACE_PROP 0x0008 /* master l.s. while PCM ACTIV|TRACE */
+#define PL_SELF_TEST 0x0010 /* QUIET|HALT while PCM in TRACE st. */
+#define PL_PCM_BREAK 0x0020 /* PCM has entered the BREAK state */
+#define PL_PCM_ENABLED 0x0040 /* asserted SC_JOIN, scrub. & ACTIV */
+#define PL_TPC_EXPIRED 0x0080 /* TPC timer reached zero */
+#define PL_TNE_EXPIRED 0x0100 /* TNE timer reached zero */
+#define PL_EBUF_ERR 0x0200 /* elastic buff. det. over-|underflow*/
+#define PL_PHYINV 0x0400 /* physical layer invalid signal */
+#define PL_VSYM_CTR 0x0800 /* violation symbol counter has incr.*/
+#define PL_MINI_CTR 0x1000 /* dep. on PLC_CNTRL_A's MINI_CTR_INT*/
+#define PL_LE_CTR 0x2000 /* link error event counter */
+#define PL_LSDO 0x4000 /* SDO input pin changed to a 1 */
+#define PL_NP_ERR 0x8000 /* NP has requested to r/w an inv. r.*/
+
+/*
+ * The PLC interrupt mask register (PL_INTR_MASK: log. addr. 0x02) constr. is
+ * equal PL_INTR_EVENT register.
+ * For each set bit, the setting of corresponding bit generate an int to NP.
+ */
+
+#ifdef MOT_ELM
+/*
+ * Quad ELM Crosbar Control register values (QELM_XBAR_?)
+ */
+#define QELM_XOUT_IDLE 0x0000 /* Idles/Passthrough */
+#define QELM_XOUT_P 0x0001 /* Output to: Bus P */
+#define QELM_XOUT_S 0x0002 /* Output to: Bus S */
+#define QELM_XOUT_R 0x0003 /* Output to: Bus R */
+#define QELM_XOUT_W 0x0004 /* Output to: ELM W */
+#define QELM_XOUT_X 0x0005 /* Output to: ELM X */
+#define QELM_XOUT_Y 0x0006 /* Output to: ELM Y */
+#define QELM_XOUT_Z 0x0007 /* Output to: ELM Z */
+
+/*
+ * Quad ELM Interrupt data and event registers.
+ */
+#define QELM_NP_ERR (1<<15) /* Node Processor Error */
+#define QELM_COUNT_Z (1<<7) /* Counter Z Interrupt */
+#define QELM_COUNT_Y (1<<6) /* Counter Y Interrupt */
+#define QELM_COUNT_X (1<<5) /* Counter X Interrupt */
+#define QELM_COUNT_W (1<<4) /* Counter W Interrupt */
+#define QELM_ELM_Z (1<<3) /* ELM Z Interrupt */
+#define QELM_ELM_Y (1<<2) /* ELM Y Interrupt */
+#define QELM_ELM_X (1<<1) /* ELM X Interrupt */
+#define QELM_ELM_W (1<<0) /* ELM W Interrupt */
+#endif /* MOT_ELM */
+/*
+ * PLC Timing Parameters
+ */
+#define TP_C_MIN 0xff9c /* 2 ms */
+#define TP_TL_MIN 0xfff0 /* 0.3 ms */
+#define TP_TB_MIN 0xff10 /* 5 ms */
+#define TP_T_OUT 0xd9db /* 200 ms */
+#define TP_LC_LENGTH 0xf676 /* 50 ms */
+#define TP_LC_LONGLN 0xa0a2 /* 500 ms */
+#define TP_T_SCRUB 0xff6d /* 3.5 ms */
+#define TP_NS_MAX 0xf021 /* 1.3 ms */
+
+/*
+ * BIST values
+ */
+#define PLC_BIST 0x6ecd /* BIST signature for PLC */
+#define PLCS_BIST 0x5b6b /* BIST signature for PLC-S */
+#define PLC_ELM_B_BIST 0x6ecd /* BIST signature of ELM Rev. B */
+#define PLC_ELM_D_BIST 0x5b6b /* BIST signature of ELM Rev. D */
+#define PLC_CAM_A_BIST 0x9e75 /* BIST signature of CAMEL Rev. A */
+#define PLC_CAM_B_BIST 0x5b6b /* BIST signature of CAMEL Rev. B */
+#define PLC_IFD_A_BIST 0x9e75 /* BIST signature of IFDDI Rev. A */
+#define PLC_IFD_B_BIST 0x5b6b /* BIST signature of IFDDI Rev. B */
+#define PLC_QELM_A_BIST 0x5b6b /* BIST signature of QELM Rev. A */
+
+/*
+ FDDI board recources
+ */
+
+/*
+ * request register array (log. addr: RQA_A + a<<1 {a=0..7}) write only.
+ * It specifies to FORMAC+ the type of buffer memory access the host requires.
+ */
+#define RQ_NOT 0 /* not request */
+#define RQ_RES 1 /* reserved */
+#define RQ_SFW 2 /* special frame write */
+#define RQ_RRQ 3 /* read request: receive queue */
+#define RQ_WSQ 4 /* write request: synchronous queue */
+#define RQ_WA0 5 /* write requ.: asynchronous queue 0 */
+#define RQ_WA1 6 /* write requ.: asynchronous queue 1 */
+#define RQ_WA2 7 /* write requ.: asynchronous queue 2 */
+
+#define SZ_LONG (sizeof(long))
+
+/*
+ * FDDI defaults
+ * NOTE : In the ANSI docs, times are specified in units of "symbol time".
+ * AMD chips use BCLK as unit. 1 BCKL == 2 symbols
+ */
+#define COMPLREF ((u_long)32*256*256) /* two's complement 21 bit */
+#define MSTOBCLK(x) ((u_long)(x)*12500L)
+#define MSTOTVX(x) (((u_long)(x)*1000L)/80/255)
+
+#endif /* _SUPERNET_ */
diff --git a/drivers/net/skfp/h/targethw.h b/drivers/net/skfp/h/targethw.h
new file mode 100644
index 0000000..22c4923
--- /dev/null
+++ b/drivers/net/skfp/h/targethw.h
@@ -0,0 +1,169 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+#ifndef _TARGETHW_
+#define _TARGETHW_
+
+ /*
+ * PCI Watermark definition
+ */
+#ifdef PCI
+#define RX_WATERMARK 24
+#define TX_WATERMARK 24
+#define SK_ML_ID_1 0x20
+#define SK_ML_ID_2 0x30
+#endif
+
+#include "h/skfbi.h"
+#ifndef TAG_MODE
+#include "h/fplus.h"
+#else
+#include "h/fplustm.h"
+#endif
+
+#ifndef HW_PTR
+#define HW_PTR void __iomem *
+#endif
+
+#ifdef MULT_OEM
+#define OI_STAT_LAST 0 /* end of OEM data base */
+#define OI_STAT_PRESENT 1 /* entry present but not empty */
+#define OI_STAT_VALID 2 /* holds valid ID, but is not active */
+#define OI_STAT_ACTIVE 3 /* holds valid ID, entry is active */
+ /* active = adapter is supported */
+
+/* Memory representation of IDs must match representation in adapter. */
+struct s_oem_ids {
+ u_char oi_status ; /* Stat: last, present, valid, active */
+ u_char oi_mark[5] ; /* "PID00" .. "PID07" .. */
+ u_char oi_id[4] ; /* id bytes, representation as */
+ /* defined by hardware, */
+#ifdef PCI
+ u_char oi_sub_id[4] ; /* sub id bytes, representation as */
+ /* defined by hardware, */
+#endif
+#ifdef ISA
+ u_char oi_logo_len ; /* the length of the adapter logo */
+ u_char oi_logo[6] ; /* the adapter logo */
+ u_char oi_reserved1 ;
+#endif /* ISA */
+} ;
+#endif /* MULT_OEM */
+
+
+struct s_smt_hw {
+ /*
+ * global
+ */
+ HW_PTR iop ; /* IO base address */
+ short dma ; /* DMA channel */
+ short irq ; /* IRQ level */
+ short eprom ; /* FLASH prom */
+#ifndef PCI
+ short DmaWriteExtraBytes ; /* add bytes for DMA write */
+#endif
+
+#ifndef SYNC
+ u_short n_a_send ; /* pending send requests */
+#endif
+
+#if (defined(EISA) || defined(MCA) || defined(PCI))
+ short slot ; /* slot number */
+ short max_slots ; /* maximum number of slots */
+#endif
+
+#if (defined(PCI) || defined(MCA))
+ short wdog_used ; /* TRUE if the watch dog is used */
+#endif
+
+#ifdef MCA
+ short slot_32 ; /* 32bit slot (1) or 16bit slot (0) */
+ short rev ; /* Board revision (FMx_REV). */
+ short VFullRead ; /* V_full value for DMA read */
+ short VFullWrite ; /* V_full value for DMA write */
+#endif
+
+#ifdef EISA
+ short led ; /* LED for FE card */
+
+ short dma_rmode ; /* read mode */
+ short dma_wmode ; /* write mode */
+ short dma_emode ; /* extend mode */
+
+ /* DMA controller channel dependent io addresses */
+ u_short dma_base_word_count ;
+ u_short dma_base_address ;
+ u_short dma_base_address_page ;
+#endif
+
+#ifdef PCI
+ u_short pci_handle ; /* handle to access the BIOS func */
+ u_long is_imask ; /* int maske for the int source reg */
+ u_long phys_mem_addr ; /* physical memory address */
+ u_short mc_dummy ; /* work around for MC compiler bug */
+ /*
+ * state of the hardware
+ */
+ u_short hw_state ; /* started or stopped */
+
+#define STARTED 1
+#define STOPPED 0
+
+ int hw_is_64bit ; /* does we have a 64 bit adapter */
+#endif
+
+#ifdef TAG_MODE
+ u_long pci_fix_value ; /* value parsed by PCIFIX */
+#endif
+
+ /*
+ * hwt.c
+ */
+ u_long t_start ; /* HWT start */
+ u_long t_stop ; /* HWT stop */
+ u_short timer_activ ; /* HWT timer active */
+
+ /*
+ * PIC
+ */
+ u_char pic_a1 ;
+ u_char pic_21 ;
+
+ /*
+ * GENERIC ; do not modify beyond this line
+ */
+
+ /*
+ * physical and canonical address
+ */
+ struct fddi_addr fddi_home_addr ;
+ struct fddi_addr fddi_canon_addr ;
+ struct fddi_addr fddi_phys_addr ;
+
+ /*
+ * mac variables
+ */
+ struct mac_parameter mac_pa ; /* tmin, tmax, tvx, treq .. */
+ struct mac_counter mac_ct ; /* recv., lost, error */
+ u_short mac_ring_is_up ; /* ring is up flag */
+
+ struct s_smt_fp fp ; /* formac+ */
+
+#ifdef MULT_OEM
+ struct s_oem_ids *oem_id ; /* pointer to selected id */
+ int oem_min_status ; /* IDs to take care of */
+#endif /* MULT_OEM */
+
+} ;
+#endif
diff --git a/drivers/net/skfp/h/targetos.h b/drivers/net/skfp/h/targetos.h
new file mode 100644
index 0000000..5d940e7
--- /dev/null
+++ b/drivers/net/skfp/h/targetos.h
@@ -0,0 +1,165 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+/*
+ * Operating system specific definitions for driver and
+ * hardware module.
+ */
+
+#ifndef TARGETOS_H
+#define TARGETOS_H
+
+
+//-------- those should go into include/linux/pci.h
+#define PCI_VENDOR_ID_SK 0x1148
+#define PCI_DEVICE_ID_SK_FP 0x4000
+//--------
+
+
+
+//-------- those should go into include/linux/if_fddi.h
+#define FDDI_MAC_HDR_LEN 13
+
+#define FDDI_RII 0x01 /* routing information bit */
+#define FDDI_RCF_DIR_BIT 0x80
+#define FDDI_RCF_LEN_MASK 0x1f
+#define FDDI_RCF_BROADCAST 0x8000
+#define FDDI_RCF_LIMITED_BROADCAST 0xA000
+#define FDDI_RCF_FRAME2K 0x20
+#define FDDI_RCF_FRAME4K 0x30
+//--------
+
+
+#undef ADDR
+
+#include <asm/io.h>
+#include <linux/netdevice.h>
+#include <linux/fddidevice.h>
+#include <linux/skbuff.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+
+// is redefined by linux, but we need our definition
+#undef ADDR
+#ifdef MEM_MAPPED_IO
+#define ADDR(a) (smc->hw.iop+(a))
+#else
+#define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), (smc->hw.iop+( ((a)&0x7F) | ((a)>>7 ? 0x80:0)) )) : (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
+#endif
+
+#include "h/hwmtm.h"
+
+#define TRUE 1
+#define FALSE 0
+
+// HWM Definitions
+// -----------------------
+#define FDDI_TRACE(string, arg1, arg2, arg3) // Performance analysis.
+#ifdef PCI
+#define NDD_TRACE(string, arg1, arg2, arg3) // Performance analysis.
+#endif // PCI
+#define SMT_PAGESIZE PAGE_SIZE // Size of a memory page (power of 2).
+// -----------------------
+
+
+// SMT Definitions
+// -----------------------
+#define TICKS_PER_SECOND HZ
+#define SMC_VERSION 1
+// -----------------------
+
+
+// OS-Driver Definitions
+// -----------------------
+#define NO_ADDRESS 0xffe0 /* No Device (I/O) Address */
+#define SKFP_MAX_NUM_BOARDS 8 /* maximum number of PCI boards */
+
+#define SK_BUS_TYPE_PCI 0
+#define SK_BUS_TYPE_EISA 1
+
+#define FP_IO_LEN 256 /* length of IO area used */
+
+#define u8 unsigned char
+#define u16 unsigned short
+#define u32 unsigned int
+
+#define MAX_TX_QUEUE_LEN 20 // number of packets queued by driver
+#define MAX_FRAME_SIZE 4550
+
+#define RX_LOW_WATERMARK NUM_RECEIVE_BUFFERS / 2
+#define TX_LOW_WATERMARK NUM_TRANSMIT_BUFFERS - 2
+
+/*
+** Include the IOCTL stuff
+*/
+#include <linux/sockios.h>
+
+#define SKFPIOCTL SIOCDEVPRIVATE
+
+struct s_skfp_ioctl {
+ unsigned short cmd; /* Command to run */
+ unsigned short len; /* Length of the data buffer */
+ unsigned char __user *data; /* Pointer to the data buffer */
+};
+
+/*
+** Recognised ioctl commands for the driver
+*/
+#define SKFP_GET_STATS 0x05 /* Get the driver statistics */
+#define SKFP_CLR_STATS 0x06 /* Zero out the driver statistics */
+
+// The per-adapter driver structure
+struct s_smt_os {
+ struct net_device *dev;
+ struct net_device *next_module;
+ u32 bus_type; /* bus type (0 == PCI, 1 == EISA) */
+ struct pci_dev pdev; /* PCI device structure */
+
+ unsigned long base_addr;
+ unsigned char factory_mac_addr[8];
+ ulong SharedMemSize;
+ ulong SharedMemHeap;
+ void* SharedMemAddr;
+ dma_addr_t SharedMemDMA;
+
+ ulong QueueSkb;
+ struct sk_buff_head SendSkbQueue;
+
+ ulong MaxFrameSize;
+ u8 ResetRequested;
+
+ // MAC statistics structure
+ struct fddi_statistics MacStat;
+
+ // receive into this local buffer if no skb available
+ // data will be not valid, because multiple RxDs can
+ // point here at the same time, it must be at least
+ // MAX_FRAME_SIZE bytes in size
+ unsigned char *LocalRxBuffer;
+ dma_addr_t LocalRxBufferDMA;
+
+ // Version (required by SMT module).
+ u_long smc_version ;
+
+ // Required by Hardware Module (HWM).
+ struct hw_modul hwm ;
+
+ // For SMP-savety
+ spinlock_t DriverLock;
+
+};
+
+typedef struct s_smt_os skfddi_priv;
+
+#endif // _TARGETOS_
diff --git a/drivers/net/skfp/h/types.h b/drivers/net/skfp/h/types.h
new file mode 100644
index 0000000..5a3bf83
--- /dev/null
+++ b/drivers/net/skfp/h/types.h
@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * (C)Copyright 1998,1999 SysKonnect,
+ * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * The information in this file is provided "AS IS" without warranty.
+ *
+ ******************************************************************************/
+
+#include <linux/types.h>
+/*
+ ----------------------
+ Basic SMT system types
+ ----------------------
+*/
+#ifndef _TYPES_
+#define _TYPES_
+
+#define _packed
+#ifndef far
+#define far
+#endif
+#ifndef _far
+#define _far
+#endif
+
+#define inp(p) ioread8(p)
+#define inpw(p) ioread16(p)
+#define inpd(p) ioread32(p)
+#define outp(p,c) iowrite8(c,p)
+#define outpw(p,s) iowrite16(s,p)
+#define outpd(p,l) iowrite32(l,p)
+
+#endif /* _TYPES_ */