)]}'
{
  "commit": "9f8fcf38e8928cccf8c7b32668d146e457f2ccf2",
  "tree": "b29696373225a93876e7b5ec64bcd51bbf75ee98",
  "parents": [
    "679262578ba975037901556b2ddc6b17a77cf671"
  ],
  "author": {
    "name": "Chris Zankel",
    "email": "chris@zankel.net",
    "time": "Fri Jan 18 16:15:29 2008 -0800"
  },
  "committer": {
    "name": "Chris Zankel",
    "email": "chris@zankel.net",
    "time": "Wed Feb 13 17:43:26 2008 -0800"
  },
  "message": "[XTENSA] Fix cache flush macro for D$/I$ aliasing/non-aliasing\n\nFor configurations that have aliasing in the data cache but\nnot in the instruction cache, we don\u0027t need to flush the\ninstruction cache. Thus, we didn\u0027t define the macros to\nflush the instruction cache. Some cache-flush functions,\nhowerver, were using those macros.\n\nSigned-off-by: Chris Zankel \u003cchris@zankel.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b773c57e75a525c344a892855d8b04a6df14473b",
      "old_mode": 33188,
      "old_path": "include/asm-xtensa/cacheflush.h",
      "new_id": "94c4c53a099eb81cf2c4dbf2292131fb8c746014",
      "new_mode": 33188,
      "new_path": "include/asm-xtensa/cacheflush.h"
    }
  ]
}