)]}'
{
  "commit": "c658eac628aa8df040dfe614556d95e6da3a9ffb",
  "tree": "e2211e1d5c894c29e92d4c744f504b38410efe41",
  "parents": [
    "71d28e6c285548106f551fde13ca6d589433d843"
  ],
  "author": {
    "name": "Chris Zankel",
    "email": "chris@zankel.net",
    "time": "Tue Feb 12 13:17:07 2008 -0800"
  },
  "committer": {
    "name": "Chris Zankel",
    "email": "chris@zankel.net",
    "time": "Wed Feb 13 17:41:43 2008 -0800"
  },
  "message": "[XTENSA] Add support for configurable registers and coprocessors\n\nThe Xtensa architecture allows to define custom instructions and\nregisters. Registers that are bound to a coprocessor are only\naccessible if the corresponding enable bit is set, which allows\nto implement a \u0027lazy\u0027 context switch mechanism. Other registers\nneeds to be saved and restore at the time of the context switch\nor during interrupt handling.\n\nThis patch adds support for these additional states:\n\n- save and restore registers that are used by the compiler upon\n  interrupt entry and exit.\n- context switch additional registers unbound to any coprocessor\n- \u0027lazy\u0027 context switch of registers bound to a coprocessor\n- ptrace interface to provide access to additional registers\n- update configuration files in include/asm-xtensa/variant-fsf\n\nSigned-off-by: Chris Zankel \u003cchris@zankel.net\u003e\n",
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