Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/i386/nmi.c |
| 3 | * |
| 4 | * NMI watchdog support on APIC systems |
| 5 | * |
| 6 | * Started by Ingo Molnar <mingo@redhat.com> |
| 7 | * |
| 8 | * Fixes: |
| 9 | * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog. |
| 10 | * Mikael Pettersson : Power Management for local APIC NMI watchdog. |
| 11 | * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog. |
| 12 | * Pavel Machek and |
| 13 | * Mikael Pettersson : PM converted to driver model. Disable/enable API. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/config.h> |
| 17 | #include <linux/mm.h> |
| 18 | #include <linux/irq.h> |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/bootmem.h> |
| 21 | #include <linux/smp_lock.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/mc146818rtc.h> |
| 24 | #include <linux/kernel_stat.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/nmi.h> |
| 27 | #include <linux/sysdev.h> |
| 28 | #include <linux/sysctl.h> |
| 29 | |
| 30 | #include <asm/smp.h> |
| 31 | #include <asm/mtrr.h> |
| 32 | #include <asm/mpspec.h> |
| 33 | #include <asm/nmi.h> |
| 34 | |
| 35 | #include "mach_traps.h" |
| 36 | |
| 37 | unsigned int nmi_watchdog = NMI_NONE; |
| 38 | extern int unknown_nmi_panic; |
| 39 | static unsigned int nmi_hz = HZ; |
| 40 | static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */ |
| 41 | static unsigned int nmi_p4_cccr_val; |
| 42 | extern void show_registers(struct pt_regs *regs); |
| 43 | |
| 44 | /* |
| 45 | * lapic_nmi_owner tracks the ownership of the lapic NMI hardware: |
| 46 | * - it may be reserved by some other driver, or not |
| 47 | * - when not reserved by some other driver, it may be used for |
| 48 | * the NMI watchdog, or not |
| 49 | * |
| 50 | * This is maintained separately from nmi_active because the NMI |
| 51 | * watchdog may also be driven from the I/O APIC timer. |
| 52 | */ |
| 53 | static DEFINE_SPINLOCK(lapic_nmi_owner_lock); |
| 54 | static unsigned int lapic_nmi_owner; |
| 55 | #define LAPIC_NMI_WATCHDOG (1<<0) |
| 56 | #define LAPIC_NMI_RESERVED (1<<1) |
| 57 | |
| 58 | /* nmi_active: |
| 59 | * +1: the lapic NMI watchdog is active, but can be disabled |
| 60 | * 0: the lapic NMI watchdog has not been set up, and cannot |
| 61 | * be enabled |
| 62 | * -1: the lapic NMI watchdog is disabled, but can be enabled |
| 63 | */ |
| 64 | int nmi_active; |
| 65 | |
| 66 | #define K7_EVNTSEL_ENABLE (1 << 22) |
| 67 | #define K7_EVNTSEL_INT (1 << 20) |
| 68 | #define K7_EVNTSEL_OS (1 << 17) |
| 69 | #define K7_EVNTSEL_USR (1 << 16) |
| 70 | #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76 |
| 71 | #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING |
| 72 | |
| 73 | #define P6_EVNTSEL0_ENABLE (1 << 22) |
| 74 | #define P6_EVNTSEL_INT (1 << 20) |
| 75 | #define P6_EVNTSEL_OS (1 << 17) |
| 76 | #define P6_EVNTSEL_USR (1 << 16) |
| 77 | #define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79 |
| 78 | #define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED |
| 79 | |
| 80 | #define MSR_P4_MISC_ENABLE 0x1A0 |
| 81 | #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7) |
| 82 | #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12) |
| 83 | #define MSR_P4_PERFCTR0 0x300 |
| 84 | #define MSR_P4_CCCR0 0x360 |
| 85 | #define P4_ESCR_EVENT_SELECT(N) ((N)<<25) |
| 86 | #define P4_ESCR_OS (1<<3) |
| 87 | #define P4_ESCR_USR (1<<2) |
| 88 | #define P4_CCCR_OVF_PMI0 (1<<26) |
| 89 | #define P4_CCCR_OVF_PMI1 (1<<27) |
| 90 | #define P4_CCCR_THRESHOLD(N) ((N)<<20) |
| 91 | #define P4_CCCR_COMPLEMENT (1<<19) |
| 92 | #define P4_CCCR_COMPARE (1<<18) |
| 93 | #define P4_CCCR_REQUIRED (3<<16) |
| 94 | #define P4_CCCR_ESCR_SELECT(N) ((N)<<13) |
| 95 | #define P4_CCCR_ENABLE (1<<12) |
| 96 | /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter |
| 97 | CRU_ESCR0 (with any non-null event selector) through a complemented |
| 98 | max threshold. [IA32-Vol3, Section 14.9.9] */ |
| 99 | #define MSR_P4_IQ_COUNTER0 0x30C |
| 100 | #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR) |
| 101 | #define P4_NMI_IQ_CCCR0 \ |
| 102 | (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \ |
| 103 | P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE) |
| 104 | |
Jack F Vogel | 67701ae | 2005-05-01 08:58:48 -0700 | [diff] [blame] | 105 | static int __init check_nmi_watchdog(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | { |
| 107 | unsigned int prev_nmi_count[NR_CPUS]; |
| 108 | int cpu; |
| 109 | |
Jack F Vogel | 67701ae | 2005-05-01 08:58:48 -0700 | [diff] [blame] | 110 | if (nmi_watchdog == NMI_NONE) |
| 111 | return 0; |
| 112 | |
| 113 | printk(KERN_INFO "Testing NMI watchdog ... "); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | |
| 115 | for (cpu = 0; cpu < NR_CPUS; cpu++) |
| 116 | prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count; |
| 117 | local_irq_enable(); |
| 118 | mdelay((10*1000)/nmi_hz); // wait 10 ticks |
| 119 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
| 121 | #ifdef CONFIG_SMP |
| 122 | /* Check cpu_callin_map here because that is set |
| 123 | after the timer is started. */ |
| 124 | if (!cpu_isset(cpu, cpu_callin_map)) |
| 125 | continue; |
| 126 | #endif |
| 127 | if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) { |
| 128 | printk("CPU#%d: NMI appears to be stuck!\n", cpu); |
| 129 | nmi_active = 0; |
| 130 | lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG; |
| 131 | return -1; |
| 132 | } |
| 133 | } |
| 134 | printk("OK.\n"); |
| 135 | |
| 136 | /* now that we know it works we can reduce NMI frequency to |
| 137 | something more reasonable; makes a difference in some configs */ |
| 138 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 139 | nmi_hz = 1; |
| 140 | |
| 141 | return 0; |
| 142 | } |
Jack F Vogel | 67701ae | 2005-05-01 08:58:48 -0700 | [diff] [blame] | 143 | /* This needs to happen later in boot so counters are working */ |
| 144 | late_initcall(check_nmi_watchdog); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 145 | |
| 146 | static int __init setup_nmi_watchdog(char *str) |
| 147 | { |
| 148 | int nmi; |
| 149 | |
| 150 | get_option(&str, &nmi); |
| 151 | |
| 152 | if (nmi >= NMI_INVALID) |
| 153 | return 0; |
| 154 | if (nmi == NMI_NONE) |
| 155 | nmi_watchdog = nmi; |
| 156 | /* |
| 157 | * If any other x86 CPU has a local APIC, then |
| 158 | * please test the NMI stuff there and send me the |
| 159 | * missing bits. Right now Intel P6/P4 and AMD K7 only. |
| 160 | */ |
| 161 | if ((nmi == NMI_LOCAL_APIC) && |
| 162 | (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && |
| 163 | (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15)) |
| 164 | nmi_watchdog = nmi; |
| 165 | if ((nmi == NMI_LOCAL_APIC) && |
| 166 | (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && |
| 167 | (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15)) |
| 168 | nmi_watchdog = nmi; |
| 169 | /* |
| 170 | * We can enable the IO-APIC watchdog |
| 171 | * unconditionally. |
| 172 | */ |
| 173 | if (nmi == NMI_IO_APIC) { |
| 174 | nmi_active = 1; |
| 175 | nmi_watchdog = nmi; |
| 176 | } |
| 177 | return 1; |
| 178 | } |
| 179 | |
| 180 | __setup("nmi_watchdog=", setup_nmi_watchdog); |
| 181 | |
| 182 | static void disable_lapic_nmi_watchdog(void) |
| 183 | { |
| 184 | if (nmi_active <= 0) |
| 185 | return; |
| 186 | switch (boot_cpu_data.x86_vendor) { |
| 187 | case X86_VENDOR_AMD: |
| 188 | wrmsr(MSR_K7_EVNTSEL0, 0, 0); |
| 189 | break; |
| 190 | case X86_VENDOR_INTEL: |
| 191 | switch (boot_cpu_data.x86) { |
| 192 | case 6: |
| 193 | if (boot_cpu_data.x86_model > 0xd) |
| 194 | break; |
| 195 | |
| 196 | wrmsr(MSR_P6_EVNTSEL0, 0, 0); |
| 197 | break; |
| 198 | case 15: |
| 199 | if (boot_cpu_data.x86_model > 0x3) |
| 200 | break; |
| 201 | |
| 202 | wrmsr(MSR_P4_IQ_CCCR0, 0, 0); |
| 203 | wrmsr(MSR_P4_CRU_ESCR0, 0, 0); |
| 204 | break; |
| 205 | } |
| 206 | break; |
| 207 | } |
| 208 | nmi_active = -1; |
| 209 | /* tell do_nmi() and others that we're not active any more */ |
| 210 | nmi_watchdog = 0; |
| 211 | } |
| 212 | |
| 213 | static void enable_lapic_nmi_watchdog(void) |
| 214 | { |
| 215 | if (nmi_active < 0) { |
| 216 | nmi_watchdog = NMI_LOCAL_APIC; |
| 217 | setup_apic_nmi_watchdog(); |
| 218 | } |
| 219 | } |
| 220 | |
| 221 | int reserve_lapic_nmi(void) |
| 222 | { |
| 223 | unsigned int old_owner; |
| 224 | |
| 225 | spin_lock(&lapic_nmi_owner_lock); |
| 226 | old_owner = lapic_nmi_owner; |
| 227 | lapic_nmi_owner |= LAPIC_NMI_RESERVED; |
| 228 | spin_unlock(&lapic_nmi_owner_lock); |
| 229 | if (old_owner & LAPIC_NMI_RESERVED) |
| 230 | return -EBUSY; |
| 231 | if (old_owner & LAPIC_NMI_WATCHDOG) |
| 232 | disable_lapic_nmi_watchdog(); |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | void release_lapic_nmi(void) |
| 237 | { |
| 238 | unsigned int new_owner; |
| 239 | |
| 240 | spin_lock(&lapic_nmi_owner_lock); |
| 241 | new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED; |
| 242 | lapic_nmi_owner = new_owner; |
| 243 | spin_unlock(&lapic_nmi_owner_lock); |
| 244 | if (new_owner & LAPIC_NMI_WATCHDOG) |
| 245 | enable_lapic_nmi_watchdog(); |
| 246 | } |
| 247 | |
| 248 | void disable_timer_nmi_watchdog(void) |
| 249 | { |
| 250 | if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0)) |
| 251 | return; |
| 252 | |
| 253 | unset_nmi_callback(); |
| 254 | nmi_active = -1; |
| 255 | nmi_watchdog = NMI_NONE; |
| 256 | } |
| 257 | |
| 258 | void enable_timer_nmi_watchdog(void) |
| 259 | { |
| 260 | if (nmi_active < 0) { |
| 261 | nmi_watchdog = NMI_IO_APIC; |
| 262 | touch_nmi_watchdog(); |
| 263 | nmi_active = 1; |
| 264 | } |
| 265 | } |
| 266 | |
| 267 | #ifdef CONFIG_PM |
| 268 | |
| 269 | static int nmi_pm_active; /* nmi_active before suspend */ |
| 270 | |
Pavel Machek | 438510f | 2005-04-16 15:25:24 -0700 | [diff] [blame] | 271 | static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | { |
| 273 | nmi_pm_active = nmi_active; |
| 274 | disable_lapic_nmi_watchdog(); |
| 275 | return 0; |
| 276 | } |
| 277 | |
| 278 | static int lapic_nmi_resume(struct sys_device *dev) |
| 279 | { |
| 280 | if (nmi_pm_active > 0) |
| 281 | enable_lapic_nmi_watchdog(); |
| 282 | return 0; |
| 283 | } |
| 284 | |
| 285 | |
| 286 | static struct sysdev_class nmi_sysclass = { |
| 287 | set_kset_name("lapic_nmi"), |
| 288 | .resume = lapic_nmi_resume, |
| 289 | .suspend = lapic_nmi_suspend, |
| 290 | }; |
| 291 | |
| 292 | static struct sys_device device_lapic_nmi = { |
| 293 | .id = 0, |
| 294 | .cls = &nmi_sysclass, |
| 295 | }; |
| 296 | |
| 297 | static int __init init_lapic_nmi_sysfs(void) |
| 298 | { |
| 299 | int error; |
| 300 | |
| 301 | if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC) |
| 302 | return 0; |
| 303 | |
| 304 | error = sysdev_class_register(&nmi_sysclass); |
| 305 | if (!error) |
| 306 | error = sysdev_register(&device_lapic_nmi); |
| 307 | return error; |
| 308 | } |
| 309 | /* must come after the local APIC's device_initcall() */ |
| 310 | late_initcall(init_lapic_nmi_sysfs); |
| 311 | |
| 312 | #endif /* CONFIG_PM */ |
| 313 | |
| 314 | /* |
| 315 | * Activate the NMI watchdog via the local APIC. |
| 316 | * Original code written by Keith Owens. |
| 317 | */ |
| 318 | |
| 319 | static void clear_msr_range(unsigned int base, unsigned int n) |
| 320 | { |
| 321 | unsigned int i; |
| 322 | |
| 323 | for(i = 0; i < n; ++i) |
| 324 | wrmsr(base+i, 0, 0); |
| 325 | } |
| 326 | |
| 327 | static void setup_k7_watchdog(void) |
| 328 | { |
| 329 | unsigned int evntsel; |
| 330 | |
| 331 | nmi_perfctr_msr = MSR_K7_PERFCTR0; |
| 332 | |
| 333 | clear_msr_range(MSR_K7_EVNTSEL0, 4); |
| 334 | clear_msr_range(MSR_K7_PERFCTR0, 4); |
| 335 | |
| 336 | evntsel = K7_EVNTSEL_INT |
| 337 | | K7_EVNTSEL_OS |
| 338 | | K7_EVNTSEL_USR |
| 339 | | K7_NMI_EVENT; |
| 340 | |
| 341 | wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); |
| 342 | Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000)); |
| 343 | wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1); |
| 344 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 345 | evntsel |= K7_EVNTSEL_ENABLE; |
| 346 | wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); |
| 347 | } |
| 348 | |
| 349 | static void setup_p6_watchdog(void) |
| 350 | { |
| 351 | unsigned int evntsel; |
| 352 | |
| 353 | nmi_perfctr_msr = MSR_P6_PERFCTR0; |
| 354 | |
| 355 | clear_msr_range(MSR_P6_EVNTSEL0, 2); |
| 356 | clear_msr_range(MSR_P6_PERFCTR0, 2); |
| 357 | |
| 358 | evntsel = P6_EVNTSEL_INT |
| 359 | | P6_EVNTSEL_OS |
| 360 | | P6_EVNTSEL_USR |
| 361 | | P6_NMI_EVENT; |
| 362 | |
| 363 | wrmsr(MSR_P6_EVNTSEL0, evntsel, 0); |
| 364 | Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000)); |
| 365 | wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0); |
| 366 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 367 | evntsel |= P6_EVNTSEL0_ENABLE; |
| 368 | wrmsr(MSR_P6_EVNTSEL0, evntsel, 0); |
| 369 | } |
| 370 | |
| 371 | static int setup_p4_watchdog(void) |
| 372 | { |
| 373 | unsigned int misc_enable, dummy; |
| 374 | |
| 375 | rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy); |
| 376 | if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL)) |
| 377 | return 0; |
| 378 | |
| 379 | nmi_perfctr_msr = MSR_P4_IQ_COUNTER0; |
| 380 | nmi_p4_cccr_val = P4_NMI_IQ_CCCR0; |
| 381 | #ifdef CONFIG_SMP |
| 382 | if (smp_num_siblings == 2) |
| 383 | nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1; |
| 384 | #endif |
| 385 | |
| 386 | if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL)) |
| 387 | clear_msr_range(0x3F1, 2); |
| 388 | /* MSR 0x3F0 seems to have a default value of 0xFC00, but current |
| 389 | docs doesn't fully define it, so leave it alone for now. */ |
| 390 | if (boot_cpu_data.x86_model >= 0x3) { |
| 391 | /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */ |
| 392 | clear_msr_range(0x3A0, 26); |
| 393 | clear_msr_range(0x3BC, 3); |
| 394 | } else { |
| 395 | clear_msr_range(0x3A0, 31); |
| 396 | } |
| 397 | clear_msr_range(0x3C0, 6); |
| 398 | clear_msr_range(0x3C8, 6); |
| 399 | clear_msr_range(0x3E0, 2); |
| 400 | clear_msr_range(MSR_P4_CCCR0, 18); |
| 401 | clear_msr_range(MSR_P4_PERFCTR0, 18); |
| 402 | |
| 403 | wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0); |
| 404 | wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0); |
| 405 | Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000)); |
| 406 | wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1); |
| 407 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 408 | wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); |
| 409 | return 1; |
| 410 | } |
| 411 | |
| 412 | void setup_apic_nmi_watchdog (void) |
| 413 | { |
| 414 | switch (boot_cpu_data.x86_vendor) { |
| 415 | case X86_VENDOR_AMD: |
| 416 | if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15) |
| 417 | return; |
| 418 | setup_k7_watchdog(); |
| 419 | break; |
| 420 | case X86_VENDOR_INTEL: |
| 421 | switch (boot_cpu_data.x86) { |
| 422 | case 6: |
| 423 | if (boot_cpu_data.x86_model > 0xd) |
| 424 | return; |
| 425 | |
| 426 | setup_p6_watchdog(); |
| 427 | break; |
| 428 | case 15: |
| 429 | if (boot_cpu_data.x86_model > 0x3) |
| 430 | return; |
| 431 | |
| 432 | if (!setup_p4_watchdog()) |
| 433 | return; |
| 434 | break; |
| 435 | default: |
| 436 | return; |
| 437 | } |
| 438 | break; |
| 439 | default: |
| 440 | return; |
| 441 | } |
| 442 | lapic_nmi_owner = LAPIC_NMI_WATCHDOG; |
| 443 | nmi_active = 1; |
| 444 | } |
| 445 | |
| 446 | /* |
| 447 | * the best way to detect whether a CPU has a 'hard lockup' problem |
| 448 | * is to check it's local APIC timer IRQ counts. If they are not |
| 449 | * changing then that CPU has some problem. |
| 450 | * |
| 451 | * as these watchdog NMI IRQs are generated on every CPU, we only |
| 452 | * have to check the current processor. |
| 453 | * |
| 454 | * since NMIs don't listen to _any_ locks, we have to be extremely |
| 455 | * careful not to rely on unsafe variables. The printk might lock |
| 456 | * up though, so we have to break up any console locks first ... |
| 457 | * [when there will be more tty-related locks, break them up |
| 458 | * here too!] |
| 459 | */ |
| 460 | |
| 461 | static unsigned int |
| 462 | last_irq_sums [NR_CPUS], |
| 463 | alert_counter [NR_CPUS]; |
| 464 | |
| 465 | void touch_nmi_watchdog (void) |
| 466 | { |
| 467 | int i; |
| 468 | |
| 469 | /* |
| 470 | * Just reset the alert counters, (other CPUs might be |
| 471 | * spinning on locks we hold): |
| 472 | */ |
| 473 | for (i = 0; i < NR_CPUS; i++) |
| 474 | alert_counter[i] = 0; |
| 475 | } |
| 476 | |
| 477 | extern void die_nmi(struct pt_regs *, const char *msg); |
| 478 | |
| 479 | void nmi_watchdog_tick (struct pt_regs * regs) |
| 480 | { |
| 481 | |
| 482 | /* |
| 483 | * Since current_thread_info()-> is always on the stack, and we |
| 484 | * always switch the stack NMI-atomically, it's safe to use |
| 485 | * smp_processor_id(). |
| 486 | */ |
| 487 | int sum, cpu = smp_processor_id(); |
| 488 | |
| 489 | sum = per_cpu(irq_stat, cpu).apic_timer_irqs; |
| 490 | |
| 491 | if (last_irq_sums[cpu] == sum) { |
| 492 | /* |
| 493 | * Ayiee, looks like this CPU is stuck ... |
| 494 | * wait a few IRQs (5 seconds) before doing the oops ... |
| 495 | */ |
| 496 | alert_counter[cpu]++; |
| 497 | if (alert_counter[cpu] == 5*nmi_hz) |
| 498 | die_nmi(regs, "NMI Watchdog detected LOCKUP"); |
| 499 | } else { |
| 500 | last_irq_sums[cpu] = sum; |
| 501 | alert_counter[cpu] = 0; |
| 502 | } |
| 503 | if (nmi_perfctr_msr) { |
| 504 | if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) { |
| 505 | /* |
| 506 | * P4 quirks: |
| 507 | * - An overflown perfctr will assert its interrupt |
| 508 | * until the OVF flag in its CCCR is cleared. |
| 509 | * - LVTPC is masked on interrupt and must be |
| 510 | * unmasked by the LVTPC handler. |
| 511 | */ |
| 512 | wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); |
| 513 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 514 | } |
| 515 | else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) { |
| 516 | /* Only P6 based Pentium M need to re-unmask |
| 517 | * the apic vector but it doesn't hurt |
| 518 | * other P6 variant */ |
| 519 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 520 | } |
| 521 | wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1); |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | #ifdef CONFIG_SYSCTL |
| 526 | |
| 527 | static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu) |
| 528 | { |
| 529 | unsigned char reason = get_nmi_reason(); |
| 530 | char buf[64]; |
| 531 | |
| 532 | if (!(reason & 0xc0)) { |
| 533 | sprintf(buf, "NMI received for unknown reason %02x\n", reason); |
| 534 | die_nmi(regs, buf); |
| 535 | } |
| 536 | return 0; |
| 537 | } |
| 538 | |
| 539 | /* |
| 540 | * proc handler for /proc/sys/kernel/unknown_nmi_panic |
| 541 | */ |
| 542 | int proc_unknown_nmi_panic(ctl_table *table, int write, struct file *file, |
| 543 | void __user *buffer, size_t *length, loff_t *ppos) |
| 544 | { |
| 545 | int old_state; |
| 546 | |
| 547 | old_state = unknown_nmi_panic; |
| 548 | proc_dointvec(table, write, file, buffer, length, ppos); |
| 549 | if (!!old_state == !!unknown_nmi_panic) |
| 550 | return 0; |
| 551 | |
| 552 | if (unknown_nmi_panic) { |
| 553 | if (reserve_lapic_nmi() < 0) { |
| 554 | unknown_nmi_panic = 0; |
| 555 | return -EBUSY; |
| 556 | } else { |
| 557 | set_nmi_callback(unknown_nmi_panic_callback); |
| 558 | } |
| 559 | } else { |
| 560 | release_lapic_nmi(); |
| 561 | unset_nmi_callback(); |
| 562 | } |
| 563 | return 0; |
| 564 | } |
| 565 | |
| 566 | #endif |
| 567 | |
| 568 | EXPORT_SYMBOL(nmi_active); |
| 569 | EXPORT_SYMBOL(nmi_watchdog); |
| 570 | EXPORT_SYMBOL(reserve_lapic_nmi); |
| 571 | EXPORT_SYMBOL(release_lapic_nmi); |
| 572 | EXPORT_SYMBOL(disable_timer_nmi_watchdog); |
| 573 | EXPORT_SYMBOL(enable_timer_nmi_watchdog); |