| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * SNI RM200 PCI specific interrupt handler code. |
| 3 | * |
| 4 | * Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000, 01 by Ralf Baechle |
| 5 | */ |
| 6 | #include <asm/asm.h> |
| 7 | #include <asm/mipsregs.h> |
| 8 | #include <asm/regdef.h> |
| 9 | #include <asm/sni.h> |
| 10 | #include <asm/stackframe.h> |
| 11 | |
| 12 | /* |
| 13 | * The PCI ASIC has the nasty property that it may delay writes if it is busy. |
| 14 | * As a consequence from writes that have not graduated when we exit from the |
| 15 | * interrupt handler we might catch a spurious interrupt. To avoid this we |
| 16 | * force the PCI ASIC to graduate all writes by executing a read from the |
| 17 | * PCI bus. |
| 18 | */ |
| 19 | .set noreorder |
| 20 | .set noat |
| 21 | .align 5 |
| 22 | NESTED(sni_rm200_pci_handle_int, PT_SIZE, sp) |
| 23 | SAVE_ALL |
| 24 | CLI |
| 25 | .set at |
| 26 | |
| 27 | /* Blinken light ... */ |
| 28 | lb t0, led_cache |
| 29 | addiu t0, 1 |
| 30 | sb t0, led_cache |
| 31 | sb t0, PCIMT_CSLED # write only register |
| 32 | .data |
| 33 | led_cache: .byte 0 |
| 34 | .text |
| 35 | |
| 36 | mfc0 t0, CP0_STATUS |
| 37 | mfc0 t1, CP0_CAUSE |
| 38 | and t0, t1 |
| 39 | |
| 40 | andi t1, t0, 0x0800 # hardware interrupt 1 |
| 41 | bnez t1, _hwint1 |
| 42 | andi t1, t0, 0x4000 # hardware interrupt 4 |
| 43 | bnez t1, _hwint4 |
| 44 | andi t1, t0, 0x2000 # hardware interrupt 3 |
| 45 | bnez t1, _hwint3 |
| 46 | andi t1, t0, 0x1000 # hardware interrupt 2 |
| 47 | bnez t1, _hwint2 |
| 48 | andi t1, t0, 0x8000 # hardware interrupt 5 |
| 49 | bnez t1, _hwint5 |
| 50 | andi t1, t0, 0x0400 # hardware interrupt 0 |
| 51 | bnez t1, _hwint0 |
| 52 | nop |
| 53 | |
| 54 | j restore_all # spurious interrupt |
| 55 | nop |
| 56 | |
| 57 | ############################################################################## |
| 58 | |
| 59 | /* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug |
| 60 | button interrupts. */ |
| 61 | _hwint0: jal pciasic_hwint0 |
| 62 | move a0, sp |
| 63 | j ret_from_irq |
| 64 | nop |
| 65 | |
| 66 | /* |
| 67 | * hwint 1 deals with EISA and SCSI interrupts |
| 68 | */ |
| 69 | _hwint1: jal pciasic_hwint1 |
| 70 | move a0, sp |
| 71 | j ret_from_irq |
| 72 | nop |
| 73 | |
| 74 | |
| 75 | /* |
| 76 | * This interrupt was used for the com1 console on the first prototypes; |
| 77 | * it's unsed otherwise |
| 78 | */ |
| 79 | _hwint2: jal pciasic_hwint2 |
| 80 | move a0, sp |
| 81 | j ret_from_irq |
| 82 | nop |
| 83 | |
| 84 | /* |
| 85 | * hwint 3 are the PCI interrupts A - D |
| 86 | */ |
| 87 | _hwint3: jal pciasic_hwint3 |
| 88 | move a0, sp |
| 89 | j ret_from_irq |
| 90 | nop |
| 91 | |
| 92 | /* |
| 93 | * hwint 4 is used for only the onboard PCnet 32. |
| 94 | */ |
| 95 | _hwint4: jal pciasic_hwint4 |
| 96 | move a0, sp |
| 97 | j ret_from_irq |
| 98 | nop |
| 99 | |
| 100 | /* hwint5 is the r4k count / compare interrupt */ |
| 101 | _hwint5: jal pciasic_hwint5 |
| 102 | move a0, sp |
| 103 | j ret_from_irq |
| 104 | nop |
| 105 | |
| 106 | END(sni_rm200_pci_handle_int) |