blob: 1e379ed17b1d7549a3bf48f8c772d4751e516baa [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Intel SMP support routines.
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
6 * (c) 2002,2003 Andi Kleen, SuSE Labs.
7 *
8 * This code is released under the GNU General Public License version 2 or
9 * later.
10 */
11
12#include <linux/init.h>
13
14#include <linux/mm.h>
15#include <linux/irq.h>
16#include <linux/delay.h>
17#include <linux/spinlock.h>
18#include <linux/smp_lock.h>
19#include <linux/smp.h>
20#include <linux/kernel_stat.h>
21#include <linux/mc146818rtc.h>
22#include <linux/interrupt.h>
23
24#include <asm/mtrr.h>
25#include <asm/pgalloc.h>
26#include <asm/tlbflush.h>
27#include <asm/mach_apic.h>
28#include <asm/mmu_context.h>
29#include <asm/proto.h>
Andi Kleena8ab26f2005-04-16 15:25:19 -070030#include <asm/apicdef.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
32/*
33 * Smarter SMP flushing macros.
34 * c/o Linus Torvalds.
35 *
36 * These mean you can really definitely utterly forget about
37 * writing to user space from interrupts. (Its not allowed anyway).
38 *
39 * Optimizations Manfred Spraul <manfred@colorfullife.com>
40 */
41
42static cpumask_t flush_cpumask;
43static struct mm_struct * flush_mm;
44static unsigned long flush_va;
45static DEFINE_SPINLOCK(tlbstate_lock);
46#define FLUSH_ALL -1ULL
47
48/*
49 * We cannot call mmdrop() because we are in interrupt context,
50 * instead update mm->cpu_vm_mask.
51 */
52static inline void leave_mm (unsigned long cpu)
53{
54 if (read_pda(mmu_state) == TLBSTATE_OK)
55 BUG();
56 clear_bit(cpu, &read_pda(active_mm)->cpu_vm_mask);
57 load_cr3(swapper_pg_dir);
58}
59
60/*
61 *
62 * The flush IPI assumes that a thread switch happens in this order:
63 * [cpu0: the cpu that switches]
64 * 1) switch_mm() either 1a) or 1b)
65 * 1a) thread switch to a different mm
66 * 1a1) clear_bit(cpu, &old_mm->cpu_vm_mask);
67 * Stop ipi delivery for the old mm. This is not synchronized with
68 * the other cpus, but smp_invalidate_interrupt ignore flush ipis
69 * for the wrong mm, and in the worst case we perform a superfluous
70 * tlb flush.
71 * 1a2) set cpu mmu_state to TLBSTATE_OK
72 * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
73 * was in lazy tlb mode.
74 * 1a3) update cpu active_mm
75 * Now cpu0 accepts tlb flushes for the new mm.
76 * 1a4) set_bit(cpu, &new_mm->cpu_vm_mask);
77 * Now the other cpus will send tlb flush ipis.
78 * 1a4) change cr3.
79 * 1b) thread switch without mm change
80 * cpu active_mm is correct, cpu0 already handles
81 * flush ipis.
82 * 1b1) set cpu mmu_state to TLBSTATE_OK
83 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
84 * Atomically set the bit [other cpus will start sending flush ipis],
85 * and test the bit.
86 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
87 * 2) switch %%esp, ie current
88 *
89 * The interrupt must handle 2 special cases:
90 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
91 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
92 * runs in kernel space, the cpu could load tlb entries for user space
93 * pages.
94 *
95 * The good news is that cpu mmu_state is local to each cpu, no
96 * write/read ordering problems.
97 */
98
99/*
100 * TLB flush IPI:
101 *
102 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
103 * 2) Leave the mm if we are in the lazy tlb mode.
104 */
105
106asmlinkage void smp_invalidate_interrupt (void)
107{
108 unsigned long cpu;
109
110 cpu = get_cpu();
111
112 if (!cpu_isset(cpu, flush_cpumask))
113 goto out;
114 /*
115 * This was a BUG() but until someone can quote me the
116 * line from the intel manual that guarantees an IPI to
117 * multiple CPUs is retried _only_ on the erroring CPUs
118 * its staying as a return
119 *
120 * BUG();
121 */
122
123 if (flush_mm == read_pda(active_mm)) {
124 if (read_pda(mmu_state) == TLBSTATE_OK) {
125 if (flush_va == FLUSH_ALL)
126 local_flush_tlb();
127 else
128 __flush_tlb_one(flush_va);
129 } else
130 leave_mm(cpu);
131 }
132 ack_APIC_irq();
133 cpu_clear(cpu, flush_cpumask);
134
135out:
136 put_cpu_no_resched();
137}
138
139static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
140 unsigned long va)
141{
142 cpumask_t tmp;
143 /*
144 * A couple of (to be removed) sanity checks:
145 *
146 * - we do not send IPIs to not-yet booted CPUs.
147 * - current CPU must not be in mask
148 * - mask must exist :)
149 */
150 BUG_ON(cpus_empty(cpumask));
151 cpus_and(tmp, cpumask, cpu_online_map);
152 BUG_ON(!cpus_equal(tmp, cpumask));
153 BUG_ON(cpu_isset(smp_processor_id(), cpumask));
154 if (!mm)
155 BUG();
156
157 /*
158 * I'm not happy about this global shared spinlock in the
159 * MM hot path, but we'll see how contended it is.
160 * Temporarily this turns IRQs off, so that lockups are
161 * detected by the NMI watchdog.
162 */
163 spin_lock(&tlbstate_lock);
164
165 flush_mm = mm;
166 flush_va = va;
167 cpus_or(flush_cpumask, cpumask, flush_cpumask);
168
169 /*
170 * We have to send the IPI only to
171 * CPUs affected.
172 */
173 send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR);
174
175 while (!cpus_empty(flush_cpumask))
176 mb(); /* nothing. lockup detection does not belong here */;
177
178 flush_mm = NULL;
179 flush_va = 0;
180 spin_unlock(&tlbstate_lock);
181}
182
183void flush_tlb_current_task(void)
184{
185 struct mm_struct *mm = current->mm;
186 cpumask_t cpu_mask;
187
188 preempt_disable();
189 cpu_mask = mm->cpu_vm_mask;
190 cpu_clear(smp_processor_id(), cpu_mask);
191
192 local_flush_tlb();
193 if (!cpus_empty(cpu_mask))
194 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
195 preempt_enable();
196}
197
198void flush_tlb_mm (struct mm_struct * mm)
199{
200 cpumask_t cpu_mask;
201
202 preempt_disable();
203 cpu_mask = mm->cpu_vm_mask;
204 cpu_clear(smp_processor_id(), cpu_mask);
205
206 if (current->active_mm == mm) {
207 if (current->mm)
208 local_flush_tlb();
209 else
210 leave_mm(smp_processor_id());
211 }
212 if (!cpus_empty(cpu_mask))
213 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
214
215 preempt_enable();
216}
217
218void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
219{
220 struct mm_struct *mm = vma->vm_mm;
221 cpumask_t cpu_mask;
222
223 preempt_disable();
224 cpu_mask = mm->cpu_vm_mask;
225 cpu_clear(smp_processor_id(), cpu_mask);
226
227 if (current->active_mm == mm) {
228 if(current->mm)
229 __flush_tlb_one(va);
230 else
231 leave_mm(smp_processor_id());
232 }
233
234 if (!cpus_empty(cpu_mask))
235 flush_tlb_others(cpu_mask, mm, va);
236
237 preempt_enable();
238}
239
240static void do_flush_tlb_all(void* info)
241{
242 unsigned long cpu = smp_processor_id();
243
244 __flush_tlb_all();
245 if (read_pda(mmu_state) == TLBSTATE_LAZY)
246 leave_mm(cpu);
247}
248
249void flush_tlb_all(void)
250{
251 on_each_cpu(do_flush_tlb_all, NULL, 1, 1);
252}
253
254void smp_kdb_stop(void)
255{
256 send_IPI_allbutself(KDB_VECTOR);
257}
258
259/*
260 * this function sends a 'reschedule' IPI to another CPU.
261 * it goes straight through and wastes no time serializing
262 * anything. Worst case is that we lose a reschedule ...
263 */
264
265void smp_send_reschedule(int cpu)
266{
267 send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
268}
269
270/*
271 * Structure and data for smp_call_function(). This is designed to minimise
272 * static memory requirements. It also looks cleaner.
273 */
274static DEFINE_SPINLOCK(call_lock);
275
276struct call_data_struct {
277 void (*func) (void *info);
278 void *info;
279 atomic_t started;
280 atomic_t finished;
281 int wait;
282};
283
284static struct call_data_struct * call_data;
285
286/*
287 * this function sends a 'generic call function' IPI to all other CPUs
288 * in the system.
289 */
290static void __smp_call_function (void (*func) (void *info), void *info,
291 int nonatomic, int wait)
292{
293 struct call_data_struct data;
294 int cpus = num_online_cpus()-1;
295
296 if (!cpus)
297 return;
298
299 data.func = func;
300 data.info = info;
301 atomic_set(&data.started, 0);
302 data.wait = wait;
303 if (wait)
304 atomic_set(&data.finished, 0);
305
306 call_data = &data;
307 wmb();
308 /* Send a message to all other CPUs and wait for them to respond */
309 send_IPI_allbutself(CALL_FUNCTION_VECTOR);
310
311 /* Wait for response */
312 while (atomic_read(&data.started) != cpus)
313 cpu_relax();
314
315 if (!wait)
316 return;
317
318 while (atomic_read(&data.finished) != cpus)
319 cpu_relax();
320}
321
322/*
323 * smp_call_function - run a function on all other CPUs.
324 * @func: The function to run. This must be fast and non-blocking.
325 * @info: An arbitrary pointer to pass to the function.
326 * @nonatomic: currently unused.
327 * @wait: If true, wait (atomically) until function has completed on other
328 * CPUs.
329 *
330 * Returns 0 on success, else a negative status code. Does not return until
331 * remote CPUs are nearly ready to execute func or are or have executed.
332 *
333 * You must not call this function with disabled interrupts or from a
334 * hardware interrupt handler or from a bottom half handler.
335 * Actually there are a few legal cases, like panic.
336 */
337int smp_call_function (void (*func) (void *info), void *info, int nonatomic,
338 int wait)
339{
340 spin_lock(&call_lock);
341 __smp_call_function(func,info,nonatomic,wait);
342 spin_unlock(&call_lock);
343 return 0;
344}
345
346void smp_stop_cpu(void)
347{
348 /*
349 * Remove this CPU:
350 */
351 cpu_clear(smp_processor_id(), cpu_online_map);
352 local_irq_disable();
353 disable_local_APIC();
354 local_irq_enable();
355}
356
357static void smp_really_stop_cpu(void *dummy)
358{
359 smp_stop_cpu();
360 for (;;)
361 asm("hlt");
362}
363
364void smp_send_stop(void)
365{
366 int nolock = 0;
367 if (reboot_force)
368 return;
369 /* Don't deadlock on the call lock in panic */
370 if (!spin_trylock(&call_lock)) {
371 /* ignore locking because we have paniced anyways */
372 nolock = 1;
373 }
374 __smp_call_function(smp_really_stop_cpu, NULL, 0, 0);
375 if (!nolock)
376 spin_unlock(&call_lock);
377
378 local_irq_disable();
379 disable_local_APIC();
380 local_irq_enable();
381}
382
383/*
384 * Reschedule call back. Nothing to do,
385 * all the work is done automatically when
386 * we return from the interrupt.
387 */
388asmlinkage void smp_reschedule_interrupt(void)
389{
390 ack_APIC_irq();
391}
392
393asmlinkage void smp_call_function_interrupt(void)
394{
395 void (*func) (void *info) = call_data->func;
396 void *info = call_data->info;
397 int wait = call_data->wait;
398
399 ack_APIC_irq();
400 /*
401 * Notify initiating CPU that I've grabbed the data and am
402 * about to execute the function
403 */
404 mb();
405 atomic_inc(&call_data->started);
406 /*
407 * At this point the info structure may be out of scope unless wait==1
408 */
409 irq_enter();
410 (*func)(info);
411 irq_exit();
412 if (wait) {
413 mb();
414 atomic_inc(&call_data->finished);
415 }
416}
Andi Kleena8ab26f2005-04-16 15:25:19 -0700417
418int safe_smp_processor_id(void)
419{
420 int apicid, i;
421
422 if (disable_apic)
423 return 0;
424
425 apicid = hard_smp_processor_id();
426 if (x86_cpu_to_apicid[apicid] == apicid)
427 return apicid;
428
429 for (i = 0; i < NR_CPUS; ++i) {
430 if (x86_cpu_to_apicid[i] == apicid)
431 return i;
432 }
433
434 /* No entries in x86_cpu_to_apicid? Either no MPS|ACPI,
435 * or called too early. Either way, we must be CPU 0. */
436 if (x86_cpu_to_apicid[0] == BAD_APICID)
437 return 0;
438
439 return 0; /* Should not happen */
440}