| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-arm/arch-ixp2000/ixp2000-regs.h |
| 3 | * |
| 4 | * Chipset register definitions for IXP2400/2800 based systems. |
| 5 | * |
| 6 | * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> |
| 7 | * |
| 8 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> |
| 9 | * |
| 10 | * Copyright (C) 2002 Intel Corp. |
| 11 | * Copyright (C) 2003-2004 MontaVista Software, Inc. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify it |
| 14 | * under the terms of the GNU General Public License as published by the |
| 15 | * Free Software Foundation; either version 2 of the License, or (at your |
| 16 | * option) any later version. |
| 17 | */ |
| 18 | #ifndef _IXP2000_REGS_H_ |
| 19 | #define _IXP2000_REGS_H_ |
| 20 | |
| 21 | /* |
| 22 | * Static I/O regions. |
| 23 | * |
| 24 | * Most of the registers are clumped in 4K regions spread throughout |
| 25 | * the 0xc0000000 -> 0xc0100000 address range, but we just map in |
| 26 | * the whole range using a single 1 MB section instead of small |
| 27 | * 4K pages. This has two advantages for us: |
| 28 | * |
| 29 | * 1) We use only one TLB entry for large number of on-chip I/O devices. |
| 30 | * |
| 31 | * 2) We can easily set the Section attributes to XCB=101 on the IXP2400 |
| 32 | * as required per erratum #66. We accomplish this by using a |
| 33 | * new MT_IXP2000_DEVICE memory type with the bits set as required. |
| 34 | * |
| 35 | * CAP stands for CSR Access Proxy. |
| 36 | * |
| 37 | * If you change the virtual address of this mapping, please propagate |
| 38 | * the change to arch/arm/kernel/debug.S, which hardcodes the virtual |
| 39 | * address of the UART located in this region. |
| 40 | */ |
| 41 | |
| 42 | #define IXP2000_CAP_PHYS_BASE 0xc0000000 |
| 43 | #define IXP2000_CAP_VIRT_BASE 0xfef00000 |
| 44 | #define IXP2000_CAP_SIZE 0x00100000 |
| 45 | |
| 46 | /* |
| 47 | * Addresses for specific on-chip peripherals |
| 48 | */ |
| 49 | #define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000 |
| 50 | #define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000 |
| 51 | #define IXP2000_UART_PHYS_BASE 0xc0030000 |
| 52 | #define IXP2000_UART_VIRT_BASE 0xfef30000 |
| 53 | #define IXP2000_TIMER_VIRT_BASE 0xfef20000 |
| 54 | #define IXP2000_GPIO_VIRT_BASE 0Xfef10000 |
| 55 | |
| 56 | /* |
| 57 | * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual |
| 58 | * addresses of the INTCTL and PCI_CSR mappings are hardcoded in |
| 59 | * entry-macro.S, so if you ever change these please propagate |
| 60 | * the change. |
| 61 | */ |
| 62 | #define IXP2000_INTCTL_PHYS_BASE 0xd6000000 |
| 63 | #define IXP2000_INTCTL_VIRT_BASE 0xfee00000 |
| 64 | #define IXP2000_INTCTL_SIZE 0x00100000 |
| 65 | |
| 66 | #define IXP2000_PCI_CREG_PHYS_BASE 0xde000000 |
| 67 | #define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000 |
| 68 | #define IXP2000_PCI_CREG_SIZE 0x00100000 |
| 69 | |
| 70 | #define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000 |
| 71 | #define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000 |
| 72 | #define IXP2000_PCI_CSR_SIZE 0x00100000 |
| 73 | |
| 74 | #define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 |
| 75 | #define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 |
| 76 | #define IXP2000_PCI_IO_SIZE 0x01000000 |
| 77 | |
| 78 | #define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000 |
| 79 | #define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000 |
| 80 | #define IXP2000_PCI_CFG0_SIZE 0x01000000 |
| 81 | |
| 82 | #define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000 |
| 83 | #define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000 |
| 84 | #define IXP2000_PCI_CFG1_SIZE 0x01000000 |
| 85 | |
| 86 | /* |
| 87 | * Timers |
| 88 | */ |
| 89 | #define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x))) |
| 90 | /* Timer control */ |
| 91 | #define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00) |
| 92 | #define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04) |
| 93 | #define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08) |
| 94 | #define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c) |
| 95 | /* Store initial value */ |
| 96 | #define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10) |
| 97 | #define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14) |
| 98 | #define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18) |
| 99 | #define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c) |
| 100 | /* Read current value */ |
| 101 | #define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20) |
| 102 | #define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24) |
| 103 | #define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28) |
| 104 | #define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c) |
| 105 | /* Clear associated timer interrupt */ |
| 106 | #define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30) |
| 107 | #define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34) |
| 108 | #define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38) |
| 109 | #define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c) |
| 110 | /* Timer watchdog enable for T4 */ |
| 111 | #define IXP2000_TWDE IXP2000_TIMER_REG(0x40) |
| 112 | |
| 113 | #define WDT_ENABLE 0x00000001 |
| 114 | #define TIMER_DIVIDER_256 0x00000008 |
| 115 | #define TIMER_ENABLE 0x00000080 |
| 116 | #define IRQ_MASK_TIMER1 (1 << 4) |
| 117 | |
| 118 | /* |
| 119 | * Interrupt controller registers |
| 120 | */ |
| 121 | #define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x)) |
| 122 | #define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08) |
| 123 | #define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10) |
| 124 | #define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10) |
| 125 | #define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18) |
| 126 | #define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14) |
| 127 | #define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24) |
| 128 | #define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c) |
| 129 | #define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30) |
| 130 | #define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34) |
| 131 | #define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60) |
| 132 | #define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64) |
| 133 | #define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68) |
| 134 | #define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c) |
| 135 | #define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80) |
| 136 | #define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84) |
| 137 | #define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88) |
| 138 | #define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c) |
| 139 | #define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160) |
| 140 | #define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164) |
| 141 | #define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168) |
| 142 | #define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c) |
| 143 | #define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180) |
| 144 | #define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184) |
| 145 | #define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188) |
| 146 | #define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c) |
| 147 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0) |
| 148 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4) |
| 149 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8) |
| 150 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec) |
| 151 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200) |
| 152 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204) |
| 153 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208) |
| 154 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c) |
| 155 | |
| 156 | /* |
| 157 | * Mask of valid IRQs in the 32-bit IRQ register. We use |
| 158 | * this to mark certain IRQs as being invalid. |
| 159 | */ |
| 160 | #define IXP2000_VALID_IRQ_MASK 0x0f0fffff |
| 161 | |
| 162 | /* |
| 163 | * PCI config register access from core |
| 164 | */ |
| 165 | #define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x)) |
| 166 | #define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04) |
| 167 | #define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10) |
| 168 | #define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14) |
| 169 | #define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18) |
| 170 | |
| 171 | /* |
| 172 | * PCI CSRs |
| 173 | */ |
| 174 | #define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x)) |
| 175 | |
| 176 | /* |
| 177 | * PCI outbound interrupts |
| 178 | */ |
| 179 | #define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30) |
| 180 | #define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34) |
| 181 | /* |
| 182 | * PCI communications |
| 183 | */ |
| 184 | #define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50) |
| 185 | #define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54) |
| 186 | #define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58) |
| 187 | #define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C) |
| 188 | #define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60) |
| 189 | #define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64) |
| 190 | #define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70) |
| 191 | #define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74) |
| 192 | |
| 193 | /* |
| 194 | * DMA engines |
| 195 | */ |
| 196 | #define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80) |
| 197 | #define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84) |
| 198 | #define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88) |
| 199 | #define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C) |
| 200 | #define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90) |
| 201 | #define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94) |
| 202 | #define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0) |
| 203 | #define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4) |
| 204 | #define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8) |
| 205 | #define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC) |
| 206 | #define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0) |
| 207 | #define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4) |
| 208 | #define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0) |
| 209 | #define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4) |
| 210 | #define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8) |
| 211 | #define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC) |
| 212 | #define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0) |
| 213 | #define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4) |
| 214 | #define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0) |
| 215 | /* |
| 216 | * Size masks for BARs |
| 217 | */ |
| 218 | #define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC) |
| 219 | #define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100) |
| 220 | /* |
| 221 | * Control and uEngine related |
| 222 | */ |
| 223 | #define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C) |
| 224 | #define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140) |
| 225 | #define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148) |
| 226 | #define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C) |
| 227 | #define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150) |
| 228 | #define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154) |
| 229 | /* |
| 230 | * Inbound PCI interrupt control |
| 231 | */ |
| 232 | #define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158) |
| 233 | #define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C) |
| 234 | |
| 235 | #define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */ |
| 236 | #define IXP2000_PCICNTL_PCF (1<<28) /* PCI Centrolfunction bit */ |
| 237 | #define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */ |
| 238 | |
| 239 | /* These are from the IRQ register in the PCI ISR register */ |
| 240 | #define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */ |
| 241 | #define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */ |
| 242 | #define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */ |
| 243 | #define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */ |
| 244 | #define PCI_CONTROL_PNR (1 << 17) /* PCI Not Reset bit */ |
| 245 | |
| 246 | #define IXP2000_PCI_RST_REL (1 << 2) |
| 247 | #define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF) |
| 248 | #define CFG_PCI_BOOT_HOST (1 << 2) |
| 249 | #define CFG_BOOT_PROM (1 << 1) |
| 250 | |
| 251 | /* |
| 252 | * SlowPort CSRs |
| 253 | * |
| 254 | * The slowport is used to access things like flash, SONET framer control |
| 255 | * ports, slave microprocessors, CPLDs, and others of chip memory mapped |
| 256 | * peripherals. |
| 257 | */ |
| 258 | #define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x)) |
| 259 | |
| 260 | #define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00) |
| 261 | #define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04) |
| 262 | #define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08) |
| 263 | #define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c) |
| 264 | #define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10) |
| 265 | #define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14) |
| 266 | #define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18) |
| 267 | #define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C) |
| 268 | #define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20) |
| 269 | #define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24) |
| 270 | #define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28) |
| 271 | |
| 272 | /* |
| 273 | * CCR values. |
| 274 | * The CCR configures the clock division for the slowport interface. |
| 275 | */ |
| 276 | #define SLOWPORT_CCR_DIV_1 0x00 |
| 277 | #define SLOWPORT_CCR_DIV_2 0x01 |
| 278 | #define SLOWPORT_CCR_DIV_4 0x02 |
| 279 | #define SLOWPORT_CCR_DIV_6 0x03 |
| 280 | #define SLOWPORT_CCR_DIV_8 0x04 |
| 281 | #define SLOWPORT_CCR_DIV_10 0x05 |
| 282 | #define SLOWPORT_CCR_DIV_12 0x06 |
| 283 | #define SLOWPORT_CCR_DIV_14 0x07 |
| 284 | #define SLOWPORT_CCR_DIV_16 0x08 |
| 285 | #define SLOWPORT_CCR_DIV_18 0x09 |
| 286 | #define SLOWPORT_CCR_DIV_20 0x0a |
| 287 | #define SLOWPORT_CCR_DIV_22 0x0b |
| 288 | #define SLOWPORT_CCR_DIV_24 0x0c |
| 289 | #define SLOWPORT_CCR_DIV_26 0x0d |
| 290 | #define SLOWPORT_CCR_DIV_28 0x0e |
| 291 | #define SLOWPORT_CCR_DIV_30 0x0f |
| 292 | |
| 293 | /* |
| 294 | * PCR values. PCR configure the mode of the interface. |
| 295 | */ |
| 296 | #define SLOWPORT_MODE_FLASH 0x00 |
| 297 | #define SLOWPORT_MODE_LUCENT 0x01 |
| 298 | #define SLOWPORT_MODE_PMC_SIERRA 0x02 |
| 299 | #define SLOWPORT_MODE_INTEL_UP 0x03 |
| 300 | #define SLOWPORT_MODE_MOTOROLA_UP 0x04 |
| 301 | |
| 302 | /* |
| 303 | * ADC values. Defines data and address bus widths. |
| 304 | */ |
| 305 | #define SLOWPORT_ADDR_WIDTH_8 0x00 |
| 306 | #define SLOWPORT_ADDR_WIDTH_16 0x01 |
| 307 | #define SLOWPORT_ADDR_WIDTH_24 0x02 |
| 308 | #define SLOWPORT_ADDR_WIDTH_32 0x03 |
| 309 | #define SLOWPORT_DATA_WIDTH_8 0x00 |
| 310 | #define SLOWPORT_DATA_WIDTH_16 0x10 |
| 311 | #define SLOWPORT_DATA_WIDTH_24 0x20 |
| 312 | #define SLOWPORT_DATA_WIDTH_32 0x30 |
| 313 | |
| 314 | /* |
| 315 | * Masks and shifts for various fields in the WTC and RTC registers. |
| 316 | */ |
| 317 | #define SLOWPORT_WRTC_MASK_HD 0x0003 |
| 318 | #define SLOWPORT_WRTC_MASK_SU 0x003c |
| 319 | #define SLOWPORT_WRTC_MASK_PW 0x03c0 |
| 320 | |
| 321 | #define SLOWPORT_WRTC_SHIFT_HD 0x00 |
| 322 | #define SLOWPORT_WRTC_SHIFT_SU 0x02 |
| 323 | #define SLOWPORT_WRTC_SHFIT_PW 0x06 |
| 324 | |
| 325 | |
| 326 | /* |
| 327 | * GPIO registers & GPIO interface. |
| 328 | */ |
| 329 | #define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x))) |
| 330 | #define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00) |
| 331 | #define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04) |
| 332 | #define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08) |
| 333 | #define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c) |
| 334 | #define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10) |
| 335 | #define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14) |
| 336 | #define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18) |
| 337 | #define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c) |
| 338 | #define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20) |
| 339 | #define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24) |
| 340 | #define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28) |
| 341 | #define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c) |
| 342 | #define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30) |
| 343 | #define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34) |
| 344 | #define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38) |
| 345 | #define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c) |
| 346 | #define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40) |
| 347 | |
| 348 | /* |
| 349 | * "Global" registers...whatever that's supposed to mean. |
| 350 | */ |
| 351 | #define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00) |
| 352 | #define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x)) |
| 353 | |
| 354 | #define IXP2000_PROD_ID GLOBAL_REG(0x00) |
| 355 | |
| 356 | #define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000 |
| 357 | #define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000 |
| 358 | #define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00 |
| 359 | #define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200 |
| 360 | #define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100 |
| 361 | #define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000 |
| 362 | #define IXP2000_MAJ_REV_MASK 0x000000F0 |
| 363 | #define IXP2000_MIN_REV_MASK 0x0000000F |
| 364 | #define IXP2000_PROD_ID_MASK 0xFFFFFFFF |
| 365 | |
| 366 | #define IXP2000_MISC_CONTROL GLOBAL_REG(0x04) |
| 367 | #define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08) |
| 368 | #define IXP2000_RESET0 GLOBAL_REG(0x0c) |
| 369 | #define IXP2000_RESET1 GLOBAL_REG(0x10) |
| 370 | #define IXP2000_CCR GLOBAL_REG(0x14) |
| 371 | #define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18) |
| 372 | |
| 373 | #define RSTALL (1 << 16) |
| 374 | #define WDT_RESET_ENABLE 0x01000000 |
| 375 | |
| 376 | |
| 377 | #endif /* _IXP2000_H_ */ |