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review.evervolv.com / android_kernel_lge_hammerhead / 3487d1d4414fbfab5d98ec559e6f84f55520cb15 / . / arch / sh64 / boot / compressed / head.S
blob: 82040b1a29cfedcb876f576c89e48bf7b322dfb2 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * arch/shmedia/boot/compressed/head.S
7 *
8 * Copied from
9 * arch/shmedia/kernel/head.S
10 * which carried the copyright:
11 * Copyright (C) 2000, 2001 Paolo Alberelli
12 *
13 * Modification for compressed loader:
14 * Copyright (C) 2002 Stuart Menefy (stuart.menefy@st.com)
15 */
16
17#include <linux/linkage.h>
18#include <asm/registers.h>
19#include <asm/cache.h>
20#include <asm/mmu_context.h>
21
22/*
23 * Fixed TLB entries to identity map the beginning of RAM
24 */
25#define MMUIR_TEXT_H 0x0000000000000003 | CONFIG_MEMORY_START
26 /* Enabled, Shared, ASID 0, Eff. Add. 0xA0000000 */
27#define MMUIR_TEXT_L 0x000000000000009a | CONFIG_MEMORY_START
28 /* 512 Mb, Cacheable (Write-back), execute, Not User, Ph. Add. */
29
30#define MMUDR_CACHED_H 0x0000000000000003 | CONFIG_MEMORY_START
31 /* Enabled, Shared, ASID 0, Eff. Add. 0xA0000000 */
32#define MMUDR_CACHED_L 0x000000000000015a | CONFIG_MEMORY_START
33 /* 512 Mb, Cacheable (Write-back), read/write, Not User, Ph. Add. */
34
35#define ICCR0_INIT_VAL ICCR0_ON | ICCR0_ICI /* ICE + ICI */
36#define ICCR1_INIT_VAL ICCR1_NOLOCK /* No locking */
37
38#if 1
39#define OCCR0_INIT_VAL OCCR0_ON | OCCR0_OCI | OCCR0_WB /* OCE + OCI + WB */
40#else
41#define OCCR0_INIT_VAL OCCR0_OFF
42#endif
43#define OCCR1_INIT_VAL OCCR1_NOLOCK /* No locking */
44
45 .text
46
47 .global startup
48startup:
49 /*
50 * Prevent speculative fetch on device memory due to
51 * uninitialized target registers.
52 * This must be executed before the first branch.
53 */
54 ptabs/u ZERO, tr0
55 ptabs/u ZERO, tr1
56 ptabs/u ZERO, tr2
57 ptabs/u ZERO, tr3
58 ptabs/u ZERO, tr4
59 ptabs/u ZERO, tr5
60 ptabs/u ZERO, tr6
61 ptabs/u ZERO, tr7
62 synci
63
64 /*
65 * Set initial TLB entries for cached and uncached regions.
66 * Note: PTA/BLINK is PIC code, PTABS/BLINK isn't !
67 */
68 /* Clear ITLBs */
69 pta 1f, tr1
70 movi ITLB_FIXED, r21
71 movi ITLB_LAST_VAR_UNRESTRICTED+TLB_STEP, r22
721: putcfg r21, 0, ZERO /* Clear MMUIR[n].PTEH.V */
73 addi r21, TLB_STEP, r21
74 bne r21, r22, tr1
75
76 /* Clear DTLBs */
77 pta 1f, tr1
78 movi DTLB_FIXED, r21
79 movi DTLB_LAST_VAR_UNRESTRICTED+TLB_STEP, r22
801: putcfg r21, 0, ZERO /* Clear MMUDR[n].PTEH.V */
81 addi r21, TLB_STEP, r21
82 bne r21, r22, tr1
83
84 /* Map one big (512Mb) page for ITLB */
85 movi ITLB_FIXED, r21
86 movi MMUIR_TEXT_L, r22 /* PTEL first */
87 putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */
88 movi MMUIR_TEXT_H, r22 /* PTEH last */
89 putcfg r21, 0, r22 /* Set MMUIR[0].PTEH */
90
91 /* Map one big CACHED (512Mb) page for DTLB */
92 movi DTLB_FIXED, r21
93 movi MMUDR_CACHED_L, r22 /* PTEL first */
94 putcfg r21, 1, r22 /* Set MMUDR[0].PTEL */
95 movi MMUDR_CACHED_H, r22 /* PTEH last */
96 putcfg r21, 0, r22 /* Set MMUDR[0].PTEH */
97
98 /* ICache */
99 movi ICCR_BASE, r21
100 movi ICCR0_INIT_VAL, r22
101 movi ICCR1_INIT_VAL, r23
102 putcfg r21, ICCR_REG0, r22
103 putcfg r21, ICCR_REG1, r23
104 synci
105
106 /* OCache */
107 movi OCCR_BASE, r21
108 movi OCCR0_INIT_VAL, r22
109 movi OCCR1_INIT_VAL, r23
110 putcfg r21, OCCR_REG0, r22
111 putcfg r21, OCCR_REG1, r23
112 synco
113
114 /*
115 * Enable the MMU.
116 * From here-on code can be non-PIC.
117 */
118 movi SR_HARMLESS | SR_ENABLE_MMU, r22
119 putcon r22, SSR
120 movi 1f, r22
121 putcon r22, SPC
122 synco
123 rte /* And now go into the hyperspace ... */
1241: /* ... that's the next instruction ! */
125
126 /* Set initial stack pointer */
127 movi datalabel stack_start, r0
128 ld.l r0, 0, r15
129
130 /*
131 * Clear bss
132 */
133 pt 1f, tr1
134 movi datalabel __bss_start, r22
135 movi datalabel _end, r23
1361: st.l r22, 0, ZERO
137 addi r22, 4, r22
138 bne r22, r23, tr1
139
140 /*
141 * Decompress the kernel.
142 */
143 pt decompress_kernel, tr0
144 blink tr0, r18
145
146 /*
147 * Disable the MMU.
148 */
149 movi SR_HARMLESS, r22
150 putcon r22, SSR
151 movi 1f, r22
152 putcon r22, SPC
153 synco
154 rte /* And now go into the hyperspace ... */
1551: /* ... that's the next instruction ! */
156
157 /* Jump into the decompressed kernel */
158 movi datalabel (CONFIG_MEMORY_START + 0x2000)+1, r19
159 ptabs r19, tr0
160 blink tr0, r18
161
162 /* Shouldn't return here, but just in case, loop forever */
163 pt 1f, tr0
1641: blink tr0, ZERO