| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| Russ Anderson | 95ff439 | 2005-04-25 13:19:11 -0700 | [diff] [blame] | 6 | * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved. |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | */ |
| 8 | #ifndef _ASM_IA64_SN_PDA_H |
| 9 | #define _ASM_IA64_SN_PDA_H |
| 10 | |
| 11 | #include <linux/cache.h> |
| 12 | #include <asm/percpu.h> |
| 13 | #include <asm/system.h> |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | |
| 15 | |
| 16 | /* |
| 17 | * CPU-specific data structure. |
| 18 | * |
| 19 | * One of these structures is allocated for each cpu of a NUMA system. |
| 20 | * |
| 21 | * This structure provides a convenient way of keeping together |
| 22 | * all SN per-cpu data structures. |
| 23 | */ |
| 24 | |
| 25 | typedef struct pda_s { |
| 26 | |
| 27 | /* Having a pointer in the begining of PDA tends to increase |
| 28 | * the chance of having this pointer in cache. (Yes something |
| 29 | * else gets pushed out). Doing this reduces the number of memory |
| 30 | * access to all nodepda variables to be one |
| 31 | */ |
| 32 | struct nodepda_s *p_nodepda; /* Pointer to Per node PDA */ |
| 33 | struct subnodepda_s *p_subnodepda; /* Pointer to CPU subnode PDA */ |
| 34 | |
| 35 | /* |
| 36 | * Support for SN LEDs |
| 37 | */ |
| 38 | volatile short *led_address; |
| 39 | u8 led_state; |
| 40 | u8 hb_state; /* supports blinking heartbeat leds */ |
| 41 | unsigned int hb_count; |
| 42 | |
| 43 | unsigned int idle_flag; |
| 44 | |
| 45 | volatile unsigned long *bedrock_rev_id; |
| 46 | volatile unsigned long *pio_write_status_addr; |
| 47 | unsigned long pio_write_status_val; |
| 48 | volatile unsigned long *pio_shub_war_cam_addr; |
| 49 | |
| 50 | unsigned long sn_soft_irr[4]; |
| 51 | unsigned long sn_in_service_ivecs[4]; |
| 52 | short cnodeid_to_nasid_table[MAX_NUMNODES]; |
| 53 | int sn_lb_int_war_ticks; |
| 54 | int sn_last_irq; |
| 55 | int sn_first_irq; |
| 56 | } pda_t; |
| 57 | |
| 58 | |
| 59 | #define CACHE_ALIGN(x) (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1)) |
| 60 | |
| 61 | /* |
| 62 | * PDA |
| 63 | * Per-cpu private data area for each cpu. The PDA is located immediately after |
| 64 | * the IA64 cpu_data area. A full page is allocated for the cp_data area for each |
| 65 | * cpu but only a small amout of the page is actually used. We put the SNIA PDA |
| 66 | * in the same page as the cpu_data area. Note that there is a check in the setup |
| 67 | * code to verify that we don't overflow the page. |
| 68 | * |
| 69 | * Seems like we should should cache-line align the pda so that any changes in the |
| 70 | * size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128 |
| 71 | * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later. |
| 72 | */ |
| 73 | DECLARE_PER_CPU(struct pda_s, pda_percpu); |
| 74 | |
| 75 | #define pda (&__ia64_per_cpu_var(pda_percpu)) |
| 76 | |
| 77 | #define pdacpu(cpu) (&per_cpu(pda_percpu, cpu)) |
| 78 | |
| 79 | #endif /* _ASM_IA64_SN_PDA_H */ |