| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | |
| 2 | #ifndef _PPC_KERNEL_M8260_PCI_H |
| 3 | #define _PPC_KERNEL_M8260_PCI_H |
| 4 | |
| 5 | #include <asm/m8260_pci.h> |
| 6 | |
| 7 | /* |
| 8 | * Local->PCI map (from CPU) controlled by |
| 9 | * MPC826x master window |
| 10 | * |
| 11 | * 0x80000000 - 0xBFFFFFFF Total CPU2PCI space PCIBR0 |
| 12 | * |
| 13 | * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1) |
| 14 | * 0xA0000000 - 0xAFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2) |
| 15 | * 0xB0000000 - 0xB0FFFFFF 32-bit PCI IO (Outbound ATU #3) |
| 16 | * |
| 17 | * PCI->Local map (from PCI) |
| 18 | * MPC826x slave window controlled by |
| 19 | * |
| 20 | * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1) |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * Slave window that allows PCI masters to access MPC826x local memory. |
| 25 | * This window is set up using the first set of Inbound ATU registers |
| 26 | */ |
| 27 | |
| 28 | #ifndef MPC826x_PCI_SLAVE_MEM_LOCAL |
| 29 | #define MPC826x_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart) |
| 30 | #define MPC826x_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart) |
| 31 | #define MPC826x_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize) |
| 32 | #endif |
| 33 | |
| 34 | /* |
| 35 | * This is the window that allows the CPU to access PCI address space. |
| 36 | * It will be setup with the SIU PCIBR0 register. All three PCI master |
| 37 | * windows, which allow the CPU to access PCI prefetch, non prefetch, |
| 38 | * and IO space (see below), must all fit within this window. |
| 39 | */ |
| 40 | #ifndef MPC826x_PCI_BASE |
| 41 | #define MPC826x_PCI_BASE 0x80000000 |
| 42 | #define MPC826x_PCI_MASK 0xc0000000 |
| 43 | #endif |
| 44 | |
| 45 | #ifndef MPC826x_PCI_LOWER_MEM |
| 46 | #define MPC826x_PCI_LOWER_MEM 0x80000000 |
| 47 | #define MPC826x_PCI_UPPER_MEM 0x9fffffff |
| 48 | #define MPC826x_PCI_MEM_OFFSET 0x00000000 |
| 49 | #endif |
| 50 | |
| 51 | #ifndef MPC826x_PCI_LOWER_MMIO |
| 52 | #define MPC826x_PCI_LOWER_MMIO 0xa0000000 |
| 53 | #define MPC826x_PCI_UPPER_MMIO 0xafffffff |
| 54 | #define MPC826x_PCI_MMIO_OFFSET 0x00000000 |
| 55 | #endif |
| 56 | |
| 57 | #ifndef MPC826x_PCI_LOWER_IO |
| 58 | #define MPC826x_PCI_LOWER_IO 0x00000000 |
| 59 | #define MPC826x_PCI_UPPER_IO 0x00ffffff |
| 60 | #define MPC826x_PCI_IO_BASE 0xb0000000 |
| 61 | #define MPC826x_PCI_IO_SIZE 0x01000000 |
| 62 | #endif |
| 63 | |
| 64 | #ifndef _IO_BASE |
| 65 | #define _IO_BASE isa_io_base |
| 66 | #endif |
| 67 | |
| 68 | #ifdef CONFIG_8260_PCI9 |
| 69 | struct pci_controller; |
| 70 | extern void setup_m8260_indirect_pci(struct pci_controller* hose, |
| 71 | u32 cfg_addr, u32 cfg_data); |
| 72 | #else |
| 73 | #define setup_m8260_indirect_pci setup_indirect_pci |
| 74 | #endif |
| 75 | |
| 76 | #endif /* _PPC_KERNEL_M8260_PCI_H */ |