| Hirokazu Takata | 9287d95 | 2006-01-06 00:18:41 -0800 | [diff] [blame] | 1 | /* | 
 | 2 |  *  linux/arch/m32r/kernel/setup_m32104ut.c | 
 | 3 |  * | 
 | 4 |  *  Setup routines for M32104UT Board | 
 | 5 |  * | 
 | 6 |  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata, | 
 | 7 |  *                           Hitoshi Yamamoto, Mamoru Sakugawa, | 
 | 8 |  *                           Naoto Sugai, Hayato Fujiwara | 
 | 9 |  */ | 
 | 10 |  | 
 | 11 | #include <linux/config.h> | 
 | 12 | #include <linux/irq.h> | 
 | 13 | #include <linux/kernel.h> | 
 | 14 | #include <linux/init.h> | 
 | 15 | #include <linux/device.h> | 
 | 16 |  | 
 | 17 | #include <asm/system.h> | 
 | 18 | #include <asm/m32r.h> | 
 | 19 | #include <asm/io.h> | 
 | 20 |  | 
 | 21 | #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long))) | 
 | 22 |  | 
 | 23 | #ifndef CONFIG_SMP | 
 | 24 | typedef struct { | 
 | 25 | 	unsigned long icucr;  /* ICU Control Register */ | 
 | 26 | } icu_data_t; | 
 | 27 | #endif /* CONFIG_SMP */ | 
 | 28 |  | 
 | 29 | icu_data_t icu_data[NR_IRQS]; | 
 | 30 |  | 
 | 31 | static void disable_m32104ut_irq(unsigned int irq) | 
 | 32 | { | 
 | 33 | 	unsigned long port, data; | 
 | 34 |  | 
 | 35 | 	port = irq2port(irq); | 
 | 36 | 	data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7; | 
 | 37 | 	outl(data, port); | 
 | 38 | } | 
 | 39 |  | 
 | 40 | static void enable_m32104ut_irq(unsigned int irq) | 
 | 41 | { | 
 | 42 | 	unsigned long port, data; | 
 | 43 |  | 
 | 44 | 	port = irq2port(irq); | 
 | 45 | 	data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; | 
 | 46 | 	outl(data, port); | 
 | 47 | } | 
 | 48 |  | 
 | 49 | static void mask_and_ack_m32104ut(unsigned int irq) | 
 | 50 | { | 
 | 51 | 	disable_m32104ut_irq(irq); | 
 | 52 | } | 
 | 53 |  | 
 | 54 | static void end_m32104ut_irq(unsigned int irq) | 
 | 55 | { | 
 | 56 | 	enable_m32104ut_irq(irq); | 
 | 57 | } | 
 | 58 |  | 
 | 59 | static unsigned int startup_m32104ut_irq(unsigned int irq) | 
 | 60 | { | 
 | 61 | 	enable_m32104ut_irq(irq); | 
 | 62 | 	return (0); | 
 | 63 | } | 
 | 64 |  | 
 | 65 | static void shutdown_m32104ut_irq(unsigned int irq) | 
 | 66 | { | 
 | 67 | 	unsigned long port; | 
 | 68 |  | 
 | 69 | 	port = irq2port(irq); | 
 | 70 | 	outl(M32R_ICUCR_ILEVEL7, port); | 
 | 71 | } | 
 | 72 |  | 
 | 73 | static struct hw_interrupt_type m32104ut_irq_type = | 
 | 74 | { | 
 | 75 | 	.typename = "M32104UT-IRQ", | 
 | 76 | 	.startup = startup_m32104ut_irq, | 
 | 77 | 	.shutdown = shutdown_m32104ut_irq, | 
 | 78 | 	.enable = enable_m32104ut_irq, | 
 | 79 | 	.disable = disable_m32104ut_irq, | 
 | 80 | 	.ack = mask_and_ack_m32104ut, | 
 | 81 | 	.end = end_m32104ut_irq | 
 | 82 | }; | 
 | 83 |  | 
 | 84 | void __init init_IRQ(void) | 
 | 85 | { | 
 | 86 | 	static int once = 0; | 
 | 87 |  | 
 | 88 | 	if (once) | 
 | 89 | 		return; | 
 | 90 | 	else | 
 | 91 | 		once++; | 
 | 92 |  | 
 | 93 | #if defined(CONFIG_SMC91X) | 
 | 94 | 	/* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ | 
 | 95 | 	irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; | 
 | 96 | 	irq_desc[M32R_IRQ_INT0].handler = &m32104ut_irq_type; | 
 | 97 | 	irq_desc[M32R_IRQ_INT0].action = 0; | 
 | 98 | 	irq_desc[M32R_IRQ_INT0].depth = 1; | 
 | 99 | 	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */ | 
 | 100 | 	disable_m32104ut_irq(M32R_IRQ_INT0); | 
 | 101 | #endif  /* CONFIG_SMC91X */ | 
 | 102 |  | 
 | 103 | 	/* MFT2 : system timer */ | 
 | 104 | 	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 
 | 105 | 	irq_desc[M32R_IRQ_MFT2].handler = &m32104ut_irq_type; | 
 | 106 | 	irq_desc[M32R_IRQ_MFT2].action = 0; | 
 | 107 | 	irq_desc[M32R_IRQ_MFT2].depth = 1; | 
 | 108 | 	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 
 | 109 | 	disable_m32104ut_irq(M32R_IRQ_MFT2); | 
 | 110 |  | 
 | 111 | #ifdef CONFIG_SERIAL_M32R_SIO | 
 | 112 | 	/* SIO0_R : uart receive data */ | 
 | 113 | 	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 
 | 114 | 	irq_desc[M32R_IRQ_SIO0_R].handler = &m32104ut_irq_type; | 
 | 115 | 	irq_desc[M32R_IRQ_SIO0_R].action = 0; | 
 | 116 | 	irq_desc[M32R_IRQ_SIO0_R].depth = 1; | 
 | 117 | 	icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; | 
 | 118 | 	disable_m32104ut_irq(M32R_IRQ_SIO0_R); | 
 | 119 |  | 
 | 120 | 	/* SIO0_S : uart send data */ | 
 | 121 | 	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 
 | 122 | 	irq_desc[M32R_IRQ_SIO0_S].handler = &m32104ut_irq_type; | 
 | 123 | 	irq_desc[M32R_IRQ_SIO0_S].action = 0; | 
 | 124 | 	irq_desc[M32R_IRQ_SIO0_S].depth = 1; | 
 | 125 | 	icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; | 
 | 126 | 	disable_m32104ut_irq(M32R_IRQ_SIO0_S); | 
 | 127 | #endif /* CONFIG_SERIAL_M32R_SIO */ | 
 | 128 | } | 
 | 129 |  | 
 | 130 | #if defined(CONFIG_SMC91X) | 
 | 131 |  | 
 | 132 | #define LAN_IOSTART     0x300 | 
 | 133 | #define LAN_IOEND       0x320 | 
 | 134 | static struct resource smc91x_resources[] = { | 
 | 135 | 	[0] = { | 
 | 136 | 		.start  = (LAN_IOSTART), | 
 | 137 | 		.end    = (LAN_IOEND), | 
 | 138 | 		.flags  = IORESOURCE_MEM, | 
 | 139 | 	}, | 
 | 140 | 	[1] = { | 
 | 141 | 		.start  = M32R_IRQ_INT0, | 
 | 142 | 		.end    = M32R_IRQ_INT0, | 
 | 143 | 		.flags  = IORESOURCE_IRQ, | 
 | 144 | 	} | 
 | 145 | }; | 
 | 146 |  | 
 | 147 | static struct platform_device smc91x_device = { | 
 | 148 | 	.name		= "smc91x", | 
 | 149 | 	.id		= 0, | 
 | 150 | 	.num_resources  = ARRAY_SIZE(smc91x_resources), | 
 | 151 | 	.resource       = smc91x_resources, | 
 | 152 | }; | 
 | 153 | #endif | 
 | 154 |  | 
 | 155 | static int __init platform_init(void) | 
 | 156 | { | 
 | 157 | #if defined(CONFIG_SMC91X) | 
 | 158 | 	platform_device_register(&smc91x_device); | 
 | 159 | #endif | 
 | 160 | 	return 0; | 
 | 161 | } | 
 | 162 | arch_initcall(platform_init); |