| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* linux/include/asm/arch-s3c2410/regs-iis.h |
| 2 | * |
| 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * S3C2410 IIS register definition |
| 11 | * |
| 12 | * Changelog: |
| 13 | * 19-06-2003 BJD Created file |
| 14 | * 26-06-2003 BJD Finished off definitions for register addresses |
| 15 | * 12-03-2004 BJD Updated include protection |
| 16 | * 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL |
| 17 | */ |
| 18 | |
| 19 | #ifndef __ASM_ARCH_REGS_IIS_H |
| 20 | #define __ASM_ARCH_REGS_IIS_H |
| 21 | |
| 22 | #define S3C2410_IISCON (0x00) |
| 23 | |
| 24 | #define S3C2440_IISCON_MPLL (1<<9) |
| 25 | #define S3C2410_IISCON_LRINDEX (1<<8) |
| 26 | #define S3C2410_IISCON_TXFIFORDY (1<<7) |
| 27 | #define S3C2410_IISCON_RXFIFORDY (1<<6) |
| 28 | #define S3C2410_IISCON_TXDMAEN (1<<5) |
| 29 | #define S3C2410_IISCON_RXDMAEN (1<<4) |
| 30 | #define S3C2410_IISCON_TXIDLE (1<<3) |
| 31 | #define S3C2410_IISCON_RXIDLE (1<<2) |
| 32 | #define S3C2410_IISCON_IISEN (1<<0) |
| 33 | |
| 34 | #define S3C2410_IISMOD (0x04) |
| 35 | |
| 36 | #define S3C2410_IISMOD_SLAVE (1<<8) |
| 37 | #define S3C2410_IISMOD_NOXFER (0<<6) |
| 38 | #define S3C2410_IISMOD_RXMODE (1<<6) |
| 39 | #define S3C2410_IISMOD_TXMODE (2<<6) |
| 40 | #define S3C2410_IISMOD_TXRXMODE (3<<6) |
| 41 | #define S3C2410_IISMOD_LR_LLOW (0<<5) |
| 42 | #define S3C2410_IISMOD_LR_RLOW (1<<5) |
| 43 | #define S3C2410_IISMOD_IIS (0<<4) |
| 44 | #define S3C2410_IISMOD_MSB (1<<4) |
| 45 | #define S3C2410_IISMOD_8BIT (0<<3) |
| 46 | #define S3C2410_IISMOD_16BIT (1<<3) |
| 47 | #define S3C2410_IISMOD_BITMASK (1<<3) |
| 48 | #define S3C2410_IISMOD_256FS (0<<1) |
| 49 | #define S3C2410_IISMOD_384FS (1<<1) |
| 50 | #define S3C2410_IISMOD_16FS (0<<0) |
| 51 | #define S3C2410_IISMOD_32FS (1<<0) |
| 52 | #define S3C2410_IISMOD_48FS (2<<0) |
| 53 | |
| 54 | #define S3C2410_IISPSR (0x08) |
| 55 | #define S3C2410_IISPSR_INTMASK (31<<5) |
| 56 | #define S3C2410_IISPSR_INTSHIFT (5) |
| 57 | #define S3C2410_IISPSR_EXTMASK (31<<0) |
| 58 | #define S3C2410_IISPSR_EXTSHFIT (0) |
| 59 | |
| 60 | #define S3C2410_IISFCON (0x0c) |
| 61 | |
| 62 | #define S3C2410_IISFCON_TXDMA (1<<15) |
| 63 | #define S3C2410_IISFCON_RXDMA (1<<14) |
| 64 | #define S3C2410_IISFCON_TXENABLE (1<<13) |
| 65 | #define S3C2410_IISFCON_RXENABLE (1<<12) |
| 66 | #define S3C2410_IISFCON_TXMASK (0x3f << 6) |
| 67 | #define S3C2410_IISFCON_TXSHIFT (6) |
| 68 | #define S3C2410_IISFCON_RXMASK (0x3f) |
| 69 | #define S3C2410_IISFCON_RXSHIFT (0) |
| 70 | |
| 71 | #define S3C2410_IISFIFO (0x10) |
| 72 | #endif /* __ASM_ARCH_REGS_IIS_H */ |