| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * This file is subject to the terms and conditions of the GNU General Public |
| 4 | * License. See the file "COPYING" in the main directory of this archive |
| 5 | * for more details. |
| 6 | * |
| 7 | * Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved. |
| 8 | */ |
| 9 | |
| 10 | #ifndef _ASM_IA64_SN_SHUB_MMR_H |
| 11 | #define _ASM_IA64_SN_SHUB_MMR_H |
| 12 | |
| 13 | /* ==================================================================== */ |
| 14 | /* Register "SH_IPI_INT" */ |
| 15 | /* SHub Inter-Processor Interrupt Registers */ |
| 16 | /* ==================================================================== */ |
| 17 | #define SH1_IPI_INT 0x0000000110000380 |
| 18 | #define SH2_IPI_INT 0x0000000010000380 |
| 19 | |
| 20 | /* SH_IPI_INT_TYPE */ |
| 21 | /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ |
| 22 | #define SH_IPI_INT_TYPE_SHFT 0 |
| 23 | #define SH_IPI_INT_TYPE_MASK 0x0000000000000007 |
| 24 | |
| 25 | /* SH_IPI_INT_AGT */ |
| 26 | /* Description: Agent, must be 0 for SHub */ |
| 27 | #define SH_IPI_INT_AGT_SHFT 3 |
| 28 | #define SH_IPI_INT_AGT_MASK 0x0000000000000008 |
| 29 | |
| 30 | /* SH_IPI_INT_PID */ |
| 31 | /* Description: Processor ID, same setting as on targeted McKinley */ |
| 32 | #define SH_IPI_INT_PID_SHFT 4 |
| 33 | #define SH_IPI_INT_PID_MASK 0x00000000000ffff0 |
| 34 | |
| 35 | /* SH_IPI_INT_BASE */ |
| 36 | /* Description: Optional interrupt vector area, 2MB aligned */ |
| 37 | #define SH_IPI_INT_BASE_SHFT 21 |
| 38 | #define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000 |
| 39 | |
| 40 | /* SH_IPI_INT_IDX */ |
| 41 | /* Description: Targeted McKinley interrupt vector */ |
| 42 | #define SH_IPI_INT_IDX_SHFT 52 |
| 43 | #define SH_IPI_INT_IDX_MASK 0x0ff0000000000000 |
| 44 | |
| 45 | /* SH_IPI_INT_SEND */ |
| 46 | /* Description: Send Interrupt Message to PI, This generates a puls */ |
| 47 | #define SH_IPI_INT_SEND_SHFT 63 |
| 48 | #define SH_IPI_INT_SEND_MASK 0x8000000000000000 |
| 49 | |
| 50 | /* ==================================================================== */ |
| 51 | /* Register "SH_EVENT_OCCURRED" */ |
| 52 | /* SHub Interrupt Event Occurred */ |
| 53 | /* ==================================================================== */ |
| 54 | #define SH1_EVENT_OCCURRED 0x0000000110010000 |
| 55 | #define SH1_EVENT_OCCURRED_ALIAS 0x0000000110010008 |
| 56 | #define SH2_EVENT_OCCURRED 0x0000000010010000 |
| 57 | #define SH2_EVENT_OCCURRED_ALIAS 0x0000000010010008 |
| 58 | |
| 59 | /* ==================================================================== */ |
| 60 | /* Register "SH_PI_CAM_CONTROL" */ |
| 61 | /* CRB CAM MMR Access Control */ |
| 62 | /* ==================================================================== */ |
| 63 | #define SH1_PI_CAM_CONTROL 0x0000000120050300 |
| 64 | |
| 65 | /* ==================================================================== */ |
| 66 | /* Register "SH_SHUB_ID" */ |
| 67 | /* SHub ID Number */ |
| 68 | /* ==================================================================== */ |
| 69 | #define SH1_SHUB_ID 0x0000000110060580 |
| 70 | #define SH1_SHUB_ID_REVISION_SHFT 28 |
| 71 | #define SH1_SHUB_ID_REVISION_MASK 0x00000000f0000000 |
| 72 | |
| 73 | /* ==================================================================== */ |
| 74 | /* Register "SH_RTC" */ |
| 75 | /* Real-time Clock */ |
| 76 | /* ==================================================================== */ |
| 77 | #define SH1_RTC 0x00000001101c0000 |
| 78 | #define SH2_RTC 0x00000002101c0000 |
| 79 | #define SH_RTC_MASK 0x007fffffffffffff |
| 80 | |
| 81 | /* ==================================================================== */ |
| 82 | /* Register "SH_PIO_WRITE_STATUS_0|1" */ |
| 83 | /* PIO Write Status for CPU 0 & 1 */ |
| 84 | /* ==================================================================== */ |
| 85 | #define SH1_PIO_WRITE_STATUS_0 0x0000000120070200 |
| 86 | #define SH1_PIO_WRITE_STATUS_1 0x0000000120070280 |
| 87 | #define SH2_PIO_WRITE_STATUS_0 0x0000000020070200 |
| 88 | #define SH2_PIO_WRITE_STATUS_1 0x0000000020070280 |
| 89 | #define SH2_PIO_WRITE_STATUS_2 0x0000000020070300 |
| 90 | #define SH2_PIO_WRITE_STATUS_3 0x0000000020070380 |
| 91 | |
| 92 | /* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ |
| 93 | /* Description: Deadlock response detected */ |
| 94 | #define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1 |
| 95 | #define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK 0x0000000000000002 |
| 96 | |
| 97 | /* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ |
| 98 | /* Description: Count of currently pending PIO writes */ |
| 99 | #define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56 |
| 100 | #define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 |
| 101 | |
| 102 | /* ==================================================================== */ |
| 103 | /* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ |
| 104 | /* ==================================================================== */ |
| 105 | #define SH1_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 |
| 106 | #define SH2_PIO_WRITE_STATUS_0_ALIAS 0x0000000020070208 |
| 107 | |
| 108 | /* ==================================================================== */ |
| 109 | /* Register "SH_EVENT_OCCURRED" */ |
| 110 | /* SHub Interrupt Event Occurred */ |
| 111 | /* ==================================================================== */ |
| 112 | /* SH_EVENT_OCCURRED_UART_INT */ |
| 113 | /* Description: Pending Junk Bus UART Interrupt */ |
| 114 | #define SH_EVENT_OCCURRED_UART_INT_SHFT 20 |
| 115 | #define SH_EVENT_OCCURRED_UART_INT_MASK 0x0000000000100000 |
| 116 | |
| 117 | /* SH_EVENT_OCCURRED_IPI_INT */ |
| 118 | /* Description: Pending IPI Interrupt */ |
| 119 | #define SH_EVENT_OCCURRED_IPI_INT_SHFT 28 |
| 120 | #define SH_EVENT_OCCURRED_IPI_INT_MASK 0x0000000010000000 |
| 121 | |
| 122 | /* SH_EVENT_OCCURRED_II_INT0 */ |
| 123 | /* Description: Pending II 0 Interrupt */ |
| 124 | #define SH_EVENT_OCCURRED_II_INT0_SHFT 29 |
| 125 | #define SH_EVENT_OCCURRED_II_INT0_MASK 0x0000000020000000 |
| 126 | |
| 127 | /* SH_EVENT_OCCURRED_II_INT1 */ |
| 128 | /* Description: Pending II 1 Interrupt */ |
| 129 | #define SH_EVENT_OCCURRED_II_INT1_SHFT 30 |
| 130 | #define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 |
| 131 | |
| Colin Ngam | be539c7 | 2005-04-25 13:06:28 -0700 | [diff] [blame^] | 132 | /* SH2_EVENT_OCCURRED_EXTIO_INT2 */ |
| 133 | /* Description: Pending SHUB 2 EXT IO INT2 */ |
| 134 | #define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33 |
| 135 | #define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK 0x0000000200000000 |
| 136 | |
| 137 | /* SH2_EVENT_OCCURRED_EXTIO_INT3 */ |
| 138 | /* Description: Pending SHUB 2 EXT IO INT3 */ |
| 139 | #define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34 |
| 140 | #define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK 0x0000000400000000 |
| 141 | |
| 142 | #define SH_ALL_INT_MASK \ |
| 143 | (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \ |
| 144 | SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \ |
| 145 | SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \ |
| 146 | SH2_EVENT_OCCURRED_EXTIO_INT3_MASK) |
| 147 | |
| 148 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | /* ==================================================================== */ |
| 150 | /* LEDS */ |
| 151 | /* ==================================================================== */ |
| 152 | #define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL |
| 153 | #define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL |
| 154 | #define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL |
| 155 | #define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL |
| 156 | |
| 157 | #define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL |
| 158 | #define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL |
| 159 | #define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL |
| 160 | #define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL |
| 161 | |
| 162 | /* ==================================================================== */ |
| 163 | /* Register "SH1_PTC_0" */ |
| 164 | /* Puge Translation Cache Message Configuration Information */ |
| 165 | /* ==================================================================== */ |
| 166 | #define SH1_PTC_0 0x00000001101a0000 |
| 167 | |
| 168 | /* SH1_PTC_0_A */ |
| 169 | /* Description: Type */ |
| 170 | #define SH1_PTC_0_A_SHFT 0 |
| 171 | |
| 172 | /* SH1_PTC_0_PS */ |
| 173 | /* Description: Page Size */ |
| 174 | #define SH1_PTC_0_PS_SHFT 2 |
| 175 | |
| 176 | /* SH1_PTC_0_RID */ |
| 177 | /* Description: Region ID */ |
| 178 | #define SH1_PTC_0_RID_SHFT 8 |
| 179 | |
| 180 | /* SH1_PTC_0_START */ |
| 181 | /* Description: Start */ |
| 182 | #define SH1_PTC_0_START_SHFT 63 |
| 183 | |
| 184 | /* ==================================================================== */ |
| 185 | /* Register "SH1_PTC_1" */ |
| 186 | /* Puge Translation Cache Message Configuration Information */ |
| 187 | /* ==================================================================== */ |
| 188 | #define SH1_PTC_1 0x00000001101a0080 |
| 189 | |
| 190 | /* SH1_PTC_1_START */ |
| 191 | /* Description: PTC_1 Start */ |
| 192 | #define SH1_PTC_1_START_SHFT 63 |
| 193 | |
| 194 | |
| 195 | /* ==================================================================== */ |
| 196 | /* Register "SH2_PTC" */ |
| 197 | /* Puge Translation Cache Message Configuration Information */ |
| 198 | /* ==================================================================== */ |
| 199 | #define SH2_PTC 0x0000000170000000 |
| 200 | |
| 201 | /* SH2_PTC_A */ |
| 202 | /* Description: Type */ |
| 203 | #define SH2_PTC_A_SHFT 0 |
| 204 | |
| 205 | /* SH2_PTC_PS */ |
| 206 | /* Description: Page Size */ |
| 207 | #define SH2_PTC_PS_SHFT 2 |
| 208 | |
| 209 | /* SH2_PTC_RID */ |
| 210 | /* Description: Region ID */ |
| 211 | #define SH2_PTC_RID_SHFT 4 |
| 212 | |
| 213 | /* SH2_PTC_START */ |
| 214 | /* Description: Start */ |
| 215 | #define SH2_PTC_START_SHFT 63 |
| 216 | |
| 217 | /* SH2_PTC_ADDR_RID */ |
| 218 | /* Description: Region ID */ |
| 219 | #define SH2_PTC_ADDR_SHFT 4 |
| 220 | #define SH2_PTC_ADDR_MASK 0x1ffffffffffff000 |
| 221 | |
| 222 | /* ==================================================================== */ |
| 223 | /* Register "SH_RTC1_INT_CONFIG" */ |
| 224 | /* SHub RTC 1 Interrupt Config Registers */ |
| 225 | /* ==================================================================== */ |
| 226 | |
| 227 | #define SH1_RTC1_INT_CONFIG 0x0000000110001480 |
| 228 | #define SH2_RTC1_INT_CONFIG 0x0000000010001480 |
| 229 | #define SH_RTC1_INT_CONFIG_MASK 0x0ff3ffffffefffff |
| 230 | #define SH_RTC1_INT_CONFIG_INIT 0x0000000000000000 |
| 231 | |
| 232 | /* SH_RTC1_INT_CONFIG_TYPE */ |
| 233 | /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ |
| 234 | #define SH_RTC1_INT_CONFIG_TYPE_SHFT 0 |
| 235 | #define SH_RTC1_INT_CONFIG_TYPE_MASK 0x0000000000000007 |
| 236 | |
| 237 | /* SH_RTC1_INT_CONFIG_AGT */ |
| 238 | /* Description: Agent, must be 0 for SHub */ |
| 239 | #define SH_RTC1_INT_CONFIG_AGT_SHFT 3 |
| 240 | #define SH_RTC1_INT_CONFIG_AGT_MASK 0x0000000000000008 |
| 241 | |
| 242 | /* SH_RTC1_INT_CONFIG_PID */ |
| 243 | /* Description: Processor ID, same setting as on targeted McKinley */ |
| 244 | #define SH_RTC1_INT_CONFIG_PID_SHFT 4 |
| 245 | #define SH_RTC1_INT_CONFIG_PID_MASK 0x00000000000ffff0 |
| 246 | |
| 247 | /* SH_RTC1_INT_CONFIG_BASE */ |
| 248 | /* Description: Optional interrupt vector area, 2MB aligned */ |
| 249 | #define SH_RTC1_INT_CONFIG_BASE_SHFT 21 |
| 250 | #define SH_RTC1_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 |
| 251 | |
| 252 | /* SH_RTC1_INT_CONFIG_IDX */ |
| 253 | /* Description: Targeted McKinley interrupt vector */ |
| 254 | #define SH_RTC1_INT_CONFIG_IDX_SHFT 52 |
| 255 | #define SH_RTC1_INT_CONFIG_IDX_MASK 0x0ff0000000000000 |
| 256 | |
| 257 | /* ==================================================================== */ |
| 258 | /* Register "SH_RTC1_INT_ENABLE" */ |
| 259 | /* SHub RTC 1 Interrupt Enable Registers */ |
| 260 | /* ==================================================================== */ |
| 261 | |
| 262 | #define SH1_RTC1_INT_ENABLE 0x0000000110001500 |
| 263 | #define SH2_RTC1_INT_ENABLE 0x0000000010001500 |
| 264 | #define SH_RTC1_INT_ENABLE_MASK 0x0000000000000001 |
| 265 | #define SH_RTC1_INT_ENABLE_INIT 0x0000000000000000 |
| 266 | |
| 267 | /* SH_RTC1_INT_ENABLE_RTC1_ENABLE */ |
| 268 | /* Description: Enable RTC 1 Interrupt */ |
| 269 | #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0 |
| 270 | #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK 0x0000000000000001 |
| 271 | |
| 272 | /* ==================================================================== */ |
| 273 | /* Register "SH_RTC2_INT_CONFIG" */ |
| 274 | /* SHub RTC 2 Interrupt Config Registers */ |
| 275 | /* ==================================================================== */ |
| 276 | |
| 277 | #define SH1_RTC2_INT_CONFIG 0x0000000110001580 |
| 278 | #define SH2_RTC2_INT_CONFIG 0x0000000010001580 |
| 279 | #define SH_RTC2_INT_CONFIG_MASK 0x0ff3ffffffefffff |
| 280 | #define SH_RTC2_INT_CONFIG_INIT 0x0000000000000000 |
| 281 | |
| 282 | /* SH_RTC2_INT_CONFIG_TYPE */ |
| 283 | /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ |
| 284 | #define SH_RTC2_INT_CONFIG_TYPE_SHFT 0 |
| 285 | #define SH_RTC2_INT_CONFIG_TYPE_MASK 0x0000000000000007 |
| 286 | |
| 287 | /* SH_RTC2_INT_CONFIG_AGT */ |
| 288 | /* Description: Agent, must be 0 for SHub */ |
| 289 | #define SH_RTC2_INT_CONFIG_AGT_SHFT 3 |
| 290 | #define SH_RTC2_INT_CONFIG_AGT_MASK 0x0000000000000008 |
| 291 | |
| 292 | /* SH_RTC2_INT_CONFIG_PID */ |
| 293 | /* Description: Processor ID, same setting as on targeted McKinley */ |
| 294 | #define SH_RTC2_INT_CONFIG_PID_SHFT 4 |
| 295 | #define SH_RTC2_INT_CONFIG_PID_MASK 0x00000000000ffff0 |
| 296 | |
| 297 | /* SH_RTC2_INT_CONFIG_BASE */ |
| 298 | /* Description: Optional interrupt vector area, 2MB aligned */ |
| 299 | #define SH_RTC2_INT_CONFIG_BASE_SHFT 21 |
| 300 | #define SH_RTC2_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 |
| 301 | |
| 302 | /* SH_RTC2_INT_CONFIG_IDX */ |
| 303 | /* Description: Targeted McKinley interrupt vector */ |
| 304 | #define SH_RTC2_INT_CONFIG_IDX_SHFT 52 |
| 305 | #define SH_RTC2_INT_CONFIG_IDX_MASK 0x0ff0000000000000 |
| 306 | |
| 307 | /* ==================================================================== */ |
| 308 | /* Register "SH_RTC2_INT_ENABLE" */ |
| 309 | /* SHub RTC 2 Interrupt Enable Registers */ |
| 310 | /* ==================================================================== */ |
| 311 | |
| 312 | #define SH1_RTC2_INT_ENABLE 0x0000000110001600 |
| 313 | #define SH2_RTC2_INT_ENABLE 0x0000000010001600 |
| 314 | #define SH_RTC2_INT_ENABLE_MASK 0x0000000000000001 |
| 315 | #define SH_RTC2_INT_ENABLE_INIT 0x0000000000000000 |
| 316 | |
| 317 | /* SH_RTC2_INT_ENABLE_RTC2_ENABLE */ |
| 318 | /* Description: Enable RTC 2 Interrupt */ |
| 319 | #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0 |
| 320 | #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK 0x0000000000000001 |
| 321 | |
| 322 | /* ==================================================================== */ |
| 323 | /* Register "SH_RTC3_INT_CONFIG" */ |
| 324 | /* SHub RTC 3 Interrupt Config Registers */ |
| 325 | /* ==================================================================== */ |
| 326 | |
| 327 | #define SH1_RTC3_INT_CONFIG 0x0000000110001680 |
| 328 | #define SH2_RTC3_INT_CONFIG 0x0000000010001680 |
| 329 | #define SH_RTC3_INT_CONFIG_MASK 0x0ff3ffffffefffff |
| 330 | #define SH_RTC3_INT_CONFIG_INIT 0x0000000000000000 |
| 331 | |
| 332 | /* SH_RTC3_INT_CONFIG_TYPE */ |
| 333 | /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ |
| 334 | #define SH_RTC3_INT_CONFIG_TYPE_SHFT 0 |
| 335 | #define SH_RTC3_INT_CONFIG_TYPE_MASK 0x0000000000000007 |
| 336 | |
| 337 | /* SH_RTC3_INT_CONFIG_AGT */ |
| 338 | /* Description: Agent, must be 0 for SHub */ |
| 339 | #define SH_RTC3_INT_CONFIG_AGT_SHFT 3 |
| 340 | #define SH_RTC3_INT_CONFIG_AGT_MASK 0x0000000000000008 |
| 341 | |
| 342 | /* SH_RTC3_INT_CONFIG_PID */ |
| 343 | /* Description: Processor ID, same setting as on targeted McKinley */ |
| 344 | #define SH_RTC3_INT_CONFIG_PID_SHFT 4 |
| 345 | #define SH_RTC3_INT_CONFIG_PID_MASK 0x00000000000ffff0 |
| 346 | |
| 347 | /* SH_RTC3_INT_CONFIG_BASE */ |
| 348 | /* Description: Optional interrupt vector area, 2MB aligned */ |
| 349 | #define SH_RTC3_INT_CONFIG_BASE_SHFT 21 |
| 350 | #define SH_RTC3_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 |
| 351 | |
| 352 | /* SH_RTC3_INT_CONFIG_IDX */ |
| 353 | /* Description: Targeted McKinley interrupt vector */ |
| 354 | #define SH_RTC3_INT_CONFIG_IDX_SHFT 52 |
| 355 | #define SH_RTC3_INT_CONFIG_IDX_MASK 0x0ff0000000000000 |
| 356 | |
| 357 | /* ==================================================================== */ |
| 358 | /* Register "SH_RTC3_INT_ENABLE" */ |
| 359 | /* SHub RTC 3 Interrupt Enable Registers */ |
| 360 | /* ==================================================================== */ |
| 361 | |
| 362 | #define SH1_RTC3_INT_ENABLE 0x0000000110001700 |
| 363 | #define SH2_RTC3_INT_ENABLE 0x0000000010001700 |
| 364 | #define SH_RTC3_INT_ENABLE_MASK 0x0000000000000001 |
| 365 | #define SH_RTC3_INT_ENABLE_INIT 0x0000000000000000 |
| 366 | |
| 367 | /* SH_RTC3_INT_ENABLE_RTC3_ENABLE */ |
| 368 | /* Description: Enable RTC 3 Interrupt */ |
| 369 | #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0 |
| 370 | #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK 0x0000000000000001 |
| 371 | |
| 372 | /* SH_EVENT_OCCURRED_RTC1_INT */ |
| 373 | /* Description: Pending RTC 1 Interrupt */ |
| 374 | #define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24 |
| 375 | #define SH_EVENT_OCCURRED_RTC1_INT_MASK 0x0000000001000000 |
| 376 | |
| 377 | /* SH_EVENT_OCCURRED_RTC2_INT */ |
| 378 | /* Description: Pending RTC 2 Interrupt */ |
| 379 | #define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25 |
| 380 | #define SH_EVENT_OCCURRED_RTC2_INT_MASK 0x0000000002000000 |
| 381 | |
| 382 | /* SH_EVENT_OCCURRED_RTC3_INT */ |
| 383 | /* Description: Pending RTC 3 Interrupt */ |
| 384 | #define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26 |
| 385 | #define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 |
| 386 | |
| 387 | /* ==================================================================== */ |
| 388 | /* Register "SH_INT_CMPB" */ |
| 389 | /* RTC Compare Value for Processor B */ |
| 390 | /* ==================================================================== */ |
| 391 | |
| 392 | #define SH1_INT_CMPB 0x00000001101b0080 |
| 393 | #define SH2_INT_CMPB 0x00000000101b0080 |
| 394 | #define SH_INT_CMPB_MASK 0x007fffffffffffff |
| 395 | #define SH_INT_CMPB_INIT 0x0000000000000000 |
| 396 | |
| 397 | /* SH_INT_CMPB_REAL_TIME_CMPB */ |
| 398 | /* Description: Real Time Clock Compare */ |
| 399 | #define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 |
| 400 | #define SH_INT_CMPB_REAL_TIME_CMPB_MASK 0x007fffffffffffff |
| 401 | |
| 402 | /* ==================================================================== */ |
| 403 | /* Register "SH_INT_CMPC" */ |
| 404 | /* RTC Compare Value for Processor C */ |
| 405 | /* ==================================================================== */ |
| 406 | |
| 407 | #define SH1_INT_CMPC 0x00000001101b0100 |
| 408 | #define SH2_INT_CMPC 0x00000000101b0100 |
| 409 | #define SH_INT_CMPC_MASK 0x007fffffffffffff |
| 410 | #define SH_INT_CMPC_INIT 0x0000000000000000 |
| 411 | |
| 412 | /* SH_INT_CMPC_REAL_TIME_CMPC */ |
| 413 | /* Description: Real Time Clock Compare */ |
| 414 | #define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 |
| 415 | #define SH_INT_CMPC_REAL_TIME_CMPC_MASK 0x007fffffffffffff |
| 416 | |
| 417 | /* ==================================================================== */ |
| 418 | /* Register "SH_INT_CMPD" */ |
| 419 | /* RTC Compare Value for Processor D */ |
| 420 | /* ==================================================================== */ |
| 421 | |
| 422 | #define SH1_INT_CMPD 0x00000001101b0180 |
| 423 | #define SH2_INT_CMPD 0x00000000101b0180 |
| 424 | #define SH_INT_CMPD_MASK 0x007fffffffffffff |
| 425 | #define SH_INT_CMPD_INIT 0x0000000000000000 |
| 426 | |
| 427 | /* SH_INT_CMPD_REAL_TIME_CMPD */ |
| 428 | /* Description: Real Time Clock Compare */ |
| 429 | #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 |
| 430 | #define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff |
| 431 | |
| 432 | |
| 433 | /* ==================================================================== */ |
| 434 | /* Some MMRs are functionally identical (or close enough) on both SHUB1 */ |
| 435 | /* and SHUB2 that it makes sense to define a geberic name for the MMR. */ |
| 436 | /* It is acceptible to use (for example) SH_IPI_INT to reference the */ |
| 437 | /* the IPI MMR. The value of SH_IPI_INT is determined at runtime based */ |
| 438 | /* on the type of the SHUB. Do not use these #defines in performance */ |
| 439 | /* critical code or loops - there is a small performance penalty. */ |
| 440 | /* ==================================================================== */ |
| 441 | #define shubmmr(a,b) (is_shub2() ? a##2_##b : a##1_##b) |
| 442 | |
| 443 | #define SH_REAL_JUNK_BUS_LED0 shubmmr(SH, REAL_JUNK_BUS_LED0) |
| 444 | #define SH_IPI_INT shubmmr(SH, IPI_INT) |
| 445 | #define SH_EVENT_OCCURRED shubmmr(SH, EVENT_OCCURRED) |
| 446 | #define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS) |
| 447 | #define SH_RTC shubmmr(SH, RTC) |
| 448 | #define SH_RTC1_INT_CONFIG shubmmr(SH, RTC1_INT_CONFIG) |
| 449 | #define SH_RTC1_INT_ENABLE shubmmr(SH, RTC1_INT_ENABLE) |
| 450 | #define SH_RTC2_INT_CONFIG shubmmr(SH, RTC2_INT_CONFIG) |
| 451 | #define SH_RTC2_INT_ENABLE shubmmr(SH, RTC2_INT_ENABLE) |
| 452 | #define SH_RTC3_INT_CONFIG shubmmr(SH, RTC3_INT_CONFIG) |
| 453 | #define SH_RTC3_INT_ENABLE shubmmr(SH, RTC3_INT_ENABLE) |
| 454 | #define SH_INT_CMPB shubmmr(SH, INT_CMPB) |
| 455 | #define SH_INT_CMPC shubmmr(SH, INT_CMPC) |
| 456 | #define SH_INT_CMPD shubmmr(SH, INT_CMPD) |
| 457 | |
| 458 | #endif /* _ASM_IA64_SN_SHUB_MMR_H */ |