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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/ia64/kernel/irq.c
3 *
4 * Copyright (C) 1998-2001 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * 6/10/99: Updated to bring in sync with x86 version to facilitate
9 * support for SMP and different interrupt controllers.
10 *
11 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
12 * PCI to vector allocation routine.
13 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
14 * Added CPU Hotplug handling for IPF.
15 */
16
17#include <linux/config.h>
18#include <linux/module.h>
19
20#include <linux/jiffies.h>
21#include <linux/errno.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/kernel_stat.h>
26#include <linux/slab.h>
27#include <linux/ptrace.h>
28#include <linux/random.h> /* for rand_initialize_irq() */
29#include <linux/signal.h>
30#include <linux/smp.h>
31#include <linux/smp_lock.h>
32#include <linux/threads.h>
33#include <linux/bitops.h>
34
35#include <asm/delay.h>
36#include <asm/intrinsics.h>
37#include <asm/io.h>
38#include <asm/hw_irq.h>
39#include <asm/machvec.h>
40#include <asm/pgtable.h>
41#include <asm/system.h>
42
43#ifdef CONFIG_PERFMON
44# include <asm/perfmon.h>
45#endif
46
47#define IRQ_DEBUG 0
48
49/* default base addr of IPI table */
50void __iomem *ipi_base_addr = ((void __iomem *)
51 (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));
52
53/*
54 * Legacy IRQ to IA-64 vector translation table.
55 */
56__u8 isa_irq_to_vector_map[16] = {
57 /* 8259 IRQ translation, first 16 entries */
58 0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
59 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
60};
61EXPORT_SYMBOL(isa_irq_to_vector_map);
62
63static unsigned long ia64_vector_mask[BITS_TO_LONGS(IA64_NUM_DEVICE_VECTORS)];
64
65int
Kenji Kaneshige24eeb562005-04-25 13:26:23 -070066assign_irq_vector_nopanic (int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -070067{
68 int pos, vector;
69 again:
70 pos = find_first_zero_bit(ia64_vector_mask, IA64_NUM_DEVICE_VECTORS);
71 vector = IA64_FIRST_DEVICE_VECTOR + pos;
72 if (vector > IA64_LAST_DEVICE_VECTOR)
Kenji Kaneshige24eeb562005-04-25 13:26:23 -070073 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -070074 if (test_and_set_bit(pos, ia64_vector_mask))
75 goto again;
76 return vector;
77}
78
Kenji Kaneshige24eeb562005-04-25 13:26:23 -070079int
80assign_irq_vector (int irq)
81{
82 int vector = assign_irq_vector_nopanic(irq);
83
84 if (vector < 0)
85 panic("assign_irq_vector: out of interrupt vectors!");
86
87 return vector;
88}
89
Linus Torvalds1da177e2005-04-16 15:20:36 -070090void
91free_irq_vector (int vector)
92{
93 int pos;
94
95 if (vector < IA64_FIRST_DEVICE_VECTOR || vector > IA64_LAST_DEVICE_VECTOR)
96 return;
97
98 pos = vector - IA64_FIRST_DEVICE_VECTOR;
99 if (!test_and_clear_bit(pos, ia64_vector_mask))
100 printk(KERN_WARNING "%s: double free!\n", __FUNCTION__);
101}
102
103#ifdef CONFIG_SMP
104# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
105#else
106# define IS_RESCHEDULE(vec) (0)
107#endif
108/*
109 * That's where the IVT branches when we get an external
110 * interrupt. This branches to the correct hardware IRQ handler via
111 * function ptr.
112 */
113void
114ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
115{
116 unsigned long saved_tpr;
117
118#if IRQ_DEBUG
119 {
120 unsigned long bsp, sp;
121
122 /*
123 * Note: if the interrupt happened while executing in
124 * the context switch routine (ia64_switch_to), we may
125 * get a spurious stack overflow here. This is
126 * because the register and the memory stack are not
127 * switched atomically.
128 */
129 bsp = ia64_getreg(_IA64_REG_AR_BSP);
130 sp = ia64_getreg(_IA64_REG_SP);
131
132 if ((sp - bsp) < 1024) {
133 static unsigned char count;
134 static long last_time;
135
136 if (jiffies - last_time > 5*HZ)
137 count = 0;
138 if (++count < 5) {
139 last_time = jiffies;
140 printk("ia64_handle_irq: DANGER: less than "
141 "1KB of free stack space!!\n"
142 "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
143 }
144 }
145 }
146#endif /* IRQ_DEBUG */
147
148 /*
149 * Always set TPR to limit maximum interrupt nesting depth to
150 * 16 (without this, it would be ~240, which could easily lead
151 * to kernel stack overflows).
152 */
153 irq_enter();
154 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
155 ia64_srlz_d();
156 while (vector != IA64_SPURIOUS_INT_VECTOR) {
157 if (!IS_RESCHEDULE(vector)) {
158 ia64_setreg(_IA64_REG_CR_TPR, vector);
159 ia64_srlz_d();
160
161 __do_IRQ(local_vector_to_irq(vector), regs);
162
163 /*
164 * Disable interrupts and send EOI:
165 */
166 local_irq_disable();
167 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
168 }
169 ia64_eoi();
170 vector = ia64_get_ivr();
171 }
172 /*
173 * This must be done *after* the ia64_eoi(). For example, the keyboard softirq
174 * handler needs to be able to wait for further keyboard interrupts, which can't
175 * come through until ia64_eoi() has been done.
176 */
177 irq_exit();
178}
179
180#ifdef CONFIG_HOTPLUG_CPU
181/*
182 * This function emulates a interrupt processing when a cpu is about to be
183 * brought down.
184 */
185void ia64_process_pending_intr(void)
186{
187 ia64_vector vector;
188 unsigned long saved_tpr;
189 extern unsigned int vectors_in_migration[NR_IRQS];
190
191 vector = ia64_get_ivr();
192
193 irq_enter();
194 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
195 ia64_srlz_d();
196
197 /*
198 * Perform normal interrupt style processing
199 */
200 while (vector != IA64_SPURIOUS_INT_VECTOR) {
201 if (!IS_RESCHEDULE(vector)) {
202 ia64_setreg(_IA64_REG_CR_TPR, vector);
203 ia64_srlz_d();
204
205 /*
206 * Now try calling normal ia64_handle_irq as it would have got called
207 * from a real intr handler. Try passing null for pt_regs, hopefully
208 * it will work. I hope it works!.
209 * Probably could shared code.
210 */
211 vectors_in_migration[local_vector_to_irq(vector)]=0;
212 __do_IRQ(local_vector_to_irq(vector), NULL);
213
214 /*
215 * Disable interrupts and send EOI
216 */
217 local_irq_disable();
218 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
219 }
220 ia64_eoi();
221 vector = ia64_get_ivr();
222 }
223 irq_exit();
224}
225#endif
226
227
228#ifdef CONFIG_SMP
229extern irqreturn_t handle_IPI (int irq, void *dev_id, struct pt_regs *regs);
230
231static struct irqaction ipi_irqaction = {
232 .handler = handle_IPI,
233 .flags = SA_INTERRUPT,
234 .name = "IPI"
235};
236#endif
237
238void
239register_percpu_irq (ia64_vector vec, struct irqaction *action)
240{
241 irq_desc_t *desc;
242 unsigned int irq;
243
244 for (irq = 0; irq < NR_IRQS; ++irq)
245 if (irq_to_vector(irq) == vec) {
246 desc = irq_descp(irq);
247 desc->status |= IRQ_PER_CPU;
248 desc->handler = &irq_type_ia64_lsapic;
249 if (action)
250 setup_irq(irq, action);
251 }
252}
253
254void __init
255init_IRQ (void)
256{
257 register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
258#ifdef CONFIG_SMP
259 register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
260#endif
261#ifdef CONFIG_PERFMON
262 pfm_init_percpu();
263#endif
264 platform_irq_init();
265}
266
267void
268ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
269{
270 void __iomem *ipi_addr;
271 unsigned long ipi_data;
272 unsigned long phys_cpu_id;
273
274#ifdef CONFIG_SMP
275 phys_cpu_id = cpu_physical_id(cpu);
276#else
277 phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
278#endif
279
280 /*
281 * cpu number is in 8bit ID and 8bit EID
282 */
283
284 ipi_data = (delivery_mode << 8) | (vector & 0xff);
285 ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));
286
287 writeq(ipi_data, ipi_addr);
288}