Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * I/O SAPIC support. |
| 3 | * |
| 4 | * Copyright (C) 1999 Intel Corp. |
| 5 | * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> |
| 6 | * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com> |
| 7 | * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co. |
| 8 | * David Mosberger-Tang <davidm@hpl.hp.com> |
| 9 | * Copyright (C) 1999 VA Linux Systems |
| 10 | * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com> |
| 11 | * |
| 12 | * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O APIC code. |
| 13 | * In particular, we now have separate handlers for edge |
| 14 | * and level triggered interrupts. |
| 15 | * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation |
| 16 | * PCI to vector mapping, shared PCI interrupts. |
| 17 | * 00/10/27 D. Mosberger Document things a bit more to make them more understandable. |
| 18 | * Clean up much of the old IOSAPIC cruft. |
| 19 | * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts and fixes for |
| 20 | * ACPI S5(SoftOff) support. |
| 21 | * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT |
| 22 | * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt vectors in |
| 23 | * iosapic_set_affinity(), initializations for |
| 24 | * /proc/irq/#/smp_affinity |
| 25 | * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing. |
| 26 | * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq |
| 27 | * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping |
| 28 | * error |
| 29 | * 02/07/29 T. Kochi Allocate interrupt vectors dynamically |
| 30 | * 02/08/04 T. Kochi Cleaned up terminology (irq, global system interrupt, vector, etc.) |
| 31 | * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's pci_irq code. |
| 32 | * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC. |
| 33 | * Remove iosapic_address & gsi_base from external interfaces. |
| 34 | * Rationalize __init/__devinit attributes. |
| 35 | * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004 |
| 36 | * Updated to work with irq migration necessary for CPU Hotplug |
| 37 | */ |
| 38 | /* |
| 39 | * Here is what the interrupt logic between a PCI device and the kernel looks like: |
| 40 | * |
| 41 | * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD). The |
| 42 | * device is uniquely identified by its bus--, and slot-number (the function |
| 43 | * number does not matter here because all functions share the same interrupt |
| 44 | * lines). |
| 45 | * |
| 46 | * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller. |
| 47 | * Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level |
| 48 | * triggered and use the same polarity). Each interrupt line has a unique Global |
| 49 | * System Interrupt (GSI) number which can be calculated as the sum of the controller's |
| 50 | * base GSI number and the IOSAPIC pin number to which the line connects. |
| 51 | * |
| 52 | * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin |
| 53 | * into the IA-64 interrupt vector. This interrupt vector is then sent to the CPU. |
| 54 | * |
| 55 | * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is used as |
| 56 | * architecture-independent interrupt handling mechanism in Linux. As an |
| 57 | * IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number |
| 58 | * mapping. On smaller systems, we use one-to-one mapping between IA-64 vector and |
| 59 | * IRQ. A platform can implement platform_irq_to_vector(irq) and |
| 60 | * platform_local_vector_to_irq(vector) APIs to differentiate the mapping. |
| 61 | * Please see also include/asm-ia64/hw_irq.h for those APIs. |
| 62 | * |
| 63 | * To sum up, there are three levels of mappings involved: |
| 64 | * |
| 65 | * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ |
| 66 | * |
| 67 | * Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts. |
| 68 | * Now we use "IRQ" only for Linux IRQ's. ISA IRQ (isa_irq) is the only exception in this |
| 69 | * source code. |
| 70 | */ |
| 71 | #include <linux/config.h> |
| 72 | |
| 73 | #include <linux/acpi.h> |
| 74 | #include <linux/init.h> |
| 75 | #include <linux/irq.h> |
| 76 | #include <linux/kernel.h> |
| 77 | #include <linux/list.h> |
| 78 | #include <linux/pci.h> |
| 79 | #include <linux/smp.h> |
| 80 | #include <linux/smp_lock.h> |
| 81 | #include <linux/string.h> |
| 82 | |
| 83 | #include <asm/delay.h> |
| 84 | #include <asm/hw_irq.h> |
| 85 | #include <asm/io.h> |
| 86 | #include <asm/iosapic.h> |
| 87 | #include <asm/machvec.h> |
| 88 | #include <asm/processor.h> |
| 89 | #include <asm/ptrace.h> |
| 90 | #include <asm/system.h> |
| 91 | |
| 92 | |
| 93 | #undef DEBUG_INTERRUPT_ROUTING |
| 94 | |
| 95 | #ifdef DEBUG_INTERRUPT_ROUTING |
| 96 | #define DBG(fmt...) printk(fmt) |
| 97 | #else |
| 98 | #define DBG(fmt...) |
| 99 | #endif |
| 100 | |
| 101 | static DEFINE_SPINLOCK(iosapic_lock); |
| 102 | |
| 103 | /* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */ |
| 104 | |
| 105 | static struct iosapic_intr_info { |
| 106 | char __iomem *addr; /* base address of IOSAPIC */ |
| 107 | u32 low32; /* current value of low word of Redirection table entry */ |
| 108 | unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */ |
| 109 | char rte_index; /* IOSAPIC RTE index (-1 => not an IOSAPIC interrupt) */ |
| 110 | unsigned char dmode : 3; /* delivery mode (see iosapic.h) */ |
| 111 | unsigned char polarity: 1; /* interrupt polarity (see iosapic.h) */ |
| 112 | unsigned char trigger : 1; /* trigger mode (see iosapic.h) */ |
| 113 | int refcnt; /* reference counter */ |
| 114 | } iosapic_intr_info[IA64_NUM_VECTORS]; |
| 115 | |
| 116 | static struct iosapic { |
| 117 | char __iomem *addr; /* base address of IOSAPIC */ |
| 118 | unsigned int gsi_base; /* first GSI assigned to this IOSAPIC */ |
| 119 | unsigned short num_rte; /* number of RTE in this IOSAPIC */ |
| 120 | #ifdef CONFIG_NUMA |
| 121 | unsigned short node; /* numa node association via pxm */ |
| 122 | #endif |
| 123 | } iosapic_lists[NR_IOSAPICS]; |
| 124 | |
| 125 | static int num_iosapic; |
| 126 | |
| 127 | static unsigned char pcat_compat __initdata; /* 8259 compatibility flag */ |
| 128 | |
| 129 | |
| 130 | /* |
| 131 | * Find an IOSAPIC associated with a GSI |
| 132 | */ |
| 133 | static inline int |
| 134 | find_iosapic (unsigned int gsi) |
| 135 | { |
| 136 | int i; |
| 137 | |
| 138 | for (i = 0; i < num_iosapic; i++) { |
| 139 | if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < iosapic_lists[i].num_rte) |
| 140 | return i; |
| 141 | } |
| 142 | |
| 143 | return -1; |
| 144 | } |
| 145 | |
| 146 | static inline int |
| 147 | _gsi_to_vector (unsigned int gsi) |
| 148 | { |
| 149 | struct iosapic_intr_info *info; |
| 150 | |
| 151 | for (info = iosapic_intr_info; info < iosapic_intr_info + IA64_NUM_VECTORS; ++info) |
| 152 | if (info->gsi_base + info->rte_index == gsi) |
| 153 | return info - iosapic_intr_info; |
| 154 | return -1; |
| 155 | } |
| 156 | |
| 157 | /* |
| 158 | * Translate GSI number to the corresponding IA-64 interrupt vector. If no |
| 159 | * entry exists, return -1. |
| 160 | */ |
| 161 | inline int |
| 162 | gsi_to_vector (unsigned int gsi) |
| 163 | { |
| 164 | return _gsi_to_vector(gsi); |
| 165 | } |
| 166 | |
| 167 | int |
| 168 | gsi_to_irq (unsigned int gsi) |
| 169 | { |
| 170 | /* |
| 171 | * XXX fix me: this assumes an identity mapping vetween IA-64 vector and Linux irq |
| 172 | * numbers... |
| 173 | */ |
| 174 | return _gsi_to_vector(gsi); |
| 175 | } |
| 176 | |
| 177 | static void |
| 178 | set_rte (unsigned int vector, unsigned int dest, int mask) |
| 179 | { |
| 180 | unsigned long pol, trigger, dmode; |
| 181 | u32 low32, high32; |
| 182 | char __iomem *addr; |
| 183 | int rte_index; |
| 184 | char redir; |
| 185 | |
| 186 | DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest); |
| 187 | |
| 188 | rte_index = iosapic_intr_info[vector].rte_index; |
| 189 | if (rte_index < 0) |
| 190 | return; /* not an IOSAPIC interrupt */ |
| 191 | |
| 192 | addr = iosapic_intr_info[vector].addr; |
| 193 | pol = iosapic_intr_info[vector].polarity; |
| 194 | trigger = iosapic_intr_info[vector].trigger; |
| 195 | dmode = iosapic_intr_info[vector].dmode; |
| 196 | vector &= (~IA64_IRQ_REDIRECTED); |
| 197 | |
| 198 | redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0; |
| 199 | |
| 200 | #ifdef CONFIG_SMP |
| 201 | { |
| 202 | unsigned int irq; |
| 203 | |
| 204 | for (irq = 0; irq < NR_IRQS; ++irq) |
| 205 | if (irq_to_vector(irq) == vector) { |
| 206 | set_irq_affinity_info(irq, (int)(dest & 0xffff), redir); |
| 207 | break; |
| 208 | } |
| 209 | } |
| 210 | #endif |
| 211 | |
| 212 | low32 = ((pol << IOSAPIC_POLARITY_SHIFT) | |
| 213 | (trigger << IOSAPIC_TRIGGER_SHIFT) | |
| 214 | (dmode << IOSAPIC_DELIVERY_SHIFT) | |
| 215 | ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) | |
| 216 | vector); |
| 217 | |
| 218 | /* dest contains both id and eid */ |
| 219 | high32 = (dest << IOSAPIC_DEST_SHIFT); |
| 220 | |
| 221 | iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32); |
| 222 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); |
| 223 | iosapic_intr_info[vector].low32 = low32; |
| 224 | } |
| 225 | |
| 226 | static void |
| 227 | nop (unsigned int vector) |
| 228 | { |
| 229 | /* do nothing... */ |
| 230 | } |
| 231 | |
| 232 | static void |
| 233 | mask_irq (unsigned int irq) |
| 234 | { |
| 235 | unsigned long flags; |
| 236 | char __iomem *addr; |
| 237 | u32 low32; |
| 238 | int rte_index; |
| 239 | ia64_vector vec = irq_to_vector(irq); |
| 240 | |
| 241 | addr = iosapic_intr_info[vec].addr; |
| 242 | rte_index = iosapic_intr_info[vec].rte_index; |
| 243 | |
| 244 | if (rte_index < 0) |
| 245 | return; /* not an IOSAPIC interrupt! */ |
| 246 | |
| 247 | spin_lock_irqsave(&iosapic_lock, flags); |
| 248 | { |
| 249 | /* set only the mask bit */ |
| 250 | low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK; |
| 251 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); |
| 252 | } |
| 253 | spin_unlock_irqrestore(&iosapic_lock, flags); |
| 254 | } |
| 255 | |
| 256 | static void |
| 257 | unmask_irq (unsigned int irq) |
| 258 | { |
| 259 | unsigned long flags; |
| 260 | char __iomem *addr; |
| 261 | u32 low32; |
| 262 | int rte_index; |
| 263 | ia64_vector vec = irq_to_vector(irq); |
| 264 | |
| 265 | addr = iosapic_intr_info[vec].addr; |
| 266 | rte_index = iosapic_intr_info[vec].rte_index; |
| 267 | if (rte_index < 0) |
| 268 | return; /* not an IOSAPIC interrupt! */ |
| 269 | |
| 270 | spin_lock_irqsave(&iosapic_lock, flags); |
| 271 | { |
| 272 | low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK; |
| 273 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); |
| 274 | } |
| 275 | spin_unlock_irqrestore(&iosapic_lock, flags); |
| 276 | } |
| 277 | |
| 278 | |
| 279 | static void |
| 280 | iosapic_set_affinity (unsigned int irq, cpumask_t mask) |
| 281 | { |
| 282 | #ifdef CONFIG_SMP |
| 283 | unsigned long flags; |
| 284 | u32 high32, low32; |
| 285 | int dest, rte_index; |
| 286 | char __iomem *addr; |
| 287 | int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; |
| 288 | ia64_vector vec; |
| 289 | |
| 290 | irq &= (~IA64_IRQ_REDIRECTED); |
| 291 | vec = irq_to_vector(irq); |
| 292 | |
| 293 | if (cpus_empty(mask)) |
| 294 | return; |
| 295 | |
| 296 | dest = cpu_physical_id(first_cpu(mask)); |
| 297 | |
| 298 | rte_index = iosapic_intr_info[vec].rte_index; |
| 299 | addr = iosapic_intr_info[vec].addr; |
| 300 | |
| 301 | if (rte_index < 0) |
| 302 | return; /* not an IOSAPIC interrupt */ |
| 303 | |
| 304 | set_irq_affinity_info(irq, dest, redir); |
| 305 | |
| 306 | /* dest contains both id and eid */ |
| 307 | high32 = dest << IOSAPIC_DEST_SHIFT; |
| 308 | |
| 309 | spin_lock_irqsave(&iosapic_lock, flags); |
| 310 | { |
| 311 | low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT); |
| 312 | |
| 313 | if (redir) |
| 314 | /* change delivery mode to lowest priority */ |
| 315 | low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT); |
| 316 | else |
| 317 | /* change delivery mode to fixed */ |
| 318 | low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT); |
| 319 | |
| 320 | iosapic_intr_info[vec].low32 = low32; |
| 321 | iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32); |
| 322 | iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); |
| 323 | } |
| 324 | spin_unlock_irqrestore(&iosapic_lock, flags); |
| 325 | #endif |
| 326 | } |
| 327 | |
| 328 | /* |
| 329 | * Handlers for level-triggered interrupts. |
| 330 | */ |
| 331 | |
| 332 | static unsigned int |
| 333 | iosapic_startup_level_irq (unsigned int irq) |
| 334 | { |
| 335 | unmask_irq(irq); |
| 336 | return 0; |
| 337 | } |
| 338 | |
| 339 | static void |
| 340 | iosapic_end_level_irq (unsigned int irq) |
| 341 | { |
| 342 | ia64_vector vec = irq_to_vector(irq); |
| 343 | |
| 344 | move_irq(irq); |
| 345 | iosapic_eoi(iosapic_intr_info[vec].addr, vec); |
| 346 | } |
| 347 | |
| 348 | #define iosapic_shutdown_level_irq mask_irq |
| 349 | #define iosapic_enable_level_irq unmask_irq |
| 350 | #define iosapic_disable_level_irq mask_irq |
| 351 | #define iosapic_ack_level_irq nop |
| 352 | |
| 353 | struct hw_interrupt_type irq_type_iosapic_level = { |
| 354 | .typename = "IO-SAPIC-level", |
| 355 | .startup = iosapic_startup_level_irq, |
| 356 | .shutdown = iosapic_shutdown_level_irq, |
| 357 | .enable = iosapic_enable_level_irq, |
| 358 | .disable = iosapic_disable_level_irq, |
| 359 | .ack = iosapic_ack_level_irq, |
| 360 | .end = iosapic_end_level_irq, |
| 361 | .set_affinity = iosapic_set_affinity |
| 362 | }; |
| 363 | |
| 364 | /* |
| 365 | * Handlers for edge-triggered interrupts. |
| 366 | */ |
| 367 | |
| 368 | static unsigned int |
| 369 | iosapic_startup_edge_irq (unsigned int irq) |
| 370 | { |
| 371 | unmask_irq(irq); |
| 372 | /* |
| 373 | * IOSAPIC simply drops interrupts pended while the |
| 374 | * corresponding pin was masked, so we can't know if an |
| 375 | * interrupt is pending already. Let's hope not... |
| 376 | */ |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | static void |
| 381 | iosapic_ack_edge_irq (unsigned int irq) |
| 382 | { |
| 383 | irq_desc_t *idesc = irq_descp(irq); |
| 384 | |
| 385 | move_irq(irq); |
| 386 | /* |
| 387 | * Once we have recorded IRQ_PENDING already, we can mask the |
| 388 | * interrupt for real. This prevents IRQ storms from unhandled |
| 389 | * devices. |
| 390 | */ |
| 391 | if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == (IRQ_PENDING|IRQ_DISABLED)) |
| 392 | mask_irq(irq); |
| 393 | } |
| 394 | |
| 395 | #define iosapic_enable_edge_irq unmask_irq |
| 396 | #define iosapic_disable_edge_irq nop |
| 397 | #define iosapic_end_edge_irq nop |
| 398 | |
| 399 | struct hw_interrupt_type irq_type_iosapic_edge = { |
| 400 | .typename = "IO-SAPIC-edge", |
| 401 | .startup = iosapic_startup_edge_irq, |
| 402 | .shutdown = iosapic_disable_edge_irq, |
| 403 | .enable = iosapic_enable_edge_irq, |
| 404 | .disable = iosapic_disable_edge_irq, |
| 405 | .ack = iosapic_ack_edge_irq, |
| 406 | .end = iosapic_end_edge_irq, |
| 407 | .set_affinity = iosapic_set_affinity |
| 408 | }; |
| 409 | |
| 410 | unsigned int |
| 411 | iosapic_version (char __iomem *addr) |
| 412 | { |
| 413 | /* |
| 414 | * IOSAPIC Version Register return 32 bit structure like: |
| 415 | * { |
| 416 | * unsigned int version : 8; |
| 417 | * unsigned int reserved1 : 8; |
| 418 | * unsigned int max_redir : 8; |
| 419 | * unsigned int reserved2 : 8; |
| 420 | * } |
| 421 | */ |
| 422 | return iosapic_read(addr, IOSAPIC_VERSION); |
| 423 | } |
| 424 | |
| 425 | /* |
| 426 | * if the given vector is already owned by other, |
| 427 | * assign a new vector for the other and make the vector available |
| 428 | */ |
| 429 | static void __init |
| 430 | iosapic_reassign_vector (int vector) |
| 431 | { |
| 432 | int new_vector; |
| 433 | |
| 434 | if (iosapic_intr_info[vector].rte_index >= 0 || iosapic_intr_info[vector].addr |
| 435 | || iosapic_intr_info[vector].gsi_base || iosapic_intr_info[vector].dmode |
| 436 | || iosapic_intr_info[vector].polarity || iosapic_intr_info[vector].trigger) |
| 437 | { |
| 438 | new_vector = assign_irq_vector(AUTO_ASSIGN); |
| 439 | printk(KERN_INFO "Reassigning vector %d to %d\n", vector, new_vector); |
| 440 | memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector], |
| 441 | sizeof(struct iosapic_intr_info)); |
| 442 | memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info)); |
| 443 | iosapic_intr_info[vector].rte_index = -1; |
| 444 | } |
| 445 | } |
| 446 | |
| 447 | static void |
| 448 | register_intr (unsigned int gsi, int vector, unsigned char delivery, |
| 449 | unsigned long polarity, unsigned long trigger) |
| 450 | { |
| 451 | irq_desc_t *idesc; |
| 452 | struct hw_interrupt_type *irq_type; |
| 453 | int rte_index; |
| 454 | int index; |
| 455 | unsigned long gsi_base; |
| 456 | void __iomem *iosapic_address; |
| 457 | |
| 458 | index = find_iosapic(gsi); |
| 459 | if (index < 0) { |
| 460 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", __FUNCTION__, gsi); |
| 461 | return; |
| 462 | } |
| 463 | |
| 464 | iosapic_address = iosapic_lists[index].addr; |
| 465 | gsi_base = iosapic_lists[index].gsi_base; |
| 466 | |
| 467 | rte_index = gsi - gsi_base; |
| 468 | iosapic_intr_info[vector].rte_index = rte_index; |
| 469 | iosapic_intr_info[vector].polarity = polarity; |
| 470 | iosapic_intr_info[vector].dmode = delivery; |
| 471 | iosapic_intr_info[vector].addr = iosapic_address; |
| 472 | iosapic_intr_info[vector].gsi_base = gsi_base; |
| 473 | iosapic_intr_info[vector].trigger = trigger; |
| 474 | iosapic_intr_info[vector].refcnt++; |
| 475 | |
| 476 | if (trigger == IOSAPIC_EDGE) |
| 477 | irq_type = &irq_type_iosapic_edge; |
| 478 | else |
| 479 | irq_type = &irq_type_iosapic_level; |
| 480 | |
| 481 | idesc = irq_descp(vector); |
| 482 | if (idesc->handler != irq_type) { |
| 483 | if (idesc->handler != &no_irq_type) |
| 484 | printk(KERN_WARNING "%s: changing vector %d from %s to %s\n", |
| 485 | __FUNCTION__, vector, idesc->handler->typename, irq_type->typename); |
| 486 | idesc->handler = irq_type; |
| 487 | } |
| 488 | } |
| 489 | |
| 490 | static unsigned int |
| 491 | get_target_cpu (unsigned int gsi, int vector) |
| 492 | { |
| 493 | #ifdef CONFIG_SMP |
| 494 | static int cpu = -1; |
| 495 | |
| 496 | /* |
| 497 | * If the platform supports redirection via XTP, let it |
| 498 | * distribute interrupts. |
| 499 | */ |
| 500 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) |
| 501 | return cpu_physical_id(smp_processor_id()); |
| 502 | |
| 503 | /* |
| 504 | * Some interrupts (ACPI SCI, for instance) are registered |
| 505 | * before the BSP is marked as online. |
| 506 | */ |
| 507 | if (!cpu_online(smp_processor_id())) |
| 508 | return cpu_physical_id(smp_processor_id()); |
| 509 | |
| 510 | #ifdef CONFIG_NUMA |
| 511 | { |
| 512 | int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0; |
| 513 | cpumask_t cpu_mask; |
| 514 | |
| 515 | iosapic_index = find_iosapic(gsi); |
| 516 | if (iosapic_index < 0 || |
| 517 | iosapic_lists[iosapic_index].node == MAX_NUMNODES) |
| 518 | goto skip_numa_setup; |
| 519 | |
| 520 | cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node); |
| 521 | |
| 522 | for_each_cpu_mask(numa_cpu, cpu_mask) { |
| 523 | if (!cpu_online(numa_cpu)) |
| 524 | cpu_clear(numa_cpu, cpu_mask); |
| 525 | } |
| 526 | |
| 527 | num_cpus = cpus_weight(cpu_mask); |
| 528 | |
| 529 | if (!num_cpus) |
| 530 | goto skip_numa_setup; |
| 531 | |
| 532 | /* Use vector assigment to distribute across cpus in node */ |
| 533 | cpu_index = vector % num_cpus; |
| 534 | |
| 535 | for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++) |
| 536 | numa_cpu = next_cpu(numa_cpu, cpu_mask); |
| 537 | |
| 538 | if (numa_cpu != NR_CPUS) |
| 539 | return cpu_physical_id(numa_cpu); |
| 540 | } |
| 541 | skip_numa_setup: |
| 542 | #endif |
| 543 | /* |
| 544 | * Otherwise, round-robin interrupt vectors across all the |
| 545 | * processors. (It'd be nice if we could be smarter in the |
| 546 | * case of NUMA.) |
| 547 | */ |
| 548 | do { |
| 549 | if (++cpu >= NR_CPUS) |
| 550 | cpu = 0; |
| 551 | } while (!cpu_online(cpu)); |
| 552 | |
| 553 | return cpu_physical_id(cpu); |
| 554 | #else |
| 555 | return cpu_physical_id(smp_processor_id()); |
| 556 | #endif |
| 557 | } |
| 558 | |
| 559 | /* |
| 560 | * ACPI can describe IOSAPIC interrupts via static tables and namespace |
| 561 | * methods. This provides an interface to register those interrupts and |
| 562 | * program the IOSAPIC RTE. |
| 563 | */ |
| 564 | int |
| 565 | iosapic_register_intr (unsigned int gsi, |
| 566 | unsigned long polarity, unsigned long trigger) |
| 567 | { |
| 568 | int vector; |
| 569 | unsigned int dest; |
| 570 | unsigned long flags; |
| 571 | |
| 572 | /* |
| 573 | * If this GSI has already been registered (i.e., it's a |
| 574 | * shared interrupt, or we lost a race to register it), |
| 575 | * don't touch the RTE. |
| 576 | */ |
| 577 | spin_lock_irqsave(&iosapic_lock, flags); |
| 578 | { |
| 579 | vector = gsi_to_vector(gsi); |
| 580 | if (vector > 0) { |
| 581 | iosapic_intr_info[vector].refcnt++; |
| 582 | spin_unlock_irqrestore(&iosapic_lock, flags); |
| 583 | return vector; |
| 584 | } |
| 585 | |
| 586 | vector = assign_irq_vector(AUTO_ASSIGN); |
| 587 | dest = get_target_cpu(gsi, vector); |
| 588 | register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, |
| 589 | polarity, trigger); |
| 590 | |
| 591 | set_rte(vector, dest, 1); |
| 592 | } |
| 593 | spin_unlock_irqrestore(&iosapic_lock, flags); |
| 594 | |
| 595 | printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n", |
| 596 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), |
| 597 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), |
| 598 | cpu_logical_id(dest), dest, vector); |
| 599 | |
| 600 | return vector; |
| 601 | } |
| 602 | |
| 603 | #ifdef CONFIG_ACPI_DEALLOCATE_IRQ |
| 604 | void |
| 605 | iosapic_unregister_intr (unsigned int gsi) |
| 606 | { |
| 607 | unsigned long flags; |
| 608 | int irq, vector; |
| 609 | irq_desc_t *idesc; |
| 610 | int rte_index; |
| 611 | unsigned long trigger, polarity; |
| 612 | |
| 613 | /* |
| 614 | * If the irq associated with the gsi is not found, |
| 615 | * iosapic_unregister_intr() is unbalanced. We need to check |
| 616 | * this again after getting locks. |
| 617 | */ |
| 618 | irq = gsi_to_irq(gsi); |
| 619 | if (irq < 0) { |
| 620 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", gsi); |
| 621 | WARN_ON(1); |
| 622 | return; |
| 623 | } |
| 624 | vector = irq_to_vector(irq); |
| 625 | |
| 626 | idesc = irq_descp(irq); |
| 627 | spin_lock_irqsave(&idesc->lock, flags); |
| 628 | spin_lock(&iosapic_lock); |
| 629 | { |
| 630 | rte_index = iosapic_intr_info[vector].rte_index; |
| 631 | if (rte_index < 0) { |
| 632 | spin_unlock(&iosapic_lock); |
| 633 | spin_unlock_irqrestore(&idesc->lock, flags); |
| 634 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", gsi); |
| 635 | WARN_ON(1); |
| 636 | return; |
| 637 | } |
| 638 | |
| 639 | if (--iosapic_intr_info[vector].refcnt > 0) { |
| 640 | spin_unlock(&iosapic_lock); |
| 641 | spin_unlock_irqrestore(&idesc->lock, flags); |
| 642 | return; |
| 643 | } |
| 644 | |
| 645 | /* |
| 646 | * If interrupt handlers still exist on the irq |
| 647 | * associated with the gsi, don't unregister the |
| 648 | * interrupt. |
| 649 | */ |
| 650 | if (idesc->action) { |
| 651 | iosapic_intr_info[vector].refcnt++; |
| 652 | spin_unlock(&iosapic_lock); |
| 653 | spin_unlock_irqrestore(&idesc->lock, flags); |
| 654 | printk(KERN_WARNING "Cannot unregister GSI. IRQ %u is still in use.\n", irq); |
| 655 | return; |
| 656 | } |
| 657 | |
| 658 | /* Clear the interrupt controller descriptor. */ |
| 659 | idesc->handler = &no_irq_type; |
| 660 | |
| 661 | trigger = iosapic_intr_info[vector].trigger; |
| 662 | polarity = iosapic_intr_info[vector].polarity; |
| 663 | |
| 664 | /* Clear the interrupt information. */ |
| 665 | memset(&iosapic_intr_info[vector], 0, sizeof(struct iosapic_intr_info)); |
| 666 | iosapic_intr_info[vector].rte_index = -1; /* mark as unused */ |
| 667 | } |
| 668 | spin_unlock(&iosapic_lock); |
| 669 | spin_unlock_irqrestore(&idesc->lock, flags); |
| 670 | |
| 671 | /* Free the interrupt vector */ |
| 672 | free_irq_vector(vector); |
| 673 | |
| 674 | printk(KERN_INFO "GSI %u (%s, %s) -> vector %d unregisterd.\n", |
| 675 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), |
| 676 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), |
| 677 | vector); |
| 678 | } |
| 679 | #endif /* CONFIG_ACPI_DEALLOCATE_IRQ */ |
| 680 | |
| 681 | /* |
| 682 | * ACPI calls this when it finds an entry for a platform interrupt. |
| 683 | * Note that the irq_base and IOSAPIC address must be set in iosapic_init(). |
| 684 | */ |
| 685 | int __init |
| 686 | iosapic_register_platform_intr (u32 int_type, unsigned int gsi, |
| 687 | int iosapic_vector, u16 eid, u16 id, |
| 688 | unsigned long polarity, unsigned long trigger) |
| 689 | { |
| 690 | static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"}; |
| 691 | unsigned char delivery; |
| 692 | int vector, mask = 0; |
| 693 | unsigned int dest = ((id << 8) | eid) & 0xffff; |
| 694 | |
| 695 | switch (int_type) { |
| 696 | case ACPI_INTERRUPT_PMI: |
| 697 | vector = iosapic_vector; |
| 698 | /* |
| 699 | * since PMI vector is alloc'd by FW(ACPI) not by kernel, |
| 700 | * we need to make sure the vector is available |
| 701 | */ |
| 702 | iosapic_reassign_vector(vector); |
| 703 | delivery = IOSAPIC_PMI; |
| 704 | break; |
| 705 | case ACPI_INTERRUPT_INIT: |
| 706 | vector = assign_irq_vector(AUTO_ASSIGN); |
| 707 | delivery = IOSAPIC_INIT; |
| 708 | break; |
| 709 | case ACPI_INTERRUPT_CPEI: |
| 710 | vector = IA64_CPE_VECTOR; |
| 711 | delivery = IOSAPIC_LOWEST_PRIORITY; |
| 712 | mask = 1; |
| 713 | break; |
| 714 | default: |
| 715 | printk(KERN_ERR "iosapic_register_platform_irq(): invalid int type 0x%x\n", int_type); |
| 716 | return -1; |
| 717 | } |
| 718 | |
| 719 | register_intr(gsi, vector, delivery, polarity, trigger); |
| 720 | |
| 721 | printk(KERN_INFO "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n", |
| 722 | int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown", |
| 723 | int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), |
| 724 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), |
| 725 | cpu_logical_id(dest), dest, vector); |
| 726 | |
| 727 | set_rte(vector, dest, mask); |
| 728 | return vector; |
| 729 | } |
| 730 | |
| 731 | |
| 732 | /* |
| 733 | * ACPI calls this when it finds an entry for a legacy ISA IRQ override. |
| 734 | * Note that the gsi_base and IOSAPIC address must be set in iosapic_init(). |
| 735 | */ |
| 736 | void __init |
| 737 | iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi, |
| 738 | unsigned long polarity, |
| 739 | unsigned long trigger) |
| 740 | { |
| 741 | int vector; |
| 742 | unsigned int dest = cpu_physical_id(smp_processor_id()); |
| 743 | |
| 744 | vector = isa_irq_to_vector(isa_irq); |
| 745 | |
| 746 | register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger); |
| 747 | |
| 748 | DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n", |
| 749 | isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level", |
| 750 | polarity == IOSAPIC_POL_HIGH ? "high" : "low", |
| 751 | cpu_logical_id(dest), dest, vector); |
| 752 | |
| 753 | set_rte(vector, dest, 1); |
| 754 | } |
| 755 | |
| 756 | void __init |
| 757 | iosapic_system_init (int system_pcat_compat) |
| 758 | { |
| 759 | int vector; |
| 760 | |
| 761 | for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) |
| 762 | iosapic_intr_info[vector].rte_index = -1; /* mark as unused */ |
| 763 | |
| 764 | pcat_compat = system_pcat_compat; |
| 765 | if (pcat_compat) { |
| 766 | /* |
| 767 | * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support |
| 768 | * enabled. |
| 769 | */ |
| 770 | printk(KERN_INFO "%s: Disabling PC-AT compatible 8259 interrupts\n", __FUNCTION__); |
| 771 | outb(0xff, 0xA1); |
| 772 | outb(0xff, 0x21); |
| 773 | } |
| 774 | } |
| 775 | |
| 776 | void __init |
| 777 | iosapic_init (unsigned long phys_addr, unsigned int gsi_base) |
| 778 | { |
| 779 | int num_rte; |
| 780 | unsigned int isa_irq, ver; |
| 781 | char __iomem *addr; |
| 782 | |
| 783 | addr = ioremap(phys_addr, 0); |
| 784 | ver = iosapic_version(addr); |
| 785 | |
| 786 | /* |
| 787 | * The MAX_REDIR register holds the highest input pin |
| 788 | * number (starting from 0). |
| 789 | * We add 1 so that we can use it for number of pins (= RTEs) |
| 790 | */ |
| 791 | num_rte = ((ver >> 16) & 0xff) + 1; |
| 792 | |
| 793 | iosapic_lists[num_iosapic].addr = addr; |
| 794 | iosapic_lists[num_iosapic].gsi_base = gsi_base; |
| 795 | iosapic_lists[num_iosapic].num_rte = num_rte; |
| 796 | #ifdef CONFIG_NUMA |
| 797 | iosapic_lists[num_iosapic].node = MAX_NUMNODES; |
| 798 | #endif |
| 799 | num_iosapic++; |
| 800 | |
| 801 | if ((gsi_base == 0) && pcat_compat) { |
| 802 | /* |
| 803 | * Map the legacy ISA devices into the IOSAPIC data. Some of these may |
| 804 | * get reprogrammed later on with data from the ACPI Interrupt Source |
| 805 | * Override table. |
| 806 | */ |
| 807 | for (isa_irq = 0; isa_irq < 16; ++isa_irq) |
| 808 | iosapic_override_isa_irq(isa_irq, isa_irq, IOSAPIC_POL_HIGH, IOSAPIC_EDGE); |
| 809 | } |
| 810 | } |
| 811 | |
| 812 | #ifdef CONFIG_NUMA |
| 813 | void __init |
| 814 | map_iosapic_to_node(unsigned int gsi_base, int node) |
| 815 | { |
| 816 | int index; |
| 817 | |
| 818 | index = find_iosapic(gsi_base); |
| 819 | if (index < 0) { |
| 820 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", |
| 821 | __FUNCTION__, gsi_base); |
| 822 | return; |
| 823 | } |
| 824 | iosapic_lists[index].node = node; |
| 825 | return; |
| 826 | } |
| 827 | #endif |