)]}'
{
  "commit": "00b65985fb2fc542b855b03fcda0d0f2bab4f442",
  "tree": "dc9372aced10184945862b9adf0848da3e0e946f",
  "parents": [
    "a0776ec8e97bf109e7d973d09fc3e1814eb32bfb"
  ],
  "author": {
    "name": "Chen, Kenneth W",
    "email": "kenneth.w.chen@intel.com",
    "time": "Fri Oct 13 10:08:13 2006 -0700"
  },
  "committer": {
    "name": "Tony Luck",
    "email": "tony.luck@intel.com",
    "time": "Tue Feb 06 15:04:48 2007 -0800"
  },
  "message": "[IA64] relax per-cpu TLB requirement to DTC\n\nInstead of pinning per-cpu TLB into a DTR, use DTC.  This will free up\none TLB entry for application, or even kernel if access pattern to\nper-cpu data area has high temporal locality.\n\nSince per-cpu is mapped at the top of region 7 address, we just need to\nadd special case in alt_dtlb_miss.  The physical address of per-cpu data\nis already conveniently stored in IA64_KR(PER_CPU_DATA).  Latency for\nalt_dtlb_miss is not affected as we can hide all the latency.  It was\nmeasured that alt_dtlb_miss handler has 23 cycles latency before and\nafter the patch.\n\nThe performance effect is massive for applications that put lots of tlb\npressure on CPU.  Workload environment like database online transaction\nprocessing or application uses tera-byte of memory would benefit the most.\nMeasurement with industry standard database benchmark shown an upward\nof 1.6% gain.  While smaller workloads like cpu, java also showing small\nimprovement.\n\nSigned-off-by: Ken Chen \u003ckenneth.w.chen@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n",
  "tree_diff": [
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      "new_path": "arch/ia64/kernel/ivt.S"
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}