[MIPS] MT: Scheduler support for SMT
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index ed5c02c..0c5a358 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -55,6 +55,7 @@
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
int srsets; /* Shadow register sets */
+ int core; /* physical core number */
#if defined(CONFIG_MIPS_MT_SMTC)
/*
* In the MIPS MT "SMTC" model, each TC is considered
@@ -63,8 +64,10 @@
* to all TCs within the same VPE.
*/
int vpe_id; /* Virtual Processor number */
- int tc_id; /* Thread Context number */
#endif /* CONFIG_MIPS_MT */
+#ifdef CONFIG_MIPS_MT_SMTC
+ int tc_id; /* Thread Context number */
+#endif
void *data; /* Additional data */
} __attribute__((aligned(SMP_CACHE_BYTES)));
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index dc77002..2326587 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -20,6 +20,9 @@
#include <linux/cpumask.h>
#include <asm/atomic.h>
+extern int smp_num_siblings;
+extern cpumask_t cpu_sibling_map[];
+
#define raw_smp_processor_id() (current_thread_info()->cpu)
/* Map from cpu id to sequential logical cpu number. This will only
diff --git a/include/asm-mips/topology.h b/include/asm-mips/topology.h
index 0440fb9..259145e 100644
--- a/include/asm-mips/topology.h
+++ b/include/asm-mips/topology.h
@@ -1 +1,17 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 by Ralf Baechle
+ */
+#ifndef __ASM_TOPOLOGY_H
+#define __ASM_TOPOLOGY_H
+
#include <topology.h>
+
+#ifdef CONFIG_SMP
+#define smt_capable() (smp_num_siblings > 1)
+#endif
+
+#endif /* __ASM_TOPOLOGY_H */