clk: tegra: Fix cdev1 and cdev2 IDs
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index c45b698..cee4c34 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -830,7 +830,7 @@
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
- clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
+ clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};