Fix common misspellings
Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
diff --git a/drivers/i2c/busses/i2c-intel-mid.c b/drivers/i2c/busses/i2c-intel-mid.c
index c714927..e828ac8 100644
--- a/drivers/i2c/busses/i2c-intel-mid.c
+++ b/drivers/i2c/busses/i2c-intel-mid.c
@@ -170,8 +170,8 @@
/* Raw Interrupt Status Register */
#define IC_RAW_INTR_STAT 0x34 /* Read Only */
#define GEN_CALL (1 << 11) /* General call */
-#define START_DET (1 << 10) /* (RE)START occured */
-#define STOP_DET (1 << 9) /* STOP occured */
+#define START_DET (1 << 10) /* (RE)START occurred */
+#define STOP_DET (1 << 9) /* STOP occurred */
#define ACTIVITY (1 << 8) /* Bus busy */
#define RX_DONE (1 << 7) /* Not used in Master mode */
#define TX_ABRT (1 << 6) /* Transmit Abort */
@@ -375,7 +375,7 @@
* I2C should be disabled prior to other register operation. If failed, an
* errno is returned. Mask and Clear all interrpts, this should be done at
* first. Set common registers which will not be modified during normal
- * transfers, including: controll register, FIFO threshold and clock freq.
+ * transfers, including: control register, FIFO threshold and clock freq.
* Check APB data width at last.
*/
static int intel_mid_i2c_hwinit(struct intel_mid_i2c_private *i2c)
@@ -455,7 +455,7 @@
*
* By reading register IC_TX_ABRT_SOURCE, various transfer errors can be
* distingushed. At present, no circumstances have been found out that
- * multiple errors would be occured simutaneously, so we simply use the
+ * multiple errors would be occurred simutaneously, so we simply use the
* register value directly.
*
* At last the error bits are cleared. (Note clear ABRT_SBYTE_NORSTRT bit need
@@ -469,7 +469,7 @@
/* Single transfer error check:
* According to databook, TX/RX FIFOs would be flushed when
- * the abort interrupt occured.
+ * the abort interrupt occurred.
*/
if (abort & ABRT_MASTER_DIS)
dev_err(&adap->dev,
@@ -569,7 +569,7 @@
* Return Values:
* 0 if the read transfer succeeds
* -ETIMEDOUT if we cannot read the "raw" interrupt register
- * -EINVAL if a transfer abort occured
+ * -EINVAL if a transfer abort occurred
*
* For every byte, a "WRITE" command will be loaded into IC_DATA_CMD prior to
* data transfer. The actual "write" operation will be performed when the
@@ -697,7 +697,7 @@
* @num: number of i2c_msg
*
* Return Values:
- * + number of messages transfered
+ * + number of messages transferred
* -ETIMEDOUT If cannot disable I2C controller or read IC_STATUS
* -EINVAL If the address in i2c_msg is invalid
*