ARM: Remove support for ARMv3 ARM610 and ARM710 CPUs
This patch removes support for ARMv3 CPUs, which haven't worked properly
for quite some time (see the FIXME comment in arch/arm/mm/fault.c). The
only V3 parts left is the cache model for ARMv3, which is needed for some
odd reason by ARM740T CPUs, and being able to build with -march=armv3,
which is required for the RiscPC platform due to its bus structure.
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 7c8a7d8..101b968 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -4,23 +4,6 @@
# which CPUs we support in the kernel image, and the compiler instruction
# optimiser behaviour.
-# ARM610
-config CPU_ARM610
- bool "Support ARM610 processor" if ARCH_RPC
- select CPU_32v3
- select CPU_CACHE_V3
- select CPU_CACHE_VIVT
- select CPU_CP15_MMU
- select CPU_COPY_V3 if MMU
- select CPU_TLB_V3 if MMU
- select CPU_PABRT_LEGACY
- help
- The ARM610 is the successor to the ARM3 processor
- and was produced by VLSI Technology Inc.
-
- Say Y if you want support for the ARM610 processor.
- Otherwise, say N.
-
# ARM7TDMI
config CPU_ARM7TDMI
bool "Support ARM7TDMI processor"
@@ -36,25 +19,6 @@
Say Y if you want support for the ARM7TDMI processor.
Otherwise, say N.
-# ARM710
-config CPU_ARM710
- bool "Support ARM710 processor" if ARCH_RPC
- select CPU_32v3
- select CPU_CACHE_V3
- select CPU_CACHE_VIVT
- select CPU_CP15_MMU
- select CPU_COPY_V3 if MMU
- select CPU_TLB_V3 if MMU
- select CPU_PABRT_LEGACY
- help
- A 32-bit RISC microprocessor based on the ARM7 processor core
- designed by Advanced RISC Machines Ltd. The ARM710 is the
- successor to the ARM610 processor. It was released in
- July 1994 by VLSI Technology Inc.
-
- Say Y if you want support for the ARM710 processor.
- Otherwise, say N.
-
# ARM720T
config CPU_ARM720T
bool "Support ARM720T processor" if ARCH_INTEGRATOR
@@ -530,9 +494,6 @@
if MMU
# The copy-page model
-config CPU_COPY_V3
- bool
-
config CPU_COPY_V4WT
bool
@@ -549,11 +510,6 @@
bool
# This selects the TLB model
-config CPU_TLB_V3
- bool
- help
- ARM Architecture Version 3 TLB.
-
config CPU_TLB_V4WT
bool
help
@@ -731,7 +687,7 @@
config CPU_ICACHE_DISABLE
bool "Disable I-Cache (I-bit)"
- depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
+ depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
help
Say Y here to disable the processor instruction cache. Unless
you have a reason not to or are unsure, say N.
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index bca7e61..8a9c4cb 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -44,7 +44,6 @@
AFLAGS_cache-v6.o :=-Wa,-march=armv6
AFLAGS_cache-v7.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o
obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o
obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o
obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o
@@ -54,7 +53,6 @@
obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o
obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o
-obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o
obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o
obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o
@@ -66,8 +64,6 @@
AFLAGS_tlb-v6.o :=-Wa,-march=armv6
AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o
-obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o
obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o
obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o
obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o
diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c
deleted file mode 100644
index 3935bdd..0000000
--- a/arch/arm/mm/copypage-v3.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * linux/arch/arm/mm/copypage-v3.c
- *
- * Copyright (C) 1995-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/highmem.h>
-
-/*
- * ARMv3 optimised copy_user_highpage
- *
- * FIXME: do we need to handle cache stuff...
- */
-static void __naked
-v3_copy_user_page(void *kto, const void *kfrom)
-{
- asm("\n\
- stmfd sp!, {r4, lr} @ 2\n\
- mov r2, %2 @ 1\n\
- ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
-1: stmia %1!, {r3, r4, ip, lr} @ 4\n\
- ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
- stmia %1!, {r3, r4, ip, lr} @ 4\n\
- ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
- stmia %1!, {r3, r4, ip, lr} @ 4\n\
- ldmia %0!, {r3, r4, ip, lr} @ 4\n\
- subs r2, r2, #1 @ 1\n\
- stmia %1!, {r3, r4, ip, lr} @ 4\n\
- ldmneia %0!, {r3, r4, ip, lr} @ 4\n\
- bne 1b @ 1\n\
- ldmfd sp!, {r4, pc} @ 3"
- :
- : "r" (kfrom), "r" (kto), "I" (PAGE_SIZE / 64));
-}
-
-void v3_copy_user_highpage(struct page *to, struct page *from,
- unsigned long vaddr, struct vm_area_struct *vma)
-{
- void *kto, *kfrom;
-
- kto = kmap_atomic(to);
- kfrom = kmap_atomic(from);
- v3_copy_user_page(kto, kfrom);
- kunmap_atomic(kfrom);
- kunmap_atomic(kto);
-}
-
-/*
- * ARMv3 optimised clear_user_page
- *
- * FIXME: do we need to handle cache stuff...
- */
-void v3_clear_user_highpage(struct page *page, unsigned long vaddr)
-{
- void *ptr, *kaddr = kmap_atomic(page);
- asm volatile("\n\
- mov r1, %2 @ 1\n\
- mov r2, #0 @ 1\n\
- mov r3, #0 @ 1\n\
- mov ip, #0 @ 1\n\
- mov lr, #0 @ 1\n\
-1: stmia %0!, {r2, r3, ip, lr} @ 4\n\
- stmia %0!, {r2, r3, ip, lr} @ 4\n\
- stmia %0!, {r2, r3, ip, lr} @ 4\n\
- stmia %0!, {r2, r3, ip, lr} @ 4\n\
- subs r1, r1, #1 @ 1\n\
- bne 1b @ 1"
- : "=r" (ptr)
- : "0" (kaddr), "I" (PAGE_SIZE / 64)
- : "r1", "r2", "r3", "ip", "lr");
- kunmap_atomic(kaddr);
-}
-
-struct cpu_user_fns v3_user_fns __initdata = {
- .cpu_clear_user_highpage = v3_clear_user_highpage,
- .cpu_copy_user_highpage = v3_copy_user_highpage,
-};
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index f074675..84aec37 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -430,9 +430,6 @@
index = pgd_index(addr);
- /*
- * FIXME: CP15 C1 is write only on ARMv3 architectures.
- */
pgd = cpu_get_pgd() + index;
pgd_k = init_mm.pgd + index;
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
deleted file mode 100644
index 4fbeb5b..0000000
--- a/arch/arm/mm/proc-arm6_7.S
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- * linux/arch/arm/mm/proc-arm6,7.S
- *
- * Copyright (C) 1997-2000 Russell King
- * hacked for non-paged-MM by Hyok S. Choi, 2003.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * These are the low level assembler for performing cache and TLB
- * functions on the ARM610 & ARM710.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/assembler.h>
-#include <asm/asm-offsets.h>
-#include <asm/hwcap.h>
-#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
-#include <asm/ptrace.h>
-
-#include "proc-macros.S"
-
-ENTRY(cpu_arm6_dcache_clean_area)
-ENTRY(cpu_arm7_dcache_clean_area)
- mov pc, lr
-
-/*
- * Function: arm6_7_data_abort ()
- *
- * Params : r2 = pt_regs
- * : r4 = aborted context pc
- * : r5 = aborted context psr
- *
- * Purpose : obtain information about current aborted instruction
- *
- * Returns : r4-r5, r10-r11, r13 preserved
- */
-
-ENTRY(cpu_arm7_data_abort)
- mrc p15, 0, r1, c5, c0, 0 @ get FSR
- mrc p15, 0, r0, c6, c0, 0 @ get FAR
- ldr r8, [r4] @ read arm instruction
- tst r8, #1 << 20 @ L = 0 -> write?
- orreq r1, r1, #1 << 11 @ yes.
- and r7, r8, #15 << 24
- add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
- nop
-
-/* 0 */ b .data_unknown
-/* 1 */ b do_DataAbort @ swp
-/* 2 */ b .data_unknown
-/* 3 */ b .data_unknown
-/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
-/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
-/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
-/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
-/* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
-/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
-/* a */ b .data_unknown
-/* b */ b .data_unknown
-/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
-/* d */ b do_DataAbort @ ldc rd, [rn, #m]
-/* e */ b .data_unknown
-/* f */
-.data_unknown: @ Part of jumptable
- mov r0, r4
- mov r1, r8
- b baddataabort
-
-ENTRY(cpu_arm6_data_abort)
- mrc p15, 0, r1, c5, c0, 0 @ get FSR
- mrc p15, 0, r0, c6, c0, 0 @ get FAR
- ldr r8, [r4] @ read arm instruction
- tst r8, #1 << 20 @ L = 0 -> write?
- orreq r1, r1, #1 << 11 @ yes.
- and r7, r8, #14 << 24
- teq r7, #8 << 24 @ was it ldm/stm
- bne do_DataAbort
-
-.data_arm_ldmstm:
- tst r8, #1 << 21 @ check writeback bit
- beq do_DataAbort @ no writeback -> no fixup
- mov r7, #0x11
- orr r7, r7, #0x1100
- and r6, r8, r7
- and r9, r8, r7, lsl #1
- add r6, r6, r9, lsr #1
- and r9, r8, r7, lsl #2
- add r6, r6, r9, lsr #2
- and r9, r8, r7, lsl #3
- add r6, r6, r9, lsr #3
- add r6, r6, r6, lsr #8
- add r6, r6, r6, lsr #4
- and r6, r6, #15 @ r6 = no. of registers to transfer.
- and r9, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
- tst r8, #1 << 23 @ Check U bit
- subne r7, r7, r6, lsl #2 @ Undo increment
- addeq r7, r7, r6, lsl #2 @ Undo decrement
- str r7, [r2, r9, lsr #14] @ Put register 'Rn'
- b do_DataAbort
-
-.data_arm_apply_r6_and_rn:
- and r9, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
- tst r8, #1 << 23 @ Check U bit
- subne r7, r7, r6 @ Undo incrmenet
- addeq r7, r7, r6 @ Undo decrement
- str r7, [r2, r9, lsr #14] @ Put register 'Rn'
- b do_DataAbort
-
-.data_arm_lateldrpreconst:
- tst r8, #1 << 21 @ check writeback bit
- beq do_DataAbort @ no writeback -> no fixup
-.data_arm_lateldrpostconst:
- movs r6, r8, lsl #20 @ Get offset
- beq do_DataAbort @ zero -> no fixup
- and r9, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
- tst r8, #1 << 23 @ Check U bit
- subne r7, r7, r6, lsr #20 @ Undo increment
- addeq r7, r7, r6, lsr #20 @ Undo decrement
- str r7, [r2, r9, lsr #14] @ Put register 'Rn'
- b do_DataAbort
-
-.data_arm_lateldrprereg:
- tst r8, #1 << 21 @ check writeback bit
- beq do_DataAbort @ no writeback -> no fixup
-.data_arm_lateldrpostreg:
- and r7, r8, #15 @ Extract 'm' from instruction
- ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
- mov r9, r8, lsr #7 @ get shift count
- ands r9, r9, #31
- and r7, r8, #0x70 @ get shift type
- orreq r7, r7, #8 @ shift count = 0
- add pc, pc, r7
- nop
-
- mov r6, r6, lsl r9 @ 0: LSL #!0
- b .data_arm_apply_r6_and_rn
- b .data_arm_apply_r6_and_rn @ 1: LSL #0
- nop
- b .data_unknown @ 2: MUL?
- nop
- b .data_unknown @ 3: MUL?
- nop
- mov r6, r6, lsr r9 @ 4: LSR #!0
- b .data_arm_apply_r6_and_rn
- mov r6, r6, lsr #32 @ 5: LSR #32
- b .data_arm_apply_r6_and_rn
- b .data_unknown @ 6: MUL?
- nop
- b .data_unknown @ 7: MUL?
- nop
- mov r6, r6, asr r9 @ 8: ASR #!0
- b .data_arm_apply_r6_and_rn
- mov r6, r6, asr #32 @ 9: ASR #32
- b .data_arm_apply_r6_and_rn
- b .data_unknown @ A: MUL?
- nop
- b .data_unknown @ B: MUL?
- nop
- mov r6, r6, ror r9 @ C: ROR #!0
- b .data_arm_apply_r6_and_rn
- mov r6, r6, rrx @ D: RRX
- b .data_arm_apply_r6_and_rn
- b .data_unknown @ E: MUL?
- nop
- b .data_unknown @ F: MUL?
-
-/*
- * Function: arm6_7_proc_init (void)
- * : arm6_7_proc_fin (void)
- *
- * Notes : This processor does not require these
- */
-ENTRY(cpu_arm6_proc_init)
-ENTRY(cpu_arm7_proc_init)
- mov pc, lr
-
-ENTRY(cpu_arm6_proc_fin)
-ENTRY(cpu_arm7_proc_fin)
- mov r0, #0x31 @ ....S..DP...M
- mcr p15, 0, r0, c1, c0, 0 @ disable caches
- mov pc, lr
-
-ENTRY(cpu_arm6_do_idle)
-ENTRY(cpu_arm7_do_idle)
- mov pc, lr
-
-/*
- * Function: arm6_7_switch_mm(unsigned long pgd_phys)
- * Params : pgd_phys Physical address of page table
- * Purpose : Perform a task switch, saving the old processes state, and restoring
- * the new.
- */
-ENTRY(cpu_arm6_switch_mm)
-ENTRY(cpu_arm7_switch_mm)
-#ifdef CONFIG_MMU
- mov r1, #0
- mcr p15, 0, r1, c7, c0, 0 @ flush cache
- mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
- mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
-#endif
- mov pc, lr
-
-/*
- * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
- * Params : r0 = Address to set
- * : r1 = value to set
- * Purpose : Set a PTE and flush it out of any WB cache
- */
- .align 5
-ENTRY(cpu_arm6_set_pte_ext)
-ENTRY(cpu_arm7_set_pte_ext)
-#ifdef CONFIG_MMU
- armv3_set_pte_ext wc_disable=0
-#endif /* CONFIG_MMU */
- mov pc, lr
-
-/*
- * Function: _arm6_7_reset
- * Params : r0 = address to jump to
- * Notes : This sets up everything for a reset
- */
- .pushsection .idmap.text, "ax"
-ENTRY(cpu_arm6_reset)
-ENTRY(cpu_arm7_reset)
- mov r1, #0
- mcr p15, 0, r1, c7, c0, 0 @ flush cache
-#ifdef CONFIG_MMU
- mcr p15, 0, r1, c5, c0, 0 @ flush TLB
-#endif
- mov r1, #0x30
- mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
- mov pc, r0
-ENDPROC(cpu_arm6_reset)
-ENDPROC(cpu_arm7_reset)
- .popsection
-
- __CPUINIT
-
- .type __arm6_setup, #function
-__arm6_setup: mov r0, #0
- mcr p15, 0, r0, c7, c0 @ flush caches on v3
-#ifdef CONFIG_MMU
- mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
- mov r0, #0x3d @ . ..RS BLDP WCAM
- orr r0, r0, #0x100 @ . ..01 0011 1101
-#else
- mov r0, #0x3c @ . ..RS BLDP WCA.
-#endif
- mov pc, lr
- .size __arm6_setup, . - __arm6_setup
-
- .type __arm7_setup, #function
-__arm7_setup: mov r0, #0
- mcr p15, 0, r0, c7, c0 @ flush caches on v3
-#ifdef CONFIG_MMU
- mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
- mcr p15, 0, r0, c3, c0 @ load domain access register
- mov r0, #0x7d @ . ..RS BLDP WCAM
- orr r0, r0, #0x100 @ . ..01 0111 1101
-#else
- mov r0, #0x7c @ . ..RS BLDP WCA.
-#endif
- mov pc, lr
- .size __arm7_setup, . - __arm7_setup
-
- __INITDATA
-
- @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
- define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort
- define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort
-
- .section ".rodata"
-
- string cpu_arch_name, "armv3"
- string cpu_elf_name, "v3"
- string cpu_arm6_name, "ARM6"
- string cpu_arm610_name, "ARM610"
- string cpu_arm7_name, "ARM7"
- string cpu_arm710_name, "ARM710"
-
- .align
-
- .section ".proc.info.init", #alloc, #execinstr
-
-.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
- cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
- .type __\name\()_proc_info, #object
-__\name\()_proc_info:
- .long \cpu_val
- .long \cpu_mask
- .long \cpu_mm_mmu_flags
- .long PMD_TYPE_SECT | \
- PMD_BIT4 | \
- PMD_SECT_AP_WRITE | \
- PMD_SECT_AP_READ
- b \cpu_flush
- .long cpu_arch_name
- .long cpu_elf_name
- .long HWCAP_SWP | HWCAP_26BIT
- .long \cpu_name
- .long \cpu_proc_funcs
- .long v3_tlb_fns
- .long v3_user_fns
- .long v3_cache_fns
- .size __\name\()_proc_info, . - __\name\()_proc_info
-.endm
-
- arm67_proc_info arm6, 0x41560600, 0xfffffff0, cpu_arm6_name, \
- 0x00000c1e, __arm6_setup, arm6_processor_functions
- arm67_proc_info arm610, 0x41560610, 0xfffffff0, cpu_arm610_name, \
- 0x00000c1e, __arm6_setup, arm6_processor_functions
- arm67_proc_info arm7, 0x41007000, 0xffffff00, cpu_arm7_name, \
- 0x00000c1e, __arm7_setup, arm7_processor_functions
- arm67_proc_info arm710, 0x41007100, 0xfff8ff00, cpu_arm710_name, \
- PMD_TYPE_SECT | \
- PMD_SECT_BUFFERABLE | \
- PMD_SECT_CACHEABLE | \
- PMD_BIT4 | \
- PMD_SECT_AP_WRITE | \
- PMD_SECT_AP_READ, \
- __arm7_setup, arm7_processor_functions
diff --git a/arch/arm/mm/tlb-v3.S b/arch/arm/mm/tlb-v3.S
deleted file mode 100644
index d253995..0000000
--- a/arch/arm/mm/tlb-v3.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * linux/arch/arm/mm/tlbv3.S
- *
- * Copyright (C) 1997-2002 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * ARM architecture version 3 TLB handling functions.
- *
- * Processors: ARM610, ARM710.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/asm-offsets.h>
-#include <asm/tlbflush.h>
-#include "proc-macros.S"
-
- .align 5
-/*
- * v3_flush_user_tlb_range(start, end, mm)
- *
- * Invalidate a range of TLB entries in the specified address space.
- *
- * - start - range start address
- * - end - range end address
- * - mm - mm_struct describing address space
- */
- .align 5
-ENTRY(v3_flush_user_tlb_range)
- vma_vm_mm r2, r2
- act_mm r3 @ get current->active_mm
- teq r2, r3 @ == mm ?
- movne pc, lr @ no, we dont do anything
-ENTRY(v3_flush_kern_tlb_range)
- bic r0, r0, #0x0ff
- bic r0, r0, #0xf00
-1: mcr p15, 0, r0, c6, c0, 0 @ invalidate TLB entry
- add r0, r0, #PAGE_SZ
- cmp r0, r1
- blo 1b
- mov pc, lr
-
- __INITDATA
-
- /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
- define_tlb_functions v3, v3_tlb_flags