)]}'
{
  "commit": "398e692fd5cecdd25d311b47bbae69f7bac3a3cb",
  "tree": "f1852c28d9f9c47c4763607630ac3db1c91930d6",
  "parents": [
    "9a4d93d49d140c196020a1bae339efcf211cac03"
  ],
  "author": {
    "name": "Lennert Buytenhek",
    "email": "buytenh@wantstofly.org",
    "time": "Sat Mar 31 12:03:20 2007 +0100"
  },
  "committer": {
    "name": "Russell King",
    "email": "rmk+kernel@arm.linux.org.uk",
    "time": "Sun Apr 01 22:38:36 2007 +0100"
  },
  "message": "[ARM] 4298/1: fix memory barriers for DMA coherent and SMP platforms\n\nThis patch:\n- Switches mb/rmb/wmb back to being full-blown DMBs on ARM SMP systems,\n  since mb/rmb/wmb are required to order Normal memory accesses as well.\n- Enables the use of DMB and ISB on XSC3 (which is an ARMv5TE ISA core\n  but conforms to the ARMv6 memory ordering model and supports the\n  various ARMv6 barriers.)\n- Makes DMA coherent platforms (only ixp23xx at the moment) map\n  mb/rmb/wmb to dmb(), as on DMA coherent platforms, DMA consistent\n  mappings are done as Normal mappings, which are weakly ordered.\n\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@wantstofly.org\u003e\nAcked-by: David Howells \u003cdhowells@redhat.com\u003e\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nAcked-by: Paul E. McKenney \u003cpaulmck@linux.vnet.ibm.com\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f06d8a43fdee9eed0553cbb910ef279ee2813a82",
      "old_mode": 33188,
      "old_path": "include/asm-arm/system.h",
      "new_id": "69134c7518c1eceec790ed06e5e388ad8c2d46c8",
      "new_mode": 33188,
      "new_path": "include/asm-arm/system.h"
    }
  ]
}