[MIPS] Don't drag a platform specific header into generic arch code.
For some platforms it's definitions may conflict. So that's the one-liner.
The rest is 10 square kilometers of collateral damage fixup this include
used to paper over.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index a7a17eb..b123364 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1350,9 +1350,6 @@
if (!secondaryTC) {
#endif /* CONFIG_MIPS_MT_SMTC */
- /*
- * Interrupt handling.
- */
if (cpu_has_veic || cpu_has_vint) {
write_c0_ebase (ebase);
/* Setting vector spacing enables EI/VI mode */
@@ -1366,6 +1363,23 @@
} else
set_c0_cause(CAUSEF_IV);
}
+
+ /*
+ * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
+ *
+ * o read IntCtl.IPTI to determine the timer interrupt
+ * o read IntCtl.IPPCI to determine the performance counter interrupt
+ */
+ if (cpu_has_mips_r2) {
+ cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
+ cp0_perfcount_irq = -1;
+ } else {
+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
+ cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
+ if (cp0_perfcount_irq != cp0_compare_irq)
+ cp0_perfcount_irq = -1;
+ }
+
#ifdef CONFIG_MIPS_MT_SMTC
}
#endif /* CONFIG_MIPS_MT_SMTC */