)]}'
{
  "commit": "56fb4df6da76c35dca22036174e2d1edef83ff1f",
  "tree": "b39f152ec9ed682edceca965a85680fd4bf736a7",
  "parents": [
    "3c936465249f863f322154ff1aaa628b84ee5750"
  ],
  "author": {
    "name": "David S. Miller",
    "email": "davem@davemloft.net",
    "time": "Sun Feb 26 23:24:22 2006 -0800"
  },
  "committer": {
    "name": "David S. Miller",
    "email": "davem@sunset.davemloft.net",
    "time": "Mon Mar 20 01:11:16 2006 -0800"
  },
  "message": "[SPARC64]: Elminate all usage of hard-coded trap globals.\n\nUltraSPARC has special sets of global registers which are switched to\nfor certain trap types.  There is one set for MMU related traps, one\nset of Interrupt Vector processing, and another set (called the\nAlternate globals) for all other trap types.\n\nFor what seems like forever we\u0027ve hard coded the values in some of\nthese trap registers.  Some examples include:\n\n1) Interrupt Vector global %g6 holds current processors interrupt\n   work struct where received interrupts are managed for IRQ handler\n   dispatch.\n\n2) MMU global %g7 holds the base of the page tables of the currently\n   active address space.\n\n3) Alternate global %g6 held the current_thread_info() value.\n\nSuch hardcoding has resulted in some serious issues in many areas.\nThere are some code sequences where having another register available\nwould help clean up the implementation.  Taking traps such as\ncross-calls from the OBP firmware requires some trick code sequences\nwherein we have to save away and restore all of the special sets of\nglobal registers when we enter/exit OBP.\n\nWe were also using the IMMU TSB register on SMP to hold the per-cpu\narea base address, which doesn\u0027t work any longer now that we actually\nuse the TSB facility of the cpu.\n\nThe implementation is pretty straight forward.  One tricky bit is\ngetting the current processor ID as that is different on different cpu\nvariants.  We use a stub with a fancy calling convention which we\npatch at boot time.  The calling convention is that the stub is\nbranched to and the (PC - 4) to return to is in register %g1.  The cpu\nnumber is left in %g6.  This stub can be invoked by using the\n__GET_CPUID macro.\n\nWe use an array of per-cpu trap state to store the current thread and\nphysical address of the current address space\u0027s page tables.  The\nTRAP_LOAD_THREAD_REG loads %g6 with the current thread from this\ntable, it uses __GET_CPUID and also clobbers %g1.\n\nTRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load\nthe current processor\u0027s IRQ software state into %g6.  It also uses\n__GET_CPUID and clobbers %g1.\n\nFinally, TRAP_LOAD_PGD_PHYS loads the physical address base of the\ncurrent address space\u0027s page tables into %g7, it clobbers %g1 and uses\n__GET_CPUID.\n\nMany refinements are possible, as well as some tuning, with this stuff\nin place.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n",
  "tree_diff": [
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